root / hw / tcx.c @ 7fc2f2c0
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/*
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* QEMU TCX Frame buffer
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*
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* Copyright (c) 2003-2005 Fabrice Bellard
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "sun4m.h" |
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#include "console.h" |
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#include "pixel_ops.h" |
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#include "sysbus.h" |
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#include "qdev-addr.h" |
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|
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#define MAXX 1024 |
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#define MAXY 768 |
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#define TCX_DAC_NREGS 16 |
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#define TCX_THC_NREGS_8 0x081c |
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#define TCX_THC_NREGS_24 0x1000 |
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#define TCX_TEC_NREGS 0x1000 |
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typedef struct TCXState { |
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SysBusDevice busdev; |
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target_phys_addr_t addr; |
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DisplayState *ds; |
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uint8_t *vram; |
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uint32_t *vram24, *cplane; |
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ram_addr_t vram_offset, vram24_offset, cplane_offset; |
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uint32_t vram_size; |
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uint16_t width, height, depth; |
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uint8_t r[256], g[256], b[256]; |
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uint32_t palette[256];
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uint8_t dac_index, dac_state; |
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} TCXState; |
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|
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static void tcx_screen_dump(void *opaque, const char *filename); |
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static void tcx24_screen_dump(void *opaque, const char *filename); |
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static void tcx_set_dirty(TCXState *s) |
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{ |
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unsigned int i; |
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for (i = 0; i < MAXX * MAXY; i += TARGET_PAGE_SIZE) { |
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cpu_physical_memory_set_dirty(s->vram_offset + i); |
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} |
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} |
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static void tcx24_set_dirty(TCXState *s) |
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{ |
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unsigned int i; |
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for (i = 0; i < MAXX * MAXY * 4; i += TARGET_PAGE_SIZE) { |
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cpu_physical_memory_set_dirty(s->vram24_offset + i); |
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cpu_physical_memory_set_dirty(s->cplane_offset + i); |
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} |
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} |
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static void update_palette_entries(TCXState *s, int start, int end) |
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{ |
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int i;
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for(i = start; i < end; i++) {
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switch(ds_get_bits_per_pixel(s->ds)) {
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default:
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case 8: |
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s->palette[i] = rgb_to_pixel8(s->r[i], s->g[i], s->b[i]); |
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break;
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case 15: |
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s->palette[i] = rgb_to_pixel15(s->r[i], s->g[i], s->b[i]); |
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break;
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case 16: |
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s->palette[i] = rgb_to_pixel16(s->r[i], s->g[i], s->b[i]); |
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break;
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case 32: |
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if (is_surface_bgr(s->ds->surface))
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s->palette[i] = rgb_to_pixel32bgr(s->r[i], s->g[i], s->b[i]); |
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else
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s->palette[i] = rgb_to_pixel32(s->r[i], s->g[i], s->b[i]); |
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break;
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} |
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} |
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if (s->depth == 24) { |
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tcx24_set_dirty(s); |
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} else {
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tcx_set_dirty(s); |
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} |
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} |
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static void tcx_draw_line32(TCXState *s1, uint8_t *d, |
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const uint8_t *s, int width) |
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{ |
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int x;
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uint8_t val; |
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uint32_t *p = (uint32_t *)d; |
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for(x = 0; x < width; x++) { |
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val = *s++; |
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*p++ = s1->palette[val]; |
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} |
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} |
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static void tcx_draw_line16(TCXState *s1, uint8_t *d, |
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const uint8_t *s, int width) |
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{ |
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int x;
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uint8_t val; |
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uint16_t *p = (uint16_t *)d; |
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for(x = 0; x < width; x++) { |
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val = *s++; |
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*p++ = s1->palette[val]; |
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} |
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} |
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static void tcx_draw_line8(TCXState *s1, uint8_t *d, |
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const uint8_t *s, int width) |
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{ |
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int x;
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uint8_t val; |
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for(x = 0; x < width; x++) { |
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val = *s++; |
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*d++ = s1->palette[val]; |
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} |
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} |
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/*
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XXX Could be much more optimal:
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* detect if line/page/whole screen is in 24 bit mode
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* if destination is also BGR, use memcpy
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*/
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static inline void tcx24_draw_line32(TCXState *s1, uint8_t *d, |
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const uint8_t *s, int width, |
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const uint32_t *cplane,
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const uint32_t *s24)
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{ |
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int x, bgr, r, g, b;
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uint8_t val, *p8; |
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uint32_t *p = (uint32_t *)d; |
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uint32_t dval; |
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bgr = is_surface_bgr(s1->ds->surface); |
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for(x = 0; x < width; x++, s++, s24++) { |
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if ((be32_to_cpu(*cplane++) & 0xff000000) == 0x03000000) { |
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// 24-bit direct, BGR order
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p8 = (uint8_t *)s24; |
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p8++; |
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b = *p8++; |
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g = *p8++; |
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r = *p8++; |
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if (bgr)
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dval = rgb_to_pixel32bgr(r, g, b); |
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else
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dval = rgb_to_pixel32(r, g, b); |
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} else {
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val = *s; |
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dval = s1->palette[val]; |
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} |
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*p++ = dval; |
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} |
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} |
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static inline int check_dirty(ram_addr_t page, ram_addr_t page24, |
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ram_addr_t cpage) |
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{ |
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int ret;
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unsigned int off; |
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ret = cpu_physical_memory_get_dirty(page, VGA_DIRTY_FLAG); |
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for (off = 0; off < TARGET_PAGE_SIZE * 4; off += TARGET_PAGE_SIZE) { |
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ret |= cpu_physical_memory_get_dirty(page24 + off, VGA_DIRTY_FLAG); |
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ret |= cpu_physical_memory_get_dirty(cpage + off, VGA_DIRTY_FLAG); |
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} |
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return ret;
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} |
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static inline void reset_dirty(TCXState *ts, ram_addr_t page_min, |
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ram_addr_t page_max, ram_addr_t page24, |
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ram_addr_t cpage) |
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{ |
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cpu_physical_memory_reset_dirty(page_min, page_max + TARGET_PAGE_SIZE, |
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VGA_DIRTY_FLAG); |
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page_min -= ts->vram_offset; |
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page_max -= ts->vram_offset; |
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cpu_physical_memory_reset_dirty(page24 + page_min * 4,
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page24 + page_max * 4 + TARGET_PAGE_SIZE,
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VGA_DIRTY_FLAG); |
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cpu_physical_memory_reset_dirty(cpage + page_min * 4,
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cpage + page_max * 4 + TARGET_PAGE_SIZE,
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VGA_DIRTY_FLAG); |
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} |
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/* Fixed line length 1024 allows us to do nice tricks not possible on
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VGA... */
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static void tcx_update_display(void *opaque) |
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{ |
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TCXState *ts = opaque; |
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ram_addr_t page, page_min, page_max; |
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int y, y_start, dd, ds;
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uint8_t *d, *s; |
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void (*f)(TCXState *s1, uint8_t *dst, const uint8_t *src, int width); |
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if (ds_get_bits_per_pixel(ts->ds) == 0) |
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return;
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page = ts->vram_offset; |
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y_start = -1;
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page_min = -1;
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page_max = 0;
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d = ds_get_data(ts->ds); |
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s = ts->vram; |
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dd = ds_get_linesize(ts->ds); |
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ds = 1024;
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switch (ds_get_bits_per_pixel(ts->ds)) {
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case 32: |
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f = tcx_draw_line32; |
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break;
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case 15: |
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case 16: |
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f = tcx_draw_line16; |
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break;
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default:
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case 8: |
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f = tcx_draw_line8; |
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break;
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case 0: |
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return;
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} |
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for(y = 0; y < ts->height; y += 4, page += TARGET_PAGE_SIZE) { |
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if (cpu_physical_memory_get_dirty(page, VGA_DIRTY_FLAG)) {
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if (y_start < 0) |
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y_start = y; |
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if (page < page_min)
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page_min = page; |
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if (page > page_max)
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page_max = page; |
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f(ts, d, s, ts->width); |
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d += dd; |
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s += ds; |
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f(ts, d, s, ts->width); |
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d += dd; |
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s += ds; |
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f(ts, d, s, ts->width); |
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d += dd; |
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s += ds; |
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f(ts, d, s, ts->width); |
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d += dd; |
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s += ds; |
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} else {
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if (y_start >= 0) { |
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/* flush to display */
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dpy_update(ts->ds, 0, y_start,
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ts->width, y - y_start); |
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y_start = -1;
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} |
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d += dd * 4;
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s += ds * 4;
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} |
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} |
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if (y_start >= 0) { |
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/* flush to display */
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dpy_update(ts->ds, 0, y_start,
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ts->width, y - y_start); |
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} |
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/* reset modified pages */
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if (page_max >= page_min) {
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cpu_physical_memory_reset_dirty(page_min, page_max + TARGET_PAGE_SIZE, |
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VGA_DIRTY_FLAG); |
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} |
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} |
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|
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static void tcx24_update_display(void *opaque) |
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{ |
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TCXState *ts = opaque; |
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ram_addr_t page, page_min, page_max, cpage, page24; |
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int y, y_start, dd, ds;
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uint8_t *d, *s; |
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uint32_t *cptr, *s24; |
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if (ds_get_bits_per_pixel(ts->ds) != 32) |
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return;
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page = ts->vram_offset; |
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page24 = ts->vram24_offset; |
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cpage = ts->cplane_offset; |
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y_start = -1;
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page_min = -1;
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page_max = 0;
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d = ds_get_data(ts->ds); |
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s = ts->vram; |
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s24 = ts->vram24; |
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cptr = ts->cplane; |
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dd = ds_get_linesize(ts->ds); |
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ds = 1024;
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for(y = 0; y < ts->height; y += 4, page += TARGET_PAGE_SIZE, |
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page24 += TARGET_PAGE_SIZE, cpage += TARGET_PAGE_SIZE) { |
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if (check_dirty(page, page24, cpage)) {
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if (y_start < 0) |
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y_start = y; |
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if (page < page_min)
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page_min = page; |
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if (page > page_max)
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page_max = page; |
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tcx24_draw_line32(ts, d, s, ts->width, cptr, s24); |
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d += dd; |
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s += ds; |
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cptr += ds; |
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s24 += ds; |
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tcx24_draw_line32(ts, d, s, ts->width, cptr, s24); |
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d += dd; |
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s += ds; |
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cptr += ds; |
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s24 += ds; |
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tcx24_draw_line32(ts, d, s, ts->width, cptr, s24); |
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d += dd; |
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s += ds; |
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cptr += ds; |
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s24 += ds; |
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tcx24_draw_line32(ts, d, s, ts->width, cptr, s24); |
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d += dd; |
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s += ds; |
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cptr += ds; |
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s24 += ds; |
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} else {
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if (y_start >= 0) { |
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/* flush to display */
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dpy_update(ts->ds, 0, y_start,
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ts->width, y - y_start); |
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y_start = -1;
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} |
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d += dd * 4;
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s += ds * 4;
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cptr += ds * 4;
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s24 += ds * 4;
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} |
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} |
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if (y_start >= 0) { |
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/* flush to display */
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dpy_update(ts->ds, 0, y_start,
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ts->width, y - y_start); |
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} |
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/* reset modified pages */
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if (page_max >= page_min) {
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reset_dirty(ts, page_min, page_max, page24, cpage); |
361 |
} |
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} |
363 |
|
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static void tcx_invalidate_display(void *opaque) |
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{ |
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TCXState *s = opaque; |
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|
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tcx_set_dirty(s); |
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qemu_console_resize(s->ds, s->width, s->height); |
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} |
371 |
|
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static void tcx24_invalidate_display(void *opaque) |
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{ |
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TCXState *s = opaque; |
375 |
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tcx_set_dirty(s); |
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tcx24_set_dirty(s); |
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qemu_console_resize(s->ds, s->width, s->height); |
379 |
} |
380 |
|
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static int vmstate_tcx_after_load(void *opaque) |
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{ |
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TCXState *s = opaque; |
384 |
|
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update_palette_entries(s, 0, 256); |
386 |
if (s->depth == 24) { |
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tcx24_set_dirty(s); |
388 |
} else {
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tcx_set_dirty(s); |
390 |
} |
391 |
|
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return 0; |
393 |
} |
394 |
|
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static const VMStateDescription vmstate_tcx = { |
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.name ="tcx",
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.version_id = 4,
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.minimum_version_id = 4,
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.minimum_version_id_old = 4,
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.run_after_load = vmstate_tcx_after_load, |
401 |
.fields = (VMStateField []) { |
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VMSTATE_UINT16(height, TCXState), |
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VMSTATE_UINT16(width, TCXState), |
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VMSTATE_UINT16(depth, TCXState), |
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VMSTATE_BUFFER(r, TCXState), |
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VMSTATE_BUFFER(g, TCXState), |
407 |
VMSTATE_BUFFER(b, TCXState), |
408 |
VMSTATE_UINT8(dac_index, TCXState), |
409 |
VMSTATE_UINT8(dac_state, TCXState), |
410 |
VMSTATE_END_OF_LIST() |
411 |
} |
412 |
}; |
413 |
|
414 |
static void tcx_reset(void *opaque) |
415 |
{ |
416 |
TCXState *s = opaque; |
417 |
|
418 |
/* Initialize palette */
|
419 |
memset(s->r, 0, 256); |
420 |
memset(s->g, 0, 256); |
421 |
memset(s->b, 0, 256); |
422 |
s->r[255] = s->g[255] = s->b[255] = 255; |
423 |
update_palette_entries(s, 0, 256); |
424 |
memset(s->vram, 0, MAXX*MAXY);
|
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cpu_physical_memory_reset_dirty(s->vram_offset, s->vram_offset + |
426 |
MAXX * MAXY * (1 + 4 + 4), VGA_DIRTY_FLAG); |
427 |
s->dac_index = 0;
|
428 |
s->dac_state = 0;
|
429 |
} |
430 |
|
431 |
static uint32_t tcx_dac_readl(void *opaque, target_phys_addr_t addr) |
432 |
{ |
433 |
return 0; |
434 |
} |
435 |
|
436 |
static void tcx_dac_writel(void *opaque, target_phys_addr_t addr, uint32_t val) |
437 |
{ |
438 |
TCXState *s = opaque; |
439 |
|
440 |
switch (addr) {
|
441 |
case 0: |
442 |
s->dac_index = val >> 24;
|
443 |
s->dac_state = 0;
|
444 |
break;
|
445 |
case 4: |
446 |
switch (s->dac_state) {
|
447 |
case 0: |
448 |
s->r[s->dac_index] = val >> 24;
|
449 |
update_palette_entries(s, s->dac_index, s->dac_index + 1);
|
450 |
s->dac_state++; |
451 |
break;
|
452 |
case 1: |
453 |
s->g[s->dac_index] = val >> 24;
|
454 |
update_palette_entries(s, s->dac_index, s->dac_index + 1);
|
455 |
s->dac_state++; |
456 |
break;
|
457 |
case 2: |
458 |
s->b[s->dac_index] = val >> 24;
|
459 |
update_palette_entries(s, s->dac_index, s->dac_index + 1);
|
460 |
s->dac_index = (s->dac_index + 1) & 255; // Index autoincrement |
461 |
default:
|
462 |
s->dac_state = 0;
|
463 |
break;
|
464 |
} |
465 |
break;
|
466 |
default:
|
467 |
break;
|
468 |
} |
469 |
return;
|
470 |
} |
471 |
|
472 |
static CPUReadMemoryFunc * const tcx_dac_read[3] = { |
473 |
NULL,
|
474 |
NULL,
|
475 |
tcx_dac_readl, |
476 |
}; |
477 |
|
478 |
static CPUWriteMemoryFunc * const tcx_dac_write[3] = { |
479 |
NULL,
|
480 |
NULL,
|
481 |
tcx_dac_writel, |
482 |
}; |
483 |
|
484 |
static uint32_t tcx_dummy_readl(void *opaque, target_phys_addr_t addr) |
485 |
{ |
486 |
return 0; |
487 |
} |
488 |
|
489 |
static void tcx_dummy_writel(void *opaque, target_phys_addr_t addr, |
490 |
uint32_t val) |
491 |
{ |
492 |
} |
493 |
|
494 |
static CPUReadMemoryFunc * const tcx_dummy_read[3] = { |
495 |
NULL,
|
496 |
NULL,
|
497 |
tcx_dummy_readl, |
498 |
}; |
499 |
|
500 |
static CPUWriteMemoryFunc * const tcx_dummy_write[3] = { |
501 |
NULL,
|
502 |
NULL,
|
503 |
tcx_dummy_writel, |
504 |
}; |
505 |
|
506 |
static int tcx_init1(SysBusDevice *dev) |
507 |
{ |
508 |
TCXState *s = FROM_SYSBUS(TCXState, dev); |
509 |
int io_memory, dummy_memory;
|
510 |
ram_addr_t vram_offset; |
511 |
int size;
|
512 |
uint8_t *vram_base; |
513 |
|
514 |
vram_offset = qemu_ram_alloc(s->vram_size * (1 + 4 + 4)); |
515 |
vram_base = qemu_get_ram_ptr(vram_offset); |
516 |
s->vram_offset = vram_offset; |
517 |
|
518 |
/* 8-bit plane */
|
519 |
s->vram = vram_base; |
520 |
size = s->vram_size; |
521 |
sysbus_init_mmio(dev, size, s->vram_offset); |
522 |
vram_offset += size; |
523 |
vram_base += size; |
524 |
|
525 |
/* DAC */
|
526 |
io_memory = cpu_register_io_memory(tcx_dac_read, tcx_dac_write, s); |
527 |
sysbus_init_mmio(dev, TCX_DAC_NREGS, io_memory); |
528 |
|
529 |
/* TEC (dummy) */
|
530 |
dummy_memory = cpu_register_io_memory(tcx_dummy_read, tcx_dummy_write, |
531 |
s); |
532 |
sysbus_init_mmio(dev, TCX_TEC_NREGS, dummy_memory); |
533 |
/* THC: NetBSD writes here even with 8-bit display: dummy */
|
534 |
sysbus_init_mmio(dev, TCX_THC_NREGS_24, dummy_memory); |
535 |
|
536 |
if (s->depth == 24) { |
537 |
/* 24-bit plane */
|
538 |
size = s->vram_size * 4;
|
539 |
s->vram24 = (uint32_t *)vram_base; |
540 |
s->vram24_offset = vram_offset; |
541 |
sysbus_init_mmio(dev, size, vram_offset); |
542 |
vram_offset += size; |
543 |
vram_base += size; |
544 |
|
545 |
/* Control plane */
|
546 |
size = s->vram_size * 4;
|
547 |
s->cplane = (uint32_t *)vram_base; |
548 |
s->cplane_offset = vram_offset; |
549 |
sysbus_init_mmio(dev, size, vram_offset); |
550 |
|
551 |
s->ds = graphic_console_init(tcx24_update_display, |
552 |
tcx24_invalidate_display, |
553 |
tcx24_screen_dump, NULL, s);
|
554 |
} else {
|
555 |
/* THC 8 bit (dummy) */
|
556 |
sysbus_init_mmio(dev, TCX_THC_NREGS_8, dummy_memory); |
557 |
|
558 |
s->ds = graphic_console_init(tcx_update_display, |
559 |
tcx_invalidate_display, |
560 |
tcx_screen_dump, NULL, s);
|
561 |
} |
562 |
|
563 |
vmstate_register(-1, &vmstate_tcx, s);
|
564 |
qemu_register_reset(tcx_reset, s); |
565 |
tcx_reset(s); |
566 |
qemu_console_resize(s->ds, s->width, s->height); |
567 |
return 0; |
568 |
} |
569 |
|
570 |
static void tcx_screen_dump(void *opaque, const char *filename) |
571 |
{ |
572 |
TCXState *s = opaque; |
573 |
FILE *f; |
574 |
uint8_t *d, *d1, v; |
575 |
int y, x;
|
576 |
|
577 |
f = fopen(filename, "wb");
|
578 |
if (!f)
|
579 |
return;
|
580 |
fprintf(f, "P6\n%d %d\n%d\n", s->width, s->height, 255); |
581 |
d1 = s->vram; |
582 |
for(y = 0; y < s->height; y++) { |
583 |
d = d1; |
584 |
for(x = 0; x < s->width; x++) { |
585 |
v = *d; |
586 |
fputc(s->r[v], f); |
587 |
fputc(s->g[v], f); |
588 |
fputc(s->b[v], f); |
589 |
d++; |
590 |
} |
591 |
d1 += MAXX; |
592 |
} |
593 |
fclose(f); |
594 |
return;
|
595 |
} |
596 |
|
597 |
static void tcx24_screen_dump(void *opaque, const char *filename) |
598 |
{ |
599 |
TCXState *s = opaque; |
600 |
FILE *f; |
601 |
uint8_t *d, *d1, v; |
602 |
uint32_t *s24, *cptr, dval; |
603 |
int y, x;
|
604 |
|
605 |
f = fopen(filename, "wb");
|
606 |
if (!f)
|
607 |
return;
|
608 |
fprintf(f, "P6\n%d %d\n%d\n", s->width, s->height, 255); |
609 |
d1 = s->vram; |
610 |
s24 = s->vram24; |
611 |
cptr = s->cplane; |
612 |
for(y = 0; y < s->height; y++) { |
613 |
d = d1; |
614 |
for(x = 0; x < s->width; x++, d++, s24++) { |
615 |
if ((*cptr++ & 0xff000000) == 0x03000000) { // 24-bit direct |
616 |
dval = *s24 & 0x00ffffff;
|
617 |
fputc((dval >> 16) & 0xff, f); |
618 |
fputc((dval >> 8) & 0xff, f); |
619 |
fputc(dval & 0xff, f);
|
620 |
} else {
|
621 |
v = *d; |
622 |
fputc(s->r[v], f); |
623 |
fputc(s->g[v], f); |
624 |
fputc(s->b[v], f); |
625 |
} |
626 |
} |
627 |
d1 += MAXX; |
628 |
} |
629 |
fclose(f); |
630 |
return;
|
631 |
} |
632 |
|
633 |
static SysBusDeviceInfo tcx_info = {
|
634 |
.init = tcx_init1, |
635 |
.qdev.name = "SUNW,tcx",
|
636 |
.qdev.size = sizeof(TCXState),
|
637 |
.qdev.props = (Property[]) { |
638 |
DEFINE_PROP_TADDR("addr", TCXState, addr, -1), |
639 |
DEFINE_PROP_HEX32("vram_size", TCXState, vram_size, -1), |
640 |
DEFINE_PROP_UINT16("width", TCXState, width, -1), |
641 |
DEFINE_PROP_UINT16("height", TCXState, height, -1), |
642 |
DEFINE_PROP_UINT16("depth", TCXState, depth, -1), |
643 |
DEFINE_PROP_END_OF_LIST(), |
644 |
} |
645 |
}; |
646 |
|
647 |
static void tcx_register_devices(void) |
648 |
{ |
649 |
sysbus_register_withprop(&tcx_info); |
650 |
} |
651 |
|
652 |
device_init(tcx_register_devices) |