root / hw / usb-ohci.c @ 7fc2f2c0
History | View | Annotate | Download (50.3 kB)
1 |
/*
|
---|---|
2 |
* QEMU USB OHCI Emulation
|
3 |
* Copyright (c) 2004 Gianni Tedesco
|
4 |
* Copyright (c) 2006 CodeSourcery
|
5 |
* Copyright (c) 2006 Openedhand Ltd.
|
6 |
*
|
7 |
* This library is free software; you can redistribute it and/or
|
8 |
* modify it under the terms of the GNU Lesser General Public
|
9 |
* License as published by the Free Software Foundation; either
|
10 |
* version 2 of the License, or (at your option) any later version.
|
11 |
*
|
12 |
* This library is distributed in the hope that it will be useful,
|
13 |
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
14 |
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
15 |
* Lesser General Public License for more details.
|
16 |
*
|
17 |
* You should have received a copy of the GNU Lesser General Public
|
18 |
* License along with this library; if not, see <http://www.gnu.org/licenses/>.
|
19 |
*
|
20 |
* TODO:
|
21 |
* o Isochronous transfers
|
22 |
* o Allocate bandwidth in frames properly
|
23 |
* o Disable timers when nothing needs to be done, or remove timer usage
|
24 |
* all together.
|
25 |
* o Handle unrecoverable errors properly
|
26 |
* o BIOS work to boot from USB storage
|
27 |
*/
|
28 |
|
29 |
#include "hw.h" |
30 |
#include "qemu-timer.h" |
31 |
#include "usb.h" |
32 |
#include "pci.h" |
33 |
#include "pxa.h" |
34 |
#include "devices.h" |
35 |
|
36 |
//#define DEBUG_OHCI
|
37 |
/* Dump packet contents. */
|
38 |
//#define DEBUG_PACKET
|
39 |
//#define DEBUG_ISOCH
|
40 |
/* This causes frames to occur 1000x slower */
|
41 |
//#define OHCI_TIME_WARP 1
|
42 |
|
43 |
#ifdef DEBUG_OHCI
|
44 |
#define dprintf printf
|
45 |
#else
|
46 |
#define dprintf(...)
|
47 |
#endif
|
48 |
|
49 |
/* Number of Downstream Ports on the root hub. */
|
50 |
|
51 |
#define OHCI_MAX_PORTS 15 |
52 |
|
53 |
static int64_t usb_frame_time;
|
54 |
static int64_t usb_bit_time;
|
55 |
|
56 |
typedef struct OHCIPort { |
57 |
USBPort port; |
58 |
uint32_t ctrl; |
59 |
} OHCIPort; |
60 |
|
61 |
enum ohci_type {
|
62 |
OHCI_TYPE_PCI, |
63 |
OHCI_TYPE_PXA, |
64 |
OHCI_TYPE_SM501, |
65 |
}; |
66 |
|
67 |
typedef struct { |
68 |
USBBus *bus; |
69 |
qemu_irq irq; |
70 |
enum ohci_type type;
|
71 |
int mem;
|
72 |
int num_ports;
|
73 |
const char *name; |
74 |
|
75 |
QEMUTimer *eof_timer; |
76 |
int64_t sof_time; |
77 |
|
78 |
/* OHCI state */
|
79 |
/* Control partition */
|
80 |
uint32_t ctl, status; |
81 |
uint32_t intr_status; |
82 |
uint32_t intr; |
83 |
|
84 |
/* memory pointer partition */
|
85 |
uint32_t hcca; |
86 |
uint32_t ctrl_head, ctrl_cur; |
87 |
uint32_t bulk_head, bulk_cur; |
88 |
uint32_t per_cur; |
89 |
uint32_t done; |
90 |
int done_count;
|
91 |
|
92 |
/* Frame counter partition */
|
93 |
uint32_t fsmps:15;
|
94 |
uint32_t fit:1;
|
95 |
uint32_t fi:14;
|
96 |
uint32_t frt:1;
|
97 |
uint16_t frame_number; |
98 |
uint16_t padding; |
99 |
uint32_t pstart; |
100 |
uint32_t lst; |
101 |
|
102 |
/* Root Hub partition */
|
103 |
uint32_t rhdesc_a, rhdesc_b; |
104 |
uint32_t rhstatus; |
105 |
OHCIPort rhport[OHCI_MAX_PORTS]; |
106 |
|
107 |
/* PXA27x Non-OHCI events */
|
108 |
uint32_t hstatus; |
109 |
uint32_t hmask; |
110 |
uint32_t hreset; |
111 |
uint32_t htest; |
112 |
|
113 |
/* SM501 local memory offset */
|
114 |
target_phys_addr_t localmem_base; |
115 |
|
116 |
/* Active packets. */
|
117 |
uint32_t old_ctl; |
118 |
USBPacket usb_packet; |
119 |
uint8_t usb_buf[8192];
|
120 |
uint32_t async_td; |
121 |
int async_complete;
|
122 |
|
123 |
} OHCIState; |
124 |
|
125 |
/* Host Controller Communications Area */
|
126 |
struct ohci_hcca {
|
127 |
uint32_t intr[32];
|
128 |
uint16_t frame, pad; |
129 |
uint32_t done; |
130 |
}; |
131 |
|
132 |
static void ohci_bus_stop(OHCIState *ohci); |
133 |
|
134 |
/* Bitfields for the first word of an Endpoint Desciptor. */
|
135 |
#define OHCI_ED_FA_SHIFT 0 |
136 |
#define OHCI_ED_FA_MASK (0x7f<<OHCI_ED_FA_SHIFT) |
137 |
#define OHCI_ED_EN_SHIFT 7 |
138 |
#define OHCI_ED_EN_MASK (0xf<<OHCI_ED_EN_SHIFT) |
139 |
#define OHCI_ED_D_SHIFT 11 |
140 |
#define OHCI_ED_D_MASK (3<<OHCI_ED_D_SHIFT) |
141 |
#define OHCI_ED_S (1<<13) |
142 |
#define OHCI_ED_K (1<<14) |
143 |
#define OHCI_ED_F (1<<15) |
144 |
#define OHCI_ED_MPS_SHIFT 16 |
145 |
#define OHCI_ED_MPS_MASK (0x7ff<<OHCI_ED_MPS_SHIFT) |
146 |
|
147 |
/* Flags in the head field of an Endpoint Desciptor. */
|
148 |
#define OHCI_ED_H 1 |
149 |
#define OHCI_ED_C 2 |
150 |
|
151 |
/* Bitfields for the first word of a Transfer Desciptor. */
|
152 |
#define OHCI_TD_R (1<<18) |
153 |
#define OHCI_TD_DP_SHIFT 19 |
154 |
#define OHCI_TD_DP_MASK (3<<OHCI_TD_DP_SHIFT) |
155 |
#define OHCI_TD_DI_SHIFT 21 |
156 |
#define OHCI_TD_DI_MASK (7<<OHCI_TD_DI_SHIFT) |
157 |
#define OHCI_TD_T0 (1<<24) |
158 |
#define OHCI_TD_T1 (1<<24) |
159 |
#define OHCI_TD_EC_SHIFT 26 |
160 |
#define OHCI_TD_EC_MASK (3<<OHCI_TD_EC_SHIFT) |
161 |
#define OHCI_TD_CC_SHIFT 28 |
162 |
#define OHCI_TD_CC_MASK (0xf<<OHCI_TD_CC_SHIFT) |
163 |
|
164 |
/* Bitfields for the first word of an Isochronous Transfer Desciptor. */
|
165 |
/* CC & DI - same as in the General Transfer Desciptor */
|
166 |
#define OHCI_TD_SF_SHIFT 0 |
167 |
#define OHCI_TD_SF_MASK (0xffff<<OHCI_TD_SF_SHIFT) |
168 |
#define OHCI_TD_FC_SHIFT 24 |
169 |
#define OHCI_TD_FC_MASK (7<<OHCI_TD_FC_SHIFT) |
170 |
|
171 |
/* Isochronous Transfer Desciptor - Offset / PacketStatusWord */
|
172 |
#define OHCI_TD_PSW_CC_SHIFT 12 |
173 |
#define OHCI_TD_PSW_CC_MASK (0xf<<OHCI_TD_PSW_CC_SHIFT) |
174 |
#define OHCI_TD_PSW_SIZE_SHIFT 0 |
175 |
#define OHCI_TD_PSW_SIZE_MASK (0xfff<<OHCI_TD_PSW_SIZE_SHIFT) |
176 |
|
177 |
#define OHCI_PAGE_MASK 0xfffff000 |
178 |
#define OHCI_OFFSET_MASK 0xfff |
179 |
|
180 |
#define OHCI_DPTR_MASK 0xfffffff0 |
181 |
|
182 |
#define OHCI_BM(val, field) \
|
183 |
(((val) & OHCI_##field##_MASK) >> OHCI_##field##_SHIFT) |
184 |
|
185 |
#define OHCI_SET_BM(val, field, newval) do { \ |
186 |
val &= ~OHCI_##field##_MASK; \ |
187 |
val |= ((newval) << OHCI_##field##_SHIFT) & OHCI_##field##_MASK; \ |
188 |
} while(0) |
189 |
|
190 |
/* endpoint descriptor */
|
191 |
struct ohci_ed {
|
192 |
uint32_t flags; |
193 |
uint32_t tail; |
194 |
uint32_t head; |
195 |
uint32_t next; |
196 |
}; |
197 |
|
198 |
/* General transfer descriptor */
|
199 |
struct ohci_td {
|
200 |
uint32_t flags; |
201 |
uint32_t cbp; |
202 |
uint32_t next; |
203 |
uint32_t be; |
204 |
}; |
205 |
|
206 |
/* Isochronous transfer descriptor */
|
207 |
struct ohci_iso_td {
|
208 |
uint32_t flags; |
209 |
uint32_t bp; |
210 |
uint32_t next; |
211 |
uint32_t be; |
212 |
uint16_t offset[8];
|
213 |
}; |
214 |
|
215 |
#define USB_HZ 12000000 |
216 |
|
217 |
/* OHCI Local stuff */
|
218 |
#define OHCI_CTL_CBSR ((1<<0)|(1<<1)) |
219 |
#define OHCI_CTL_PLE (1<<2) |
220 |
#define OHCI_CTL_IE (1<<3) |
221 |
#define OHCI_CTL_CLE (1<<4) |
222 |
#define OHCI_CTL_BLE (1<<5) |
223 |
#define OHCI_CTL_HCFS ((1<<6)|(1<<7)) |
224 |
#define OHCI_USB_RESET 0x00 |
225 |
#define OHCI_USB_RESUME 0x40 |
226 |
#define OHCI_USB_OPERATIONAL 0x80 |
227 |
#define OHCI_USB_SUSPEND 0xc0 |
228 |
#define OHCI_CTL_IR (1<<8) |
229 |
#define OHCI_CTL_RWC (1<<9) |
230 |
#define OHCI_CTL_RWE (1<<10) |
231 |
|
232 |
#define OHCI_STATUS_HCR (1<<0) |
233 |
#define OHCI_STATUS_CLF (1<<1) |
234 |
#define OHCI_STATUS_BLF (1<<2) |
235 |
#define OHCI_STATUS_OCR (1<<3) |
236 |
#define OHCI_STATUS_SOC ((1<<6)|(1<<7)) |
237 |
|
238 |
#define OHCI_INTR_SO (1<<0) /* Scheduling overrun */ |
239 |
#define OHCI_INTR_WD (1<<1) /* HcDoneHead writeback */ |
240 |
#define OHCI_INTR_SF (1<<2) /* Start of frame */ |
241 |
#define OHCI_INTR_RD (1<<3) /* Resume detect */ |
242 |
#define OHCI_INTR_UE (1<<4) /* Unrecoverable error */ |
243 |
#define OHCI_INTR_FNO (1<<5) /* Frame number overflow */ |
244 |
#define OHCI_INTR_RHSC (1<<6) /* Root hub status change */ |
245 |
#define OHCI_INTR_OC (1<<30) /* Ownership change */ |
246 |
#define OHCI_INTR_MIE (1<<31) /* Master Interrupt Enable */ |
247 |
|
248 |
#define OHCI_HCCA_SIZE 0x100 |
249 |
#define OHCI_HCCA_MASK 0xffffff00 |
250 |
|
251 |
#define OHCI_EDPTR_MASK 0xfffffff0 |
252 |
|
253 |
#define OHCI_FMI_FI 0x00003fff |
254 |
#define OHCI_FMI_FSMPS 0xffff0000 |
255 |
#define OHCI_FMI_FIT 0x80000000 |
256 |
|
257 |
#define OHCI_FR_RT (1<<31) |
258 |
|
259 |
#define OHCI_LS_THRESH 0x628 |
260 |
|
261 |
#define OHCI_RHA_RW_MASK 0x00000000 /* Mask of supported features. */ |
262 |
#define OHCI_RHA_PSM (1<<8) |
263 |
#define OHCI_RHA_NPS (1<<9) |
264 |
#define OHCI_RHA_DT (1<<10) |
265 |
#define OHCI_RHA_OCPM (1<<11) |
266 |
#define OHCI_RHA_NOCP (1<<12) |
267 |
#define OHCI_RHA_POTPGT_MASK 0xff000000 |
268 |
|
269 |
#define OHCI_RHS_LPS (1<<0) |
270 |
#define OHCI_RHS_OCI (1<<1) |
271 |
#define OHCI_RHS_DRWE (1<<15) |
272 |
#define OHCI_RHS_LPSC (1<<16) |
273 |
#define OHCI_RHS_OCIC (1<<17) |
274 |
#define OHCI_RHS_CRWE (1<<31) |
275 |
|
276 |
#define OHCI_PORT_CCS (1<<0) |
277 |
#define OHCI_PORT_PES (1<<1) |
278 |
#define OHCI_PORT_PSS (1<<2) |
279 |
#define OHCI_PORT_POCI (1<<3) |
280 |
#define OHCI_PORT_PRS (1<<4) |
281 |
#define OHCI_PORT_PPS (1<<8) |
282 |
#define OHCI_PORT_LSDA (1<<9) |
283 |
#define OHCI_PORT_CSC (1<<16) |
284 |
#define OHCI_PORT_PESC (1<<17) |
285 |
#define OHCI_PORT_PSSC (1<<18) |
286 |
#define OHCI_PORT_OCIC (1<<19) |
287 |
#define OHCI_PORT_PRSC (1<<20) |
288 |
#define OHCI_PORT_WTC (OHCI_PORT_CSC|OHCI_PORT_PESC|OHCI_PORT_PSSC \
|
289 |
|OHCI_PORT_OCIC|OHCI_PORT_PRSC) |
290 |
|
291 |
#define OHCI_TD_DIR_SETUP 0x0 |
292 |
#define OHCI_TD_DIR_OUT 0x1 |
293 |
#define OHCI_TD_DIR_IN 0x2 |
294 |
#define OHCI_TD_DIR_RESERVED 0x3 |
295 |
|
296 |
#define OHCI_CC_NOERROR 0x0 |
297 |
#define OHCI_CC_CRC 0x1 |
298 |
#define OHCI_CC_BITSTUFFING 0x2 |
299 |
#define OHCI_CC_DATATOGGLEMISMATCH 0x3 |
300 |
#define OHCI_CC_STALL 0x4 |
301 |
#define OHCI_CC_DEVICENOTRESPONDING 0x5 |
302 |
#define OHCI_CC_PIDCHECKFAILURE 0x6 |
303 |
#define OHCI_CC_UNDEXPETEDPID 0x7 |
304 |
#define OHCI_CC_DATAOVERRUN 0x8 |
305 |
#define OHCI_CC_DATAUNDERRUN 0x9 |
306 |
#define OHCI_CC_BUFFEROVERRUN 0xc |
307 |
#define OHCI_CC_BUFFERUNDERRUN 0xd |
308 |
|
309 |
#define OHCI_HRESET_FSBIR (1 << 0) |
310 |
|
311 |
/* Update IRQ levels */
|
312 |
static inline void ohci_intr_update(OHCIState *ohci) |
313 |
{ |
314 |
int level = 0; |
315 |
|
316 |
if ((ohci->intr & OHCI_INTR_MIE) &&
|
317 |
(ohci->intr_status & ohci->intr)) |
318 |
level = 1;
|
319 |
|
320 |
qemu_set_irq(ohci->irq, level); |
321 |
} |
322 |
|
323 |
/* Set an interrupt */
|
324 |
static inline void ohci_set_interrupt(OHCIState *ohci, uint32_t intr) |
325 |
{ |
326 |
ohci->intr_status |= intr; |
327 |
ohci_intr_update(ohci); |
328 |
} |
329 |
|
330 |
/* Attach or detach a device on a root hub port. */
|
331 |
static void ohci_attach(USBPort *port1, USBDevice *dev) |
332 |
{ |
333 |
OHCIState *s = port1->opaque; |
334 |
OHCIPort *port = &s->rhport[port1->index]; |
335 |
uint32_t old_state = port->ctrl; |
336 |
|
337 |
if (dev) {
|
338 |
if (port->port.dev) {
|
339 |
usb_attach(port1, NULL);
|
340 |
} |
341 |
/* set connect status */
|
342 |
port->ctrl |= OHCI_PORT_CCS | OHCI_PORT_CSC; |
343 |
|
344 |
/* update speed */
|
345 |
if (dev->speed == USB_SPEED_LOW)
|
346 |
port->ctrl |= OHCI_PORT_LSDA; |
347 |
else
|
348 |
port->ctrl &= ~OHCI_PORT_LSDA; |
349 |
port->port.dev = dev; |
350 |
|
351 |
/* notify of remote-wakeup */
|
352 |
if ((s->ctl & OHCI_CTL_HCFS) == OHCI_USB_SUSPEND)
|
353 |
ohci_set_interrupt(s, OHCI_INTR_RD); |
354 |
|
355 |
/* send the attach message */
|
356 |
usb_send_msg(dev, USB_MSG_ATTACH); |
357 |
dprintf("usb-ohci: Attached port %d\n", port1->index);
|
358 |
} else {
|
359 |
/* set connect status */
|
360 |
if (port->ctrl & OHCI_PORT_CCS) {
|
361 |
port->ctrl &= ~OHCI_PORT_CCS; |
362 |
port->ctrl |= OHCI_PORT_CSC; |
363 |
} |
364 |
/* disable port */
|
365 |
if (port->ctrl & OHCI_PORT_PES) {
|
366 |
port->ctrl &= ~OHCI_PORT_PES; |
367 |
port->ctrl |= OHCI_PORT_PESC; |
368 |
} |
369 |
dev = port->port.dev; |
370 |
if (dev) {
|
371 |
/* send the detach message */
|
372 |
usb_send_msg(dev, USB_MSG_DETACH); |
373 |
} |
374 |
port->port.dev = NULL;
|
375 |
dprintf("usb-ohci: Detached port %d\n", port1->index);
|
376 |
} |
377 |
|
378 |
if (old_state != port->ctrl)
|
379 |
ohci_set_interrupt(s, OHCI_INTR_RHSC); |
380 |
} |
381 |
|
382 |
/* Reset the controller */
|
383 |
static void ohci_reset(void *opaque) |
384 |
{ |
385 |
OHCIState *ohci = opaque; |
386 |
OHCIPort *port; |
387 |
int i;
|
388 |
|
389 |
ohci_bus_stop(ohci); |
390 |
ohci->ctl = 0;
|
391 |
ohci->old_ctl = 0;
|
392 |
ohci->status = 0;
|
393 |
ohci->intr_status = 0;
|
394 |
ohci->intr = OHCI_INTR_MIE; |
395 |
|
396 |
ohci->hcca = 0;
|
397 |
ohci->ctrl_head = ohci->ctrl_cur = 0;
|
398 |
ohci->bulk_head = ohci->bulk_cur = 0;
|
399 |
ohci->per_cur = 0;
|
400 |
ohci->done = 0;
|
401 |
ohci->done_count = 7;
|
402 |
|
403 |
/* FSMPS is marked TBD in OCHI 1.0, what gives ffs?
|
404 |
* I took the value linux sets ...
|
405 |
*/
|
406 |
ohci->fsmps = 0x2778;
|
407 |
ohci->fi = 0x2edf;
|
408 |
ohci->fit = 0;
|
409 |
ohci->frt = 0;
|
410 |
ohci->frame_number = 0;
|
411 |
ohci->pstart = 0;
|
412 |
ohci->lst = OHCI_LS_THRESH; |
413 |
|
414 |
ohci->rhdesc_a = OHCI_RHA_NPS | ohci->num_ports; |
415 |
ohci->rhdesc_b = 0x0; /* Impl. specific */ |
416 |
ohci->rhstatus = 0;
|
417 |
|
418 |
for (i = 0; i < ohci->num_ports; i++) |
419 |
{ |
420 |
port = &ohci->rhport[i]; |
421 |
port->ctrl = 0;
|
422 |
if (port->port.dev)
|
423 |
ohci_attach(&port->port, port->port.dev); |
424 |
} |
425 |
if (ohci->async_td) {
|
426 |
usb_cancel_packet(&ohci->usb_packet); |
427 |
ohci->async_td = 0;
|
428 |
} |
429 |
dprintf("usb-ohci: Reset %s\n", ohci->name);
|
430 |
} |
431 |
|
432 |
/* Get an array of dwords from main memory */
|
433 |
static inline int get_dwords(OHCIState *ohci, |
434 |
uint32_t addr, uint32_t *buf, int num)
|
435 |
{ |
436 |
int i;
|
437 |
|
438 |
addr += ohci->localmem_base; |
439 |
|
440 |
for (i = 0; i < num; i++, buf++, addr += sizeof(*buf)) { |
441 |
cpu_physical_memory_rw(addr, (uint8_t *)buf, sizeof(*buf), 0); |
442 |
*buf = le32_to_cpu(*buf); |
443 |
} |
444 |
|
445 |
return 1; |
446 |
} |
447 |
|
448 |
/* Put an array of dwords in to main memory */
|
449 |
static inline int put_dwords(OHCIState *ohci, |
450 |
uint32_t addr, uint32_t *buf, int num)
|
451 |
{ |
452 |
int i;
|
453 |
|
454 |
addr += ohci->localmem_base; |
455 |
|
456 |
for (i = 0; i < num; i++, buf++, addr += sizeof(*buf)) { |
457 |
uint32_t tmp = cpu_to_le32(*buf); |
458 |
cpu_physical_memory_rw(addr, (uint8_t *)&tmp, sizeof(tmp), 1); |
459 |
} |
460 |
|
461 |
return 1; |
462 |
} |
463 |
|
464 |
/* Get an array of words from main memory */
|
465 |
static inline int get_words(OHCIState *ohci, |
466 |
uint32_t addr, uint16_t *buf, int num)
|
467 |
{ |
468 |
int i;
|
469 |
|
470 |
addr += ohci->localmem_base; |
471 |
|
472 |
for (i = 0; i < num; i++, buf++, addr += sizeof(*buf)) { |
473 |
cpu_physical_memory_rw(addr, (uint8_t *)buf, sizeof(*buf), 0); |
474 |
*buf = le16_to_cpu(*buf); |
475 |
} |
476 |
|
477 |
return 1; |
478 |
} |
479 |
|
480 |
/* Put an array of words in to main memory */
|
481 |
static inline int put_words(OHCIState *ohci, |
482 |
uint32_t addr, uint16_t *buf, int num)
|
483 |
{ |
484 |
int i;
|
485 |
|
486 |
addr += ohci->localmem_base; |
487 |
|
488 |
for (i = 0; i < num; i++, buf++, addr += sizeof(*buf)) { |
489 |
uint16_t tmp = cpu_to_le16(*buf); |
490 |
cpu_physical_memory_rw(addr, (uint8_t *)&tmp, sizeof(tmp), 1); |
491 |
} |
492 |
|
493 |
return 1; |
494 |
} |
495 |
|
496 |
static inline int ohci_read_ed(OHCIState *ohci, |
497 |
uint32_t addr, struct ohci_ed *ed)
|
498 |
{ |
499 |
return get_dwords(ohci, addr, (uint32_t *)ed, sizeof(*ed) >> 2); |
500 |
} |
501 |
|
502 |
static inline int ohci_read_td(OHCIState *ohci, |
503 |
uint32_t addr, struct ohci_td *td)
|
504 |
{ |
505 |
return get_dwords(ohci, addr, (uint32_t *)td, sizeof(*td) >> 2); |
506 |
} |
507 |
|
508 |
static inline int ohci_read_iso_td(OHCIState *ohci, |
509 |
uint32_t addr, struct ohci_iso_td *td)
|
510 |
{ |
511 |
return (get_dwords(ohci, addr, (uint32_t *)td, 4) && |
512 |
get_words(ohci, addr + 16, td->offset, 8)); |
513 |
} |
514 |
|
515 |
static inline int ohci_read_hcca(OHCIState *ohci, |
516 |
uint32_t addr, struct ohci_hcca *hcca)
|
517 |
{ |
518 |
cpu_physical_memory_rw(addr + ohci->localmem_base, |
519 |
(uint8_t *)hcca, sizeof(*hcca), 0); |
520 |
return 1; |
521 |
} |
522 |
|
523 |
static inline int ohci_put_ed(OHCIState *ohci, |
524 |
uint32_t addr, struct ohci_ed *ed)
|
525 |
{ |
526 |
return put_dwords(ohci, addr, (uint32_t *)ed, sizeof(*ed) >> 2); |
527 |
} |
528 |
|
529 |
static inline int ohci_put_td(OHCIState *ohci, |
530 |
uint32_t addr, struct ohci_td *td)
|
531 |
{ |
532 |
return put_dwords(ohci, addr, (uint32_t *)td, sizeof(*td) >> 2); |
533 |
} |
534 |
|
535 |
static inline int ohci_put_iso_td(OHCIState *ohci, |
536 |
uint32_t addr, struct ohci_iso_td *td)
|
537 |
{ |
538 |
return (put_dwords(ohci, addr, (uint32_t *)td, 4) && |
539 |
put_words(ohci, addr + 16, td->offset, 8)); |
540 |
} |
541 |
|
542 |
static inline int ohci_put_hcca(OHCIState *ohci, |
543 |
uint32_t addr, struct ohci_hcca *hcca)
|
544 |
{ |
545 |
cpu_physical_memory_rw(addr + ohci->localmem_base, |
546 |
(uint8_t *)hcca, sizeof(*hcca), 1); |
547 |
return 1; |
548 |
} |
549 |
|
550 |
/* Read/Write the contents of a TD from/to main memory. */
|
551 |
static void ohci_copy_td(OHCIState *ohci, struct ohci_td *td, |
552 |
uint8_t *buf, int len, int write) |
553 |
{ |
554 |
uint32_t ptr; |
555 |
uint32_t n; |
556 |
|
557 |
ptr = td->cbp; |
558 |
n = 0x1000 - (ptr & 0xfff); |
559 |
if (n > len)
|
560 |
n = len; |
561 |
cpu_physical_memory_rw(ptr + ohci->localmem_base, buf, n, write); |
562 |
if (n == len)
|
563 |
return;
|
564 |
ptr = td->be & ~0xfffu;
|
565 |
buf += n; |
566 |
cpu_physical_memory_rw(ptr + ohci->localmem_base, buf, len - n, write); |
567 |
} |
568 |
|
569 |
/* Read/Write the contents of an ISO TD from/to main memory. */
|
570 |
static void ohci_copy_iso_td(OHCIState *ohci, |
571 |
uint32_t start_addr, uint32_t end_addr, |
572 |
uint8_t *buf, int len, int write) |
573 |
{ |
574 |
uint32_t ptr; |
575 |
uint32_t n; |
576 |
|
577 |
ptr = start_addr; |
578 |
n = 0x1000 - (ptr & 0xfff); |
579 |
if (n > len)
|
580 |
n = len; |
581 |
cpu_physical_memory_rw(ptr + ohci->localmem_base, buf, n, write); |
582 |
if (n == len)
|
583 |
return;
|
584 |
ptr = end_addr & ~0xfffu;
|
585 |
buf += n; |
586 |
cpu_physical_memory_rw(ptr + ohci->localmem_base, buf, len - n, write); |
587 |
} |
588 |
|
589 |
static void ohci_process_lists(OHCIState *ohci, int completion); |
590 |
|
591 |
static void ohci_async_complete_packet(USBPacket *packet, void *opaque) |
592 |
{ |
593 |
OHCIState *ohci = opaque; |
594 |
#ifdef DEBUG_PACKET
|
595 |
dprintf("Async packet complete\n");
|
596 |
#endif
|
597 |
ohci->async_complete = 1;
|
598 |
ohci_process_lists(ohci, 1);
|
599 |
} |
600 |
|
601 |
#define USUB(a, b) ((int16_t)((uint16_t)(a) - (uint16_t)(b)))
|
602 |
|
603 |
static int ohci_service_iso_td(OHCIState *ohci, struct ohci_ed *ed, |
604 |
int completion)
|
605 |
{ |
606 |
int dir;
|
607 |
size_t len = 0;
|
608 |
const char *str = NULL; |
609 |
int pid;
|
610 |
int ret;
|
611 |
int i;
|
612 |
USBDevice *dev; |
613 |
struct ohci_iso_td iso_td;
|
614 |
uint32_t addr; |
615 |
uint16_t starting_frame; |
616 |
int16_t relative_frame_number; |
617 |
int frame_count;
|
618 |
uint32_t start_offset, next_offset, end_offset = 0;
|
619 |
uint32_t start_addr, end_addr; |
620 |
|
621 |
addr = ed->head & OHCI_DPTR_MASK; |
622 |
|
623 |
if (!ohci_read_iso_td(ohci, addr, &iso_td)) {
|
624 |
printf("usb-ohci: ISO_TD read error at %x\n", addr);
|
625 |
return 0; |
626 |
} |
627 |
|
628 |
starting_frame = OHCI_BM(iso_td.flags, TD_SF); |
629 |
frame_count = OHCI_BM(iso_td.flags, TD_FC); |
630 |
relative_frame_number = USUB(ohci->frame_number, starting_frame); |
631 |
|
632 |
#ifdef DEBUG_ISOCH
|
633 |
printf("--- ISO_TD ED head 0x%.8x tailp 0x%.8x\n"
|
634 |
"0x%.8x 0x%.8x 0x%.8x 0x%.8x\n"
|
635 |
"0x%.8x 0x%.8x 0x%.8x 0x%.8x\n"
|
636 |
"0x%.8x 0x%.8x 0x%.8x 0x%.8x\n"
|
637 |
"frame_number 0x%.8x starting_frame 0x%.8x\n"
|
638 |
"frame_count 0x%.8x relative %d\n"
|
639 |
"di 0x%.8x cc 0x%.8x\n",
|
640 |
ed->head & OHCI_DPTR_MASK, ed->tail & OHCI_DPTR_MASK, |
641 |
iso_td.flags, iso_td.bp, iso_td.next, iso_td.be, |
642 |
iso_td.offset[0], iso_td.offset[1], iso_td.offset[2], iso_td.offset[3], |
643 |
iso_td.offset[4], iso_td.offset[5], iso_td.offset[6], iso_td.offset[7], |
644 |
ohci->frame_number, starting_frame, |
645 |
frame_count, relative_frame_number, |
646 |
OHCI_BM(iso_td.flags, TD_DI), OHCI_BM(iso_td.flags, TD_CC)); |
647 |
#endif
|
648 |
|
649 |
if (relative_frame_number < 0) { |
650 |
dprintf("usb-ohci: ISO_TD R=%d < 0\n", relative_frame_number);
|
651 |
return 1; |
652 |
} else if (relative_frame_number > frame_count) { |
653 |
/* ISO TD expired - retire the TD to the Done Queue and continue with
|
654 |
the next ISO TD of the same ED */
|
655 |
dprintf("usb-ohci: ISO_TD R=%d > FC=%d\n", relative_frame_number,
|
656 |
frame_count); |
657 |
OHCI_SET_BM(iso_td.flags, TD_CC, OHCI_CC_DATAOVERRUN); |
658 |
ed->head &= ~OHCI_DPTR_MASK; |
659 |
ed->head |= (iso_td.next & OHCI_DPTR_MASK); |
660 |
iso_td.next = ohci->done; |
661 |
ohci->done = addr; |
662 |
i = OHCI_BM(iso_td.flags, TD_DI); |
663 |
if (i < ohci->done_count)
|
664 |
ohci->done_count = i; |
665 |
ohci_put_iso_td(ohci, addr, &iso_td); |
666 |
return 0; |
667 |
} |
668 |
|
669 |
dir = OHCI_BM(ed->flags, ED_D); |
670 |
switch (dir) {
|
671 |
case OHCI_TD_DIR_IN:
|
672 |
str = "in";
|
673 |
pid = USB_TOKEN_IN; |
674 |
break;
|
675 |
case OHCI_TD_DIR_OUT:
|
676 |
str = "out";
|
677 |
pid = USB_TOKEN_OUT; |
678 |
break;
|
679 |
case OHCI_TD_DIR_SETUP:
|
680 |
str = "setup";
|
681 |
pid = USB_TOKEN_SETUP; |
682 |
break;
|
683 |
default:
|
684 |
printf("usb-ohci: Bad direction %d\n", dir);
|
685 |
return 1; |
686 |
} |
687 |
|
688 |
if (!iso_td.bp || !iso_td.be) {
|
689 |
printf("usb-ohci: ISO_TD bp 0x%.8x be 0x%.8x\n", iso_td.bp, iso_td.be);
|
690 |
return 1; |
691 |
} |
692 |
|
693 |
start_offset = iso_td.offset[relative_frame_number]; |
694 |
next_offset = iso_td.offset[relative_frame_number + 1];
|
695 |
|
696 |
if (!(OHCI_BM(start_offset, TD_PSW_CC) & 0xe) || |
697 |
((relative_frame_number < frame_count) && |
698 |
!(OHCI_BM(next_offset, TD_PSW_CC) & 0xe))) {
|
699 |
printf("usb-ohci: ISO_TD cc != not accessed 0x%.8x 0x%.8x\n",
|
700 |
start_offset, next_offset); |
701 |
return 1; |
702 |
} |
703 |
|
704 |
if ((relative_frame_number < frame_count) && (start_offset > next_offset)) {
|
705 |
printf("usb-ohci: ISO_TD start_offset=0x%.8x > next_offset=0x%.8x\n",
|
706 |
start_offset, next_offset); |
707 |
return 1; |
708 |
} |
709 |
|
710 |
if ((start_offset & 0x1000) == 0) { |
711 |
start_addr = (iso_td.bp & OHCI_PAGE_MASK) | |
712 |
(start_offset & OHCI_OFFSET_MASK); |
713 |
} else {
|
714 |
start_addr = (iso_td.be & OHCI_PAGE_MASK) | |
715 |
(start_offset & OHCI_OFFSET_MASK); |
716 |
} |
717 |
|
718 |
if (relative_frame_number < frame_count) {
|
719 |
end_offset = next_offset - 1;
|
720 |
if ((end_offset & 0x1000) == 0) { |
721 |
end_addr = (iso_td.bp & OHCI_PAGE_MASK) | |
722 |
(end_offset & OHCI_OFFSET_MASK); |
723 |
} else {
|
724 |
end_addr = (iso_td.be & OHCI_PAGE_MASK) | |
725 |
(end_offset & OHCI_OFFSET_MASK); |
726 |
} |
727 |
} else {
|
728 |
/* Last packet in the ISO TD */
|
729 |
end_addr = iso_td.be; |
730 |
} |
731 |
|
732 |
if ((start_addr & OHCI_PAGE_MASK) != (end_addr & OHCI_PAGE_MASK)) {
|
733 |
len = (end_addr & OHCI_OFFSET_MASK) + 0x1001
|
734 |
- (start_addr & OHCI_OFFSET_MASK); |
735 |
} else {
|
736 |
len = end_addr - start_addr + 1;
|
737 |
} |
738 |
|
739 |
if (len && dir != OHCI_TD_DIR_IN) {
|
740 |
ohci_copy_iso_td(ohci, start_addr, end_addr, ohci->usb_buf, len, 0);
|
741 |
} |
742 |
|
743 |
if (completion) {
|
744 |
ret = ohci->usb_packet.len; |
745 |
} else {
|
746 |
ret = USB_RET_NODEV; |
747 |
for (i = 0; i < ohci->num_ports; i++) { |
748 |
dev = ohci->rhport[i].port.dev; |
749 |
if ((ohci->rhport[i].ctrl & OHCI_PORT_PES) == 0) |
750 |
continue;
|
751 |
ohci->usb_packet.pid = pid; |
752 |
ohci->usb_packet.devaddr = OHCI_BM(ed->flags, ED_FA); |
753 |
ohci->usb_packet.devep = OHCI_BM(ed->flags, ED_EN); |
754 |
ohci->usb_packet.data = ohci->usb_buf; |
755 |
ohci->usb_packet.len = len; |
756 |
ohci->usb_packet.complete_cb = ohci_async_complete_packet; |
757 |
ohci->usb_packet.complete_opaque = ohci; |
758 |
ret = dev->info->handle_packet(dev, &ohci->usb_packet); |
759 |
if (ret != USB_RET_NODEV)
|
760 |
break;
|
761 |
} |
762 |
|
763 |
if (ret == USB_RET_ASYNC) {
|
764 |
return 1; |
765 |
} |
766 |
} |
767 |
|
768 |
#ifdef DEBUG_ISOCH
|
769 |
printf("so 0x%.8x eo 0x%.8x\nsa 0x%.8x ea 0x%.8x\ndir %s len %zu ret %d\n",
|
770 |
start_offset, end_offset, start_addr, end_addr, str, len, ret); |
771 |
#endif
|
772 |
|
773 |
/* Writeback */
|
774 |
if (dir == OHCI_TD_DIR_IN && ret >= 0 && ret <= len) { |
775 |
/* IN transfer succeeded */
|
776 |
ohci_copy_iso_td(ohci, start_addr, end_addr, ohci->usb_buf, ret, 1);
|
777 |
OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_CC, |
778 |
OHCI_CC_NOERROR); |
779 |
OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_SIZE, ret); |
780 |
} else if (dir == OHCI_TD_DIR_OUT && ret == len) { |
781 |
/* OUT transfer succeeded */
|
782 |
OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_CC, |
783 |
OHCI_CC_NOERROR); |
784 |
OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_SIZE, 0);
|
785 |
} else {
|
786 |
if (ret > (ssize_t) len) {
|
787 |
printf("usb-ohci: DataOverrun %d > %zu\n", ret, len);
|
788 |
OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_CC, |
789 |
OHCI_CC_DATAOVERRUN); |
790 |
OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_SIZE, |
791 |
len); |
792 |
} else if (ret >= 0) { |
793 |
printf("usb-ohci: DataUnderrun %d\n", ret);
|
794 |
OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_CC, |
795 |
OHCI_CC_DATAUNDERRUN); |
796 |
} else {
|
797 |
switch (ret) {
|
798 |
case USB_RET_NODEV:
|
799 |
OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_CC, |
800 |
OHCI_CC_DEVICENOTRESPONDING); |
801 |
OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_SIZE, |
802 |
0);
|
803 |
break;
|
804 |
case USB_RET_NAK:
|
805 |
case USB_RET_STALL:
|
806 |
printf("usb-ohci: got NAK/STALL %d\n", ret);
|
807 |
OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_CC, |
808 |
OHCI_CC_STALL); |
809 |
OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_SIZE, |
810 |
0);
|
811 |
break;
|
812 |
default:
|
813 |
printf("usb-ohci: Bad device response %d\n", ret);
|
814 |
OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_CC, |
815 |
OHCI_CC_UNDEXPETEDPID); |
816 |
break;
|
817 |
} |
818 |
} |
819 |
} |
820 |
|
821 |
if (relative_frame_number == frame_count) {
|
822 |
/* Last data packet of ISO TD - retire the TD to the Done Queue */
|
823 |
OHCI_SET_BM(iso_td.flags, TD_CC, OHCI_CC_NOERROR); |
824 |
ed->head &= ~OHCI_DPTR_MASK; |
825 |
ed->head |= (iso_td.next & OHCI_DPTR_MASK); |
826 |
iso_td.next = ohci->done; |
827 |
ohci->done = addr; |
828 |
i = OHCI_BM(iso_td.flags, TD_DI); |
829 |
if (i < ohci->done_count)
|
830 |
ohci->done_count = i; |
831 |
} |
832 |
ohci_put_iso_td(ohci, addr, &iso_td); |
833 |
return 1; |
834 |
} |
835 |
|
836 |
/* Service a transport descriptor.
|
837 |
Returns nonzero to terminate processing of this endpoint. */
|
838 |
|
839 |
static int ohci_service_td(OHCIState *ohci, struct ohci_ed *ed) |
840 |
{ |
841 |
int dir;
|
842 |
size_t len = 0;
|
843 |
const char *str = NULL; |
844 |
int pid;
|
845 |
int ret;
|
846 |
int i;
|
847 |
USBDevice *dev; |
848 |
struct ohci_td td;
|
849 |
uint32_t addr; |
850 |
int flag_r;
|
851 |
int completion;
|
852 |
|
853 |
addr = ed->head & OHCI_DPTR_MASK; |
854 |
/* See if this TD has already been submitted to the device. */
|
855 |
completion = (addr == ohci->async_td); |
856 |
if (completion && !ohci->async_complete) {
|
857 |
#ifdef DEBUG_PACKET
|
858 |
dprintf("Skipping async TD\n");
|
859 |
#endif
|
860 |
return 1; |
861 |
} |
862 |
if (!ohci_read_td(ohci, addr, &td)) {
|
863 |
fprintf(stderr, "usb-ohci: TD read error at %x\n", addr);
|
864 |
return 0; |
865 |
} |
866 |
|
867 |
dir = OHCI_BM(ed->flags, ED_D); |
868 |
switch (dir) {
|
869 |
case OHCI_TD_DIR_OUT:
|
870 |
case OHCI_TD_DIR_IN:
|
871 |
/* Same value. */
|
872 |
break;
|
873 |
default:
|
874 |
dir = OHCI_BM(td.flags, TD_DP); |
875 |
break;
|
876 |
} |
877 |
|
878 |
switch (dir) {
|
879 |
case OHCI_TD_DIR_IN:
|
880 |
str = "in";
|
881 |
pid = USB_TOKEN_IN; |
882 |
break;
|
883 |
case OHCI_TD_DIR_OUT:
|
884 |
str = "out";
|
885 |
pid = USB_TOKEN_OUT; |
886 |
break;
|
887 |
case OHCI_TD_DIR_SETUP:
|
888 |
str = "setup";
|
889 |
pid = USB_TOKEN_SETUP; |
890 |
break;
|
891 |
default:
|
892 |
fprintf(stderr, "usb-ohci: Bad direction\n");
|
893 |
return 1; |
894 |
} |
895 |
if (td.cbp && td.be) {
|
896 |
if ((td.cbp & 0xfffff000) != (td.be & 0xfffff000)) { |
897 |
len = (td.be & 0xfff) + 0x1001 - (td.cbp & 0xfff); |
898 |
} else {
|
899 |
len = (td.be - td.cbp) + 1;
|
900 |
} |
901 |
|
902 |
if (len && dir != OHCI_TD_DIR_IN && !completion) {
|
903 |
ohci_copy_td(ohci, &td, ohci->usb_buf, len, 0);
|
904 |
} |
905 |
} |
906 |
|
907 |
flag_r = (td.flags & OHCI_TD_R) != 0;
|
908 |
#ifdef DEBUG_PACKET
|
909 |
dprintf(" TD @ 0x%.8x %" PRId64 " bytes %s r=%d cbp=0x%.8x be=0x%.8x\n", |
910 |
addr, len, str, flag_r, td.cbp, td.be); |
911 |
|
912 |
if (len > 0 && dir != OHCI_TD_DIR_IN) { |
913 |
dprintf(" data:");
|
914 |
for (i = 0; i < len; i++) |
915 |
printf(" %.2x", ohci->usb_buf[i]);
|
916 |
dprintf("\n");
|
917 |
} |
918 |
#endif
|
919 |
if (completion) {
|
920 |
ret = ohci->usb_packet.len; |
921 |
ohci->async_td = 0;
|
922 |
ohci->async_complete = 0;
|
923 |
} else {
|
924 |
ret = USB_RET_NODEV; |
925 |
for (i = 0; i < ohci->num_ports; i++) { |
926 |
dev = ohci->rhport[i].port.dev; |
927 |
if ((ohci->rhport[i].ctrl & OHCI_PORT_PES) == 0) |
928 |
continue;
|
929 |
|
930 |
if (ohci->async_td) {
|
931 |
/* ??? The hardware should allow one active packet per
|
932 |
endpoint. We only allow one active packet per controller.
|
933 |
This should be sufficient as long as devices respond in a
|
934 |
timely manner.
|
935 |
*/
|
936 |
#ifdef DEBUG_PACKET
|
937 |
dprintf("Too many pending packets\n");
|
938 |
#endif
|
939 |
return 1; |
940 |
} |
941 |
ohci->usb_packet.pid = pid; |
942 |
ohci->usb_packet.devaddr = OHCI_BM(ed->flags, ED_FA); |
943 |
ohci->usb_packet.devep = OHCI_BM(ed->flags, ED_EN); |
944 |
ohci->usb_packet.data = ohci->usb_buf; |
945 |
ohci->usb_packet.len = len; |
946 |
ohci->usb_packet.complete_cb = ohci_async_complete_packet; |
947 |
ohci->usb_packet.complete_opaque = ohci; |
948 |
ret = dev->info->handle_packet(dev, &ohci->usb_packet); |
949 |
if (ret != USB_RET_NODEV)
|
950 |
break;
|
951 |
} |
952 |
#ifdef DEBUG_PACKET
|
953 |
dprintf("ret=%d\n", ret);
|
954 |
#endif
|
955 |
if (ret == USB_RET_ASYNC) {
|
956 |
ohci->async_td = addr; |
957 |
return 1; |
958 |
} |
959 |
} |
960 |
if (ret >= 0) { |
961 |
if (dir == OHCI_TD_DIR_IN) {
|
962 |
ohci_copy_td(ohci, &td, ohci->usb_buf, ret, 1);
|
963 |
#ifdef DEBUG_PACKET
|
964 |
dprintf(" data:");
|
965 |
for (i = 0; i < ret; i++) |
966 |
printf(" %.2x", ohci->usb_buf[i]);
|
967 |
dprintf("\n");
|
968 |
#endif
|
969 |
} else {
|
970 |
ret = len; |
971 |
} |
972 |
} |
973 |
|
974 |
/* Writeback */
|
975 |
if (ret == len || (dir == OHCI_TD_DIR_IN && ret >= 0 && flag_r)) { |
976 |
/* Transmission succeeded. */
|
977 |
if (ret == len) {
|
978 |
td.cbp = 0;
|
979 |
} else {
|
980 |
td.cbp += ret; |
981 |
if ((td.cbp & 0xfff) + ret > 0xfff) { |
982 |
td.cbp &= 0xfff;
|
983 |
td.cbp |= td.be & ~0xfff;
|
984 |
} |
985 |
} |
986 |
td.flags |= OHCI_TD_T1; |
987 |
td.flags ^= OHCI_TD_T0; |
988 |
OHCI_SET_BM(td.flags, TD_CC, OHCI_CC_NOERROR); |
989 |
OHCI_SET_BM(td.flags, TD_EC, 0);
|
990 |
|
991 |
ed->head &= ~OHCI_ED_C; |
992 |
if (td.flags & OHCI_TD_T0)
|
993 |
ed->head |= OHCI_ED_C; |
994 |
} else {
|
995 |
if (ret >= 0) { |
996 |
dprintf("usb-ohci: Underrun\n");
|
997 |
OHCI_SET_BM(td.flags, TD_CC, OHCI_CC_DATAUNDERRUN); |
998 |
} else {
|
999 |
switch (ret) {
|
1000 |
case USB_RET_NODEV:
|
1001 |
OHCI_SET_BM(td.flags, TD_CC, OHCI_CC_DEVICENOTRESPONDING); |
1002 |
case USB_RET_NAK:
|
1003 |
dprintf("usb-ohci: got NAK\n");
|
1004 |
return 1; |
1005 |
case USB_RET_STALL:
|
1006 |
dprintf("usb-ohci: got STALL\n");
|
1007 |
OHCI_SET_BM(td.flags, TD_CC, OHCI_CC_STALL); |
1008 |
break;
|
1009 |
case USB_RET_BABBLE:
|
1010 |
dprintf("usb-ohci: got BABBLE\n");
|
1011 |
OHCI_SET_BM(td.flags, TD_CC, OHCI_CC_DATAOVERRUN); |
1012 |
break;
|
1013 |
default:
|
1014 |
fprintf(stderr, "usb-ohci: Bad device response %d\n", ret);
|
1015 |
OHCI_SET_BM(td.flags, TD_CC, OHCI_CC_UNDEXPETEDPID); |
1016 |
OHCI_SET_BM(td.flags, TD_EC, 3);
|
1017 |
break;
|
1018 |
} |
1019 |
} |
1020 |
ed->head |= OHCI_ED_H; |
1021 |
} |
1022 |
|
1023 |
/* Retire this TD */
|
1024 |
ed->head &= ~OHCI_DPTR_MASK; |
1025 |
ed->head |= td.next & OHCI_DPTR_MASK; |
1026 |
td.next = ohci->done; |
1027 |
ohci->done = addr; |
1028 |
i = OHCI_BM(td.flags, TD_DI); |
1029 |
if (i < ohci->done_count)
|
1030 |
ohci->done_count = i; |
1031 |
ohci_put_td(ohci, addr, &td); |
1032 |
return OHCI_BM(td.flags, TD_CC) != OHCI_CC_NOERROR;
|
1033 |
} |
1034 |
|
1035 |
/* Service an endpoint list. Returns nonzero if active TD were found. */
|
1036 |
static int ohci_service_ed_list(OHCIState *ohci, uint32_t head, int completion) |
1037 |
{ |
1038 |
struct ohci_ed ed;
|
1039 |
uint32_t next_ed; |
1040 |
uint32_t cur; |
1041 |
int active;
|
1042 |
|
1043 |
active = 0;
|
1044 |
|
1045 |
if (head == 0) |
1046 |
return 0; |
1047 |
|
1048 |
for (cur = head; cur; cur = next_ed) {
|
1049 |
if (!ohci_read_ed(ohci, cur, &ed)) {
|
1050 |
fprintf(stderr, "usb-ohci: ED read error at %x\n", cur);
|
1051 |
return 0; |
1052 |
} |
1053 |
|
1054 |
next_ed = ed.next & OHCI_DPTR_MASK; |
1055 |
|
1056 |
if ((ed.head & OHCI_ED_H) || (ed.flags & OHCI_ED_K)) {
|
1057 |
uint32_t addr; |
1058 |
/* Cancel pending packets for ED that have been paused. */
|
1059 |
addr = ed.head & OHCI_DPTR_MASK; |
1060 |
if (ohci->async_td && addr == ohci->async_td) {
|
1061 |
usb_cancel_packet(&ohci->usb_packet); |
1062 |
ohci->async_td = 0;
|
1063 |
} |
1064 |
continue;
|
1065 |
} |
1066 |
|
1067 |
while ((ed.head & OHCI_DPTR_MASK) != ed.tail) {
|
1068 |
#ifdef DEBUG_PACKET
|
1069 |
dprintf("ED @ 0x%.8x fa=%u en=%u d=%u s=%u k=%u f=%u mps=%u "
|
1070 |
"h=%u c=%u\n head=0x%.8x tailp=0x%.8x next=0x%.8x\n", cur,
|
1071 |
OHCI_BM(ed.flags, ED_FA), OHCI_BM(ed.flags, ED_EN), |
1072 |
OHCI_BM(ed.flags, ED_D), (ed.flags & OHCI_ED_S)!= 0,
|
1073 |
(ed.flags & OHCI_ED_K) != 0, (ed.flags & OHCI_ED_F) != 0, |
1074 |
OHCI_BM(ed.flags, ED_MPS), (ed.head & OHCI_ED_H) != 0,
|
1075 |
(ed.head & OHCI_ED_C) != 0, ed.head & OHCI_DPTR_MASK,
|
1076 |
ed.tail & OHCI_DPTR_MASK, ed.next & OHCI_DPTR_MASK); |
1077 |
#endif
|
1078 |
active = 1;
|
1079 |
|
1080 |
if ((ed.flags & OHCI_ED_F) == 0) { |
1081 |
if (ohci_service_td(ohci, &ed))
|
1082 |
break;
|
1083 |
} else {
|
1084 |
/* Handle isochronous endpoints */
|
1085 |
if (ohci_service_iso_td(ohci, &ed, completion))
|
1086 |
break;
|
1087 |
} |
1088 |
} |
1089 |
|
1090 |
ohci_put_ed(ohci, cur, &ed); |
1091 |
} |
1092 |
|
1093 |
return active;
|
1094 |
} |
1095 |
|
1096 |
/* Generate a SOF event, and set a timer for EOF */
|
1097 |
static void ohci_sof(OHCIState *ohci) |
1098 |
{ |
1099 |
ohci->sof_time = qemu_get_clock(vm_clock); |
1100 |
qemu_mod_timer(ohci->eof_timer, ohci->sof_time + usb_frame_time); |
1101 |
ohci_set_interrupt(ohci, OHCI_INTR_SF); |
1102 |
} |
1103 |
|
1104 |
/* Process Control and Bulk lists. */
|
1105 |
static void ohci_process_lists(OHCIState *ohci, int completion) |
1106 |
{ |
1107 |
if ((ohci->ctl & OHCI_CTL_CLE) && (ohci->status & OHCI_STATUS_CLF)) {
|
1108 |
if (ohci->ctrl_cur && ohci->ctrl_cur != ohci->ctrl_head)
|
1109 |
dprintf("usb-ohci: head %x, cur %x\n",
|
1110 |
ohci->ctrl_head, ohci->ctrl_cur); |
1111 |
if (!ohci_service_ed_list(ohci, ohci->ctrl_head, completion)) {
|
1112 |
ohci->ctrl_cur = 0;
|
1113 |
ohci->status &= ~OHCI_STATUS_CLF; |
1114 |
} |
1115 |
} |
1116 |
|
1117 |
if ((ohci->ctl & OHCI_CTL_BLE) && (ohci->status & OHCI_STATUS_BLF)) {
|
1118 |
if (!ohci_service_ed_list(ohci, ohci->bulk_head, completion)) {
|
1119 |
ohci->bulk_cur = 0;
|
1120 |
ohci->status &= ~OHCI_STATUS_BLF; |
1121 |
} |
1122 |
} |
1123 |
} |
1124 |
|
1125 |
/* Do frame processing on frame boundary */
|
1126 |
static void ohci_frame_boundary(void *opaque) |
1127 |
{ |
1128 |
OHCIState *ohci = opaque; |
1129 |
struct ohci_hcca hcca;
|
1130 |
|
1131 |
ohci_read_hcca(ohci, ohci->hcca, &hcca); |
1132 |
|
1133 |
/* Process all the lists at the end of the frame */
|
1134 |
if (ohci->ctl & OHCI_CTL_PLE) {
|
1135 |
int n;
|
1136 |
|
1137 |
n = ohci->frame_number & 0x1f;
|
1138 |
ohci_service_ed_list(ohci, le32_to_cpu(hcca.intr[n]), 0);
|
1139 |
} |
1140 |
|
1141 |
/* Cancel all pending packets if either of the lists has been disabled. */
|
1142 |
if (ohci->async_td &&
|
1143 |
ohci->old_ctl & (~ohci->ctl) & (OHCI_CTL_BLE | OHCI_CTL_CLE)) { |
1144 |
usb_cancel_packet(&ohci->usb_packet); |
1145 |
ohci->async_td = 0;
|
1146 |
} |
1147 |
ohci->old_ctl = ohci->ctl; |
1148 |
ohci_process_lists(ohci, 0);
|
1149 |
|
1150 |
/* Frame boundary, so do EOF stuf here */
|
1151 |
ohci->frt = ohci->fit; |
1152 |
|
1153 |
/* Increment frame number and take care of endianness. */
|
1154 |
ohci->frame_number = (ohci->frame_number + 1) & 0xffff; |
1155 |
hcca.frame = cpu_to_le16(ohci->frame_number); |
1156 |
|
1157 |
if (ohci->done_count == 0 && !(ohci->intr_status & OHCI_INTR_WD)) { |
1158 |
if (!ohci->done)
|
1159 |
abort(); |
1160 |
if (ohci->intr & ohci->intr_status)
|
1161 |
ohci->done |= 1;
|
1162 |
hcca.done = cpu_to_le32(ohci->done); |
1163 |
ohci->done = 0;
|
1164 |
ohci->done_count = 7;
|
1165 |
ohci_set_interrupt(ohci, OHCI_INTR_WD); |
1166 |
} |
1167 |
|
1168 |
if (ohci->done_count != 7 && ohci->done_count != 0) |
1169 |
ohci->done_count--; |
1170 |
|
1171 |
/* Do SOF stuff here */
|
1172 |
ohci_sof(ohci); |
1173 |
|
1174 |
/* Writeback HCCA */
|
1175 |
ohci_put_hcca(ohci, ohci->hcca, &hcca); |
1176 |
} |
1177 |
|
1178 |
/* Start sending SOF tokens across the USB bus, lists are processed in
|
1179 |
* next frame
|
1180 |
*/
|
1181 |
static int ohci_bus_start(OHCIState *ohci) |
1182 |
{ |
1183 |
ohci->eof_timer = qemu_new_timer(vm_clock, |
1184 |
ohci_frame_boundary, |
1185 |
ohci); |
1186 |
|
1187 |
if (ohci->eof_timer == NULL) { |
1188 |
fprintf(stderr, "usb-ohci: %s: qemu_new_timer failed\n", ohci->name);
|
1189 |
/* TODO: Signal unrecoverable error */
|
1190 |
return 0; |
1191 |
} |
1192 |
|
1193 |
dprintf("usb-ohci: %s: USB Operational\n", ohci->name);
|
1194 |
|
1195 |
ohci_sof(ohci); |
1196 |
|
1197 |
return 1; |
1198 |
} |
1199 |
|
1200 |
/* Stop sending SOF tokens on the bus */
|
1201 |
static void ohci_bus_stop(OHCIState *ohci) |
1202 |
{ |
1203 |
if (ohci->eof_timer)
|
1204 |
qemu_del_timer(ohci->eof_timer); |
1205 |
ohci->eof_timer = NULL;
|
1206 |
} |
1207 |
|
1208 |
/* Sets a flag in a port status register but only set it if the port is
|
1209 |
* connected, if not set ConnectStatusChange flag. If flag is enabled
|
1210 |
* return 1.
|
1211 |
*/
|
1212 |
static int ohci_port_set_if_connected(OHCIState *ohci, int i, uint32_t val) |
1213 |
{ |
1214 |
int ret = 1; |
1215 |
|
1216 |
/* writing a 0 has no effect */
|
1217 |
if (val == 0) |
1218 |
return 0; |
1219 |
|
1220 |
/* If CurrentConnectStatus is cleared we set
|
1221 |
* ConnectStatusChange
|
1222 |
*/
|
1223 |
if (!(ohci->rhport[i].ctrl & OHCI_PORT_CCS)) {
|
1224 |
ohci->rhport[i].ctrl |= OHCI_PORT_CSC; |
1225 |
if (ohci->rhstatus & OHCI_RHS_DRWE) {
|
1226 |
/* TODO: CSC is a wakeup event */
|
1227 |
} |
1228 |
return 0; |
1229 |
} |
1230 |
|
1231 |
if (ohci->rhport[i].ctrl & val)
|
1232 |
ret = 0;
|
1233 |
|
1234 |
/* set the bit */
|
1235 |
ohci->rhport[i].ctrl |= val; |
1236 |
|
1237 |
return ret;
|
1238 |
} |
1239 |
|
1240 |
/* Set the frame interval - frame interval toggle is manipulated by the hcd only */
|
1241 |
static void ohci_set_frame_interval(OHCIState *ohci, uint16_t val) |
1242 |
{ |
1243 |
val &= OHCI_FMI_FI; |
1244 |
|
1245 |
if (val != ohci->fi) {
|
1246 |
dprintf("usb-ohci: %s: FrameInterval = 0x%x (%u)\n",
|
1247 |
ohci->name, ohci->fi, ohci->fi); |
1248 |
} |
1249 |
|
1250 |
ohci->fi = val; |
1251 |
} |
1252 |
|
1253 |
static void ohci_port_power(OHCIState *ohci, int i, int p) |
1254 |
{ |
1255 |
if (p) {
|
1256 |
ohci->rhport[i].ctrl |= OHCI_PORT_PPS; |
1257 |
} else {
|
1258 |
ohci->rhport[i].ctrl &= ~(OHCI_PORT_PPS| |
1259 |
OHCI_PORT_CCS| |
1260 |
OHCI_PORT_PSS| |
1261 |
OHCI_PORT_PRS); |
1262 |
} |
1263 |
} |
1264 |
|
1265 |
/* Set HcControlRegister */
|
1266 |
static void ohci_set_ctl(OHCIState *ohci, uint32_t val) |
1267 |
{ |
1268 |
uint32_t old_state; |
1269 |
uint32_t new_state; |
1270 |
|
1271 |
old_state = ohci->ctl & OHCI_CTL_HCFS; |
1272 |
ohci->ctl = val; |
1273 |
new_state = ohci->ctl & OHCI_CTL_HCFS; |
1274 |
|
1275 |
/* no state change */
|
1276 |
if (old_state == new_state)
|
1277 |
return;
|
1278 |
|
1279 |
switch (new_state) {
|
1280 |
case OHCI_USB_OPERATIONAL:
|
1281 |
ohci_bus_start(ohci); |
1282 |
break;
|
1283 |
case OHCI_USB_SUSPEND:
|
1284 |
ohci_bus_stop(ohci); |
1285 |
dprintf("usb-ohci: %s: USB Suspended\n", ohci->name);
|
1286 |
break;
|
1287 |
case OHCI_USB_RESUME:
|
1288 |
dprintf("usb-ohci: %s: USB Resume\n", ohci->name);
|
1289 |
break;
|
1290 |
case OHCI_USB_RESET:
|
1291 |
ohci_reset(ohci); |
1292 |
dprintf("usb-ohci: %s: USB Reset\n", ohci->name);
|
1293 |
break;
|
1294 |
} |
1295 |
} |
1296 |
|
1297 |
static uint32_t ohci_get_frame_remaining(OHCIState *ohci)
|
1298 |
{ |
1299 |
uint16_t fr; |
1300 |
int64_t tks; |
1301 |
|
1302 |
if ((ohci->ctl & OHCI_CTL_HCFS) != OHCI_USB_OPERATIONAL)
|
1303 |
return (ohci->frt << 31); |
1304 |
|
1305 |
/* Being in USB operational state guarnatees sof_time was
|
1306 |
* set already.
|
1307 |
*/
|
1308 |
tks = qemu_get_clock(vm_clock) - ohci->sof_time; |
1309 |
|
1310 |
/* avoid muldiv if possible */
|
1311 |
if (tks >= usb_frame_time)
|
1312 |
return (ohci->frt << 31); |
1313 |
|
1314 |
tks = muldiv64(1, tks, usb_bit_time);
|
1315 |
fr = (uint16_t)(ohci->fi - tks); |
1316 |
|
1317 |
return (ohci->frt << 31) | fr; |
1318 |
} |
1319 |
|
1320 |
|
1321 |
/* Set root hub status */
|
1322 |
static void ohci_set_hub_status(OHCIState *ohci, uint32_t val) |
1323 |
{ |
1324 |
uint32_t old_state; |
1325 |
|
1326 |
old_state = ohci->rhstatus; |
1327 |
|
1328 |
/* write 1 to clear OCIC */
|
1329 |
if (val & OHCI_RHS_OCIC)
|
1330 |
ohci->rhstatus &= ~OHCI_RHS_OCIC; |
1331 |
|
1332 |
if (val & OHCI_RHS_LPS) {
|
1333 |
int i;
|
1334 |
|
1335 |
for (i = 0; i < ohci->num_ports; i++) |
1336 |
ohci_port_power(ohci, i, 0);
|
1337 |
dprintf("usb-ohci: powered down all ports\n");
|
1338 |
} |
1339 |
|
1340 |
if (val & OHCI_RHS_LPSC) {
|
1341 |
int i;
|
1342 |
|
1343 |
for (i = 0; i < ohci->num_ports; i++) |
1344 |
ohci_port_power(ohci, i, 1);
|
1345 |
dprintf("usb-ohci: powered up all ports\n");
|
1346 |
} |
1347 |
|
1348 |
if (val & OHCI_RHS_DRWE)
|
1349 |
ohci->rhstatus |= OHCI_RHS_DRWE; |
1350 |
|
1351 |
if (val & OHCI_RHS_CRWE)
|
1352 |
ohci->rhstatus &= ~OHCI_RHS_DRWE; |
1353 |
|
1354 |
if (old_state != ohci->rhstatus)
|
1355 |
ohci_set_interrupt(ohci, OHCI_INTR_RHSC); |
1356 |
} |
1357 |
|
1358 |
/* Set root hub port status */
|
1359 |
static void ohci_port_set_status(OHCIState *ohci, int portnum, uint32_t val) |
1360 |
{ |
1361 |
uint32_t old_state; |
1362 |
OHCIPort *port; |
1363 |
|
1364 |
port = &ohci->rhport[portnum]; |
1365 |
old_state = port->ctrl; |
1366 |
|
1367 |
/* Write to clear CSC, PESC, PSSC, OCIC, PRSC */
|
1368 |
if (val & OHCI_PORT_WTC)
|
1369 |
port->ctrl &= ~(val & OHCI_PORT_WTC); |
1370 |
|
1371 |
if (val & OHCI_PORT_CCS)
|
1372 |
port->ctrl &= ~OHCI_PORT_PES; |
1373 |
|
1374 |
ohci_port_set_if_connected(ohci, portnum, val & OHCI_PORT_PES); |
1375 |
|
1376 |
if (ohci_port_set_if_connected(ohci, portnum, val & OHCI_PORT_PSS))
|
1377 |
dprintf("usb-ohci: port %d: SUSPEND\n", portnum);
|
1378 |
|
1379 |
if (ohci_port_set_if_connected(ohci, portnum, val & OHCI_PORT_PRS)) {
|
1380 |
dprintf("usb-ohci: port %d: RESET\n", portnum);
|
1381 |
usb_send_msg(port->port.dev, USB_MSG_RESET); |
1382 |
port->ctrl &= ~OHCI_PORT_PRS; |
1383 |
/* ??? Should this also set OHCI_PORT_PESC. */
|
1384 |
port->ctrl |= OHCI_PORT_PES | OHCI_PORT_PRSC; |
1385 |
} |
1386 |
|
1387 |
/* Invert order here to ensure in ambiguous case, device is
|
1388 |
* powered up...
|
1389 |
*/
|
1390 |
if (val & OHCI_PORT_LSDA)
|
1391 |
ohci_port_power(ohci, portnum, 0);
|
1392 |
if (val & OHCI_PORT_PPS)
|
1393 |
ohci_port_power(ohci, portnum, 1);
|
1394 |
|
1395 |
if (old_state != port->ctrl)
|
1396 |
ohci_set_interrupt(ohci, OHCI_INTR_RHSC); |
1397 |
|
1398 |
return;
|
1399 |
} |
1400 |
|
1401 |
static uint32_t ohci_mem_read(void *ptr, target_phys_addr_t addr) |
1402 |
{ |
1403 |
OHCIState *ohci = ptr; |
1404 |
uint32_t retval; |
1405 |
|
1406 |
/* Only aligned reads are allowed on OHCI */
|
1407 |
if (addr & 3) { |
1408 |
fprintf(stderr, "usb-ohci: Mis-aligned read\n");
|
1409 |
return 0xffffffff; |
1410 |
} else if (addr >= 0x54 && addr < 0x54 + ohci->num_ports * 4) { |
1411 |
/* HcRhPortStatus */
|
1412 |
retval = ohci->rhport[(addr - 0x54) >> 2].ctrl | OHCI_PORT_PPS; |
1413 |
} else {
|
1414 |
switch (addr >> 2) { |
1415 |
case 0: /* HcRevision */ |
1416 |
retval = 0x10;
|
1417 |
break;
|
1418 |
|
1419 |
case 1: /* HcControl */ |
1420 |
retval = ohci->ctl; |
1421 |
break;
|
1422 |
|
1423 |
case 2: /* HcCommandStatus */ |
1424 |
retval = ohci->status; |
1425 |
break;
|
1426 |
|
1427 |
case 3: /* HcInterruptStatus */ |
1428 |
retval = ohci->intr_status; |
1429 |
break;
|
1430 |
|
1431 |
case 4: /* HcInterruptEnable */ |
1432 |
case 5: /* HcInterruptDisable */ |
1433 |
retval = ohci->intr; |
1434 |
break;
|
1435 |
|
1436 |
case 6: /* HcHCCA */ |
1437 |
retval = ohci->hcca; |
1438 |
break;
|
1439 |
|
1440 |
case 7: /* HcPeriodCurrentED */ |
1441 |
retval = ohci->per_cur; |
1442 |
break;
|
1443 |
|
1444 |
case 8: /* HcControlHeadED */ |
1445 |
retval = ohci->ctrl_head; |
1446 |
break;
|
1447 |
|
1448 |
case 9: /* HcControlCurrentED */ |
1449 |
retval = ohci->ctrl_cur; |
1450 |
break;
|
1451 |
|
1452 |
case 10: /* HcBulkHeadED */ |
1453 |
retval = ohci->bulk_head; |
1454 |
break;
|
1455 |
|
1456 |
case 11: /* HcBulkCurrentED */ |
1457 |
retval = ohci->bulk_cur; |
1458 |
break;
|
1459 |
|
1460 |
case 12: /* HcDoneHead */ |
1461 |
retval = ohci->done; |
1462 |
break;
|
1463 |
|
1464 |
case 13: /* HcFmInterretval */ |
1465 |
retval = (ohci->fit << 31) | (ohci->fsmps << 16) | (ohci->fi); |
1466 |
break;
|
1467 |
|
1468 |
case 14: /* HcFmRemaining */ |
1469 |
retval = ohci_get_frame_remaining(ohci); |
1470 |
break;
|
1471 |
|
1472 |
case 15: /* HcFmNumber */ |
1473 |
retval = ohci->frame_number; |
1474 |
break;
|
1475 |
|
1476 |
case 16: /* HcPeriodicStart */ |
1477 |
retval = ohci->pstart; |
1478 |
break;
|
1479 |
|
1480 |
case 17: /* HcLSThreshold */ |
1481 |
retval = ohci->lst; |
1482 |
break;
|
1483 |
|
1484 |
case 18: /* HcRhDescriptorA */ |
1485 |
retval = ohci->rhdesc_a; |
1486 |
break;
|
1487 |
|
1488 |
case 19: /* HcRhDescriptorB */ |
1489 |
retval = ohci->rhdesc_b; |
1490 |
break;
|
1491 |
|
1492 |
case 20: /* HcRhStatus */ |
1493 |
retval = ohci->rhstatus; |
1494 |
break;
|
1495 |
|
1496 |
/* PXA27x specific registers */
|
1497 |
case 24: /* HcStatus */ |
1498 |
retval = ohci->hstatus & ohci->hmask; |
1499 |
break;
|
1500 |
|
1501 |
case 25: /* HcHReset */ |
1502 |
retval = ohci->hreset; |
1503 |
break;
|
1504 |
|
1505 |
case 26: /* HcHInterruptEnable */ |
1506 |
retval = ohci->hmask; |
1507 |
break;
|
1508 |
|
1509 |
case 27: /* HcHInterruptTest */ |
1510 |
retval = ohci->htest; |
1511 |
break;
|
1512 |
|
1513 |
default:
|
1514 |
fprintf(stderr, "ohci_read: Bad offset %x\n", (int)addr); |
1515 |
retval = 0xffffffff;
|
1516 |
} |
1517 |
} |
1518 |
|
1519 |
#ifdef TARGET_WORDS_BIGENDIAN
|
1520 |
retval = bswap32(retval); |
1521 |
#endif
|
1522 |
return retval;
|
1523 |
} |
1524 |
|
1525 |
static void ohci_mem_write(void *ptr, target_phys_addr_t addr, uint32_t val) |
1526 |
{ |
1527 |
OHCIState *ohci = ptr; |
1528 |
|
1529 |
#ifdef TARGET_WORDS_BIGENDIAN
|
1530 |
val = bswap32(val); |
1531 |
#endif
|
1532 |
|
1533 |
/* Only aligned reads are allowed on OHCI */
|
1534 |
if (addr & 3) { |
1535 |
fprintf(stderr, "usb-ohci: Mis-aligned write\n");
|
1536 |
return;
|
1537 |
} |
1538 |
|
1539 |
if (addr >= 0x54 && addr < 0x54 + ohci->num_ports * 4) { |
1540 |
/* HcRhPortStatus */
|
1541 |
ohci_port_set_status(ohci, (addr - 0x54) >> 2, val); |
1542 |
return;
|
1543 |
} |
1544 |
|
1545 |
switch (addr >> 2) { |
1546 |
case 1: /* HcControl */ |
1547 |
ohci_set_ctl(ohci, val); |
1548 |
break;
|
1549 |
|
1550 |
case 2: /* HcCommandStatus */ |
1551 |
/* SOC is read-only */
|
1552 |
val = (val & ~OHCI_STATUS_SOC); |
1553 |
|
1554 |
/* Bits written as '0' remain unchanged in the register */
|
1555 |
ohci->status |= val; |
1556 |
|
1557 |
if (ohci->status & OHCI_STATUS_HCR)
|
1558 |
ohci_reset(ohci); |
1559 |
break;
|
1560 |
|
1561 |
case 3: /* HcInterruptStatus */ |
1562 |
ohci->intr_status &= ~val; |
1563 |
ohci_intr_update(ohci); |
1564 |
break;
|
1565 |
|
1566 |
case 4: /* HcInterruptEnable */ |
1567 |
ohci->intr |= val; |
1568 |
ohci_intr_update(ohci); |
1569 |
break;
|
1570 |
|
1571 |
case 5: /* HcInterruptDisable */ |
1572 |
ohci->intr &= ~val; |
1573 |
ohci_intr_update(ohci); |
1574 |
break;
|
1575 |
|
1576 |
case 6: /* HcHCCA */ |
1577 |
ohci->hcca = val & OHCI_HCCA_MASK; |
1578 |
break;
|
1579 |
|
1580 |
case 8: /* HcControlHeadED */ |
1581 |
ohci->ctrl_head = val & OHCI_EDPTR_MASK; |
1582 |
break;
|
1583 |
|
1584 |
case 9: /* HcControlCurrentED */ |
1585 |
ohci->ctrl_cur = val & OHCI_EDPTR_MASK; |
1586 |
break;
|
1587 |
|
1588 |
case 10: /* HcBulkHeadED */ |
1589 |
ohci->bulk_head = val & OHCI_EDPTR_MASK; |
1590 |
break;
|
1591 |
|
1592 |
case 11: /* HcBulkCurrentED */ |
1593 |
ohci->bulk_cur = val & OHCI_EDPTR_MASK; |
1594 |
break;
|
1595 |
|
1596 |
case 13: /* HcFmInterval */ |
1597 |
ohci->fsmps = (val & OHCI_FMI_FSMPS) >> 16;
|
1598 |
ohci->fit = (val & OHCI_FMI_FIT) >> 31;
|
1599 |
ohci_set_frame_interval(ohci, val); |
1600 |
break;
|
1601 |
|
1602 |
case 15: /* HcFmNumber */ |
1603 |
break;
|
1604 |
|
1605 |
case 16: /* HcPeriodicStart */ |
1606 |
ohci->pstart = val & 0xffff;
|
1607 |
break;
|
1608 |
|
1609 |
case 17: /* HcLSThreshold */ |
1610 |
ohci->lst = val & 0xffff;
|
1611 |
break;
|
1612 |
|
1613 |
case 18: /* HcRhDescriptorA */ |
1614 |
ohci->rhdesc_a &= ~OHCI_RHA_RW_MASK; |
1615 |
ohci->rhdesc_a |= val & OHCI_RHA_RW_MASK; |
1616 |
break;
|
1617 |
|
1618 |
case 19: /* HcRhDescriptorB */ |
1619 |
break;
|
1620 |
|
1621 |
case 20: /* HcRhStatus */ |
1622 |
ohci_set_hub_status(ohci, val); |
1623 |
break;
|
1624 |
|
1625 |
/* PXA27x specific registers */
|
1626 |
case 24: /* HcStatus */ |
1627 |
ohci->hstatus &= ~(val & ohci->hmask); |
1628 |
|
1629 |
case 25: /* HcHReset */ |
1630 |
ohci->hreset = val & ~OHCI_HRESET_FSBIR; |
1631 |
if (val & OHCI_HRESET_FSBIR)
|
1632 |
ohci_reset(ohci); |
1633 |
break;
|
1634 |
|
1635 |
case 26: /* HcHInterruptEnable */ |
1636 |
ohci->hmask = val; |
1637 |
break;
|
1638 |
|
1639 |
case 27: /* HcHInterruptTest */ |
1640 |
ohci->htest = val; |
1641 |
break;
|
1642 |
|
1643 |
default:
|
1644 |
fprintf(stderr, "ohci_write: Bad offset %x\n", (int)addr); |
1645 |
break;
|
1646 |
} |
1647 |
} |
1648 |
|
1649 |
/* Only dword reads are defined on OHCI register space */
|
1650 |
static CPUReadMemoryFunc * const ohci_readfn[3]={ |
1651 |
ohci_mem_read, |
1652 |
ohci_mem_read, |
1653 |
ohci_mem_read |
1654 |
}; |
1655 |
|
1656 |
/* Only dword writes are defined on OHCI register space */
|
1657 |
static CPUWriteMemoryFunc * const ohci_writefn[3]={ |
1658 |
ohci_mem_write, |
1659 |
ohci_mem_write, |
1660 |
ohci_mem_write |
1661 |
}; |
1662 |
|
1663 |
static void usb_ohci_init(OHCIState *ohci, DeviceState *dev, |
1664 |
int num_ports, int devfn, |
1665 |
qemu_irq irq, enum ohci_type type,
|
1666 |
const char *name, uint32_t localmem_base) |
1667 |
{ |
1668 |
int i;
|
1669 |
|
1670 |
if (usb_frame_time == 0) { |
1671 |
#ifdef OHCI_TIME_WARP
|
1672 |
usb_frame_time = ticks_per_sec; |
1673 |
usb_bit_time = muldiv64(1, ticks_per_sec, USB_HZ/1000); |
1674 |
#else
|
1675 |
usb_frame_time = muldiv64(1, ticks_per_sec, 1000); |
1676 |
if (ticks_per_sec >= USB_HZ) {
|
1677 |
usb_bit_time = muldiv64(1, ticks_per_sec, USB_HZ);
|
1678 |
} else {
|
1679 |
usb_bit_time = 1;
|
1680 |
} |
1681 |
#endif
|
1682 |
dprintf("usb-ohci: usb_bit_time=%" PRId64 " usb_frame_time=%" PRId64 "\n", |
1683 |
usb_frame_time, usb_bit_time); |
1684 |
} |
1685 |
|
1686 |
ohci->mem = cpu_register_io_memory(ohci_readfn, ohci_writefn, ohci); |
1687 |
ohci->localmem_base = localmem_base; |
1688 |
ohci->name = name; |
1689 |
|
1690 |
ohci->irq = irq; |
1691 |
ohci->type = type; |
1692 |
|
1693 |
ohci->bus = usb_bus_new(dev); |
1694 |
ohci->num_ports = num_ports; |
1695 |
for (i = 0; i < num_ports; i++) { |
1696 |
usb_register_port(ohci->bus, &ohci->rhport[i].port, ohci, i, ohci_attach); |
1697 |
} |
1698 |
|
1699 |
ohci->async_td = 0;
|
1700 |
qemu_register_reset(ohci_reset, ohci); |
1701 |
ohci_reset(ohci); |
1702 |
} |
1703 |
|
1704 |
typedef struct { |
1705 |
PCIDevice pci_dev; |
1706 |
OHCIState state; |
1707 |
} OHCIPCIState; |
1708 |
|
1709 |
static void ohci_mapfunc(PCIDevice *pci_dev, int i, |
1710 |
uint32_t addr, uint32_t size, int type)
|
1711 |
{ |
1712 |
OHCIPCIState *ohci = DO_UPCAST(OHCIPCIState, pci_dev, pci_dev); |
1713 |
cpu_register_physical_memory(addr, size, ohci->state.mem); |
1714 |
} |
1715 |
|
1716 |
static int usb_ohci_initfn_pci(struct PCIDevice *dev) |
1717 |
{ |
1718 |
OHCIPCIState *ohci = DO_UPCAST(OHCIPCIState, pci_dev, dev); |
1719 |
int num_ports = 3; |
1720 |
|
1721 |
pci_config_set_vendor_id(ohci->pci_dev.config, PCI_VENDOR_ID_APPLE); |
1722 |
pci_config_set_device_id(ohci->pci_dev.config, |
1723 |
PCI_DEVICE_ID_APPLE_IPID_USB); |
1724 |
ohci->pci_dev.config[0x09] = 0x10; /* OHCI */ |
1725 |
pci_config_set_class(ohci->pci_dev.config, PCI_CLASS_SERIAL_USB); |
1726 |
ohci->pci_dev.config[0x3d] = 0x01; /* interrupt pin 1 */ |
1727 |
|
1728 |
usb_ohci_init(&ohci->state, &dev->qdev, num_ports, |
1729 |
ohci->pci_dev.devfn, ohci->pci_dev.irq[0],
|
1730 |
OHCI_TYPE_PCI, ohci->pci_dev.name, 0);
|
1731 |
|
1732 |
pci_register_bar((struct PCIDevice *)ohci, 0, 256, |
1733 |
PCI_ADDRESS_SPACE_MEM, ohci_mapfunc); |
1734 |
return 0; |
1735 |
} |
1736 |
|
1737 |
void usb_ohci_init_pci(struct PCIBus *bus, int devfn) |
1738 |
{ |
1739 |
pci_create_simple(bus, devfn, "OHCI USB PCI");
|
1740 |
} |
1741 |
|
1742 |
void usb_ohci_init_pxa(target_phys_addr_t base, int num_ports, int devfn, |
1743 |
qemu_irq irq) |
1744 |
{ |
1745 |
OHCIState *ohci = (OHCIState *)qemu_mallocz(sizeof(OHCIState));
|
1746 |
|
1747 |
usb_ohci_init(ohci, NULL /* FIXME */, num_ports, devfn, irq, |
1748 |
OHCI_TYPE_PXA, "OHCI USB", 0); |
1749 |
|
1750 |
cpu_register_physical_memory(base, 0x1000, ohci->mem);
|
1751 |
} |
1752 |
|
1753 |
void usb_ohci_init_sm501(uint32_t mmio_base, uint32_t localmem_base,
|
1754 |
int num_ports, int devfn, qemu_irq irq) |
1755 |
{ |
1756 |
OHCIState *ohci = (OHCIState *)qemu_mallocz(sizeof(OHCIState));
|
1757 |
|
1758 |
usb_ohci_init(ohci, NULL /* FIXME */, num_ports, devfn, irq, |
1759 |
OHCI_TYPE_SM501, "OHCI USB", localmem_base);
|
1760 |
|
1761 |
cpu_register_physical_memory(mmio_base, 0x1000, ohci->mem);
|
1762 |
} |
1763 |
|
1764 |
static PCIDeviceInfo ohci_info = {
|
1765 |
.qdev.name = "OHCI USB PCI",
|
1766 |
.qdev.alias = "pci-ohci",
|
1767 |
.qdev.desc = "Apple USB Controller",
|
1768 |
.qdev.size = sizeof(OHCIPCIState),
|
1769 |
.init = usb_ohci_initfn_pci, |
1770 |
}; |
1771 |
|
1772 |
static void ohci_register(void) |
1773 |
{ |
1774 |
pci_qdev_register(&ohci_info); |
1775 |
} |
1776 |
device_init(ohci_register); |