Archipelago » qemu

/*

 *  CRIS emulation for qemu: main translation routines.

 *

 *  Copyright (c) 2008 AXIS Communications AB

 *  Written by Edgar E. Iglesias.

 *

 * This library is free software; you can redistribute it and/or

 * modify it under the terms of the GNU Lesser General Public

 * License as published by the Free Software Foundation; either

 * version 2 of the License, or (at your option) any later version.

 *

 * This library is distributed in the hope that it will be useful,

 * but WITHOUT ANY WARRANTY; without even the implied warranty of

 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU

 * Lesser General Public License for more details.

 *

 * You should have received a copy of the GNU Lesser General Public

 * License along with this library; if not, see <http://www.gnu.org/licenses/>.

 */

/*

 * FIXME:

 * The condition code translation is in need of attention.

 */

#include "cpu.h"

#include "disas/disas.h"

#include "tcg-op.h"

#include "helper.h"

#include "mmu.h"

#include "crisv32-decode.h"

#define GEN_HELPER 1

#include "helper.h"

#define DISAS_CRIS 0

#if DISAS_CRIS

#  define LOG_DIS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__)

#else

#  define LOG_DIS(...) do { } while (0)

#endif

#define D(x)

#define BUG() (gen_BUG(dc, __FILE__, __LINE__))

#define BUG_ON(x) ({if (x) BUG();})

#define DISAS_SWI 5

/* Used by the decoder.  */

#define EXTRACT_FIELD(src, start, end) \

            (((src) >> start) & ((1 << (end - start + 1)) - 1))

#define CC_MASK_NZ 0xc

#define CC_MASK_NZV 0xe

#define CC_MASK_NZVC 0xf

#define CC_MASK_RNZV 0x10e

static TCGv_ptr cpu_env;

static TCGv cpu_R[16];

static TCGv cpu_PR[16];

static TCGv cc_x;

static TCGv cc_src;

static TCGv cc_dest;

static TCGv cc_result;

static TCGv cc_op;

static TCGv cc_size;

static TCGv cc_mask;

static TCGv env_btaken;

static TCGv env_btarget;

static TCGv env_pc;

#include "exec/gen-icount.h"

/* This is the state at translation time.  */

typedef struct DisasContext {

    CPUCRISState *env;

    target_ulong pc, ppc;

    /* Decoder.  */

        unsigned int (*decoder)(CPUCRISState *env, struct DisasContext *dc);

    uint32_t ir;

    uint32_t opcode;

    unsigned int op1;

    unsigned int op2;

    unsigned int zsize, zzsize;

    unsigned int mode;

    unsigned int postinc;

    unsigned int size;

    unsigned int src;

    unsigned int dst;

    unsigned int cond;

    int update_cc;

    int cc_op;

    int cc_size;

    uint32_t cc_mask;

    int cc_size_uptodate; /* -1 invalid or last written value.  */

    int cc_x_uptodate;  /* 1 - ccs, 2 - known | X_FLAG. 0 not uptodate.  */

    int flags_uptodate; /* Wether or not $ccs is uptodate.  */

    int flagx_known; /* Wether or not flags_x has the x flag known at

                translation time.  */

    int flags_x;

    int clear_x; /* Clear x after this insn?  */

    int clear_prefix; /* Clear prefix after this insn?  */

    int clear_locked_irq; /* Clear the irq lockout.  */

    int cpustate_changed;

    unsigned int tb_flags; /* tb dependent flags.  */

    int is_jmp;

#define JMP_NOJMP     0

#define JMP_DIRECT    1

#define JMP_DIRECT_CC 2

#define JMP_INDIRECT  3

    int jmp; /* 0=nojmp, 1=direct, 2=indirect.  */

    uint32_t jmp_pc;

    int delayed_branch;

    struct TranslationBlock *tb;

    int singlestep_enabled;

} DisasContext;

static void gen_BUG(DisasContext *dc, const char *file, int line)

{

    printf("BUG: pc=%x %s %d\n", dc->pc, file, line);

    qemu_log("BUG: pc=%x %s %d\n", dc->pc, file, line);

    cpu_abort(dc->env, "%s:%d\n", file, line);

}

static const char *regnames[] =

{

    "$r0", "$r1", "$r2", "$r3",

    "$r4", "$r5", "$r6", "$r7",

    "$r8", "$r9", "$r10", "$r11",

    "$r12", "$r13", "$sp", "$acr",

};

static const char *pregnames[] =

{

    "$bz", "$vr", "$pid", "$srs",

    "$wz", "$exs", "$eda", "$mof",

    "$dz", "$ebp", "$erp", "$srp",

    "$nrp", "$ccs", "$usp", "$spc",

};

/* We need this table to handle preg-moves with implicit width.  */

static int preg_sizes[] = {

    1, /* bz.  */

    1, /* vr.  */

    4, /* pid.  */

    1, /* srs.  */

    2, /* wz.  */

    4, 4, 4,

    4, 4, 4, 4,

    4, 4, 4, 4,

};

#define t_gen_mov_TN_env(tn, member) \

 _t_gen_mov_TN_env((tn), offsetof(CPUCRISState, member))

#define t_gen_mov_env_TN(member, tn) \

 _t_gen_mov_env_TN(offsetof(CPUCRISState, member), (tn))

static inline void t_gen_mov_TN_reg(TCGv tn, int r)

{

    if (r < 0 || r > 15) {

        fprintf(stderr, "wrong register read $r%d\n", r);

    }

    tcg_gen_mov_tl(tn, cpu_R[r]);

}

static inline void t_gen_mov_reg_TN(int r, TCGv tn)

{

    if (r < 0 || r > 15) {

        fprintf(stderr, "wrong register write $r%d\n", r);

    }

    tcg_gen_mov_tl(cpu_R[r], tn);

}

static inline void _t_gen_mov_TN_env(TCGv tn, int offset)

{

    if (offset > sizeof(CPUCRISState)) {

        fprintf(stderr, "wrong load from env from off=%d\n", offset);

    }

    tcg_gen_ld_tl(tn, cpu_env, offset);

}

static inline void _t_gen_mov_env_TN(int offset, TCGv tn)

{

    if (offset > sizeof(CPUCRISState)) {

        fprintf(stderr, "wrong store to env at off=%d\n", offset);

    }

    tcg_gen_st_tl(tn, cpu_env, offset);

}

static inline void t_gen_mov_TN_preg(TCGv tn, int r)

{

    if (r < 0 || r > 15) {

        fprintf(stderr, "wrong register read $p%d\n", r);

    }

    if (r == PR_BZ || r == PR_WZ || r == PR_DZ) {

        tcg_gen_mov_tl(tn, tcg_const_tl(0));

    } else if (r == PR_VR) {

        tcg_gen_mov_tl(tn, tcg_const_tl(32));

    } else {

        tcg_gen_mov_tl(tn, cpu_PR[r]);

    }

}

static inline void t_gen_mov_preg_TN(DisasContext *dc, int r, TCGv tn)

{

    if (r < 0 || r > 15) {

        fprintf(stderr, "wrong register write $p%d\n", r);

    }

    if (r == PR_BZ || r == PR_WZ || r == PR_DZ) {

        return;

    } else if (r == PR_SRS) {

        tcg_gen_andi_tl(cpu_PR[r], tn, 3);

    } else {

        if (r == PR_PID) {

            gen_helper_tlb_flush_pid(cpu_env, tn);

        }

        if (dc->tb_flags & S_FLAG && r == PR_SPC) {

            gen_helper_spc_write(cpu_env, tn);

        } else if (r == PR_CCS) {

            dc->cpustate_changed = 1;

        }

        tcg_gen_mov_tl(cpu_PR[r], tn);

    }

}

/* Sign extend at translation time.  */

static int sign_extend(unsigned int val, unsigned int width)

{

    int sval;

    /* LSL.  */

    val <<= 31 - width;

    sval = val;

    /* ASR.  */

    sval >>= 31 - width;

    return sval;

}

static int cris_fetch(CPUCRISState *env, DisasContext *dc, uint32_t addr,

              unsigned int size, unsigned int sign)

{

    int r;

    switch (size) {

    case 4:

    {

        r = cpu_ldl_code(env, addr);

        break;

    }

    case 2:

    {

        if (sign) {

            r = cpu_ldsw_code(env, addr);

        } else {

            r = cpu_lduw_code(env, addr);

        }

        break;

    }

    case 1:

    {

        if (sign) {

            r = cpu_ldsb_code(env, addr);

        } else {

            r = cpu_ldub_code(env, addr);

        }

        break;

    }

    default:

        cpu_abort(dc->env, "Invalid fetch size %d\n", size);

        break;

    }

    return r;

}

static void cris_lock_irq(DisasContext *dc)

{

    dc->clear_locked_irq = 0;

    t_gen_mov_env_TN(locked_irq, tcg_const_tl(1));

}

static inline void t_gen_raise_exception(uint32_t index)

{

        TCGv_i32 tmp = tcg_const_i32(index);

        gen_helper_raise_exception(cpu_env, tmp);

        tcg_temp_free_i32(tmp);

}

static void t_gen_lsl(TCGv d, TCGv a, TCGv b)

{

    TCGv t0, t_31;

    t0 = tcg_temp_new();

    t_31 = tcg_const_tl(31);

    tcg_gen_shl_tl(d, a, b);

    tcg_gen_sub_tl(t0, t_31, b);

    tcg_gen_sar_tl(t0, t0, t_31);

    tcg_gen_and_tl(t0, t0, d);

    tcg_gen_xor_tl(d, d, t0);

    tcg_temp_free(t0);

    tcg_temp_free(t_31);

}

static void t_gen_lsr(TCGv d, TCGv a, TCGv b)

{

    TCGv t0, t_31;

    t0 = tcg_temp_new();

    t_31 = tcg_temp_new();

    tcg_gen_shr_tl(d, a, b);

    tcg_gen_movi_tl(t_31, 31);

    tcg_gen_sub_tl(t0, t_31, b);

    tcg_gen_sar_tl(t0, t0, t_31);

    tcg_gen_and_tl(t0, t0, d);

    tcg_gen_xor_tl(d, d, t0);

    tcg_temp_free(t0);

    tcg_temp_free(t_31);

}

static void t_gen_asr(TCGv d, TCGv a, TCGv b)

{

    TCGv t0, t_31;

    t0 = tcg_temp_new();

    t_31 = tcg_temp_new();

    tcg_gen_sar_tl(d, a, b);

    tcg_gen_movi_tl(t_31, 31);

    tcg_gen_sub_tl(t0, t_31, b);

    tcg_gen_sar_tl(t0, t0, t_31);

    tcg_gen_or_tl(d, d, t0);

    tcg_temp_free(t0);

    tcg_temp_free(t_31);

}

static void t_gen_cris_dstep(TCGv d, TCGv a, TCGv b)

{

    int l1;

    l1 = gen_new_label();

    /*

     * d <<= 1

     * if (d >= s)

     *    d -= s;

     */

    tcg_gen_shli_tl(d, a, 1);

    tcg_gen_brcond_tl(TCG_COND_LTU, d, b, l1);

    tcg_gen_sub_tl(d, d, b);

    gen_set_label(l1);

}

static void t_gen_cris_mstep(TCGv d, TCGv a, TCGv b, TCGv ccs)

{

    TCGv t;

    /*

     * d <<= 1

     * if (n)

     *    d += s;

     */

    t = tcg_temp_new();

    tcg_gen_shli_tl(d, a, 1);

    tcg_gen_shli_tl(t, ccs, 31 - 3);

    tcg_gen_sari_tl(t, t, 31);

    tcg_gen_and_tl(t, t, b);

    tcg_gen_add_tl(d, d, t);

    tcg_temp_free(t);

}

/* Extended arithmetics on CRIS.  */

static inline void t_gen_add_flag(TCGv d, int flag)

{

    TCGv c;

    c = tcg_temp_new();

    t_gen_mov_TN_preg(c, PR_CCS);

    /* Propagate carry into d.  */

    tcg_gen_andi_tl(c, c, 1 << flag);

    if (flag) {

        tcg_gen_shri_tl(c, c, flag);

    }

    tcg_gen_add_tl(d, d, c);

    tcg_temp_free(c);

}

static inline void t_gen_addx_carry(DisasContext *dc, TCGv d)

{

    if (dc->flagx_known) {

        if (dc->flags_x) {

            TCGv c;

            c = tcg_temp_new();

            t_gen_mov_TN_preg(c, PR_CCS);

            /* C flag is already at bit 0.  */

            tcg_gen_andi_tl(c, c, C_FLAG);

            tcg_gen_add_tl(d, d, c);

            tcg_temp_free(c);

        }

    } else {

        TCGv x, c;

        x = tcg_temp_new();

        c = tcg_temp_new();

        t_gen_mov_TN_preg(x, PR_CCS);

        tcg_gen_mov_tl(c, x);

        /* Propagate carry into d if X is set. Branch free.  */

        tcg_gen_andi_tl(c, c, C_FLAG);

        tcg_gen_andi_tl(x, x, X_FLAG);

        tcg_gen_shri_tl(x, x, 4);

        tcg_gen_and_tl(x, x, c);

        tcg_gen_add_tl(d, d, x);

        tcg_temp_free(x);

        tcg_temp_free(c);

    }

}

static inline void t_gen_subx_carry(DisasContext *dc, TCGv d)

{

    if (dc->flagx_known) {

        if (dc->flags_x) {

            TCGv c;

            c = tcg_temp_new();

            t_gen_mov_TN_preg(c, PR_CCS);

            /* C flag is already at bit 0.  */

            tcg_gen_andi_tl(c, c, C_FLAG);

            tcg_gen_sub_tl(d, d, c);

            tcg_temp_free(c);

        }

    } else {

        TCGv x, c;

        x = tcg_temp_new();

        c = tcg_temp_new();

        t_gen_mov_TN_preg(x, PR_CCS);

        tcg_gen_mov_tl(c, x);

        /* Propagate carry into d if X is set. Branch free.  */

        tcg_gen_andi_tl(c, c, C_FLAG);

        tcg_gen_andi_tl(x, x, X_FLAG);

        tcg_gen_shri_tl(x, x, 4);

        tcg_gen_and_tl(x, x, c);

        tcg_gen_sub_tl(d, d, x);

        tcg_temp_free(x);

        tcg_temp_free(c);

    }

}

/* Swap the two bytes within each half word of the s operand.

   T0 = ((T0 << 8) & 0xff00ff00) | ((T0 >> 8) & 0x00ff00ff)  */

static inline void t_gen_swapb(TCGv d, TCGv s)

{

    TCGv t, org_s;

    t = tcg_temp_new();

    org_s = tcg_temp_new();

    /* d and s may refer to the same object.  */

    tcg_gen_mov_tl(org_s, s);

    tcg_gen_shli_tl(t, org_s, 8);

    tcg_gen_andi_tl(d, t, 0xff00ff00);

    tcg_gen_shri_tl(t, org_s, 8);

    tcg_gen_andi_tl(t, t, 0x00ff00ff);

    tcg_gen_or_tl(d, d, t);

    tcg_temp_free(t);

    tcg_temp_free(org_s);

}

/* Swap the halfwords of the s operand.  */

static inline void t_gen_swapw(TCGv d, TCGv s)

{

    TCGv t;

    /* d and s refer the same object.  */

    t = tcg_temp_new();

    tcg_gen_mov_tl(t, s);

    tcg_gen_shli_tl(d, t, 16);

    tcg_gen_shri_tl(t, t, 16);

    tcg_gen_or_tl(d, d, t);

    tcg_temp_free(t);

}

/* Reverse the within each byte.

   T0 = (((T0 << 7) & 0x80808080) |

   ((T0 << 5) & 0x40404040) |

   ((T0 << 3) & 0x20202020) |

   ((T0 << 1) & 0x10101010) |

   ((T0 >> 1) & 0x08080808) |

   ((T0 >> 3) & 0x04040404) |

   ((T0 >> 5) & 0x02020202) |

   ((T0 >> 7) & 0x01010101));

 */

static inline void t_gen_swapr(TCGv d, TCGv s)

{

    struct {

        int shift; /* LSL when positive, LSR when negative.  */

        uint32_t mask;

    } bitrev[] = {

        {7, 0x80808080},

        {5, 0x40404040},

        {3, 0x20202020},

        {1, 0x10101010},

        {-1, 0x08080808},

        {-3, 0x04040404},

        {-5, 0x02020202},

        {-7, 0x01010101}

    };

    int i;

    TCGv t, org_s;

    /* d and s refer the same object.  */

    t = tcg_temp_new();

    org_s = tcg_temp_new();

    tcg_gen_mov_tl(org_s, s);

    tcg_gen_shli_tl(t, org_s,  bitrev[0].shift);

    tcg_gen_andi_tl(d, t,  bitrev[0].mask);

    for (i = 1; i < ARRAY_SIZE(bitrev); i++) {

        if (bitrev[i].shift >= 0) {

            tcg_gen_shli_tl(t, org_s,  bitrev[i].shift);

        } else {

            tcg_gen_shri_tl(t, org_s,  -bitrev[i].shift);

        }

        tcg_gen_andi_tl(t, t,  bitrev[i].mask);

        tcg_gen_or_tl(d, d, t);

    }

    tcg_temp_free(t);

    tcg_temp_free(org_s);

}

static void t_gen_cc_jmp(TCGv pc_true, TCGv pc_false)

{

    int l1;

    l1 = gen_new_label();

    /* Conditional jmp.  */

    tcg_gen_mov_tl(env_pc, pc_false);

    tcg_gen_brcondi_tl(TCG_COND_EQ, env_btaken, 0, l1);

    tcg_gen_mov_tl(env_pc, pc_true);

    gen_set_label(l1);

}

static void gen_goto_tb(DisasContext *dc, int n, target_ulong dest)

{

    TranslationBlock *tb;

    tb = dc->tb;

    if ((tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK)) {

        tcg_gen_goto_tb(n);

        tcg_gen_movi_tl(env_pc, dest);

                tcg_gen_exit_tb((tcg_target_long)tb + n);

    } else {

        tcg_gen_movi_tl(env_pc, dest);

        tcg_gen_exit_tb(0);

    }

}

static inline void cris_clear_x_flag(DisasContext *dc)

{

    if (dc->flagx_known && dc->flags_x) {

        dc->flags_uptodate = 0;

    }

    dc->flagx_known = 1;

    dc->flags_x = 0;

}

static void cris_flush_cc_state(DisasContext *dc)

{

    if (dc->cc_size_uptodate != dc->cc_size) {

        tcg_gen_movi_tl(cc_size, dc->cc_size);

        dc->cc_size_uptodate = dc->cc_size;

    }

    tcg_gen_movi_tl(cc_op, dc->cc_op);

    tcg_gen_movi_tl(cc_mask, dc->cc_mask);

}

static void cris_evaluate_flags(DisasContext *dc)

{

    if (dc->flags_uptodate) {

        return;

    }

    cris_flush_cc_state(dc);

    switch (dc->cc_op) {

    case CC_OP_MCP:

        gen_helper_evaluate_flags_mcp(cpu_PR[PR_CCS], cpu_env,

                cpu_PR[PR_CCS], cc_src,

                cc_dest, cc_result);

        break;

    case CC_OP_MULS:

        gen_helper_evaluate_flags_muls(cpu_PR[PR_CCS], cpu_env,

                cpu_PR[PR_CCS], cc_result,

                cpu_PR[PR_MOF]);

        break;

    case CC_OP_MULU:

        gen_helper_evaluate_flags_mulu(cpu_PR[PR_CCS], cpu_env,

                cpu_PR[PR_CCS], cc_result,

                cpu_PR[PR_MOF]);

        break;

    case CC_OP_MOVE:

    case CC_OP_AND:

    case CC_OP_OR:

    case CC_OP_XOR:

    case CC_OP_ASR:

    case CC_OP_LSR:

    case CC_OP_LSL:

        switch (dc->cc_size) {

        case 4:

            gen_helper_evaluate_flags_move_4(cpu_PR[PR_CCS],

                    cpu_env, cpu_PR[PR_CCS], cc_result);

            break;

        case 2:

            gen_helper_evaluate_flags_move_2(cpu_PR[PR_CCS],

                    cpu_env, cpu_PR[PR_CCS], cc_result);

            break;

        default:

            gen_helper_evaluate_flags(cpu_env);

            break;

        }

        break;

    case CC_OP_FLAGS:

        /* live.  */

        break;

    case CC_OP_SUB:

    case CC_OP_CMP:

        if (dc->cc_size == 4) {

            gen_helper_evaluate_flags_sub_4(cpu_PR[PR_CCS], cpu_env,

                    cpu_PR[PR_CCS], cc_src, cc_dest, cc_result);

        } else {

            gen_helper_evaluate_flags(cpu_env);

        }

        break;

    default:

        switch (dc->cc_size) {

        case 4:

            gen_helper_evaluate_flags_alu_4(cpu_PR[PR_CCS], cpu_env,

                    cpu_PR[PR_CCS], cc_src, cc_dest, cc_result);

            break;

        default:

            gen_helper_evaluate_flags(cpu_env);

            break;

        }

        break;

    }

    if (dc->flagx_known) {

        if (dc->flags_x) {

            tcg_gen_ori_tl(cpu_PR[PR_CCS], cpu_PR[PR_CCS], X_FLAG);

        } else if (dc->cc_op == CC_OP_FLAGS) {

            tcg_gen_andi_tl(cpu_PR[PR_CCS], cpu_PR[PR_CCS], ~X_FLAG);

        }

    }

    dc->flags_uptodate = 1;

}

static void cris_cc_mask(DisasContext *dc, unsigned int mask)

{

    uint32_t ovl;

    if (!mask) {

        dc->update_cc = 0;

        return;

    }

    /* Check if we need to evaluate the condition codes due to

       CC overlaying.  */

    ovl = (dc->cc_mask ^ mask) & ~mask;

    if (ovl) {

        /* TODO: optimize this case. It trigs all the time.  */

        cris_evaluate_flags(dc);

    }

    dc->cc_mask = mask;

    dc->update_cc = 1;

}

static void cris_update_cc_op(DisasContext *dc, int op, int size)

{

    dc->cc_op = op;

    dc->cc_size = size;

    dc->flags_uptodate = 0;

}

static inline void cris_update_cc_x(DisasContext *dc)

{

    /* Save the x flag state at the time of the cc snapshot.  */

    if (dc->flagx_known) {

        if (dc->cc_x_uptodate == (2 | dc->flags_x)) {

            return;

        }

        tcg_gen_movi_tl(cc_x, dc->flags_x);

        dc->cc_x_uptodate = 2 | dc->flags_x;

    } else {

        tcg_gen_andi_tl(cc_x, cpu_PR[PR_CCS], X_FLAG);

        dc->cc_x_uptodate = 1;

    }

}

/* Update cc prior to executing ALU op. Needs source operands untouched.  */

static void cris_pre_alu_update_cc(DisasContext *dc, int op, 

                   TCGv dst, TCGv src, int size)

{

    if (dc->update_cc) {

        cris_update_cc_op(dc, op, size);

        tcg_gen_mov_tl(cc_src, src);

        if (op != CC_OP_MOVE

            && op != CC_OP_AND

            && op != CC_OP_OR

            && op != CC_OP_XOR

            && op != CC_OP_ASR

            && op != CC_OP_LSR

            && op != CC_OP_LSL) {

            tcg_gen_mov_tl(cc_dest, dst);

        }

        cris_update_cc_x(dc);

    }

}

/* Update cc after executing ALU op. needs the result.  */

static inline void cris_update_result(DisasContext *dc, TCGv res)

{

    if (dc->update_cc) {

        tcg_gen_mov_tl(cc_result, res);

    }

}

/* Returns one if the write back stage should execute.  */

static void cris_alu_op_exec(DisasContext *dc, int op, 

                   TCGv dst, TCGv a, TCGv b, int size)

{

    /* Emit the ALU insns.  */

    switch (op) {

    case CC_OP_ADD:

        tcg_gen_add_tl(dst, a, b);

        /* Extended arithmetics.  */

        t_gen_addx_carry(dc, dst);

        break;

    case CC_OP_ADDC:

        tcg_gen_add_tl(dst, a, b);

        t_gen_add_flag(dst, 0); /* C_FLAG.  */

        break;

    case CC_OP_MCP:

        tcg_gen_add_tl(dst, a, b);

        t_gen_add_flag(dst, 8); /* R_FLAG.  */

        break;

    case CC_OP_SUB:

        tcg_gen_sub_tl(dst, a, b);

        /* Extended arithmetics.  */

        t_gen_subx_carry(dc, dst);

        break;

    case CC_OP_MOVE:

        tcg_gen_mov_tl(dst, b);

        break;

    case CC_OP_OR:

        tcg_gen_or_tl(dst, a, b);

        break;

    case CC_OP_AND:

        tcg_gen_and_tl(dst, a, b);

        break;

    case CC_OP_XOR:

        tcg_gen_xor_tl(dst, a, b);

        break;

    case CC_OP_LSL:

        t_gen_lsl(dst, a, b);

        break;

    case CC_OP_LSR:

        t_gen_lsr(dst, a, b);

        break;

    case CC_OP_ASR:

        t_gen_asr(dst, a, b);

        break;

    case CC_OP_NEG:

        tcg_gen_neg_tl(dst, b);

        /* Extended arithmetics.  */

        t_gen_subx_carry(dc, dst);

        break;

    case CC_OP_LZ:

        gen_helper_lz(dst, b);

        break;

    case CC_OP_MULS:

        tcg_gen_muls2_tl(dst, cpu_PR[PR_MOF], a, b);

        break;

    case CC_OP_MULU:

        tcg_gen_mulu2_tl(dst, cpu_PR[PR_MOF], a, b);

        break;

    case CC_OP_DSTEP:

        t_gen_cris_dstep(dst, a, b);

        break;

    case CC_OP_MSTEP:

        t_gen_cris_mstep(dst, a, b, cpu_PR[PR_CCS]);

        break;

    case CC_OP_BOUND:

    {

        int l1;

        l1 = gen_new_label();

        tcg_gen_mov_tl(dst, a);

        tcg_gen_brcond_tl(TCG_COND_LEU, a, b, l1);

        tcg_gen_mov_tl(dst, b);

        gen_set_label(l1);

    }

        break;

    case CC_OP_CMP:

        tcg_gen_sub_tl(dst, a, b);

        /* Extended arithmetics.  */

        t_gen_subx_carry(dc, dst);

        break;

    default:

        qemu_log("illegal ALU op.\n");

        BUG();

        break;

    }

    if (size == 1) {

        tcg_gen_andi_tl(dst, dst, 0xff);

    } else if (size == 2) {

        tcg_gen_andi_tl(dst, dst, 0xffff);

    }

}

static void cris_alu(DisasContext *dc, int op,

                   TCGv d, TCGv op_a, TCGv op_b, int size)

{

    TCGv tmp;

    int writeback;

    writeback = 1;

    if (op == CC_OP_CMP) {

        tmp = tcg_temp_new();

        writeback = 0;

    } else if (size == 4) {

        tmp = d;

        writeback = 0;

    } else {

        tmp = tcg_temp_new();

    }

    cris_pre_alu_update_cc(dc, op, op_a, op_b, size);

    cris_alu_op_exec(dc, op, tmp, op_a, op_b, size);

    cris_update_result(dc, tmp);

    /* Writeback.  */

    if (writeback) {

        if (size == 1) {

            tcg_gen_andi_tl(d, d, ~0xff);

        } else {

            tcg_gen_andi_tl(d, d, ~0xffff);

        }

        tcg_gen_or_tl(d, d, tmp);

    }

    if (!TCGV_EQUAL(tmp, d)) {

        tcg_temp_free(tmp);

    }

}

static int arith_cc(DisasContext *dc)

{

    if (dc->update_cc) {

        switch (dc->cc_op) {

        case CC_OP_ADDC: return 1;

        case CC_OP_ADD: return 1;

        case CC_OP_SUB: return 1;

        case CC_OP_DSTEP: return 1;

        case CC_OP_LSL: return 1;

        case CC_OP_LSR: return 1;

        case CC_OP_ASR: return 1;

        case CC_OP_CMP: return 1;

        case CC_OP_NEG: return 1;

        case CC_OP_OR: return 1;

        case CC_OP_AND: return 1;

        case CC_OP_XOR: return 1;

        case CC_OP_MULU: return 1;

        case CC_OP_MULS: return 1;