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1 | 80cabfad | bellard | /*
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2 | 80cabfad | bellard | * QEMU MC146818 RTC emulation
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3 | 5fafdf24 | ths | *
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4 | 80cabfad | bellard | * Copyright (c) 2003-2004 Fabrice Bellard
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5 | 5fafdf24 | ths | *
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6 | 80cabfad | bellard | * Permission is hereby granted, free of charge, to any person obtaining a copy
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7 | 80cabfad | bellard | * of this software and associated documentation files (the "Software"), to deal
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8 | 80cabfad | bellard | * in the Software without restriction, including without limitation the rights
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9 | 80cabfad | bellard | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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10 | 80cabfad | bellard | * copies of the Software, and to permit persons to whom the Software is
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11 | 80cabfad | bellard | * furnished to do so, subject to the following conditions:
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12 | 80cabfad | bellard | *
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13 | 80cabfad | bellard | * The above copyright notice and this permission notice shall be included in
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14 | 80cabfad | bellard | * all copies or substantial portions of the Software.
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15 | 80cabfad | bellard | *
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16 | 80cabfad | bellard | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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17 | 80cabfad | bellard | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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18 | 80cabfad | bellard | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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19 | 80cabfad | bellard | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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20 | 80cabfad | bellard | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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21 | 80cabfad | bellard | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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22 | 80cabfad | bellard | * THE SOFTWARE.
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23 | 80cabfad | bellard | */
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24 | 87ecb68b | pbrook | #include "hw.h" |
25 | 87ecb68b | pbrook | #include "qemu-timer.h" |
26 | 87ecb68b | pbrook | #include "sysemu.h" |
27 | 87ecb68b | pbrook | #include "pc.h" |
28 | 87ecb68b | pbrook | #include "isa.h" |
29 | 16b29ae1 | aliguori | #include "hpet_emul.h" |
30 | 80cabfad | bellard | |
31 | 80cabfad | bellard | //#define DEBUG_CMOS
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32 | 80cabfad | bellard | |
33 | 80cabfad | bellard | #define RTC_SECONDS 0 |
34 | 80cabfad | bellard | #define RTC_SECONDS_ALARM 1 |
35 | 80cabfad | bellard | #define RTC_MINUTES 2 |
36 | 80cabfad | bellard | #define RTC_MINUTES_ALARM 3 |
37 | 80cabfad | bellard | #define RTC_HOURS 4 |
38 | 80cabfad | bellard | #define RTC_HOURS_ALARM 5 |
39 | 80cabfad | bellard | #define RTC_ALARM_DONT_CARE 0xC0 |
40 | 80cabfad | bellard | |
41 | 80cabfad | bellard | #define RTC_DAY_OF_WEEK 6 |
42 | 80cabfad | bellard | #define RTC_DAY_OF_MONTH 7 |
43 | 80cabfad | bellard | #define RTC_MONTH 8 |
44 | 80cabfad | bellard | #define RTC_YEAR 9 |
45 | 80cabfad | bellard | |
46 | 80cabfad | bellard | #define RTC_REG_A 10 |
47 | 80cabfad | bellard | #define RTC_REG_B 11 |
48 | 80cabfad | bellard | #define RTC_REG_C 12 |
49 | 80cabfad | bellard | #define RTC_REG_D 13 |
50 | 80cabfad | bellard | |
51 | dff38e7b | bellard | #define REG_A_UIP 0x80 |
52 | 80cabfad | bellard | |
53 | 100d9891 | aurel32 | #define REG_B_SET 0x80 |
54 | 100d9891 | aurel32 | #define REG_B_PIE 0x40 |
55 | 100d9891 | aurel32 | #define REG_B_AIE 0x20 |
56 | 100d9891 | aurel32 | #define REG_B_UIE 0x10 |
57 | 100d9891 | aurel32 | #define REG_B_SQWE 0x08 |
58 | 100d9891 | aurel32 | #define REG_B_DM 0x04 |
59 | dff38e7b | bellard | |
60 | dff38e7b | bellard | struct RTCState {
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61 | dff38e7b | bellard | uint8_t cmos_data[128];
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62 | dff38e7b | bellard | uint8_t cmos_index; |
63 | 43f493af | bellard | struct tm current_tm;
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64 | 42fc73a1 | aurel32 | int base_year;
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65 | d537cf6c | pbrook | qemu_irq irq; |
66 | 100d9891 | aurel32 | qemu_irq sqw_irq; |
67 | 18c6e2ff | ths | int it_shift;
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68 | dff38e7b | bellard | /* periodic timer */
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69 | dff38e7b | bellard | QEMUTimer *periodic_timer; |
70 | dff38e7b | bellard | int64_t next_periodic_time; |
71 | dff38e7b | bellard | /* second update */
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72 | dff38e7b | bellard | int64_t next_second_time; |
73 | 73822ec8 | aliguori | #ifdef TARGET_I386
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74 | 73822ec8 | aliguori | uint32_t irq_coalesced; |
75 | 73822ec8 | aliguori | uint32_t period; |
76 | 73822ec8 | aliguori | #endif
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77 | dff38e7b | bellard | QEMUTimer *second_timer; |
78 | dff38e7b | bellard | QEMUTimer *second_timer2; |
79 | dff38e7b | bellard | }; |
80 | dff38e7b | bellard | |
81 | 16b29ae1 | aliguori | static void rtc_irq_raise(qemu_irq irq) { |
82 | c50c2d68 | aurel32 | /* When HPET is operating in legacy mode, RTC interrupts are disabled
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83 | 16b29ae1 | aliguori | * We block qemu_irq_raise, but not qemu_irq_lower, in case legacy
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84 | c50c2d68 | aurel32 | * mode is established while interrupt is raised. We want it to
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85 | 16b29ae1 | aliguori | * be lowered in any case
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86 | c50c2d68 | aurel32 | */
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87 | 16b29ae1 | aliguori | #if defined TARGET_I386 || defined TARGET_X86_64
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88 | c50c2d68 | aurel32 | if (!hpet_in_legacy_mode())
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89 | 16b29ae1 | aliguori | #endif
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90 | 16b29ae1 | aliguori | qemu_irq_raise(irq); |
91 | 16b29ae1 | aliguori | } |
92 | 16b29ae1 | aliguori | |
93 | dff38e7b | bellard | static void rtc_set_time(RTCState *s); |
94 | dff38e7b | bellard | static void rtc_copy_date(RTCState *s); |
95 | dff38e7b | bellard | |
96 | dff38e7b | bellard | static void rtc_timer_update(RTCState *s, int64_t current_time) |
97 | dff38e7b | bellard | { |
98 | dff38e7b | bellard | int period_code, period;
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99 | dff38e7b | bellard | int64_t cur_clock, next_irq_clock; |
100 | 100d9891 | aurel32 | int enable_pie;
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101 | dff38e7b | bellard | |
102 | dff38e7b | bellard | period_code = s->cmos_data[RTC_REG_A] & 0x0f;
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103 | 16b29ae1 | aliguori | #if defined TARGET_I386 || defined TARGET_X86_64
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104 | c50c2d68 | aurel32 | /* disable periodic timer if hpet is in legacy mode, since interrupts are
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105 | 16b29ae1 | aliguori | * disabled anyway.
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106 | 16b29ae1 | aliguori | */
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107 | 100d9891 | aurel32 | enable_pie = hpet_in_legacy_mode(); |
108 | 16b29ae1 | aliguori | #else
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109 | 100d9891 | aurel32 | enable_pie = 1;
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110 | 16b29ae1 | aliguori | #endif
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111 | 100d9891 | aurel32 | if (period_code != 0 |
112 | 100d9891 | aurel32 | && (((s->cmos_data[RTC_REG_B] & REG_B_PIE) && enable_pie) |
113 | 100d9891 | aurel32 | || ((s->cmos_data[RTC_REG_B] & REG_B_SQWE) && s->sqw_irq))) { |
114 | dff38e7b | bellard | if (period_code <= 2) |
115 | dff38e7b | bellard | period_code += 7;
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116 | dff38e7b | bellard | /* period in 32 Khz cycles */
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117 | dff38e7b | bellard | period = 1 << (period_code - 1); |
118 | 73822ec8 | aliguori | #ifdef TARGET_I386
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119 | 73822ec8 | aliguori | if(period != s->period)
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120 | 73822ec8 | aliguori | s->irq_coalesced = (s->irq_coalesced * s->period) / period; |
121 | 73822ec8 | aliguori | s->period = period; |
122 | 73822ec8 | aliguori | #endif
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123 | dff38e7b | bellard | /* compute 32 khz clock */
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124 | dff38e7b | bellard | cur_clock = muldiv64(current_time, 32768, ticks_per_sec);
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125 | dff38e7b | bellard | next_irq_clock = (cur_clock & ~(period - 1)) + period;
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126 | dff38e7b | bellard | s->next_periodic_time = muldiv64(next_irq_clock, ticks_per_sec, 32768) + 1; |
127 | dff38e7b | bellard | qemu_mod_timer(s->periodic_timer, s->next_periodic_time); |
128 | dff38e7b | bellard | } else {
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129 | 73822ec8 | aliguori | #ifdef TARGET_I386
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130 | 73822ec8 | aliguori | s->irq_coalesced = 0;
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131 | 73822ec8 | aliguori | #endif
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132 | dff38e7b | bellard | qemu_del_timer(s->periodic_timer); |
133 | dff38e7b | bellard | } |
134 | dff38e7b | bellard | } |
135 | dff38e7b | bellard | |
136 | dff38e7b | bellard | static void rtc_periodic_timer(void *opaque) |
137 | dff38e7b | bellard | { |
138 | dff38e7b | bellard | RTCState *s = opaque; |
139 | dff38e7b | bellard | |
140 | dff38e7b | bellard | rtc_timer_update(s, s->next_periodic_time); |
141 | 73822ec8 | aliguori | #ifdef TARGET_I386
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142 | 73822ec8 | aliguori | if ((s->cmos_data[RTC_REG_C] & 0xc0) && rtc_td_hack) { |
143 | 73822ec8 | aliguori | s->irq_coalesced++; |
144 | 73822ec8 | aliguori | return;
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145 | 73822ec8 | aliguori | } |
146 | 73822ec8 | aliguori | #endif
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147 | 100d9891 | aurel32 | if (s->cmos_data[RTC_REG_B] & REG_B_PIE) {
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148 | 100d9891 | aurel32 | s->cmos_data[RTC_REG_C] |= 0xc0;
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149 | 100d9891 | aurel32 | rtc_irq_raise(s->irq); |
150 | 100d9891 | aurel32 | } |
151 | 100d9891 | aurel32 | if (s->cmos_data[RTC_REG_B] & REG_B_SQWE) {
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152 | 100d9891 | aurel32 | /* Not square wave at all but we don't want 2048Hz interrupts!
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153 | 100d9891 | aurel32 | Must be seen as a pulse. */
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154 | 100d9891 | aurel32 | qemu_irq_raise(s->sqw_irq); |
155 | 100d9891 | aurel32 | } |
156 | dff38e7b | bellard | } |
157 | 80cabfad | bellard | |
158 | b41a2cd1 | bellard | static void cmos_ioport_write(void *opaque, uint32_t addr, uint32_t data) |
159 | 80cabfad | bellard | { |
160 | b41a2cd1 | bellard | RTCState *s = opaque; |
161 | 80cabfad | bellard | |
162 | 80cabfad | bellard | if ((addr & 1) == 0) { |
163 | 80cabfad | bellard | s->cmos_index = data & 0x7f;
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164 | 80cabfad | bellard | } else {
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165 | 80cabfad | bellard | #ifdef DEBUG_CMOS
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166 | 80cabfad | bellard | printf("cmos: write index=0x%02x val=0x%02x\n",
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167 | 80cabfad | bellard | s->cmos_index, data); |
168 | 3b46e624 | ths | #endif
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169 | dff38e7b | bellard | switch(s->cmos_index) {
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170 | 80cabfad | bellard | case RTC_SECONDS_ALARM:
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171 | 80cabfad | bellard | case RTC_MINUTES_ALARM:
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172 | 80cabfad | bellard | case RTC_HOURS_ALARM:
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173 | 80cabfad | bellard | /* XXX: not supported */
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174 | 80cabfad | bellard | s->cmos_data[s->cmos_index] = data; |
175 | 80cabfad | bellard | break;
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176 | 80cabfad | bellard | case RTC_SECONDS:
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177 | 80cabfad | bellard | case RTC_MINUTES:
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178 | 80cabfad | bellard | case RTC_HOURS:
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179 | 80cabfad | bellard | case RTC_DAY_OF_WEEK:
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180 | 80cabfad | bellard | case RTC_DAY_OF_MONTH:
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181 | 80cabfad | bellard | case RTC_MONTH:
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182 | 80cabfad | bellard | case RTC_YEAR:
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183 | 80cabfad | bellard | s->cmos_data[s->cmos_index] = data; |
184 | dff38e7b | bellard | /* if in set mode, do not update the time */
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185 | dff38e7b | bellard | if (!(s->cmos_data[RTC_REG_B] & REG_B_SET)) {
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186 | dff38e7b | bellard | rtc_set_time(s); |
187 | dff38e7b | bellard | } |
188 | 80cabfad | bellard | break;
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189 | 80cabfad | bellard | case RTC_REG_A:
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190 | dff38e7b | bellard | /* UIP bit is read only */
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191 | dff38e7b | bellard | s->cmos_data[RTC_REG_A] = (data & ~REG_A_UIP) | |
192 | dff38e7b | bellard | (s->cmos_data[RTC_REG_A] & REG_A_UIP); |
193 | dff38e7b | bellard | rtc_timer_update(s, qemu_get_clock(vm_clock)); |
194 | dff38e7b | bellard | break;
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195 | 80cabfad | bellard | case RTC_REG_B:
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196 | dff38e7b | bellard | if (data & REG_B_SET) {
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197 | dff38e7b | bellard | /* set mode: reset UIP mode */
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198 | dff38e7b | bellard | s->cmos_data[RTC_REG_A] &= ~REG_A_UIP; |
199 | dff38e7b | bellard | data &= ~REG_B_UIE; |
200 | dff38e7b | bellard | } else {
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201 | dff38e7b | bellard | /* if disabling set mode, update the time */
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202 | dff38e7b | bellard | if (s->cmos_data[RTC_REG_B] & REG_B_SET) {
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203 | dff38e7b | bellard | rtc_set_time(s); |
204 | dff38e7b | bellard | } |
205 | dff38e7b | bellard | } |
206 | dff38e7b | bellard | s->cmos_data[RTC_REG_B] = data; |
207 | dff38e7b | bellard | rtc_timer_update(s, qemu_get_clock(vm_clock)); |
208 | 80cabfad | bellard | break;
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209 | 80cabfad | bellard | case RTC_REG_C:
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210 | 80cabfad | bellard | case RTC_REG_D:
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211 | 80cabfad | bellard | /* cannot write to them */
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212 | 80cabfad | bellard | break;
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213 | 80cabfad | bellard | default:
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214 | 80cabfad | bellard | s->cmos_data[s->cmos_index] = data; |
215 | 80cabfad | bellard | break;
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216 | 80cabfad | bellard | } |
217 | 80cabfad | bellard | } |
218 | 80cabfad | bellard | } |
219 | 80cabfad | bellard | |
220 | dff38e7b | bellard | static inline int to_bcd(RTCState *s, int a) |
221 | 80cabfad | bellard | { |
222 | 6f1bf24d | aurel32 | if (s->cmos_data[RTC_REG_B] & REG_B_DM) {
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223 | dff38e7b | bellard | return a;
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224 | dff38e7b | bellard | } else {
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225 | dff38e7b | bellard | return ((a / 10) << 4) | (a % 10); |
226 | dff38e7b | bellard | } |
227 | 80cabfad | bellard | } |
228 | 80cabfad | bellard | |
229 | dff38e7b | bellard | static inline int from_bcd(RTCState *s, int a) |
230 | 80cabfad | bellard | { |
231 | 6f1bf24d | aurel32 | if (s->cmos_data[RTC_REG_B] & REG_B_DM) {
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232 | dff38e7b | bellard | return a;
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233 | dff38e7b | bellard | } else {
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234 | dff38e7b | bellard | return ((a >> 4) * 10) + (a & 0x0f); |
235 | dff38e7b | bellard | } |
236 | dff38e7b | bellard | } |
237 | dff38e7b | bellard | |
238 | dff38e7b | bellard | static void rtc_set_time(RTCState *s) |
239 | dff38e7b | bellard | { |
240 | 43f493af | bellard | struct tm *tm = &s->current_tm;
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241 | dff38e7b | bellard | |
242 | dff38e7b | bellard | tm->tm_sec = from_bcd(s, s->cmos_data[RTC_SECONDS]); |
243 | dff38e7b | bellard | tm->tm_min = from_bcd(s, s->cmos_data[RTC_MINUTES]); |
244 | 43f493af | bellard | tm->tm_hour = from_bcd(s, s->cmos_data[RTC_HOURS] & 0x7f);
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245 | 43f493af | bellard | if (!(s->cmos_data[RTC_REG_B] & 0x02) && |
246 | 43f493af | bellard | (s->cmos_data[RTC_HOURS] & 0x80)) {
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247 | 43f493af | bellard | tm->tm_hour += 12;
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248 | 43f493af | bellard | } |
249 | 6f1bf24d | aurel32 | tm->tm_wday = from_bcd(s, s->cmos_data[RTC_DAY_OF_WEEK]) - 1;
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250 | dff38e7b | bellard | tm->tm_mday = from_bcd(s, s->cmos_data[RTC_DAY_OF_MONTH]); |
251 | dff38e7b | bellard | tm->tm_mon = from_bcd(s, s->cmos_data[RTC_MONTH]) - 1;
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252 | 42fc73a1 | aurel32 | tm->tm_year = from_bcd(s, s->cmos_data[RTC_YEAR]) + s->base_year - 1900;
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253 | 43f493af | bellard | } |
254 | 43f493af | bellard | |
255 | 43f493af | bellard | static void rtc_copy_date(RTCState *s) |
256 | 43f493af | bellard | { |
257 | 43f493af | bellard | const struct tm *tm = &s->current_tm; |
258 | 42fc73a1 | aurel32 | int year;
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259 | dff38e7b | bellard | |
260 | 43f493af | bellard | s->cmos_data[RTC_SECONDS] = to_bcd(s, tm->tm_sec); |
261 | 43f493af | bellard | s->cmos_data[RTC_MINUTES] = to_bcd(s, tm->tm_min); |
262 | 43f493af | bellard | if (s->cmos_data[RTC_REG_B] & 0x02) { |
263 | 43f493af | bellard | /* 24 hour format */
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264 | 43f493af | bellard | s->cmos_data[RTC_HOURS] = to_bcd(s, tm->tm_hour); |
265 | 43f493af | bellard | } else {
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266 | 43f493af | bellard | /* 12 hour format */
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267 | 43f493af | bellard | s->cmos_data[RTC_HOURS] = to_bcd(s, tm->tm_hour % 12);
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268 | 43f493af | bellard | if (tm->tm_hour >= 12) |
269 | 43f493af | bellard | s->cmos_data[RTC_HOURS] |= 0x80;
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270 | 43f493af | bellard | } |
271 | 6f1bf24d | aurel32 | s->cmos_data[RTC_DAY_OF_WEEK] = to_bcd(s, tm->tm_wday + 1);
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272 | 43f493af | bellard | s->cmos_data[RTC_DAY_OF_MONTH] = to_bcd(s, tm->tm_mday); |
273 | 43f493af | bellard | s->cmos_data[RTC_MONTH] = to_bcd(s, tm->tm_mon + 1);
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274 | 42fc73a1 | aurel32 | year = (tm->tm_year - s->base_year) % 100;
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275 | 42fc73a1 | aurel32 | if (year < 0) |
276 | 42fc73a1 | aurel32 | year += 100;
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277 | 42fc73a1 | aurel32 | s->cmos_data[RTC_YEAR] = to_bcd(s, year); |
278 | 43f493af | bellard | } |
279 | 43f493af | bellard | |
280 | 43f493af | bellard | /* month is between 0 and 11. */
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281 | 43f493af | bellard | static int get_days_in_month(int month, int year) |
282 | 43f493af | bellard | { |
283 | 5fafdf24 | ths | static const int days_tab[12] = { |
284 | 5fafdf24 | ths | 31, 28, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31 |
285 | 43f493af | bellard | }; |
286 | 43f493af | bellard | int d;
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287 | 43f493af | bellard | if ((unsigned )month >= 12) |
288 | 43f493af | bellard | return 31; |
289 | 43f493af | bellard | d = days_tab[month]; |
290 | 43f493af | bellard | if (month == 1) { |
291 | 43f493af | bellard | if ((year % 4) == 0 && ((year % 100) != 0 || (year % 400) == 0)) |
292 | 43f493af | bellard | d++; |
293 | 43f493af | bellard | } |
294 | 43f493af | bellard | return d;
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295 | 43f493af | bellard | } |
296 | 43f493af | bellard | |
297 | 43f493af | bellard | /* update 'tm' to the next second */
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298 | 43f493af | bellard | static void rtc_next_second(struct tm *tm) |
299 | 43f493af | bellard | { |
300 | 43f493af | bellard | int days_in_month;
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301 | 43f493af | bellard | |
302 | 43f493af | bellard | tm->tm_sec++; |
303 | 43f493af | bellard | if ((unsigned)tm->tm_sec >= 60) { |
304 | 43f493af | bellard | tm->tm_sec = 0;
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305 | 43f493af | bellard | tm->tm_min++; |
306 | 43f493af | bellard | if ((unsigned)tm->tm_min >= 60) { |
307 | 43f493af | bellard | tm->tm_min = 0;
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308 | 43f493af | bellard | tm->tm_hour++; |
309 | 43f493af | bellard | if ((unsigned)tm->tm_hour >= 24) { |
310 | 43f493af | bellard | tm->tm_hour = 0;
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311 | 43f493af | bellard | /* next day */
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312 | 43f493af | bellard | tm->tm_wday++; |
313 | 43f493af | bellard | if ((unsigned)tm->tm_wday >= 7) |
314 | 43f493af | bellard | tm->tm_wday = 0;
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315 | 5fafdf24 | ths | days_in_month = get_days_in_month(tm->tm_mon, |
316 | 43f493af | bellard | tm->tm_year + 1900);
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317 | 43f493af | bellard | tm->tm_mday++; |
318 | 43f493af | bellard | if (tm->tm_mday < 1) { |
319 | 43f493af | bellard | tm->tm_mday = 1;
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320 | 43f493af | bellard | } else if (tm->tm_mday > days_in_month) { |
321 | 43f493af | bellard | tm->tm_mday = 1;
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322 | 43f493af | bellard | tm->tm_mon++; |
323 | 43f493af | bellard | if (tm->tm_mon >= 12) { |
324 | 43f493af | bellard | tm->tm_mon = 0;
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325 | 43f493af | bellard | tm->tm_year++; |
326 | 43f493af | bellard | } |
327 | 43f493af | bellard | } |
328 | 43f493af | bellard | } |
329 | 43f493af | bellard | } |
330 | 43f493af | bellard | } |
331 | dff38e7b | bellard | } |
332 | dff38e7b | bellard | |
333 | 43f493af | bellard | |
334 | dff38e7b | bellard | static void rtc_update_second(void *opaque) |
335 | dff38e7b | bellard | { |
336 | dff38e7b | bellard | RTCState *s = opaque; |
337 | 4721c457 | bellard | int64_t delay; |
338 | dff38e7b | bellard | |
339 | dff38e7b | bellard | /* if the oscillator is not in normal operation, we do not update */
|
340 | dff38e7b | bellard | if ((s->cmos_data[RTC_REG_A] & 0x70) != 0x20) { |
341 | dff38e7b | bellard | s->next_second_time += ticks_per_sec; |
342 | dff38e7b | bellard | qemu_mod_timer(s->second_timer, s->next_second_time); |
343 | dff38e7b | bellard | } else {
|
344 | 43f493af | bellard | rtc_next_second(&s->current_tm); |
345 | 3b46e624 | ths | |
346 | dff38e7b | bellard | if (!(s->cmos_data[RTC_REG_B] & REG_B_SET)) {
|
347 | dff38e7b | bellard | /* update in progress bit */
|
348 | dff38e7b | bellard | s->cmos_data[RTC_REG_A] |= REG_A_UIP; |
349 | dff38e7b | bellard | } |
350 | 4721c457 | bellard | /* should be 244 us = 8 / 32768 seconds, but currently the
|
351 | 4721c457 | bellard | timers do not have the necessary resolution. */
|
352 | 4721c457 | bellard | delay = (ticks_per_sec * 1) / 100; |
353 | 4721c457 | bellard | if (delay < 1) |
354 | 4721c457 | bellard | delay = 1;
|
355 | 5fafdf24 | ths | qemu_mod_timer(s->second_timer2, |
356 | 4721c457 | bellard | s->next_second_time + delay); |
357 | dff38e7b | bellard | } |
358 | dff38e7b | bellard | } |
359 | dff38e7b | bellard | |
360 | dff38e7b | bellard | static void rtc_update_second2(void *opaque) |
361 | dff38e7b | bellard | { |
362 | dff38e7b | bellard | RTCState *s = opaque; |
363 | dff38e7b | bellard | |
364 | dff38e7b | bellard | if (!(s->cmos_data[RTC_REG_B] & REG_B_SET)) {
|
365 | dff38e7b | bellard | rtc_copy_date(s); |
366 | dff38e7b | bellard | } |
367 | dff38e7b | bellard | |
368 | dff38e7b | bellard | /* check alarm */
|
369 | dff38e7b | bellard | if (s->cmos_data[RTC_REG_B] & REG_B_AIE) {
|
370 | dff38e7b | bellard | if (((s->cmos_data[RTC_SECONDS_ALARM] & 0xc0) == 0xc0 || |
371 | 43f493af | bellard | s->cmos_data[RTC_SECONDS_ALARM] == s->current_tm.tm_sec) && |
372 | dff38e7b | bellard | ((s->cmos_data[RTC_MINUTES_ALARM] & 0xc0) == 0xc0 || |
373 | 43f493af | bellard | s->cmos_data[RTC_MINUTES_ALARM] == s->current_tm.tm_mon) && |
374 | dff38e7b | bellard | ((s->cmos_data[RTC_HOURS_ALARM] & 0xc0) == 0xc0 || |
375 | 43f493af | bellard | s->cmos_data[RTC_HOURS_ALARM] == s->current_tm.tm_hour)) { |
376 | dff38e7b | bellard | |
377 | 5fafdf24 | ths | s->cmos_data[RTC_REG_C] |= 0xa0;
|
378 | 16b29ae1 | aliguori | rtc_irq_raise(s->irq); |
379 | dff38e7b | bellard | } |
380 | dff38e7b | bellard | } |
381 | dff38e7b | bellard | |
382 | dff38e7b | bellard | /* update ended interrupt */
|
383 | dff38e7b | bellard | if (s->cmos_data[RTC_REG_B] & REG_B_UIE) {
|
384 | 5fafdf24 | ths | s->cmos_data[RTC_REG_C] |= 0x90;
|
385 | 16b29ae1 | aliguori | rtc_irq_raise(s->irq); |
386 | dff38e7b | bellard | } |
387 | dff38e7b | bellard | |
388 | dff38e7b | bellard | /* clear update in progress bit */
|
389 | dff38e7b | bellard | s->cmos_data[RTC_REG_A] &= ~REG_A_UIP; |
390 | dff38e7b | bellard | |
391 | dff38e7b | bellard | s->next_second_time += ticks_per_sec; |
392 | dff38e7b | bellard | qemu_mod_timer(s->second_timer, s->next_second_time); |
393 | 80cabfad | bellard | } |
394 | 80cabfad | bellard | |
395 | b41a2cd1 | bellard | static uint32_t cmos_ioport_read(void *opaque, uint32_t addr) |
396 | 80cabfad | bellard | { |
397 | b41a2cd1 | bellard | RTCState *s = opaque; |
398 | 80cabfad | bellard | int ret;
|
399 | 80cabfad | bellard | if ((addr & 1) == 0) { |
400 | 80cabfad | bellard | return 0xff; |
401 | 80cabfad | bellard | } else {
|
402 | 80cabfad | bellard | switch(s->cmos_index) {
|
403 | 80cabfad | bellard | case RTC_SECONDS:
|
404 | 80cabfad | bellard | case RTC_MINUTES:
|
405 | 80cabfad | bellard | case RTC_HOURS:
|
406 | 80cabfad | bellard | case RTC_DAY_OF_WEEK:
|
407 | 80cabfad | bellard | case RTC_DAY_OF_MONTH:
|
408 | 80cabfad | bellard | case RTC_MONTH:
|
409 | 80cabfad | bellard | case RTC_YEAR:
|
410 | 80cabfad | bellard | ret = s->cmos_data[s->cmos_index]; |
411 | 80cabfad | bellard | break;
|
412 | 80cabfad | bellard | case RTC_REG_A:
|
413 | 80cabfad | bellard | ret = s->cmos_data[s->cmos_index]; |
414 | 80cabfad | bellard | break;
|
415 | 80cabfad | bellard | case RTC_REG_C:
|
416 | 80cabfad | bellard | ret = s->cmos_data[s->cmos_index]; |
417 | d537cf6c | pbrook | qemu_irq_lower(s->irq); |
418 | 73822ec8 | aliguori | #ifdef TARGET_I386
|
419 | 73822ec8 | aliguori | if(s->irq_coalesced) {
|
420 | 73822ec8 | aliguori | apic_reset_irq_delivered(); |
421 | 73822ec8 | aliguori | qemu_irq_raise(s->irq); |
422 | 73822ec8 | aliguori | if (apic_get_irq_delivered())
|
423 | 73822ec8 | aliguori | s->irq_coalesced--; |
424 | 73822ec8 | aliguori | break;
|
425 | 73822ec8 | aliguori | } |
426 | 73822ec8 | aliguori | #endif
|
427 | 5fafdf24 | ths | s->cmos_data[RTC_REG_C] = 0x00;
|
428 | 80cabfad | bellard | break;
|
429 | 80cabfad | bellard | default:
|
430 | 80cabfad | bellard | ret = s->cmos_data[s->cmos_index]; |
431 | 80cabfad | bellard | break;
|
432 | 80cabfad | bellard | } |
433 | 80cabfad | bellard | #ifdef DEBUG_CMOS
|
434 | 80cabfad | bellard | printf("cmos: read index=0x%02x val=0x%02x\n",
|
435 | 80cabfad | bellard | s->cmos_index, ret); |
436 | 80cabfad | bellard | #endif
|
437 | 80cabfad | bellard | return ret;
|
438 | 80cabfad | bellard | } |
439 | 80cabfad | bellard | } |
440 | 80cabfad | bellard | |
441 | dff38e7b | bellard | void rtc_set_memory(RTCState *s, int addr, int val) |
442 | dff38e7b | bellard | { |
443 | dff38e7b | bellard | if (addr >= 0 && addr <= 127) |
444 | dff38e7b | bellard | s->cmos_data[addr] = val; |
445 | dff38e7b | bellard | } |
446 | dff38e7b | bellard | |
447 | dff38e7b | bellard | void rtc_set_date(RTCState *s, const struct tm *tm) |
448 | dff38e7b | bellard | { |
449 | 43f493af | bellard | s->current_tm = *tm; |
450 | dff38e7b | bellard | rtc_copy_date(s); |
451 | dff38e7b | bellard | } |
452 | dff38e7b | bellard | |
453 | ea55ffb3 | ths | /* PC cmos mappings */
|
454 | ea55ffb3 | ths | #define REG_IBM_CENTURY_BYTE 0x32 |
455 | ea55ffb3 | ths | #define REG_IBM_PS2_CENTURY_BYTE 0x37 |
456 | ea55ffb3 | ths | |
457 | 9596ebb7 | pbrook | static void rtc_set_date_from_host(RTCState *s) |
458 | ea55ffb3 | ths | { |
459 | f6503059 | balrog | struct tm tm;
|
460 | ea55ffb3 | ths | int val;
|
461 | ea55ffb3 | ths | |
462 | ea55ffb3 | ths | /* set the CMOS date */
|
463 | f6503059 | balrog | qemu_get_timedate(&tm, 0);
|
464 | f6503059 | balrog | rtc_set_date(s, &tm); |
465 | ea55ffb3 | ths | |
466 | f6503059 | balrog | val = to_bcd(s, (tm.tm_year / 100) + 19); |
467 | ea55ffb3 | ths | rtc_set_memory(s, REG_IBM_CENTURY_BYTE, val); |
468 | ea55ffb3 | ths | rtc_set_memory(s, REG_IBM_PS2_CENTURY_BYTE, val); |
469 | ea55ffb3 | ths | } |
470 | ea55ffb3 | ths | |
471 | dff38e7b | bellard | static void rtc_save(QEMUFile *f, void *opaque) |
472 | dff38e7b | bellard | { |
473 | dff38e7b | bellard | RTCState *s = opaque; |
474 | dff38e7b | bellard | |
475 | dff38e7b | bellard | qemu_put_buffer(f, s->cmos_data, 128);
|
476 | dff38e7b | bellard | qemu_put_8s(f, &s->cmos_index); |
477 | 3b46e624 | ths | |
478 | bee8d684 | ths | qemu_put_be32(f, s->current_tm.tm_sec); |
479 | bee8d684 | ths | qemu_put_be32(f, s->current_tm.tm_min); |
480 | bee8d684 | ths | qemu_put_be32(f, s->current_tm.tm_hour); |
481 | bee8d684 | ths | qemu_put_be32(f, s->current_tm.tm_wday); |
482 | bee8d684 | ths | qemu_put_be32(f, s->current_tm.tm_mday); |
483 | bee8d684 | ths | qemu_put_be32(f, s->current_tm.tm_mon); |
484 | bee8d684 | ths | qemu_put_be32(f, s->current_tm.tm_year); |
485 | dff38e7b | bellard | |
486 | dff38e7b | bellard | qemu_put_timer(f, s->periodic_timer); |
487 | bee8d684 | ths | qemu_put_be64(f, s->next_periodic_time); |
488 | dff38e7b | bellard | |
489 | bee8d684 | ths | qemu_put_be64(f, s->next_second_time); |
490 | dff38e7b | bellard | qemu_put_timer(f, s->second_timer); |
491 | dff38e7b | bellard | qemu_put_timer(f, s->second_timer2); |
492 | 80cabfad | bellard | } |
493 | 80cabfad | bellard | |
494 | dff38e7b | bellard | static int rtc_load(QEMUFile *f, void *opaque, int version_id) |
495 | 80cabfad | bellard | { |
496 | dff38e7b | bellard | RTCState *s = opaque; |
497 | dff38e7b | bellard | |
498 | dff38e7b | bellard | if (version_id != 1) |
499 | dff38e7b | bellard | return -EINVAL;
|
500 | 80cabfad | bellard | |
501 | dff38e7b | bellard | qemu_get_buffer(f, s->cmos_data, 128);
|
502 | dff38e7b | bellard | qemu_get_8s(f, &s->cmos_index); |
503 | 43f493af | bellard | |
504 | bee8d684 | ths | s->current_tm.tm_sec=qemu_get_be32(f); |
505 | bee8d684 | ths | s->current_tm.tm_min=qemu_get_be32(f); |
506 | bee8d684 | ths | s->current_tm.tm_hour=qemu_get_be32(f); |
507 | bee8d684 | ths | s->current_tm.tm_wday=qemu_get_be32(f); |
508 | bee8d684 | ths | s->current_tm.tm_mday=qemu_get_be32(f); |
509 | bee8d684 | ths | s->current_tm.tm_mon=qemu_get_be32(f); |
510 | bee8d684 | ths | s->current_tm.tm_year=qemu_get_be32(f); |
511 | dff38e7b | bellard | |
512 | dff38e7b | bellard | qemu_get_timer(f, s->periodic_timer); |
513 | bee8d684 | ths | s->next_periodic_time=qemu_get_be64(f); |
514 | dff38e7b | bellard | |
515 | bee8d684 | ths | s->next_second_time=qemu_get_be64(f); |
516 | dff38e7b | bellard | qemu_get_timer(f, s->second_timer); |
517 | dff38e7b | bellard | qemu_get_timer(f, s->second_timer2); |
518 | dff38e7b | bellard | return 0; |
519 | dff38e7b | bellard | } |
520 | dff38e7b | bellard | |
521 | 73822ec8 | aliguori | #ifdef TARGET_I386
|
522 | 73822ec8 | aliguori | static void rtc_save_td(QEMUFile *f, void *opaque) |
523 | 73822ec8 | aliguori | { |
524 | 73822ec8 | aliguori | RTCState *s = opaque; |
525 | 73822ec8 | aliguori | |
526 | 73822ec8 | aliguori | qemu_put_be32(f, s->irq_coalesced); |
527 | 73822ec8 | aliguori | qemu_put_be32(f, s->period); |
528 | 73822ec8 | aliguori | } |
529 | 73822ec8 | aliguori | |
530 | 73822ec8 | aliguori | static int rtc_load_td(QEMUFile *f, void *opaque, int version_id) |
531 | 73822ec8 | aliguori | { |
532 | 73822ec8 | aliguori | RTCState *s = opaque; |
533 | 73822ec8 | aliguori | |
534 | 73822ec8 | aliguori | if (version_id != 1) |
535 | 73822ec8 | aliguori | return -EINVAL;
|
536 | 73822ec8 | aliguori | |
537 | 73822ec8 | aliguori | s->irq_coalesced = qemu_get_be32(f); |
538 | 73822ec8 | aliguori | s->period = qemu_get_be32(f); |
539 | 73822ec8 | aliguori | return 0; |
540 | 73822ec8 | aliguori | } |
541 | 73822ec8 | aliguori | #endif
|
542 | 73822ec8 | aliguori | |
543 | 100d9891 | aurel32 | RTCState *rtc_init_sqw(int base, qemu_irq irq, qemu_irq sqw_irq, int base_year) |
544 | dff38e7b | bellard | { |
545 | dff38e7b | bellard | RTCState *s; |
546 | dff38e7b | bellard | |
547 | dff38e7b | bellard | s = qemu_mallocz(sizeof(RTCState));
|
548 | 80cabfad | bellard | |
549 | 80cabfad | bellard | s->irq = irq; |
550 | 100d9891 | aurel32 | s->sqw_irq = sqw_irq; |
551 | 80cabfad | bellard | s->cmos_data[RTC_REG_A] = 0x26;
|
552 | 80cabfad | bellard | s->cmos_data[RTC_REG_B] = 0x02;
|
553 | 80cabfad | bellard | s->cmos_data[RTC_REG_C] = 0x00;
|
554 | 80cabfad | bellard | s->cmos_data[RTC_REG_D] = 0x80;
|
555 | 80cabfad | bellard | |
556 | 42fc73a1 | aurel32 | s->base_year = base_year; |
557 | ea55ffb3 | ths | rtc_set_date_from_host(s); |
558 | ea55ffb3 | ths | |
559 | 5fafdf24 | ths | s->periodic_timer = qemu_new_timer(vm_clock, |
560 | dff38e7b | bellard | rtc_periodic_timer, s); |
561 | 5fafdf24 | ths | s->second_timer = qemu_new_timer(vm_clock, |
562 | dff38e7b | bellard | rtc_update_second, s); |
563 | 5fafdf24 | ths | s->second_timer2 = qemu_new_timer(vm_clock, |
564 | dff38e7b | bellard | rtc_update_second2, s); |
565 | dff38e7b | bellard | |
566 | dff38e7b | bellard | s->next_second_time = qemu_get_clock(vm_clock) + (ticks_per_sec * 99) / 100; |
567 | dff38e7b | bellard | qemu_mod_timer(s->second_timer2, s->next_second_time); |
568 | dff38e7b | bellard | |
569 | b41a2cd1 | bellard | register_ioport_write(base, 2, 1, cmos_ioport_write, s); |
570 | b41a2cd1 | bellard | register_ioport_read(base, 2, 1, cmos_ioport_read, s); |
571 | dff38e7b | bellard | |
572 | dff38e7b | bellard | register_savevm("mc146818rtc", base, 1, rtc_save, rtc_load, s); |
573 | 73822ec8 | aliguori | #ifdef TARGET_I386
|
574 | 73822ec8 | aliguori | if (rtc_td_hack)
|
575 | 73822ec8 | aliguori | register_savevm("mc146818rtc-td", base, 1, rtc_save_td, rtc_load_td, s); |
576 | 73822ec8 | aliguori | #endif
|
577 | dff38e7b | bellard | return s;
|
578 | 80cabfad | bellard | } |
579 | 80cabfad | bellard | |
580 | 100d9891 | aurel32 | RTCState *rtc_init(int base, qemu_irq irq, int base_year) |
581 | 100d9891 | aurel32 | { |
582 | 100d9891 | aurel32 | return rtc_init_sqw(base, irq, NULL, base_year); |
583 | 100d9891 | aurel32 | } |
584 | 100d9891 | aurel32 | |
585 | 2ca9d013 | ths | /* Memory mapped interface */
|
586 | 9596ebb7 | pbrook | static uint32_t cmos_mm_readb (void *opaque, target_phys_addr_t addr) |
587 | 2ca9d013 | ths | { |
588 | 2ca9d013 | ths | RTCState *s = opaque; |
589 | 2ca9d013 | ths | |
590 | 8da3ff18 | pbrook | return cmos_ioport_read(s, addr >> s->it_shift) & 0xFF; |
591 | 2ca9d013 | ths | } |
592 | 2ca9d013 | ths | |
593 | 9596ebb7 | pbrook | static void cmos_mm_writeb (void *opaque, |
594 | 9596ebb7 | pbrook | target_phys_addr_t addr, uint32_t value) |
595 | 2ca9d013 | ths | { |
596 | 2ca9d013 | ths | RTCState *s = opaque; |
597 | 2ca9d013 | ths | |
598 | 8da3ff18 | pbrook | cmos_ioport_write(s, addr >> s->it_shift, value & 0xFF);
|
599 | 2ca9d013 | ths | } |
600 | 2ca9d013 | ths | |
601 | 9596ebb7 | pbrook | static uint32_t cmos_mm_readw (void *opaque, target_phys_addr_t addr) |
602 | 2ca9d013 | ths | { |
603 | 2ca9d013 | ths | RTCState *s = opaque; |
604 | 18c6e2ff | ths | uint32_t val; |
605 | 2ca9d013 | ths | |
606 | 8da3ff18 | pbrook | val = cmos_ioport_read(s, addr >> s->it_shift) & 0xFFFF;
|
607 | 18c6e2ff | ths | #ifdef TARGET_WORDS_BIGENDIAN
|
608 | 18c6e2ff | ths | val = bswap16(val); |
609 | 18c6e2ff | ths | #endif
|
610 | 18c6e2ff | ths | return val;
|
611 | 2ca9d013 | ths | } |
612 | 2ca9d013 | ths | |
613 | 9596ebb7 | pbrook | static void cmos_mm_writew (void *opaque, |
614 | 9596ebb7 | pbrook | target_phys_addr_t addr, uint32_t value) |
615 | 2ca9d013 | ths | { |
616 | 2ca9d013 | ths | RTCState *s = opaque; |
617 | 18c6e2ff | ths | #ifdef TARGET_WORDS_BIGENDIAN
|
618 | 18c6e2ff | ths | value = bswap16(value); |
619 | 18c6e2ff | ths | #endif
|
620 | 8da3ff18 | pbrook | cmos_ioport_write(s, addr >> s->it_shift, value & 0xFFFF);
|
621 | 2ca9d013 | ths | } |
622 | 2ca9d013 | ths | |
623 | 9596ebb7 | pbrook | static uint32_t cmos_mm_readl (void *opaque, target_phys_addr_t addr) |
624 | 2ca9d013 | ths | { |
625 | 2ca9d013 | ths | RTCState *s = opaque; |
626 | 18c6e2ff | ths | uint32_t val; |
627 | 2ca9d013 | ths | |
628 | 8da3ff18 | pbrook | val = cmos_ioport_read(s, addr >> s->it_shift); |
629 | 18c6e2ff | ths | #ifdef TARGET_WORDS_BIGENDIAN
|
630 | 18c6e2ff | ths | val = bswap32(val); |
631 | 18c6e2ff | ths | #endif
|
632 | 18c6e2ff | ths | return val;
|
633 | 2ca9d013 | ths | } |
634 | 2ca9d013 | ths | |
635 | 9596ebb7 | pbrook | static void cmos_mm_writel (void *opaque, |
636 | 9596ebb7 | pbrook | target_phys_addr_t addr, uint32_t value) |
637 | 2ca9d013 | ths | { |
638 | 2ca9d013 | ths | RTCState *s = opaque; |
639 | 18c6e2ff | ths | #ifdef TARGET_WORDS_BIGENDIAN
|
640 | 18c6e2ff | ths | value = bswap32(value); |
641 | 18c6e2ff | ths | #endif
|
642 | 8da3ff18 | pbrook | cmos_ioport_write(s, addr >> s->it_shift, value); |
643 | 2ca9d013 | ths | } |
644 | 2ca9d013 | ths | |
645 | 2ca9d013 | ths | static CPUReadMemoryFunc *rtc_mm_read[] = {
|
646 | 2ca9d013 | ths | &cmos_mm_readb, |
647 | 2ca9d013 | ths | &cmos_mm_readw, |
648 | 2ca9d013 | ths | &cmos_mm_readl, |
649 | 2ca9d013 | ths | }; |
650 | 2ca9d013 | ths | |
651 | 2ca9d013 | ths | static CPUWriteMemoryFunc *rtc_mm_write[] = {
|
652 | 2ca9d013 | ths | &cmos_mm_writeb, |
653 | 2ca9d013 | ths | &cmos_mm_writew, |
654 | 2ca9d013 | ths | &cmos_mm_writel, |
655 | 2ca9d013 | ths | }; |
656 | 2ca9d013 | ths | |
657 | 42fc73a1 | aurel32 | RTCState *rtc_mm_init(target_phys_addr_t base, int it_shift, qemu_irq irq,
|
658 | 42fc73a1 | aurel32 | int base_year)
|
659 | 2ca9d013 | ths | { |
660 | 2ca9d013 | ths | RTCState *s; |
661 | 2ca9d013 | ths | int io_memory;
|
662 | 2ca9d013 | ths | |
663 | 2ca9d013 | ths | s = qemu_mallocz(sizeof(RTCState));
|
664 | 2ca9d013 | ths | |
665 | 2ca9d013 | ths | s->irq = irq; |
666 | 2ca9d013 | ths | s->cmos_data[RTC_REG_A] = 0x26;
|
667 | 2ca9d013 | ths | s->cmos_data[RTC_REG_B] = 0x02;
|
668 | 2ca9d013 | ths | s->cmos_data[RTC_REG_C] = 0x00;
|
669 | 2ca9d013 | ths | s->cmos_data[RTC_REG_D] = 0x80;
|
670 | 2ca9d013 | ths | |
671 | 42fc73a1 | aurel32 | s->base_year = base_year; |
672 | 2ca9d013 | ths | rtc_set_date_from_host(s); |
673 | 2ca9d013 | ths | |
674 | 2ca9d013 | ths | s->periodic_timer = qemu_new_timer(vm_clock, |
675 | 2ca9d013 | ths | rtc_periodic_timer, s); |
676 | 2ca9d013 | ths | s->second_timer = qemu_new_timer(vm_clock, |
677 | 2ca9d013 | ths | rtc_update_second, s); |
678 | 2ca9d013 | ths | s->second_timer2 = qemu_new_timer(vm_clock, |
679 | 2ca9d013 | ths | rtc_update_second2, s); |
680 | 2ca9d013 | ths | |
681 | 2ca9d013 | ths | s->next_second_time = qemu_get_clock(vm_clock) + (ticks_per_sec * 99) / 100; |
682 | 2ca9d013 | ths | qemu_mod_timer(s->second_timer2, s->next_second_time); |
683 | 2ca9d013 | ths | |
684 | 2ca9d013 | ths | io_memory = cpu_register_io_memory(0, rtc_mm_read, rtc_mm_write, s);
|
685 | 18c6e2ff | ths | cpu_register_physical_memory(base, 2 << it_shift, io_memory);
|
686 | 2ca9d013 | ths | |
687 | 2ca9d013 | ths | register_savevm("mc146818rtc", base, 1, rtc_save, rtc_load, s); |
688 | 73822ec8 | aliguori | #ifdef TARGET_I386
|
689 | 73822ec8 | aliguori | if (rtc_td_hack)
|
690 | 73822ec8 | aliguori | register_savevm("mc146818rtc-td", base, 1, rtc_save_td, rtc_load_td, s); |
691 | 73822ec8 | aliguori | #endif
|
692 | 2ca9d013 | ths | return s;
|
693 | 2ca9d013 | ths | } |