Archipelago » qemu

/*

 * gdb server stub

 *

 * Copyright (c) 2003-2005 Fabrice Bellard

 *

 * This library is free software; you can redistribute it and/or

 * modify it under the terms of the GNU Lesser General Public

 * License as published by the Free Software Foundation; either

 * version 2 of the License, or (at your option) any later version.

 *

 * This library is distributed in the hope that it will be useful,

 * but WITHOUT ANY WARRANTY; without even the implied warranty of

 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU

 * Lesser General Public License for more details.

 *

 * You should have received a copy of the GNU Lesser General Public

 * License along with this library; if not, write to the Free Software

 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA

 */

#include "config.h"

#include "qemu-common.h"

#ifdef CONFIG_USER_ONLY

#include <stdlib.h>

#include <stdio.h>

#include <stdarg.h>

#include <string.h>

#include <errno.h>

#include <unistd.h>

#include <fcntl.h>

#include "qemu.h"

#else

#include "qemu-char.h"

#include "sysemu.h"

#include "gdbstub.h"

#endif

#define MAX_PACKET_LENGTH 4096

#include "qemu_socket.h"

#ifdef _WIN32

/* XXX: these constants may be independent of the host ones even for Unix */

#ifndef SIGTRAP

#define SIGTRAP 5

#endif

#ifndef SIGINT

#define SIGINT 2

#endif

#else

#include <signal.h>

#endif

//#define DEBUG_GDB

typedef struct GDBRegisterState {

    int base_reg;

    int num_regs;

    gdb_reg_cb get_reg;

    gdb_reg_cb set_reg;

    const char *xml;

    struct GDBRegisterState *next;

} GDBRegisterState;

enum RSState {

    RS_IDLE,

    RS_GETLINE,

    RS_CHKSUM1,

    RS_CHKSUM2,

    RS_SYSCALL,

};

typedef struct GDBState {

    CPUState *c_cpu; /* current CPU for step/continue ops */

    CPUState *g_cpu; /* current CPU for other ops */

    CPUState *query_cpu; /* for q{f|s}ThreadInfo */

    enum RSState state; /* parsing state */

    char line_buf[MAX_PACKET_LENGTH];

    int line_buf_index;

    int line_csum;

    uint8_t last_packet[MAX_PACKET_LENGTH + 4];

    int last_packet_len;

    int signal;

#ifdef CONFIG_USER_ONLY

    int fd;

    int running_state;

#else

    CharDriverState *chr;

#endif

} GDBState;

/* By default use no IRQs and no timers while single stepping so as to

 * make single stepping like an ICE HW step.

 */

static int sstep_flags = SSTEP_ENABLE|SSTEP_NOIRQ|SSTEP_NOTIMER;

static GDBState *gdbserver_state;

/* This is an ugly hack to cope with both new and old gdb.

   If gdb sends qXfer:features:read then assume we're talking to a newish

   gdb that understands target descriptions.  */

static int gdb_has_xml;

#ifdef CONFIG_USER_ONLY

/* XXX: This is not thread safe.  Do we care?  */

static int gdbserver_fd = -1;

static int get_char(GDBState *s)

{

    uint8_t ch;

    int ret;

    for(;;) {

        ret = recv(s->fd, &ch, 1, 0);

        if (ret < 0) {

            if (errno == ECONNRESET)

                s->fd = -1;

            if (errno != EINTR && errno != EAGAIN)

                return -1;

        } else if (ret == 0) {

            close(s->fd);

            s->fd = -1;

            return -1;

        } else {

            break;

        }

    }

    return ch;

}

#endif

static gdb_syscall_complete_cb gdb_current_syscall_cb;

enum {

    GDB_SYS_UNKNOWN,

    GDB_SYS_ENABLED,

    GDB_SYS_DISABLED,

} gdb_syscall_mode;

/* If gdb is connected when the first semihosting syscall occurs then use

   remote gdb syscalls.  Otherwise use native file IO.  */

int use_gdb_syscalls(void)

{

    if (gdb_syscall_mode == GDB_SYS_UNKNOWN) {

        gdb_syscall_mode = (gdbserver_state ? GDB_SYS_ENABLED

                                            : GDB_SYS_DISABLED);

    }

    return gdb_syscall_mode == GDB_SYS_ENABLED;

}

/* Resume execution.  */

static inline void gdb_continue(GDBState *s)

{

#ifdef CONFIG_USER_ONLY

    s->running_state = 1;

#else

    vm_start();

#endif

}

static void put_buffer(GDBState *s, const uint8_t *buf, int len)

{

#ifdef CONFIG_USER_ONLY

    int ret;

    while (len > 0) {

        ret = send(s->fd, buf, len, 0);

        if (ret < 0) {

            if (errno != EINTR && errno != EAGAIN)

                return;

        } else {

            buf += ret;

            len -= ret;

        }

    }

#else

    qemu_chr_write(s->chr, buf, len);

#endif

}

static inline int fromhex(int v)

{

    if (v >= '0' && v <= '9')

        return v - '0';

    else if (v >= 'A' && v <= 'F')

        return v - 'A' + 10;

    else if (v >= 'a' && v <= 'f')

        return v - 'a' + 10;

    else

        return 0;

}

static inline int tohex(int v)

{

    if (v < 10)

        return v + '0';

    else

        return v - 10 + 'a';

}

static void memtohex(char *buf, const uint8_t *mem, int len)

{

    int i, c;

    char *q;

    q = buf;

    for(i = 0; i < len; i++) {

        c = mem[i];

        *q++ = tohex(c >> 4);

        *q++ = tohex(c & 0xf);

    }

    *q = '\0';

}

static void hextomem(uint8_t *mem, const char *buf, int len)

{

    int i;

    for(i = 0; i < len; i++) {

        mem[i] = (fromhex(buf[0]) << 4) | fromhex(buf[1]);

        buf += 2;

    }

}

/* return -1 if error, 0 if OK */

static int put_packet_binary(GDBState *s, const char *buf, int len)

{

    int csum, i;

    uint8_t *p;

    for(;;) {

        p = s->last_packet;

        *(p++) = '$';

        memcpy(p, buf, len);

        p += len;

        csum = 0;

        for(i = 0; i < len; i++) {

            csum += buf[i];

        }

        *(p++) = '#';

        *(p++) = tohex((csum >> 4) & 0xf);

        *(p++) = tohex((csum) & 0xf);

        s->last_packet_len = p - s->last_packet;

        put_buffer(s, (uint8_t *)s->last_packet, s->last_packet_len);

#ifdef CONFIG_USER_ONLY

        i = get_char(s);

        if (i < 0)

            return -1;

        if (i == '+')

            break;

#else

        break;

#endif

    }

    return 0;

}

/* return -1 if error, 0 if OK */

static int put_packet(GDBState *s, const char *buf)

{

#ifdef DEBUG_GDB

    printf("reply='%s'\n", buf);

#endif

    return put_packet_binary(s, buf, strlen(buf));

}

/* The GDB remote protocol transfers values in target byte order.  This means

   we can use the raw memory access routines to access the value buffer.

   Conveniently, these also handle the case where the buffer is mis-aligned.

 */

#define GET_REG8(val) do { \

    stb_p(mem_buf, val); \

    return 1; \

    } while(0)

#define GET_REG16(val) do { \

    stw_p(mem_buf, val); \

    return 2; \

    } while(0)

#define GET_REG32(val) do { \

    stl_p(mem_buf, val); \

    return 4; \

    } while(0)

#define GET_REG64(val) do { \

    stq_p(mem_buf, val); \

    return 8; \

    } while(0)

#if TARGET_LONG_BITS == 64

#define GET_REGL(val) GET_REG64(val)

#define ldtul_p(addr) ldq_p(addr)

#else

#define GET_REGL(val) GET_REG32(val)

#define ldtul_p(addr) ldl_p(addr)

#endif

#if defined(TARGET_I386)

#ifdef TARGET_X86_64

static const int gpr_map[16] = {

    R_EAX, R_EBX, R_ECX, R_EDX, R_ESI, R_EDI, R_EBP, R_ESP,

    8, 9, 10, 11, 12, 13, 14, 15

};

#else

static const int gpr_map[8] = {0, 1, 2, 3, 4, 5, 6, 7};

#endif

#define NUM_CORE_REGS (CPU_NB_REGS * 2 + 25)

static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n)

{

    if (n < CPU_NB_REGS) {

        GET_REGL(env->regs[gpr_map[n]]);

    } else if (n >= CPU_NB_REGS + 8 && n < CPU_NB_REGS + 16) {

        /* FIXME: byteswap float values.  */

#ifdef USE_X86LDOUBLE

        memcpy(mem_buf, &env->fpregs[n - (CPU_NB_REGS + 8)], 10);

#else

        memset(mem_buf, 0, 10);

#endif

        return 10;

    } else if (n >= CPU_NB_REGS + 24) {

        n -= CPU_NB_REGS + 24;

        if (n < CPU_NB_REGS) {

            stq_p(mem_buf, env->xmm_regs[n].XMM_Q(0));

            stq_p(mem_buf + 8, env->xmm_regs[n].XMM_Q(1));

            return 16;

        } else if (n == CPU_NB_REGS) {

            GET_REG32(env->mxcsr);

        } 

    } else {

        n -= CPU_NB_REGS;

        switch (n) {

        case 0: GET_REGL(env->eip);

        case 1: GET_REG32(env->eflags);

        case 2: GET_REG32(env->segs[R_CS].selector);

        case 3: GET_REG32(env->segs[R_SS].selector);

        case 4: GET_REG32(env->segs[R_DS].selector);

        case 5: GET_REG32(env->segs[R_ES].selector);

        case 6: GET_REG32(env->segs[R_FS].selector);

        case 7: GET_REG32(env->segs[R_GS].selector);

        /* 8...15 x87 regs.  */

        case 16: GET_REG32(env->fpuc);

        case 17: GET_REG32((env->fpus & ~0x3800) | (env->fpstt & 0x7) << 11);

        case 18: GET_REG32(0); /* ftag */

        case 19: GET_REG32(0); /* fiseg */

        case 20: GET_REG32(0); /* fioff */

        case 21: GET_REG32(0); /* foseg */

        case 22: GET_REG32(0); /* fooff */

        case 23: GET_REG32(0); /* fop */

        /* 24+ xmm regs.  */

        }

    }

    return 0;

}

static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int i)

{

    uint32_t tmp;

    if (i < CPU_NB_REGS) {

        env->regs[gpr_map[i]] = ldtul_p(mem_buf);

        return sizeof(target_ulong);

    } else if (i >= CPU_NB_REGS + 8 && i < CPU_NB_REGS + 16) {

        i -= CPU_NB_REGS + 8;

#ifdef USE_X86LDOUBLE

        memcpy(&env->fpregs[i], mem_buf, 10);

#endif

        return 10;

    } else if (i >= CPU_NB_REGS + 24) {

        i -= CPU_NB_REGS + 24;

        if (i < CPU_NB_REGS) {

            env->xmm_regs[i].XMM_Q(0) = ldq_p(mem_buf);

            env->xmm_regs[i].XMM_Q(1) = ldq_p(mem_buf + 8);

            return 16;

        } else if (i == CPU_NB_REGS) {

            env->mxcsr = ldl_p(mem_buf);

            return 4;

        }

    } else {

        i -= CPU_NB_REGS;

        switch (i) {

        case 0: env->eip = ldtul_p(mem_buf); return sizeof(target_ulong);

        case 1: env->eflags = ldl_p(mem_buf); return 4;

#if defined(CONFIG_USER_ONLY)

#define LOAD_SEG(index, sreg)\

            tmp = ldl_p(mem_buf);\

            if (tmp != env->segs[sreg].selector)\

                cpu_x86_load_seg(env, sreg, tmp);

#else

/* FIXME: Honor segment registers.  Needs to avoid raising an exception

   when the selector is invalid.  */

#define LOAD_SEG(index, sreg) do {} while(0)

#endif

        case 2: LOAD_SEG(10, R_CS); return 4;

        case 3: LOAD_SEG(11, R_SS); return 4;

        case 4: LOAD_SEG(12, R_DS); return 4;

        case 5: LOAD_SEG(13, R_ES); return 4;

        case 6: LOAD_SEG(14, R_FS); return 4;

        case 7: LOAD_SEG(15, R_GS); return 4;

        /* 8...15 x87 regs.  */

        case 16: env->fpuc = ldl_p(mem_buf); return 4;

        case 17:

                 tmp = ldl_p(mem_buf);

                 env->fpstt = (tmp >> 11) & 7;

                 env->fpus = tmp & ~0x3800;

                 return 4;

        case 18: /* ftag */ return 4;

        case 19: /* fiseg */ return 4;

        case 20: /* fioff */ return 4;

        case 21: /* foseg */ return 4;

        case 22: /* fooff */ return 4;

        case 23: /* fop */ return 4;

        /* 24+ xmm regs.  */

        }

    }

    /* Unrecognised register.  */

    return 0;

}

#elif defined (TARGET_PPC)

#define NUM_CORE_REGS 71

static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n)

{

    if (n < 32) {

        /* gprs */

        GET_REGL(env->gpr[n]);

    } else if (n < 64) {

        /* fprs */

        stfq_p(mem_buf, env->fpr[n-32]);

        return 8;

    } else {

        switch (n) {

        case 64: GET_REGL(env->nip);

        case 65: GET_REGL(env->msr);

        case 66:

            {

                uint32_t cr = 0;

                int i;

                for (i = 0; i < 8; i++)

                    cr |= env->crf[i] << (32 - ((i + 1) * 4));

                GET_REG32(cr);

            }

        case 67: GET_REGL(env->lr);

        case 68: GET_REGL(env->ctr);

        case 69: GET_REGL(env->xer);

        case 70: GET_REG32(0); /* fpscr */

        }

    }

    return 0;

}

static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n)

{

    if (n < 32) {

        /* gprs */

        env->gpr[n] = ldtul_p(mem_buf);

        return sizeof(target_ulong);

    } else if (n < 64) {

        /* fprs */

        env->fpr[n-32] = ldfq_p(mem_buf);

        return 8;

    } else {

        switch (n) {

        case 64:

            env->nip = ldtul_p(mem_buf);

            return sizeof(target_ulong);

        case 65:

            ppc_store_msr(env, ldtul_p(mem_buf));

            return sizeof(target_ulong);

        case 66:

            {

                uint32_t cr = ldl_p(mem_buf);

                int i;

                for (i = 0; i < 8; i++)

                    env->crf[i] = (cr >> (32 - ((i + 1) * 4))) & 0xF;

                return 4;

            }

        case 67:

            env->lr = ldtul_p(mem_buf);

            return sizeof(target_ulong);

        case 68:

            env->ctr = ldtul_p(mem_buf);

            return sizeof(target_ulong);

        case 69:

            env->xer = ldtul_p(mem_buf);

            return sizeof(target_ulong);

        case 70:

            /* fpscr */

            return 4;

        }

    }

    return 0;

}

#elif defined (TARGET_SPARC)

#if defined(TARGET_SPARC64) && !defined(TARGET_ABI32)

#define NUM_CORE_REGS 86

#else

#define NUM_CORE_REGS 73

#endif

#ifdef TARGET_ABI32

#define GET_REGA(val) GET_REG32(val)

#else

#define GET_REGA(val) GET_REGL(val)

#endif

static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n)

{

    if (n < 8) {

        /* g0..g7 */

        GET_REGA(env->gregs[n]);

    }

    if (n < 32) {

        /* register window */

        GET_REGA(env->regwptr[n - 8]);

    }

#if defined(TARGET_ABI32) || !defined(TARGET_SPARC64)

    if (n < 64) {

        /* fprs */

        GET_REG32(*((uint32_t *)&env->fpr[n - 32]));

    }

    /* Y, PSR, WIM, TBR, PC, NPC, FPSR, CPSR */

    switch (n) {

    case 64: GET_REGA(env->y);

    case 65: GET_REGA(GET_PSR(env));

    case 66: GET_REGA(env->wim);

    case 67: GET_REGA(env->tbr);

    case 68: GET_REGA(env->pc);

    case 69: GET_REGA(env->npc);

    case 70: GET_REGA(env->fsr);

    case 71: GET_REGA(0); /* csr */

    case 72: GET_REGA(0);

    }

#else

    if (n < 64) {

        /* f0-f31 */

        GET_REG32(*((uint32_t *)&env->fpr[n - 32]));

    }

    if (n < 80) {

        /* f32-f62 (double width, even numbers only) */

        uint64_t val;

        val = (uint64_t)*((uint32_t *)&env->fpr[(n - 64) * 2 + 32]) << 32;

        val |= *((uint32_t *)&env->fpr[(n - 64) * 2 + 33]);

        GET_REG64(val);

    }

    switch (n) {

    case 80: GET_REGL(env->pc);

    case 81: GET_REGL(env->npc);

    case 82: GET_REGL(((uint64_t)GET_CCR(env) << 32) |

                           ((env->asi & 0xff) << 24) |

                           ((env->pstate & 0xfff) << 8) |

                           GET_CWP64(env));

    case 83: GET_REGL(env->fsr);

    case 84: GET_REGL(env->fprs);

    case 85: GET_REGL(env->y);

    }

#endif

    return 0;

}

static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n)

{

#if defined(TARGET_ABI32)

    abi_ulong tmp;

    tmp = ldl_p(mem_buf);

#else

    target_ulong tmp;

    tmp = ldtul_p(mem_buf);

#endif

    if (n < 8) {

        /* g0..g7 */

        env->gregs[n] = tmp;

    } else if (n < 32) {

        /* register window */

        env->regwptr[n - 8] = tmp;

    }

#if defined(TARGET_ABI32) || !defined(TARGET_SPARC64)

    else if (n < 64) {

        /* fprs */

        *((uint32_t *)&env->fpr[n - 32]) = tmp;

    } else {

        /* Y, PSR, WIM, TBR, PC, NPC, FPSR, CPSR */

        switch (n) {

        case 64: env->y = tmp; break;

        case 65: PUT_PSR(env, tmp); break;

        case 66: env->wim = tmp; break;

        case 67: env->tbr = tmp; break;

        case 68: env->pc = tmp; break;

        case 69: env->npc = tmp; break;

        case 70: env->fsr = tmp; break;

        default: return 0;

        }

    }

    return 4;

#else

    else if (n < 64) {

        /* f0-f31 */

        env->fpr[n] = ldfl_p(mem_buf);

        return 4;

    } else if (n < 80) {

        /* f32-f62 (double width, even numbers only) */

        *((uint32_t *)&env->fpr[(n - 64) * 2 + 32]) = tmp >> 32;

        *((uint32_t *)&env->fpr[(n - 64) * 2 + 33]) = tmp;

    } else {

        switch (n) {

        case 80: env->pc = tmp; break;

        case 81: env->npc = tmp; break;

        case 82:

            PUT_CCR(env, tmp >> 32);

            env->asi = (tmp >> 24) & 0xff;

            env->pstate = (tmp >> 8) & 0xfff;

            PUT_CWP64(env, tmp & 0xff);

            break;

        case 83: env->fsr = tmp; break;

        case 84: env->fprs = tmp; break;

        case 85: env->y = tmp; break;

        default: return 0;

        }

    }

    return 8;

#endif

}

#elif defined (TARGET_ARM)

/* Old gdb always expect FPA registers.  Newer (xml-aware) gdb only expect

   whatever the target description contains.  Due to a historical mishap

   the FPA registers appear in between core integer regs and the CPSR.

   We hack round this by giving the FPA regs zero size when talking to a

   newer gdb.  */

#define NUM_CORE_REGS 26

#define GDB_CORE_XML "arm-core.xml"

static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n)

{

    if (n < 16) {

        /* Core integer register.  */

        GET_REG32(env->regs[n]);

    }

    if (n < 24) {

        /* FPA registers.  */

        if (gdb_has_xml)

            return 0;

        memset(mem_buf, 0, 12);

        return 12;

    }

    switch (n) {

    case 24:

        /* FPA status register.  */

        if (gdb_has_xml)

            return 0;

        GET_REG32(0);

    case 25:

        /* CPSR */

        GET_REG32(cpsr_read(env));

    }

    /* Unknown register.  */

    return 0;

}

static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n)

{

    uint32_t tmp;

    tmp = ldl_p(mem_buf);

    /* Mask out low bit of PC to workaround gdb bugs.  This will probably

       cause problems if we ever implement the Jazelle DBX extensions.  */

    if (n == 15)

        tmp &= ~1;

    if (n < 16) {

        /* Core integer register.  */

        env->regs[n] = tmp;

        return 4;

    }

    if (n < 24) { /* 16-23 */

        /* FPA registers (ignored).  */

        if (gdb_has_xml)

            return 0;

        return 12;

    }

    switch (n) {

    case 24:

        /* FPA status register (ignored).  */

        if (gdb_has_xml)

            return 0;

        return 4;

    case 25:

        /* CPSR */

        cpsr_write (env, tmp, 0xffffffff);

        return 4;

    }

    /* Unknown register.  */

    return 0;

}

#elif defined (TARGET_M68K)

#define NUM_CORE_REGS 18

#define GDB_CORE_XML "cf-core.xml"

static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n)

{

    if (n < 8) {

        /* D0-D7 */

        GET_REG32(env->dregs[n]);

    } else if (n < 16) {

        /* A0-A7 */

        GET_REG32(env->aregs[n - 8]);

    } else {

        switch (n) {

        case 16: GET_REG32(env->sr);

        case 17: GET_REG32(env->pc);

        }

    }

    /* FP registers not included here because they vary between

       ColdFire and m68k.  Use XML bits for these.  */

    return 0;

}

static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n)

{

    uint32_t tmp;

    tmp = ldl_p(mem_buf);

    if (n < 8) {

        /* D0-D7 */

        env->dregs[n] = tmp;

    } else if (n < 8) {

        /* A0-A7 */

        env->aregs[n - 8] = tmp;

    } else {

        switch (n) {

        case 16: env->sr = tmp; break;

        case 17: env->pc = tmp; break;

        default: return 0;

        }

    }

    return 4;

}

#elif defined (TARGET_MIPS)

#define NUM_CORE_REGS 73

static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n)

{

    if (n < 32) {

        GET_REGL(env->active_tc.gpr[n]);

    }

    if (env->CP0_Config1 & (1 << CP0C1_FP)) {

        if (n >= 38 && n < 70) {

            if (env->CP0_Status & (1 << CP0St_FR))

                GET_REGL(env->active_fpu.fpr[n - 38].d);

            else

                GET_REGL(env->active_fpu.fpr[n - 38].w[FP_ENDIAN_IDX]);

        }

        switch (n) {

        case 70: GET_REGL((int32_t)env->active_fpu.fcr31);

        case 71: GET_REGL((int32_t)env->active_fpu.fcr0);

        }

    }

    switch (n) {

    case 32: GET_REGL((int32_t)env->CP0_Status);

    case 33: GET_REGL(env->active_tc.LO[0]);

    case 34: GET_REGL(env->active_tc.HI[0]);

    case 35: GET_REGL(env->CP0_BadVAddr);

    case 36: GET_REGL((int32_t)env->CP0_Cause);

    case 37: GET_REGL(env->active_tc.PC);

    case 72: GET_REGL(0); /* fp */

    case 89: GET_REGL((int32_t)env->CP0_PRid);

    }

    if (n >= 73 && n <= 88) {

        /* 16 embedded regs.  */

        GET_REGL(0);

    }

    return 0;

}

/* convert MIPS rounding mode in FCR31 to IEEE library */

static unsigned int ieee_rm[] =

  {

    float_round_nearest_even,

    float_round_to_zero,

    float_round_up,

    float_round_down

  };

#define RESTORE_ROUNDING_MODE \

    set_float_rounding_mode(ieee_rm[env->active_fpu.fcr31 & 3], &env->active_fpu.fp_status)

static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n)

{

    target_ulong tmp;

    tmp = ldtul_p(mem_buf);

    if (n < 32) {

        env->active_tc.gpr[n] = tmp;

        return sizeof(target_ulong);

    }

    if (env->CP0_Config1 & (1 << CP0C1_FP)

            && n >= 38 && n < 73) {

        if (n < 70) {

            if (env->CP0_Status & (1 << CP0St_FR))

              env->active_fpu.fpr[n - 38].d = tmp;

            else

              env->active_fpu.fpr[n - 38].w[FP_ENDIAN_IDX] = tmp;

        }

        switch (n) {

        case 70:

            env->active_fpu.fcr31 = tmp & 0xFF83FFFF;

            /* set rounding mode */

            RESTORE_ROUNDING_MODE;

#ifndef CONFIG_SOFTFLOAT

            /* no floating point exception for native float */

            SET_FP_ENABLE(env->active_fpu.fcr31, 0);

#endif

            break;

        case 71: env->active_fpu.fcr0 = tmp; break;

        }

        return sizeof(target_ulong);

    }

    switch (n) {

    case 32: env->CP0_Status = tmp; break;

    case 33: env->active_tc.LO[0] = tmp; break;

    case 34: env->active_tc.HI[0] = tmp; break;

    case 35: env->CP0_BadVAddr = tmp; break;

    case 36: env->CP0_Cause = tmp; break;

    case 37: env->active_tc.PC = tmp; break;

    case 72: /* fp, ignored */ break;

    default: 

        if (n > 89)

            return 0;

        /* Other registers are readonly.  Ignore writes.  */

        break;

    }

    return sizeof(target_ulong);

}

#elif defined (TARGET_SH4)

/* Hint: Use "set architecture sh4" in GDB to see fpu registers */

/* FIXME: We should use XML for this.  */