Revision 8098ed41 hw/pci.c

b/hw/pci.c
381 381 
            case 0x0b:
382 382 
            case 0x0e:
383 383 
            case 0x10 ... 0x27: /* base */
384 
            case 0x2c ... 0x2f: /* read-only subsystem ID & vendor ID */
384 385 
            case 0x30 ... 0x33: /* rom */
385 386 
            case 0x3d:
386 387 
                can_write = 0;
......
402 403 
            case 0x0a:
403 404 
            case 0x0b:
404 405 
            case 0x0e:
406 
            case 0x2c ... 0x2f: /* read-only subsystem ID & vendor ID */
405 407 
            case 0x38 ... 0x3b: /* rom */
406 408 
            case 0x3d:
407 409 
                can_write = 0;
......
413 415 
            break;
414 416 
        }
415 417 
        if (can_write) {
418 
            /* Mask out writes to reserved bits in registers */
419 
            switch (addr) {
420 
            case 0x06:
421 
                val &= ~PCI_STATUS_RESERVED_MASK_LO;
422 
                break;
423 
            case 0x07:
424 
                val &= ~PCI_STATUS_RESERVED_MASK_HI;
425 
                break;
426 
            }
416 427 
            d->config[addr] = val;
417 428 
        }
418 429 
        if (++addr > 0xff)

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