root / target-unicore32 / helper.c @ 8141905a
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/*
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* Copyright (C) 2010-2011 GUAN Xue-tao
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include "cpu.h" |
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#include "gdbstub.h" |
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#include "helper.h" |
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#include "host-utils.h" |
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static inline void set_feature(CPUState *env, int feature) |
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{
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env->features |= feature; |
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} |
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struct uc32_cpu_t {
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uint32_t id; |
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const char *name; |
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}; |
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static const struct uc32_cpu_t uc32_cpu_names[] = { |
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{ UC32_CPUID_UCV2, "UniCore-II"},
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{ UC32_CPUID_ANY, "any"},
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{ 0, NULL}
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}; |
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/* return 0 if not found */
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static uint32_t uc32_cpu_find_by_name(const char *name) |
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{
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int i;
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uint32_t id; |
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id = 0;
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for (i = 0; uc32_cpu_names[i].name; i++) { |
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if (strcmp(name, uc32_cpu_names[i].name) == 0) { |
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id = uc32_cpu_names[i].id; |
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break;
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} |
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} |
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return id;
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} |
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CPUState *uc32_cpu_init(const char *cpu_model) |
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{
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CPUState *env; |
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uint32_t id; |
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static int inited = 1; |
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|
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env = g_malloc0(sizeof(CPUState));
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cpu_exec_init(env); |
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id = uc32_cpu_find_by_name(cpu_model); |
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switch (id) {
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case UC32_CPUID_UCV2:
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set_feature(env, UC32_HWCAP_CMOV); |
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set_feature(env, UC32_HWCAP_UCF64); |
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env->ucf64.xregs[UC32_UCF64_FPSCR] = 0;
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env->cp0.c0_cachetype = 0x1dd20d2;
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env->cp0.c1_sys = 0x00090078;
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break;
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case UC32_CPUID_ANY: /* For userspace emulation. */ |
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set_feature(env, UC32_HWCAP_CMOV); |
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set_feature(env, UC32_HWCAP_UCF64); |
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break;
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default:
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cpu_abort(env, "Bad CPU ID: %x\n", id);
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} |
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env->cpu_model_str = cpu_model; |
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env->cp0.c0_cpuid = id; |
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env->uncached_asr = ASR_MODE_USER; |
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env->regs[31] = 0; |
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if (inited) {
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inited = 0;
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uc32_translate_init(); |
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} |
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tlb_flush(env, 1);
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qemu_init_vcpu(env); |
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return env;
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} |
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uint32_t HELPER(clo)(uint32_t x) |
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{
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return clo32(x);
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} |
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uint32_t HELPER(clz)(uint32_t x) |
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{
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return clz32(x);
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} |
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void do_interrupt(CPUState *env)
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{
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env->exception_index = -1;
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} |
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int uc32_cpu_handle_mmu_fault(CPUState *env, target_ulong address, int rw, |
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int mmu_idx)
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{
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env->exception_index = UC32_EXCP_TRAP; |
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env->cp0.c4_faultaddr = address; |
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return 1; |
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} |
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/* These should probably raise undefined insn exceptions. */
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void HELPER(set_cp)(CPUState *env, uint32_t insn, uint32_t val)
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{
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int op1 = (insn >> 8) & 0xf; |
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cpu_abort(env, "cp%i insn %08x\n", op1, insn);
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return;
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} |
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uint32_t HELPER(get_cp)(CPUState *env, uint32_t insn) |
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{
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int op1 = (insn >> 8) & 0xf; |
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cpu_abort(env, "cp%i insn %08x\n", op1, insn);
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return 0; |
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} |
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void HELPER(set_cp0)(CPUState *env, uint32_t insn, uint32_t val)
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{
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cpu_abort(env, "cp0 insn %08x\n", insn);
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} |
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uint32_t HELPER(get_cp0)(CPUState *env, uint32_t insn) |
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{
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cpu_abort(env, "cp0 insn %08x\n", insn);
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return 0; |
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} |
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void switch_mode(CPUState *env, int mode) |
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{
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if (mode != ASR_MODE_USER) {
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cpu_abort(env, "Tried to switch out of user mode\n");
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} |
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} |
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void HELPER(set_r29_banked)(CPUState *env, uint32_t mode, uint32_t val)
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{
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cpu_abort(env, "banked r29 write\n");
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} |
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uint32_t HELPER(get_r29_banked)(CPUState *env, uint32_t mode) |
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{
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cpu_abort(env, "banked r29 read\n");
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return 0; |
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} |
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/* UniCore-F64 support. We follow the convention used for F64 instrunctions:
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Single precition routines have a "s" suffix, double precision a
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"d" suffix. */
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/* Convert host exception flags to f64 form. */
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static inline int ucf64_exceptbits_from_host(int host_bits) |
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{
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int target_bits = 0; |
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if (host_bits & float_flag_invalid) {
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target_bits |= UCF64_FPSCR_FLAG_INVALID; |
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} |
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if (host_bits & float_flag_divbyzero) {
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target_bits |= UCF64_FPSCR_FLAG_DIVZERO; |
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} |
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if (host_bits & float_flag_overflow) {
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target_bits |= UCF64_FPSCR_FLAG_OVERFLOW; |
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} |
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if (host_bits & float_flag_underflow) {
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target_bits |= UCF64_FPSCR_FLAG_UNDERFLOW; |
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} |
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if (host_bits & float_flag_inexact) {
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target_bits |= UCF64_FPSCR_FLAG_INEXACT; |
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} |
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return target_bits;
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} |
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uint32_t HELPER(ucf64_get_fpscr)(CPUState *env) |
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{
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int i;
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uint32_t fpscr; |
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fpscr = (env->ucf64.xregs[UC32_UCF64_FPSCR] & UCF64_FPSCR_MASK); |
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i = get_float_exception_flags(&env->ucf64.fp_status); |
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fpscr |= ucf64_exceptbits_from_host(i); |
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return fpscr;
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} |
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/* Convert ucf64 exception flags to target form. */
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static inline int ucf64_exceptbits_to_host(int target_bits) |
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{
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int host_bits = 0; |
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if (target_bits & UCF64_FPSCR_FLAG_INVALID) {
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host_bits |= float_flag_invalid; |
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} |
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if (target_bits & UCF64_FPSCR_FLAG_DIVZERO) {
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host_bits |= float_flag_divbyzero; |
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} |
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if (target_bits & UCF64_FPSCR_FLAG_OVERFLOW) {
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host_bits |= float_flag_overflow; |
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} |
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if (target_bits & UCF64_FPSCR_FLAG_UNDERFLOW) {
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host_bits |= float_flag_underflow; |
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} |
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if (target_bits & UCF64_FPSCR_FLAG_INEXACT) {
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host_bits |= float_flag_inexact; |
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} |
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return host_bits;
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} |
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void HELPER(ucf64_set_fpscr)(CPUState *env, uint32_t val)
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{
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int i;
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uint32_t changed; |
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changed = env->ucf64.xregs[UC32_UCF64_FPSCR]; |
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env->ucf64.xregs[UC32_UCF64_FPSCR] = (val & UCF64_FPSCR_MASK); |
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changed ^= val; |
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if (changed & (UCF64_FPSCR_RND_MASK)) {
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i = UCF64_FPSCR_RND(val); |
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switch (i) {
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case 0: |
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i = float_round_nearest_even; |
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break;
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case 1: |
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i = float_round_to_zero; |
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break;
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case 2: |
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i = float_round_up; |
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break;
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case 3: |
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i = float_round_down; |
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break;
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default: /* 100 and 101 not implement */ |
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cpu_abort(env, "Unsupported UniCore-F64 round mode");
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} |
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set_float_rounding_mode(i, &env->ucf64.fp_status); |
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} |
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i = ucf64_exceptbits_to_host(UCF64_FPSCR_TRAPEN(val)); |
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set_float_exception_flags(i, &env->ucf64.fp_status); |
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} |
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float32 HELPER(ucf64_adds)(float32 a, float32 b, CPUState *env) |
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{
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return float32_add(a, b, &env->ucf64.fp_status);
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} |
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float64 HELPER(ucf64_addd)(float64 a, float64 b, CPUState *env) |
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{
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return float64_add(a, b, &env->ucf64.fp_status);
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} |
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float32 HELPER(ucf64_subs)(float32 a, float32 b, CPUState *env) |
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{
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return float32_sub(a, b, &env->ucf64.fp_status);
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} |
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float64 HELPER(ucf64_subd)(float64 a, float64 b, CPUState *env) |
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{
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return float64_sub(a, b, &env->ucf64.fp_status);
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} |
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float32 HELPER(ucf64_muls)(float32 a, float32 b, CPUState *env) |
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{
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return float32_mul(a, b, &env->ucf64.fp_status);
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} |
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float64 HELPER(ucf64_muld)(float64 a, float64 b, CPUState *env) |
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{
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return float64_mul(a, b, &env->ucf64.fp_status);
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} |
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float32 HELPER(ucf64_divs)(float32 a, float32 b, CPUState *env) |
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{
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return float32_div(a, b, &env->ucf64.fp_status);
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} |
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float64 HELPER(ucf64_divd)(float64 a, float64 b, CPUState *env) |
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{
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return float64_div(a, b, &env->ucf64.fp_status);
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} |
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float32 HELPER(ucf64_negs)(float32 a) |
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{
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return float32_chs(a);
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} |
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float64 HELPER(ucf64_negd)(float64 a) |
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{
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return float64_chs(a);
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} |
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float32 HELPER(ucf64_abss)(float32 a) |
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{
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return float32_abs(a);
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} |
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float64 HELPER(ucf64_absd)(float64 a) |
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{
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return float64_abs(a);
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} |
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/* XXX: check quiet/signaling case */
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void HELPER(ucf64_cmps)(float32 a, float32 b, uint32_t c, CPUState *env)
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{
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int flag;
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flag = float32_compare_quiet(a, b, &env->ucf64.fp_status); |
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env->CF = 0;
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switch (c & 0x7) { |
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case 0: /* F */ |
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break;
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case 1: /* UN */ |
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if (flag == 2) { |
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env->CF = 1;
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} |
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break;
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case 2: /* EQ */ |
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if (flag == 0) { |
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env->CF = 1;
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} |
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break;
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case 3: /* UEQ */ |
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if ((flag == 0) || (flag == 2)) { |
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env->CF = 1;
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} |
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break;
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case 4: /* OLT */ |
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if (flag == -1) { |
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env->CF = 1;
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} |
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break;
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case 5: /* ULT */ |
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if ((flag == -1) || (flag == 2)) { |
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env->CF = 1;
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} |
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break;
|
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case 6: /* OLE */ |
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if ((flag == -1) || (flag == 0)) { |
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env->CF = 1;
|
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} |
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break;
|
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case 7: /* ULE */ |
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if (flag != 1) { |
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env->CF = 1;
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} |
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break;
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} |
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env->ucf64.xregs[UC32_UCF64_FPSCR] = (env->CF << 29)
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| (env->ucf64.xregs[UC32_UCF64_FPSCR] & 0x0fffffff);
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} |
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|
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void HELPER(ucf64_cmpd)(float64 a, float64 b, uint32_t c, CPUState *env)
|
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{
|
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int flag;
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flag = float64_compare_quiet(a, b, &env->ucf64.fp_status); |
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env->CF = 0;
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switch (c & 0x7) { |
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case 0: /* F */ |
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break;
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case 1: /* UN */ |
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if (flag == 2) { |
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env->CF = 1;
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} |
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break;
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case 2: /* EQ */ |
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if (flag == 0) { |
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env->CF = 1;
|
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} |
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break;
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case 3: /* UEQ */ |
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if ((flag == 0) || (flag == 2)) { |
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env->CF = 1;
|
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} |
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break;
|
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case 4: /* OLT */ |
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if (flag == -1) { |
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env->CF = 1;
|
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} |
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break;
|
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case 5: /* ULT */ |
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if ((flag == -1) || (flag == 2)) { |
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env->CF = 1;
|
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} |
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break;
|
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case 6: /* OLE */ |
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if ((flag == -1) || (flag == 0)) { |
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env->CF = 1;
|
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} |
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break;
|
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case 7: /* ULE */ |
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if (flag != 1) { |
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env->CF = 1;
|
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} |
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break;
|
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} |
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env->ucf64.xregs[UC32_UCF64_FPSCR] = (env->CF << 29)
|
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| (env->ucf64.xregs[UC32_UCF64_FPSCR] & 0x0fffffff);
|
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} |
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|
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/* Helper routines to perform bitwise copies between float and int. */
|
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static inline float32 ucf64_itos(uint32_t i) |
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{
|
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union {
|
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uint32_t i; |
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float32 s; |
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} v; |
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|
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v.i = i; |
| 415 |
return v.s;
|
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} |
| 417 |
|
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static inline uint32_t ucf64_stoi(float32 s) |
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{
|
| 420 |
union {
|
| 421 |
uint32_t i; |
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float32 s; |
| 423 |
} v; |
| 424 |
|
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v.s = s; |
| 426 |
return v.i;
|
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} |
| 428 |
|
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static inline float64 ucf64_itod(uint64_t i) |
| 430 |
{
|
| 431 |
union {
|
| 432 |
uint64_t i; |
| 433 |
float64 d; |
| 434 |
} v; |
| 435 |
|
| 436 |
v.i = i; |
| 437 |
return v.d;
|
| 438 |
} |
| 439 |
|
| 440 |
static inline uint64_t ucf64_dtoi(float64 d) |
| 441 |
{
|
| 442 |
union {
|
| 443 |
uint64_t i; |
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float64 d; |
| 445 |
} v; |
| 446 |
|
| 447 |
v.d = d; |
| 448 |
return v.i;
|
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} |
| 450 |
|
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/* Integer to float conversion. */
|
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float32 HELPER(ucf64_si2sf)(float32 x, CPUState *env) |
| 453 |
{
|
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return int32_to_float32(ucf64_stoi(x), &env->ucf64.fp_status);
|
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} |
| 456 |
|
| 457 |
float64 HELPER(ucf64_si2df)(float32 x, CPUState *env) |
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{
|
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return int32_to_float64(ucf64_stoi(x), &env->ucf64.fp_status);
|
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} |
| 461 |
|
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/* Float to integer conversion. */
|
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float32 HELPER(ucf64_sf2si)(float32 x, CPUState *env) |
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{
|
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return ucf64_itos(float32_to_int32(x, &env->ucf64.fp_status));
|
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} |
| 467 |
|
| 468 |
float32 HELPER(ucf64_df2si)(float64 x, CPUState *env) |
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{
|
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return ucf64_itos(float64_to_int32(x, &env->ucf64.fp_status));
|
| 471 |
} |
| 472 |
|
| 473 |
/* floating point conversion */
|
| 474 |
float64 HELPER(ucf64_sf2df)(float32 x, CPUState *env) |
| 475 |
{
|
| 476 |
return float32_to_float64(x, &env->ucf64.fp_status);
|
| 477 |
} |
| 478 |
|
| 479 |
float32 HELPER(ucf64_df2sf)(float64 x, CPUState *env) |
| 480 |
{
|
| 481 |
return float64_to_float32(x, &env->ucf64.fp_status);
|
| 482 |
} |