root / target-ppc / translate_init.c @ 814589c4
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/*
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* PowerPC CPU initialization for qemu.
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*
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* Copyright (c) 2003-2007 Jocelyn Mayer
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* Copyright 2011 Freescale Semiconductor, Inc.
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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/* A lot of PowerPC definition have been included here.
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* Most of them are not usable for now but have been kept
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* inside "#if defined(TODO) ... #endif" statements to make tests easier.
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*/
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#include "dis-asm.h" |
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#include "gdbstub.h" |
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#include <kvm.h> |
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#include "kvm_ppc.h" |
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//#define PPC_DUMP_CPU
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//#define PPC_DEBUG_SPR
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//#define PPC_DUMP_SPR_ACCESSES
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#if defined(CONFIG_USER_ONLY)
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#define TODO_USER_ONLY 1 |
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#endif
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/* For user-mode emulation, we don't emulate any IRQ controller */
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#if defined(CONFIG_USER_ONLY)
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#define PPC_IRQ_INIT_FN(name) \
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static inline void glue(glue(ppc, name),_irq_init) (CPUPPCState *env) \ |
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{ \ |
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} |
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#else
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#define PPC_IRQ_INIT_FN(name) \
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void glue(glue(ppc, name),_irq_init) (CPUPPCState *env);
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#endif
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PPC_IRQ_INIT_FN(40x);
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PPC_IRQ_INIT_FN(6xx);
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PPC_IRQ_INIT_FN(970);
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PPC_IRQ_INIT_FN(POWER7); |
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PPC_IRQ_INIT_FN(e500); |
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/* Generic callbacks:
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* do nothing but store/retrieve spr value
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*/
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static void spr_load_dump_spr(int sprn) |
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{ |
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#ifdef PPC_DUMP_SPR_ACCESSES
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TCGv_i32 t0 = tcg_const_i32(sprn); |
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gen_helper_load_dump_spr(t0); |
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tcg_temp_free_i32(t0); |
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#endif
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} |
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static void spr_read_generic (void *opaque, int gprn, int sprn) |
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{ |
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gen_load_spr(cpu_gpr[gprn], sprn); |
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spr_load_dump_spr(sprn); |
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} |
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static void spr_store_dump_spr(int sprn) |
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{ |
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#ifdef PPC_DUMP_SPR_ACCESSES
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TCGv_i32 t0 = tcg_const_i32(sprn); |
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gen_helper_store_dump_spr(t0); |
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tcg_temp_free_i32(t0); |
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#endif
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} |
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static void spr_write_generic (void *opaque, int sprn, int gprn) |
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{ |
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gen_store_spr(sprn, cpu_gpr[gprn]); |
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spr_store_dump_spr(sprn); |
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} |
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#if !defined(CONFIG_USER_ONLY)
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static void spr_write_generic32(void *opaque, int sprn, int gprn) |
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{ |
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#ifdef TARGET_PPC64
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TCGv t0 = tcg_temp_new(); |
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tcg_gen_ext32u_tl(t0, cpu_gpr[gprn]); |
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gen_store_spr(sprn, t0); |
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tcg_temp_free(t0); |
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spr_store_dump_spr(sprn); |
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#else
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spr_write_generic(opaque, sprn, gprn); |
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#endif
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} |
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static void spr_write_clear (void *opaque, int sprn, int gprn) |
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{ |
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TCGv t0 = tcg_temp_new(); |
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TCGv t1 = tcg_temp_new(); |
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gen_load_spr(t0, sprn); |
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tcg_gen_neg_tl(t1, cpu_gpr[gprn]); |
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tcg_gen_and_tl(t0, t0, t1); |
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gen_store_spr(sprn, t0); |
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tcg_temp_free(t0); |
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tcg_temp_free(t1); |
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} |
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#endif
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/* SPR common to all PowerPC */
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/* XER */
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static void spr_read_xer (void *opaque, int gprn, int sprn) |
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{ |
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tcg_gen_mov_tl(cpu_gpr[gprn], cpu_xer); |
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} |
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static void spr_write_xer (void *opaque, int sprn, int gprn) |
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{ |
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tcg_gen_mov_tl(cpu_xer, cpu_gpr[gprn]); |
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} |
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/* LR */
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static void spr_read_lr (void *opaque, int gprn, int sprn) |
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{ |
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tcg_gen_mov_tl(cpu_gpr[gprn], cpu_lr); |
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} |
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static void spr_write_lr (void *opaque, int sprn, int gprn) |
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{ |
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tcg_gen_mov_tl(cpu_lr, cpu_gpr[gprn]); |
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} |
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/* CFAR */
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#if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY)
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static void spr_read_cfar (void *opaque, int gprn, int sprn) |
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{ |
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tcg_gen_mov_tl(cpu_gpr[gprn], cpu_cfar); |
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} |
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static void spr_write_cfar (void *opaque, int sprn, int gprn) |
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{ |
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tcg_gen_mov_tl(cpu_cfar, cpu_gpr[gprn]); |
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} |
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#endif /* defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) */ |
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/* CTR */
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static void spr_read_ctr (void *opaque, int gprn, int sprn) |
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{ |
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tcg_gen_mov_tl(cpu_gpr[gprn], cpu_ctr); |
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} |
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static void spr_write_ctr (void *opaque, int sprn, int gprn) |
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{ |
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tcg_gen_mov_tl(cpu_ctr, cpu_gpr[gprn]); |
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} |
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/* User read access to SPR */
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/* USPRx */
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/* UMMCRx */
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/* UPMCx */
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/* USIA */
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/* UDECR */
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static void spr_read_ureg (void *opaque, int gprn, int sprn) |
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{ |
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gen_load_spr(cpu_gpr[gprn], sprn + 0x10);
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} |
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/* SPR common to all non-embedded PowerPC */
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/* DECR */
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#if !defined(CONFIG_USER_ONLY)
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static void spr_read_decr (void *opaque, int gprn, int sprn) |
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{ |
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if (use_icount) {
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gen_io_start(); |
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} |
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gen_helper_load_decr(cpu_gpr[gprn], cpu_env); |
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if (use_icount) {
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gen_io_end(); |
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gen_stop_exception(opaque); |
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} |
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} |
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static void spr_write_decr (void *opaque, int sprn, int gprn) |
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{ |
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if (use_icount) {
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gen_io_start(); |
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} |
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gen_helper_store_decr(cpu_env, cpu_gpr[gprn]); |
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if (use_icount) {
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gen_io_end(); |
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gen_stop_exception(opaque); |
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} |
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} |
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#endif
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/* SPR common to all non-embedded PowerPC, except 601 */
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/* Time base */
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static void spr_read_tbl (void *opaque, int gprn, int sprn) |
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{ |
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if (use_icount) {
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gen_io_start(); |
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} |
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gen_helper_load_tbl(cpu_gpr[gprn], cpu_env); |
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if (use_icount) {
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gen_io_end(); |
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gen_stop_exception(opaque); |
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} |
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} |
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static void spr_read_tbu (void *opaque, int gprn, int sprn) |
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{ |
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if (use_icount) {
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gen_io_start(); |
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} |
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gen_helper_load_tbu(cpu_gpr[gprn], cpu_env); |
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if (use_icount) {
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gen_io_end(); |
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gen_stop_exception(opaque); |
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} |
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} |
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__attribute__ (( unused )) |
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static void spr_read_atbl (void *opaque, int gprn, int sprn) |
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{ |
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gen_helper_load_atbl(cpu_gpr[gprn], cpu_env); |
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} |
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__attribute__ (( unused )) |
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static void spr_read_atbu (void *opaque, int gprn, int sprn) |
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{ |
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gen_helper_load_atbu(cpu_gpr[gprn], cpu_env); |
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} |
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#if !defined(CONFIG_USER_ONLY)
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static void spr_write_tbl (void *opaque, int sprn, int gprn) |
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{ |
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if (use_icount) {
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gen_io_start(); |
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} |
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gen_helper_store_tbl(cpu_env, cpu_gpr[gprn]); |
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if (use_icount) {
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gen_io_end(); |
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gen_stop_exception(opaque); |
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} |
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} |
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static void spr_write_tbu (void *opaque, int sprn, int gprn) |
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{ |
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if (use_icount) {
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gen_io_start(); |
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} |
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gen_helper_store_tbu(cpu_env, cpu_gpr[gprn]); |
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if (use_icount) {
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gen_io_end(); |
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gen_stop_exception(opaque); |
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} |
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} |
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__attribute__ (( unused )) |
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static void spr_write_atbl (void *opaque, int sprn, int gprn) |
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{ |
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gen_helper_store_atbl(cpu_env, cpu_gpr[gprn]); |
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} |
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__attribute__ (( unused )) |
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static void spr_write_atbu (void *opaque, int sprn, int gprn) |
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{ |
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gen_helper_store_atbu(cpu_env, cpu_gpr[gprn]); |
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} |
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#if defined(TARGET_PPC64)
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__attribute__ (( unused )) |
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static void spr_read_purr (void *opaque, int gprn, int sprn) |
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{ |
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gen_helper_load_purr(cpu_gpr[gprn], cpu_env); |
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} |
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#endif
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#endif
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#if !defined(CONFIG_USER_ONLY)
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/* IBAT0U...IBAT0U */
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/* IBAT0L...IBAT7L */
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static void spr_read_ibat (void *opaque, int gprn, int sprn) |
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{ |
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tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, IBAT[sprn & 1][(sprn - SPR_IBAT0U) / 2])); |
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} |
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static void spr_read_ibat_h (void *opaque, int gprn, int sprn) |
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{ |
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tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, IBAT[sprn & 1][(sprn - SPR_IBAT4U) / 2])); |
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} |
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static void spr_write_ibatu (void *opaque, int sprn, int gprn) |
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{ |
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TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2);
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gen_helper_store_ibatu(cpu_env, t0, cpu_gpr[gprn]); |
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tcg_temp_free_i32(t0); |
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} |
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static void spr_write_ibatu_h (void *opaque, int sprn, int gprn) |
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{ |
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TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_IBAT4U) / 2) + 4); |
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gen_helper_store_ibatu(cpu_env, t0, cpu_gpr[gprn]); |
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tcg_temp_free_i32(t0); |
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} |
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static void spr_write_ibatl (void *opaque, int sprn, int gprn) |
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{ |
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TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0L) / 2);
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gen_helper_store_ibatl(cpu_env, t0, cpu_gpr[gprn]); |
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tcg_temp_free_i32(t0); |
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} |
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static void spr_write_ibatl_h (void *opaque, int sprn, int gprn) |
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{ |
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TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_IBAT4L) / 2) + 4); |
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gen_helper_store_ibatl(cpu_env, t0, cpu_gpr[gprn]); |
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tcg_temp_free_i32(t0); |
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} |
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/* DBAT0U...DBAT7U */
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/* DBAT0L...DBAT7L */
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static void spr_read_dbat (void *opaque, int gprn, int sprn) |
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{ |
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tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, DBAT[sprn & 1][(sprn - SPR_DBAT0U) / 2])); |
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} |
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static void spr_read_dbat_h (void *opaque, int gprn, int sprn) |
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{ |
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tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, DBAT[sprn & 1][((sprn - SPR_DBAT4U) / 2) + 4])); |
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} |
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static void spr_write_dbatu (void *opaque, int sprn, int gprn) |
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{ |
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TCGv_i32 t0 = tcg_const_i32((sprn - SPR_DBAT0U) / 2);
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gen_helper_store_dbatu(cpu_env, t0, cpu_gpr[gprn]); |
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tcg_temp_free_i32(t0); |
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} |
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static void spr_write_dbatu_h (void *opaque, int sprn, int gprn) |
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{ |
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TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_DBAT4U) / 2) + 4); |
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gen_helper_store_dbatu(cpu_env, t0, cpu_gpr[gprn]); |
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tcg_temp_free_i32(t0); |
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} |
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static void spr_write_dbatl (void *opaque, int sprn, int gprn) |
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{ |
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TCGv_i32 t0 = tcg_const_i32((sprn - SPR_DBAT0L) / 2);
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gen_helper_store_dbatl(cpu_env, t0, cpu_gpr[gprn]); |
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tcg_temp_free_i32(t0); |
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} |
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static void spr_write_dbatl_h (void *opaque, int sprn, int gprn) |
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{ |
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TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_DBAT4L) / 2) + 4); |
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gen_helper_store_dbatl(cpu_env, t0, cpu_gpr[gprn]); |
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tcg_temp_free_i32(t0); |
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} |
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/* SDR1 */
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static void spr_write_sdr1 (void *opaque, int sprn, int gprn) |
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{ |
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gen_helper_store_sdr1(cpu_env, cpu_gpr[gprn]); |
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} |
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/* 64 bits PowerPC specific SPRs */
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/* ASR */
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#if defined(TARGET_PPC64)
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static void spr_read_hior (void *opaque, int gprn, int sprn) |
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{ |
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tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, excp_prefix)); |
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} |
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static void spr_write_hior (void *opaque, int sprn, int gprn) |
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{ |
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TCGv t0 = tcg_temp_new(); |
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tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0x3FFFFF00000ULL);
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tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_prefix)); |
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tcg_temp_free(t0); |
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} |
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static void spr_read_asr (void *opaque, int gprn, int sprn) |
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{ |
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tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, asr)); |
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} |
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static void spr_write_asr (void *opaque, int sprn, int gprn) |
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{ |
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gen_helper_store_asr(cpu_env, cpu_gpr[gprn]); |
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} |
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#endif
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#endif
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|
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/* PowerPC 601 specific registers */
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/* RTC */
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static void spr_read_601_rtcl (void *opaque, int gprn, int sprn) |
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{ |
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gen_helper_load_601_rtcl(cpu_gpr[gprn], cpu_env); |
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} |
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static void spr_read_601_rtcu (void *opaque, int gprn, int sprn) |
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{ |
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gen_helper_load_601_rtcu(cpu_gpr[gprn], cpu_env); |
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} |
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|
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#if !defined(CONFIG_USER_ONLY)
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static void spr_write_601_rtcu (void *opaque, int sprn, int gprn) |
414 |
{ |
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gen_helper_store_601_rtcu(cpu_env, cpu_gpr[gprn]); |
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} |
417 |
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static void spr_write_601_rtcl (void *opaque, int sprn, int gprn) |
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{ |
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gen_helper_store_601_rtcl(cpu_env, cpu_gpr[gprn]); |
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} |
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static void spr_write_hid0_601 (void *opaque, int sprn, int gprn) |
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{ |
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DisasContext *ctx = opaque; |
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gen_helper_store_hid0_601(cpu_env, cpu_gpr[gprn]); |
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/* Must stop the translation as endianness may have changed */
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gen_stop_exception(ctx); |
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} |
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#endif
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|
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/* Unified bats */
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#if !defined(CONFIG_USER_ONLY)
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static void spr_read_601_ubat (void *opaque, int gprn, int sprn) |
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{ |
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tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, IBAT[sprn & 1][(sprn - SPR_IBAT0U) / 2])); |
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} |
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static void spr_write_601_ubatu (void *opaque, int sprn, int gprn) |
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{ |
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TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2);
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gen_helper_store_601_batl(cpu_env, t0, cpu_gpr[gprn]); |
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tcg_temp_free_i32(t0); |
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} |
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static void spr_write_601_ubatl (void *opaque, int sprn, int gprn) |
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{ |
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TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2);
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gen_helper_store_601_batu(cpu_env, t0, cpu_gpr[gprn]); |
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tcg_temp_free_i32(t0); |
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} |
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#endif
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|
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/* PowerPC 40x specific registers */
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#if !defined(CONFIG_USER_ONLY)
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static void spr_read_40x_pit (void *opaque, int gprn, int sprn) |
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{ |
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gen_helper_load_40x_pit(cpu_gpr[gprn], cpu_env); |
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} |
461 |
|
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static void spr_write_40x_pit (void *opaque, int sprn, int gprn) |
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{ |
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gen_helper_store_40x_pit(cpu_env, cpu_gpr[gprn]); |
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} |
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static void spr_write_40x_dbcr0 (void *opaque, int sprn, int gprn) |
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{ |
469 |
DisasContext *ctx = opaque; |
470 |
|
471 |
gen_helper_store_40x_dbcr0(cpu_env, cpu_gpr[gprn]); |
472 |
/* We must stop translation as we may have rebooted */
|
473 |
gen_stop_exception(ctx); |
474 |
} |
475 |
|
476 |
static void spr_write_40x_sler (void *opaque, int sprn, int gprn) |
477 |
{ |
478 |
gen_helper_store_40x_sler(cpu_env, cpu_gpr[gprn]); |
479 |
} |
480 |
|
481 |
static void spr_write_booke_tcr (void *opaque, int sprn, int gprn) |
482 |
{ |
483 |
gen_helper_store_booke_tcr(cpu_env, cpu_gpr[gprn]); |
484 |
} |
485 |
|
486 |
static void spr_write_booke_tsr (void *opaque, int sprn, int gprn) |
487 |
{ |
488 |
gen_helper_store_booke_tsr(cpu_env, cpu_gpr[gprn]); |
489 |
} |
490 |
#endif
|
491 |
|
492 |
/* PowerPC 403 specific registers */
|
493 |
/* PBL1 / PBU1 / PBL2 / PBU2 */
|
494 |
#if !defined(CONFIG_USER_ONLY)
|
495 |
static void spr_read_403_pbr (void *opaque, int gprn, int sprn) |
496 |
{ |
497 |
tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, pb[sprn - SPR_403_PBL1])); |
498 |
} |
499 |
|
500 |
static void spr_write_403_pbr (void *opaque, int sprn, int gprn) |
501 |
{ |
502 |
TCGv_i32 t0 = tcg_const_i32(sprn - SPR_403_PBL1); |
503 |
gen_helper_store_403_pbr(cpu_env, t0, cpu_gpr[gprn]); |
504 |
tcg_temp_free_i32(t0); |
505 |
} |
506 |
|
507 |
static void spr_write_pir (void *opaque, int sprn, int gprn) |
508 |
{ |
509 |
TCGv t0 = tcg_temp_new(); |
510 |
tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0xF);
|
511 |
gen_store_spr(SPR_PIR, t0); |
512 |
tcg_temp_free(t0); |
513 |
} |
514 |
#endif
|
515 |
|
516 |
/* SPE specific registers */
|
517 |
static void spr_read_spefscr (void *opaque, int gprn, int sprn) |
518 |
{ |
519 |
TCGv_i32 t0 = tcg_temp_new_i32(); |
520 |
tcg_gen_ld_i32(t0, cpu_env, offsetof(CPUPPCState, spe_fscr)); |
521 |
tcg_gen_extu_i32_tl(cpu_gpr[gprn], t0); |
522 |
tcg_temp_free_i32(t0); |
523 |
} |
524 |
|
525 |
static void spr_write_spefscr (void *opaque, int sprn, int gprn) |
526 |
{ |
527 |
TCGv_i32 t0 = tcg_temp_new_i32(); |
528 |
tcg_gen_trunc_tl_i32(t0, cpu_gpr[gprn]); |
529 |
tcg_gen_st_i32(t0, cpu_env, offsetof(CPUPPCState, spe_fscr)); |
530 |
tcg_temp_free_i32(t0); |
531 |
} |
532 |
|
533 |
#if !defined(CONFIG_USER_ONLY)
|
534 |
/* Callback used to write the exception vector base */
|
535 |
static void spr_write_excp_prefix (void *opaque, int sprn, int gprn) |
536 |
{ |
537 |
TCGv t0 = tcg_temp_new(); |
538 |
tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUPPCState, ivpr_mask)); |
539 |
tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]); |
540 |
tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_prefix)); |
541 |
gen_store_spr(sprn, t0); |
542 |
tcg_temp_free(t0); |
543 |
} |
544 |
|
545 |
static void spr_write_excp_vector (void *opaque, int sprn, int gprn) |
546 |
{ |
547 |
DisasContext *ctx = opaque; |
548 |
int sprn_offs;
|
549 |
|
550 |
if (sprn >= SPR_BOOKE_IVOR0 && sprn <= SPR_BOOKE_IVOR15) {
|
551 |
sprn_offs = sprn - SPR_BOOKE_IVOR0; |
552 |
} else if (sprn >= SPR_BOOKE_IVOR32 && sprn <= SPR_BOOKE_IVOR37) { |
553 |
sprn_offs = sprn - SPR_BOOKE_IVOR32 + 32;
|
554 |
} else if (sprn >= SPR_BOOKE_IVOR38 && sprn <= SPR_BOOKE_IVOR42) { |
555 |
sprn_offs = sprn - SPR_BOOKE_IVOR38 + 38;
|
556 |
} else {
|
557 |
printf("Trying to write an unknown exception vector %d %03x\n",
|
558 |
sprn, sprn); |
559 |
gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
560 |
return;
|
561 |
} |
562 |
|
563 |
TCGv t0 = tcg_temp_new(); |
564 |
tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUPPCState, ivor_mask)); |
565 |
tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]); |
566 |
tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_vectors[sprn_offs])); |
567 |
gen_store_spr(sprn, t0); |
568 |
tcg_temp_free(t0); |
569 |
} |
570 |
#endif
|
571 |
|
572 |
static inline void vscr_init (CPUPPCState *env, uint32_t val) |
573 |
{ |
574 |
env->vscr = val; |
575 |
/* Altivec always uses round-to-nearest */
|
576 |
set_float_rounding_mode(float_round_nearest_even, &env->vec_status); |
577 |
set_flush_to_zero(vscr_nj, &env->vec_status); |
578 |
} |
579 |
|
580 |
#if defined(CONFIG_USER_ONLY)
|
581 |
#define spr_register(env, num, name, uea_read, uea_write, \
|
582 |
oea_read, oea_write, initial_value) \ |
583 |
do { \
|
584 |
_spr_register(env, num, name, uea_read, uea_write, initial_value); \ |
585 |
} while (0) |
586 |
static inline void _spr_register (CPUPPCState *env, int num, |
587 |
const char *name, |
588 |
void (*uea_read)(void *opaque, int gprn, int sprn), |
589 |
void (*uea_write)(void *opaque, int sprn, int gprn), |
590 |
target_ulong initial_value) |
591 |
#else
|
592 |
static inline void spr_register (CPUPPCState *env, int num, |
593 |
const char *name, |
594 |
void (*uea_read)(void *opaque, int gprn, int sprn), |
595 |
void (*uea_write)(void *opaque, int sprn, int gprn), |
596 |
void (*oea_read)(void *opaque, int gprn, int sprn), |
597 |
void (*oea_write)(void *opaque, int sprn, int gprn), |
598 |
target_ulong initial_value) |
599 |
#endif
|
600 |
{ |
601 |
ppc_spr_t *spr; |
602 |
|
603 |
spr = &env->spr_cb[num]; |
604 |
if (spr->name != NULL ||env-> spr[num] != 0x00000000 || |
605 |
#if !defined(CONFIG_USER_ONLY)
|
606 |
spr->oea_read != NULL || spr->oea_write != NULL || |
607 |
#endif
|
608 |
spr->uea_read != NULL || spr->uea_write != NULL) { |
609 |
printf("Error: Trying to register SPR %d (%03x) twice !\n", num, num);
|
610 |
exit(1);
|
611 |
} |
612 |
#if defined(PPC_DEBUG_SPR)
|
613 |
printf("*** register spr %d (%03x) %s val " TARGET_FMT_lx "\n", num, num, |
614 |
name, initial_value); |
615 |
#endif
|
616 |
spr->name = name; |
617 |
spr->uea_read = uea_read; |
618 |
spr->uea_write = uea_write; |
619 |
#if !defined(CONFIG_USER_ONLY)
|
620 |
spr->oea_read = oea_read; |
621 |
spr->oea_write = oea_write; |
622 |
#endif
|
623 |
env->spr[num] = initial_value; |
624 |
} |
625 |
|
626 |
/* Generic PowerPC SPRs */
|
627 |
static void gen_spr_generic (CPUPPCState *env) |
628 |
{ |
629 |
/* Integer processing */
|
630 |
spr_register(env, SPR_XER, "XER",
|
631 |
&spr_read_xer, &spr_write_xer, |
632 |
&spr_read_xer, &spr_write_xer, |
633 |
0x00000000);
|
634 |
/* Branch contol */
|
635 |
spr_register(env, SPR_LR, "LR",
|
636 |
&spr_read_lr, &spr_write_lr, |
637 |
&spr_read_lr, &spr_write_lr, |
638 |
0x00000000);
|
639 |
spr_register(env, SPR_CTR, "CTR",
|
640 |
&spr_read_ctr, &spr_write_ctr, |
641 |
&spr_read_ctr, &spr_write_ctr, |
642 |
0x00000000);
|
643 |
/* Interrupt processing */
|
644 |
spr_register(env, SPR_SRR0, "SRR0",
|
645 |
SPR_NOACCESS, SPR_NOACCESS, |
646 |
&spr_read_generic, &spr_write_generic, |
647 |
0x00000000);
|
648 |
spr_register(env, SPR_SRR1, "SRR1",
|
649 |
SPR_NOACCESS, SPR_NOACCESS, |
650 |
&spr_read_generic, &spr_write_generic, |
651 |
0x00000000);
|
652 |
/* Processor control */
|
653 |
spr_register(env, SPR_SPRG0, "SPRG0",
|
654 |
SPR_NOACCESS, SPR_NOACCESS, |
655 |
&spr_read_generic, &spr_write_generic, |
656 |
0x00000000);
|
657 |
spr_register(env, SPR_SPRG1, "SPRG1",
|
658 |
SPR_NOACCESS, SPR_NOACCESS, |
659 |
&spr_read_generic, &spr_write_generic, |
660 |
0x00000000);
|
661 |
spr_register(env, SPR_SPRG2, "SPRG2",
|
662 |
SPR_NOACCESS, SPR_NOACCESS, |
663 |
&spr_read_generic, &spr_write_generic, |
664 |
0x00000000);
|
665 |
spr_register(env, SPR_SPRG3, "SPRG3",
|
666 |
SPR_NOACCESS, SPR_NOACCESS, |
667 |
&spr_read_generic, &spr_write_generic, |
668 |
0x00000000);
|
669 |
} |
670 |
|
671 |
/* SPR common to all non-embedded PowerPC, including 601 */
|
672 |
static void gen_spr_ne_601 (CPUPPCState *env) |
673 |
{ |
674 |
/* Exception processing */
|
675 |
spr_register(env, SPR_DSISR, "DSISR",
|
676 |
SPR_NOACCESS, SPR_NOACCESS, |
677 |
&spr_read_generic, &spr_write_generic, |
678 |
0x00000000);
|
679 |
spr_register(env, SPR_DAR, "DAR",
|
680 |
SPR_NOACCESS, SPR_NOACCESS, |
681 |
&spr_read_generic, &spr_write_generic, |
682 |
0x00000000);
|
683 |
/* Timer */
|
684 |
spr_register(env, SPR_DECR, "DECR",
|
685 |
SPR_NOACCESS, SPR_NOACCESS, |
686 |
&spr_read_decr, &spr_write_decr, |
687 |
0x00000000);
|
688 |
/* Memory management */
|
689 |
spr_register(env, SPR_SDR1, "SDR1",
|
690 |
SPR_NOACCESS, SPR_NOACCESS, |
691 |
&spr_read_generic, &spr_write_sdr1, |
692 |
0x00000000);
|
693 |
} |
694 |
|
695 |
/* BATs 0-3 */
|
696 |
static void gen_low_BATs (CPUPPCState *env) |
697 |
{ |
698 |
#if !defined(CONFIG_USER_ONLY)
|
699 |
spr_register(env, SPR_IBAT0U, "IBAT0U",
|
700 |
SPR_NOACCESS, SPR_NOACCESS, |
701 |
&spr_read_ibat, &spr_write_ibatu, |
702 |
0x00000000);
|
703 |
spr_register(env, SPR_IBAT0L, "IBAT0L",
|
704 |
SPR_NOACCESS, SPR_NOACCESS, |
705 |
&spr_read_ibat, &spr_write_ibatl, |
706 |
0x00000000);
|
707 |
spr_register(env, SPR_IBAT1U, "IBAT1U",
|
708 |
SPR_NOACCESS, SPR_NOACCESS, |
709 |
&spr_read_ibat, &spr_write_ibatu, |
710 |
0x00000000);
|
711 |
spr_register(env, SPR_IBAT1L, "IBAT1L",
|
712 |
SPR_NOACCESS, SPR_NOACCESS, |
713 |
&spr_read_ibat, &spr_write_ibatl, |
714 |
0x00000000);
|
715 |
spr_register(env, SPR_IBAT2U, "IBAT2U",
|
716 |
SPR_NOACCESS, SPR_NOACCESS, |
717 |
&spr_read_ibat, &spr_write_ibatu, |
718 |
0x00000000);
|
719 |
spr_register(env, SPR_IBAT2L, "IBAT2L",
|
720 |
SPR_NOACCESS, SPR_NOACCESS, |
721 |
&spr_read_ibat, &spr_write_ibatl, |
722 |
0x00000000);
|
723 |
spr_register(env, SPR_IBAT3U, "IBAT3U",
|
724 |
SPR_NOACCESS, SPR_NOACCESS, |
725 |
&spr_read_ibat, &spr_write_ibatu, |
726 |
0x00000000);
|
727 |
spr_register(env, SPR_IBAT3L, "IBAT3L",
|
728 |
SPR_NOACCESS, SPR_NOACCESS, |
729 |
&spr_read_ibat, &spr_write_ibatl, |
730 |
0x00000000);
|
731 |
spr_register(env, SPR_DBAT0U, "DBAT0U",
|
732 |
SPR_NOACCESS, SPR_NOACCESS, |
733 |
&spr_read_dbat, &spr_write_dbatu, |
734 |
0x00000000);
|
735 |
spr_register(env, SPR_DBAT0L, "DBAT0L",
|
736 |
SPR_NOACCESS, SPR_NOACCESS, |
737 |
&spr_read_dbat, &spr_write_dbatl, |
738 |
0x00000000);
|
739 |
spr_register(env, SPR_DBAT1U, "DBAT1U",
|
740 |
SPR_NOACCESS, SPR_NOACCESS, |
741 |
&spr_read_dbat, &spr_write_dbatu, |
742 |
0x00000000);
|
743 |
spr_register(env, SPR_DBAT1L, "DBAT1L",
|
744 |
SPR_NOACCESS, SPR_NOACCESS, |
745 |
&spr_read_dbat, &spr_write_dbatl, |
746 |
0x00000000);
|
747 |
spr_register(env, SPR_DBAT2U, "DBAT2U",
|
748 |
SPR_NOACCESS, SPR_NOACCESS, |
749 |
&spr_read_dbat, &spr_write_dbatu, |
750 |
0x00000000);
|
751 |
spr_register(env, SPR_DBAT2L, "DBAT2L",
|
752 |
SPR_NOACCESS, SPR_NOACCESS, |
753 |
&spr_read_dbat, &spr_write_dbatl, |
754 |
0x00000000);
|
755 |
spr_register(env, SPR_DBAT3U, "DBAT3U",
|
756 |
SPR_NOACCESS, SPR_NOACCESS, |
757 |
&spr_read_dbat, &spr_write_dbatu, |
758 |
0x00000000);
|
759 |
spr_register(env, SPR_DBAT3L, "DBAT3L",
|
760 |
SPR_NOACCESS, SPR_NOACCESS, |
761 |
&spr_read_dbat, &spr_write_dbatl, |
762 |
0x00000000);
|
763 |
env->nb_BATs += 4;
|
764 |
#endif
|
765 |
} |
766 |
|
767 |
/* BATs 4-7 */
|
768 |
static void gen_high_BATs (CPUPPCState *env) |
769 |
{ |
770 |
#if !defined(CONFIG_USER_ONLY)
|
771 |
spr_register(env, SPR_IBAT4U, "IBAT4U",
|
772 |
SPR_NOACCESS, SPR_NOACCESS, |
773 |
&spr_read_ibat_h, &spr_write_ibatu_h, |
774 |
0x00000000);
|
775 |
spr_register(env, SPR_IBAT4L, "IBAT4L",
|
776 |
SPR_NOACCESS, SPR_NOACCESS, |
777 |
&spr_read_ibat_h, &spr_write_ibatl_h, |
778 |
0x00000000);
|
779 |
spr_register(env, SPR_IBAT5U, "IBAT5U",
|
780 |
SPR_NOACCESS, SPR_NOACCESS, |
781 |
&spr_read_ibat_h, &spr_write_ibatu_h, |
782 |
0x00000000);
|
783 |
spr_register(env, SPR_IBAT5L, "IBAT5L",
|
784 |
SPR_NOACCESS, SPR_NOACCESS, |
785 |
&spr_read_ibat_h, &spr_write_ibatl_h, |
786 |
0x00000000);
|
787 |
spr_register(env, SPR_IBAT6U, "IBAT6U",
|
788 |
SPR_NOACCESS, SPR_NOACCESS, |
789 |
&spr_read_ibat_h, &spr_write_ibatu_h, |
790 |
0x00000000);
|
791 |
spr_register(env, SPR_IBAT6L, "IBAT6L",
|
792 |
SPR_NOACCESS, SPR_NOACCESS, |
793 |
&spr_read_ibat_h, &spr_write_ibatl_h, |
794 |
0x00000000);
|
795 |
spr_register(env, SPR_IBAT7U, "IBAT7U",
|
796 |
SPR_NOACCESS, SPR_NOACCESS, |
797 |
&spr_read_ibat_h, &spr_write_ibatu_h, |
798 |
0x00000000);
|
799 |
spr_register(env, SPR_IBAT7L, "IBAT7L",
|
800 |
SPR_NOACCESS, SPR_NOACCESS, |
801 |
&spr_read_ibat_h, &spr_write_ibatl_h, |
802 |
0x00000000);
|
803 |
spr_register(env, SPR_DBAT4U, "DBAT4U",
|
804 |
SPR_NOACCESS, SPR_NOACCESS, |
805 |
&spr_read_dbat_h, &spr_write_dbatu_h, |
806 |
0x00000000);
|
807 |
spr_register(env, SPR_DBAT4L, "DBAT4L",
|
808 |
SPR_NOACCESS, SPR_NOACCESS, |
809 |
&spr_read_dbat_h, &spr_write_dbatl_h, |
810 |
0x00000000);
|
811 |
spr_register(env, SPR_DBAT5U, "DBAT5U",
|
812 |
SPR_NOACCESS, SPR_NOACCESS, |
813 |
&spr_read_dbat_h, &spr_write_dbatu_h, |
814 |
0x00000000);
|
815 |
spr_register(env, SPR_DBAT5L, "DBAT5L",
|
816 |
SPR_NOACCESS, SPR_NOACCESS, |
817 |
&spr_read_dbat_h, &spr_write_dbatl_h, |
818 |
0x00000000);
|
819 |
spr_register(env, SPR_DBAT6U, "DBAT6U",
|
820 |
SPR_NOACCESS, SPR_NOACCESS, |
821 |
&spr_read_dbat_h, &spr_write_dbatu_h, |
822 |
0x00000000);
|
823 |
spr_register(env, SPR_DBAT6L, "DBAT6L",
|
824 |
SPR_NOACCESS, SPR_NOACCESS, |
825 |
&spr_read_dbat_h, &spr_write_dbatl_h, |
826 |
0x00000000);
|
827 |
spr_register(env, SPR_DBAT7U, "DBAT7U",
|
828 |
SPR_NOACCESS, SPR_NOACCESS, |
829 |
&spr_read_dbat_h, &spr_write_dbatu_h, |
830 |
0x00000000);
|
831 |
spr_register(env, SPR_DBAT7L, "DBAT7L",
|
832 |
SPR_NOACCESS, SPR_NOACCESS, |
833 |
&spr_read_dbat_h, &spr_write_dbatl_h, |
834 |
0x00000000);
|
835 |
env->nb_BATs += 4;
|
836 |
#endif
|
837 |
} |
838 |
|
839 |
/* Generic PowerPC time base */
|
840 |
static void gen_tbl (CPUPPCState *env) |
841 |
{ |
842 |
spr_register(env, SPR_VTBL, "TBL",
|
843 |
&spr_read_tbl, SPR_NOACCESS, |
844 |
&spr_read_tbl, SPR_NOACCESS, |
845 |
0x00000000);
|
846 |
spr_register(env, SPR_TBL, "TBL",
|
847 |
&spr_read_tbl, SPR_NOACCESS, |
848 |
&spr_read_tbl, &spr_write_tbl, |
849 |
0x00000000);
|
850 |
spr_register(env, SPR_VTBU, "TBU",
|
851 |
&spr_read_tbu, SPR_NOACCESS, |
852 |
&spr_read_tbu, SPR_NOACCESS, |
853 |
0x00000000);
|
854 |
spr_register(env, SPR_TBU, "TBU",
|
855 |
&spr_read_tbu, SPR_NOACCESS, |
856 |
&spr_read_tbu, &spr_write_tbu, |
857 |
0x00000000);
|
858 |
} |
859 |
|
860 |
/* Softare table search registers */
|
861 |
static void gen_6xx_7xx_soft_tlb (CPUPPCState *env, int nb_tlbs, int nb_ways) |
862 |
{ |
863 |
#if !defined(CONFIG_USER_ONLY)
|
864 |
env->nb_tlb = nb_tlbs; |
865 |
env->nb_ways = nb_ways; |
866 |
env->id_tlbs = 1;
|
867 |
env->tlb_type = TLB_6XX; |
868 |
spr_register(env, SPR_DMISS, "DMISS",
|
869 |
SPR_NOACCESS, SPR_NOACCESS, |
870 |
&spr_read_generic, SPR_NOACCESS, |
871 |
0x00000000);
|
872 |
spr_register(env, SPR_DCMP, "DCMP",
|
873 |
SPR_NOACCESS, SPR_NOACCESS, |
874 |
&spr_read_generic, SPR_NOACCESS, |
875 |
0x00000000);
|
876 |
spr_register(env, SPR_HASH1, "HASH1",
|
877 |
SPR_NOACCESS, SPR_NOACCESS, |
878 |
&spr_read_generic, SPR_NOACCESS, |
879 |
0x00000000);
|
880 |
spr_register(env, SPR_HASH2, "HASH2",
|
881 |
SPR_NOACCESS, SPR_NOACCESS, |
882 |
&spr_read_generic, SPR_NOACCESS, |
883 |
0x00000000);
|
884 |
spr_register(env, SPR_IMISS, "IMISS",
|
885 |
SPR_NOACCESS, SPR_NOACCESS, |
886 |
&spr_read_generic, SPR_NOACCESS, |
887 |
0x00000000);
|
888 |
spr_register(env, SPR_ICMP, "ICMP",
|
889 |
SPR_NOACCESS, SPR_NOACCESS, |
890 |
&spr_read_generic, SPR_NOACCESS, |
891 |
0x00000000);
|
892 |
spr_register(env, SPR_RPA, "RPA",
|
893 |
SPR_NOACCESS, SPR_NOACCESS, |
894 |
&spr_read_generic, &spr_write_generic, |
895 |
0x00000000);
|
896 |
#endif
|
897 |
} |
898 |
|
899 |
/* SPR common to MPC755 and G2 */
|
900 |
static void gen_spr_G2_755 (CPUPPCState *env) |
901 |
{ |
902 |
/* SGPRs */
|
903 |
spr_register(env, SPR_SPRG4, "SPRG4",
|
904 |
SPR_NOACCESS, SPR_NOACCESS, |
905 |
&spr_read_generic, &spr_write_generic, |
906 |
0x00000000);
|
907 |
spr_register(env, SPR_SPRG5, "SPRG5",
|
908 |
SPR_NOACCESS, SPR_NOACCESS, |
909 |
&spr_read_generic, &spr_write_generic, |
910 |
0x00000000);
|
911 |
spr_register(env, SPR_SPRG6, "SPRG6",
|
912 |
SPR_NOACCESS, SPR_NOACCESS, |
913 |
&spr_read_generic, &spr_write_generic, |
914 |
0x00000000);
|
915 |
spr_register(env, SPR_SPRG7, "SPRG7",
|
916 |
SPR_NOACCESS, SPR_NOACCESS, |
917 |
&spr_read_generic, &spr_write_generic, |
918 |
0x00000000);
|
919 |
} |
920 |
|
921 |
/* SPR common to all 7xx PowerPC implementations */
|
922 |
static void gen_spr_7xx (CPUPPCState *env) |
923 |
{ |
924 |
/* Breakpoints */
|
925 |
/* XXX : not implemented */
|
926 |
spr_register(env, SPR_DABR, "DABR",
|
927 |
SPR_NOACCESS, SPR_NOACCESS, |
928 |
&spr_read_generic, &spr_write_generic, |
929 |
0x00000000);
|
930 |
/* XXX : not implemented */
|
931 |
spr_register(env, SPR_IABR, "IABR",
|
932 |
SPR_NOACCESS, SPR_NOACCESS, |
933 |
&spr_read_generic, &spr_write_generic, |
934 |
0x00000000);
|
935 |
/* Cache management */
|
936 |
/* XXX : not implemented */
|
937 |
spr_register(env, SPR_ICTC, "ICTC",
|
938 |
SPR_NOACCESS, SPR_NOACCESS, |
939 |
&spr_read_generic, &spr_write_generic, |
940 |
0x00000000);
|
941 |
/* Performance monitors */
|
942 |
/* XXX : not implemented */
|
943 |
spr_register(env, SPR_MMCR0, "MMCR0",
|
944 |
SPR_NOACCESS, SPR_NOACCESS, |
945 |
&spr_read_generic, &spr_write_generic, |
946 |
0x00000000);
|
947 |
/* XXX : not implemented */
|
948 |
spr_register(env, SPR_MMCR1, "MMCR1",
|
949 |
SPR_NOACCESS, SPR_NOACCESS, |
950 |
&spr_read_generic, &spr_write_generic, |
951 |
0x00000000);
|
952 |
/* XXX : not implemented */
|
953 |
spr_register(env, SPR_PMC1, "PMC1",
|
954 |
SPR_NOACCESS, SPR_NOACCESS, |
955 |
&spr_read_generic, &spr_write_generic, |
956 |
0x00000000);
|
957 |
/* XXX : not implemented */
|
958 |
spr_register(env, SPR_PMC2, "PMC2",
|
959 |
SPR_NOACCESS, SPR_NOACCESS, |
960 |
&spr_read_generic, &spr_write_generic, |
961 |
0x00000000);
|
962 |
/* XXX : not implemented */
|
963 |
spr_register(env, SPR_PMC3, "PMC3",
|
964 |
SPR_NOACCESS, SPR_NOACCESS, |
965 |
&spr_read_generic, &spr_write_generic, |
966 |
0x00000000);
|
967 |
/* XXX : not implemented */
|
968 |
spr_register(env, SPR_PMC4, "PMC4",
|
969 |
SPR_NOACCESS, SPR_NOACCESS, |
970 |
&spr_read_generic, &spr_write_generic, |
971 |
0x00000000);
|
972 |
/* XXX : not implemented */
|
973 |
spr_register(env, SPR_SIAR, "SIAR",
|
974 |
SPR_NOACCESS, SPR_NOACCESS, |
975 |
&spr_read_generic, SPR_NOACCESS, |
976 |
0x00000000);
|
977 |
/* XXX : not implemented */
|
978 |
spr_register(env, SPR_UMMCR0, "UMMCR0",
|
979 |
&spr_read_ureg, SPR_NOACCESS, |
980 |
&spr_read_ureg, SPR_NOACCESS, |
981 |
0x00000000);
|
982 |
/* XXX : not implemented */
|
983 |
spr_register(env, SPR_UMMCR1, "UMMCR1",
|
984 |
&spr_read_ureg, SPR_NOACCESS, |
985 |
&spr_read_ureg, SPR_NOACCESS, |
986 |
0x00000000);
|
987 |
/* XXX : not implemented */
|
988 |
spr_register(env, SPR_UPMC1, "UPMC1",
|
989 |
&spr_read_ureg, SPR_NOACCESS, |
990 |
&spr_read_ureg, SPR_NOACCESS, |
991 |
0x00000000);
|
992 |
/* XXX : not implemented */
|
993 |
spr_register(env, SPR_UPMC2, "UPMC2",
|
994 |
&spr_read_ureg, SPR_NOACCESS, |
995 |
&spr_read_ureg, SPR_NOACCESS, |
996 |
0x00000000);
|
997 |
/* XXX : not implemented */
|
998 |
spr_register(env, SPR_UPMC3, "UPMC3",
|
999 |
&spr_read_ureg, SPR_NOACCESS, |
1000 |
&spr_read_ureg, SPR_NOACCESS, |
1001 |
0x00000000);
|
1002 |
/* XXX : not implemented */
|
1003 |
spr_register(env, SPR_UPMC4, "UPMC4",
|
1004 |
&spr_read_ureg, SPR_NOACCESS, |
1005 |
&spr_read_ureg, SPR_NOACCESS, |
1006 |
0x00000000);
|
1007 |
/* XXX : not implemented */
|
1008 |
spr_register(env, SPR_USIAR, "USIAR",
|
1009 |
&spr_read_ureg, SPR_NOACCESS, |
1010 |
&spr_read_ureg, SPR_NOACCESS, |
1011 |
0x00000000);
|
1012 |
/* External access control */
|
1013 |
/* XXX : not implemented */
|
1014 |
spr_register(env, SPR_EAR, "EAR",
|
1015 |
SPR_NOACCESS, SPR_NOACCESS, |
1016 |
&spr_read_generic, &spr_write_generic, |
1017 |
0x00000000);
|
1018 |
} |
1019 |
|
1020 |
static void gen_spr_thrm (CPUPPCState *env) |
1021 |
{ |
1022 |
/* Thermal management */
|
1023 |
/* XXX : not implemented */
|
1024 |
spr_register(env, SPR_THRM1, "THRM1",
|
1025 |
SPR_NOACCESS, SPR_NOACCESS, |
1026 |
&spr_read_generic, &spr_write_generic, |
1027 |
0x00000000);
|
1028 |
/* XXX : not implemented */
|
1029 |
spr_register(env, SPR_THRM2, "THRM2",
|
1030 |
SPR_NOACCESS, SPR_NOACCESS, |
1031 |
&spr_read_generic, &spr_write_generic, |
1032 |
0x00000000);
|
1033 |
/* XXX : not implemented */
|
1034 |
spr_register(env, SPR_THRM3, "THRM3",
|
1035 |
SPR_NOACCESS, SPR_NOACCESS, |
1036 |
&spr_read_generic, &spr_write_generic, |
1037 |
0x00000000);
|
1038 |
} |
1039 |
|
1040 |
/* SPR specific to PowerPC 604 implementation */
|
1041 |
static void gen_spr_604 (CPUPPCState *env) |
1042 |
{ |
1043 |
/* Processor identification */
|
1044 |
spr_register(env, SPR_PIR, "PIR",
|
1045 |
SPR_NOACCESS, SPR_NOACCESS, |
1046 |
&spr_read_generic, &spr_write_pir, |
1047 |
0x00000000);
|
1048 |
/* Breakpoints */
|
1049 |
/* XXX : not implemented */
|
1050 |
spr_register(env, SPR_IABR, "IABR",
|
1051 |
SPR_NOACCESS, SPR_NOACCESS, |
1052 |
&spr_read_generic, &spr_write_generic, |
1053 |
0x00000000);
|
1054 |
/* XXX : not implemented */
|
1055 |
spr_register(env, SPR_DABR, "DABR",
|
1056 |
SPR_NOACCESS, SPR_NOACCESS, |
1057 |
&spr_read_generic, &spr_write_generic, |
1058 |
0x00000000);
|
1059 |
/* Performance counters */
|
1060 |
/* XXX : not implemented */
|
1061 |
spr_register(env, SPR_MMCR0, "MMCR0",
|
1062 |
SPR_NOACCESS, SPR_NOACCESS, |
1063 |
&spr_read_generic, &spr_write_generic, |
1064 |
0x00000000);
|
1065 |
/* XXX : not implemented */
|
1066 |
spr_register(env, SPR_PMC1, "PMC1",
|
1067 |
SPR_NOACCESS, SPR_NOACCESS, |
1068 |
&spr_read_generic, &spr_write_generic, |
1069 |
0x00000000);
|
1070 |
/* XXX : not implemented */
|
1071 |
spr_register(env, SPR_PMC2, "PMC2",
|
1072 |
SPR_NOACCESS, SPR_NOACCESS, |
1073 |
&spr_read_generic, &spr_write_generic, |
1074 |
0x00000000);
|
1075 |
/* XXX : not implemented */
|
1076 |
spr_register(env, SPR_SIAR, "SIAR",
|
1077 |
SPR_NOACCESS, SPR_NOACCESS, |
1078 |
&spr_read_generic, SPR_NOACCESS, |
1079 |
0x00000000);
|
1080 |
/* XXX : not implemented */
|
1081 |
spr_register(env, SPR_SDA, "SDA",
|
1082 |
SPR_NOACCESS, SPR_NOACCESS, |
1083 |
&spr_read_generic, SPR_NOACCESS, |
1084 |
0x00000000);
|
1085 |
/* External access control */
|
1086 |
/* XXX : not implemented */
|
1087 |
spr_register(env, SPR_EAR, "EAR",
|
1088 |
SPR_NOACCESS, SPR_NOACCESS, |
1089 |
&spr_read_generic, &spr_write_generic, |
1090 |
0x00000000);
|
1091 |
} |
1092 |
|
1093 |
/* SPR specific to PowerPC 603 implementation */
|
1094 |
static void gen_spr_603 (CPUPPCState *env) |
1095 |
{ |
1096 |
/* External access control */
|
1097 |
/* XXX : not implemented */
|
1098 |
spr_register(env, SPR_EAR, "EAR",
|
1099 |
SPR_NOACCESS, SPR_NOACCESS, |
1100 |
&spr_read_generic, &spr_write_generic, |
1101 |
0x00000000);
|
1102 |
} |
1103 |
|
1104 |
/* SPR specific to PowerPC G2 implementation */
|
1105 |
static void gen_spr_G2 (CPUPPCState *env) |
1106 |
{ |
1107 |
/* Memory base address */
|
1108 |
/* MBAR */
|
1109 |
/* XXX : not implemented */
|
1110 |
spr_register(env, SPR_MBAR, "MBAR",
|
1111 |
SPR_NOACCESS, SPR_NOACCESS, |
1112 |
&spr_read_generic, &spr_write_generic, |
1113 |
0x00000000);
|
1114 |
/* Exception processing */
|
1115 |
spr_register(env, SPR_BOOKE_CSRR0, "CSRR0",
|
1116 |
SPR_NOACCESS, SPR_NOACCESS, |
1117 |
&spr_read_generic, &spr_write_generic, |
1118 |
0x00000000);
|
1119 |
spr_register(env, SPR_BOOKE_CSRR1, "CSRR1",
|
1120 |
SPR_NOACCESS, SPR_NOACCESS, |
1121 |
&spr_read_generic, &spr_write_generic, |
1122 |
0x00000000);
|
1123 |
/* Breakpoints */
|
1124 |
/* XXX : not implemented */
|
1125 |
spr_register(env, SPR_DABR, "DABR",
|
1126 |
SPR_NOACCESS, SPR_NOACCESS, |
1127 |
&spr_read_generic, &spr_write_generic, |
1128 |
0x00000000);
|
1129 |
/* XXX : not implemented */
|
1130 |
spr_register(env, SPR_DABR2, "DABR2",
|
1131 |
SPR_NOACCESS, SPR_NOACCESS, |
1132 |
&spr_read_generic, &spr_write_generic, |
1133 |
0x00000000);
|
1134 |
/* XXX : not implemented */
|
1135 |
spr_register(env, SPR_IABR, "IABR",
|
1136 |
SPR_NOACCESS, SPR_NOACCESS, |
1137 |
&spr_read_generic, &spr_write_generic, |
1138 |
0x00000000);
|
1139 |
/* XXX : not implemented */
|
1140 |
spr_register(env, SPR_IABR2, "IABR2",
|
1141 |
SPR_NOACCESS, SPR_NOACCESS, |
1142 |
&spr_read_generic, &spr_write_generic, |
1143 |
0x00000000);
|
1144 |
/* XXX : not implemented */
|
1145 |
spr_register(env, SPR_IBCR, "IBCR",
|
1146 |
SPR_NOACCESS, SPR_NOACCESS, |
1147 |
&spr_read_generic, &spr_write_generic, |
1148 |
0x00000000);
|
1149 |
/* XXX : not implemented */
|
1150 |
spr_register(env, SPR_DBCR, "DBCR",
|
1151 |
SPR_NOACCESS, SPR_NOACCESS, |
1152 |
&spr_read_generic, &spr_write_generic, |
1153 |
0x00000000);
|
1154 |
} |
1155 |
|
1156 |
/* SPR specific to PowerPC 602 implementation */
|
1157 |
static void gen_spr_602 (CPUPPCState *env) |
1158 |
{ |
1159 |
/* ESA registers */
|
1160 |
/* XXX : not implemented */
|
1161 |
spr_register(env, SPR_SER, "SER",
|
1162 |
SPR_NOACCESS, SPR_NOACCESS, |
1163 |
&spr_read_generic, &spr_write_generic, |
1164 |
0x00000000);
|
1165 |
/* XXX : not implemented */
|
1166 |
spr_register(env, SPR_SEBR, "SEBR",
|
1167 |
SPR_NOACCESS, SPR_NOACCESS, |
1168 |
&spr_read_generic, &spr_write_generic, |
1169 |
0x00000000);
|
1170 |
/* XXX : not implemented */
|
1171 |
spr_register(env, SPR_ESASRR, "ESASRR",
|
1172 |
SPR_NOACCESS, SPR_NOACCESS, |
1173 |
&spr_read_generic, &spr_write_generic, |
1174 |
0x00000000);
|
1175 |
/* Floating point status */
|
1176 |
/* XXX : not implemented */
|
1177 |
spr_register(env, SPR_SP, "SP",
|
1178 |
SPR_NOACCESS, SPR_NOACCESS, |
1179 |
&spr_read_generic, &spr_write_generic, |
1180 |
0x00000000);
|
1181 |
/* XXX : not implemented */
|
1182 |
spr_register(env, SPR_LT, "LT",
|
1183 |
SPR_NOACCESS, SPR_NOACCESS, |
1184 |
&spr_read_generic, &spr_write_generic, |
1185 |
0x00000000);
|
1186 |
/* Watchdog timer */
|
1187 |
/* XXX : not implemented */
|
1188 |
spr_register(env, SPR_TCR, "TCR",
|
1189 |
SPR_NOACCESS, SPR_NOACCESS, |
1190 |
&spr_read_generic, &spr_write_generic, |
1191 |
0x00000000);
|
1192 |
/* Interrupt base */
|
1193 |
spr_register(env, SPR_IBR, "IBR",
|
1194 |
SPR_NOACCESS, SPR_NOACCESS, |
1195 |
&spr_read_generic, &spr_write_generic, |
1196 |
0x00000000);
|
1197 |
/* XXX : not implemented */
|
1198 |
spr_register(env, SPR_IABR, "IABR",
|
1199 |
SPR_NOACCESS, SPR_NOACCESS, |
1200 |
&spr_read_generic, &spr_write_generic, |
1201 |
0x00000000);
|
1202 |
} |
1203 |
|
1204 |
/* SPR specific to PowerPC 601 implementation */
|
1205 |
static void gen_spr_601 (CPUPPCState *env) |
1206 |
{ |
1207 |
/* Multiplication/division register */
|
1208 |
/* MQ */
|
1209 |
spr_register(env, SPR_MQ, "MQ",
|
1210 |
&spr_read_generic, &spr_write_generic, |
1211 |
&spr_read_generic, &spr_write_generic, |
1212 |
0x00000000);
|
1213 |
/* RTC registers */
|
1214 |
spr_register(env, SPR_601_RTCU, "RTCU",
|
1215 |
SPR_NOACCESS, SPR_NOACCESS, |
1216 |
SPR_NOACCESS, &spr_write_601_rtcu, |
1217 |
0x00000000);
|
1218 |
spr_register(env, SPR_601_VRTCU, "RTCU",
|
1219 |
&spr_read_601_rtcu, SPR_NOACCESS, |
1220 |
&spr_read_601_rtcu, SPR_NOACCESS, |
1221 |
0x00000000);
|
1222 |
spr_register(env, SPR_601_RTCL, "RTCL",
|
1223 |
SPR_NOACCESS, SPR_NOACCESS, |
1224 |
SPR_NOACCESS, &spr_write_601_rtcl, |
1225 |
0x00000000);
|
1226 |
spr_register(env, SPR_601_VRTCL, "RTCL",
|
1227 |
&spr_read_601_rtcl, SPR_NOACCESS, |
1228 |
&spr_read_601_rtcl, SPR_NOACCESS, |
1229 |
0x00000000);
|
1230 |
/* Timer */
|
1231 |
#if 0 /* ? */
|
1232 |
spr_register(env, SPR_601_UDECR, "UDECR",
|
1233 |
&spr_read_decr, SPR_NOACCESS,
|
1234 |
&spr_read_decr, SPR_NOACCESS,
|
1235 |
0x00000000);
|
1236 |
#endif
|
1237 |
/* External access control */
|
1238 |
/* XXX : not implemented */
|
1239 |
spr_register(env, SPR_EAR, "EAR",
|
1240 |
SPR_NOACCESS, SPR_NOACCESS, |
1241 |
&spr_read_generic, &spr_write_generic, |
1242 |
0x00000000);
|
1243 |
/* Memory management */
|
1244 |
#if !defined(CONFIG_USER_ONLY)
|
1245 |
spr_register(env, SPR_IBAT0U, "IBAT0U",
|
1246 |
SPR_NOACCESS, SPR_NOACCESS, |
1247 |
&spr_read_601_ubat, &spr_write_601_ubatu, |
1248 |
0x00000000);
|
1249 |
spr_register(env, SPR_IBAT0L, "IBAT0L",
|
1250 |
SPR_NOACCESS, SPR_NOACCESS, |
1251 |
&spr_read_601_ubat, &spr_write_601_ubatl, |
1252 |
0x00000000);
|
1253 |
spr_register(env, SPR_IBAT1U, "IBAT1U",
|
1254 |
SPR_NOACCESS, SPR_NOACCESS, |
1255 |
&spr_read_601_ubat, &spr_write_601_ubatu, |
1256 |
0x00000000);
|
1257 |
spr_register(env, SPR_IBAT1L, "IBAT1L",
|
1258 |
SPR_NOACCESS, SPR_NOACCESS, |
1259 |
&spr_read_601_ubat, &spr_write_601_ubatl, |
1260 |
0x00000000);
|
1261 |
spr_register(env, SPR_IBAT2U, "IBAT2U",
|
1262 |
SPR_NOACCESS, SPR_NOACCESS, |
1263 |
&spr_read_601_ubat, &spr_write_601_ubatu, |
1264 |
0x00000000);
|
1265 |
spr_register(env, SPR_IBAT2L, "IBAT2L",
|
1266 |
SPR_NOACCESS, SPR_NOACCESS, |
1267 |
&spr_read_601_ubat, &spr_write_601_ubatl, |
1268 |
0x00000000);
|
1269 |
spr_register(env, SPR_IBAT3U, "IBAT3U",
|
1270 |
SPR_NOACCESS, SPR_NOACCESS, |
1271 |
&spr_read_601_ubat, &spr_write_601_ubatu, |
1272 |
0x00000000);
|
1273 |
spr_register(env, SPR_IBAT3L, "IBAT3L",
|
1274 |
SPR_NOACCESS, SPR_NOACCESS, |
1275 |
&spr_read_601_ubat, &spr_write_601_ubatl, |
1276 |
0x00000000);
|
1277 |
env->nb_BATs = 4;
|
1278 |
#endif
|
1279 |
} |
1280 |
|
1281 |
static void gen_spr_74xx (CPUPPCState *env) |
1282 |
{ |
1283 |
/* Processor identification */
|
1284 |
spr_register(env, SPR_PIR, "PIR",
|
1285 |
SPR_NOACCESS, SPR_NOACCESS, |
1286 |
&spr_read_generic, &spr_write_pir, |
1287 |
0x00000000);
|
1288 |
/* XXX : not implemented */
|
1289 |
spr_register(env, SPR_MMCR2, "MMCR2",
|
1290 |
SPR_NOACCESS, SPR_NOACCESS, |
1291 |
&spr_read_generic, &spr_write_generic, |
1292 |
0x00000000);
|
1293 |
/* XXX : not implemented */
|
1294 |
spr_register(env, SPR_UMMCR2, "UMMCR2",
|
1295 |
&spr_read_ureg, SPR_NOACCESS, |
1296 |
&spr_read_ureg, SPR_NOACCESS, |
1297 |
0x00000000);
|
1298 |
/* XXX: not implemented */
|
1299 |
spr_register(env, SPR_BAMR, "BAMR",
|
1300 |
SPR_NOACCESS, SPR_NOACCESS, |
1301 |
&spr_read_generic, &spr_write_generic, |
1302 |
0x00000000);
|
1303 |
/* XXX : not implemented */
|
1304 |
spr_register(env, SPR_MSSCR0, "MSSCR0",
|
1305 |
SPR_NOACCESS, SPR_NOACCESS, |
1306 |
&spr_read_generic, &spr_write_generic, |
1307 |
0x00000000);
|
1308 |
/* Hardware implementation registers */
|
1309 |
/* XXX : not implemented */
|
1310 |
spr_register(env, SPR_HID0, "HID0",
|
1311 |
SPR_NOACCESS, SPR_NOACCESS, |
1312 |
&spr_read_generic, &spr_write_generic, |
1313 |
0x00000000);
|
1314 |
/* XXX : not implemented */
|
1315 |
spr_register(env, SPR_HID1, "HID1",
|
1316 |
SPR_NOACCESS, SPR_NOACCESS, |
1317 |
&spr_read_generic, &spr_write_generic, |
1318 |
0x00000000);
|
1319 |
/* Altivec */
|
1320 |
spr_register(env, SPR_VRSAVE, "VRSAVE",
|
1321 |
&spr_read_generic, &spr_write_generic, |
1322 |
&spr_read_generic, &spr_write_generic, |
1323 |
0x00000000);
|
1324 |
/* XXX : not implemented */
|
1325 |
spr_register(env, SPR_L2CR, "L2CR",
|
1326 |
SPR_NOACCESS, SPR_NOACCESS, |
1327 |
&spr_read_generic, &spr_write_generic, |
1328 |
0x00000000);
|
1329 |
/* Not strictly an SPR */
|
1330 |
vscr_init(env, 0x00010000);
|
1331 |
} |
1332 |
|
1333 |
static void gen_l3_ctrl (CPUPPCState *env) |
1334 |
{ |
1335 |
/* L3CR */
|
1336 |
/* XXX : not implemented */
|
1337 |
spr_register(env, SPR_L3CR, "L3CR",
|
1338 |
SPR_NOACCESS, SPR_NOACCESS, |
1339 |
&spr_read_generic, &spr_write_generic, |
1340 |
0x00000000);
|
1341 |
/* L3ITCR0 */
|
1342 |
/* XXX : not implemented */
|
1343 |
spr_register(env, SPR_L3ITCR0, "L3ITCR0",
|
1344 |
SPR_NOACCESS, SPR_NOACCESS, |
1345 |
&spr_read_generic, &spr_write_generic, |
1346 |
0x00000000);
|
1347 |
/* L3PM */
|
1348 |
/* XXX : not implemented */
|
1349 |
spr_register(env, SPR_L3PM, "L3PM",
|
1350 |
SPR_NOACCESS, SPR_NOACCESS, |
1351 |
&spr_read_generic, &spr_write_generic, |
1352 |
0x00000000);
|
1353 |
} |
1354 |
|
1355 |
static void gen_74xx_soft_tlb (CPUPPCState *env, int nb_tlbs, int nb_ways) |
1356 |
{ |
1357 |
#if !defined(CONFIG_USER_ONLY)
|
1358 |
env->nb_tlb = nb_tlbs; |
1359 |
env->nb_ways = nb_ways; |
1360 |
env->id_tlbs = 1;
|
1361 |
env->tlb_type = TLB_6XX; |
1362 |
/* XXX : not implemented */
|
1363 |
spr_register(env, SPR_PTEHI, "PTEHI",
|
1364 |
SPR_NOACCESS, SPR_NOACCESS, |
1365 |
&spr_read_generic, &spr_write_generic, |
1366 |
0x00000000);
|
1367 |
/* XXX : not implemented */
|
1368 |
spr_register(env, SPR_PTELO, "PTELO",
|
1369 |
SPR_NOACCESS, SPR_NOACCESS, |
1370 |
&spr_read_generic, &spr_write_generic, |
1371 |
0x00000000);
|
1372 |
/* XXX : not implemented */
|
1373 |
spr_register(env, SPR_TLBMISS, "TLBMISS",
|
1374 |
SPR_NOACCESS, SPR_NOACCESS, |
1375 |
&spr_read_generic, &spr_write_generic, |
1376 |
0x00000000);
|
1377 |
#endif
|
1378 |
} |
1379 |
|
1380 |
#if !defined(CONFIG_USER_ONLY)
|
1381 |
static void spr_write_e500_l1csr0 (void *opaque, int sprn, int gprn) |
1382 |
{ |
1383 |
TCGv t0 = tcg_temp_new(); |
1384 |
|
1385 |
tcg_gen_andi_tl(t0, cpu_gpr[gprn], ~256);
|
1386 |
gen_store_spr(sprn, t0); |
1387 |
tcg_temp_free(t0); |
1388 |
} |
1389 |
|
1390 |
static void spr_write_booke206_mmucsr0 (void *opaque, int sprn, int gprn) |
1391 |
{ |
1392 |
TCGv_i32 t0 = tcg_const_i32(sprn); |
1393 |
gen_helper_booke206_tlbflush(cpu_env, t0); |
1394 |
tcg_temp_free_i32(t0); |
1395 |
} |
1396 |
|
1397 |
static void spr_write_booke_pid (void *opaque, int sprn, int gprn) |
1398 |
{ |
1399 |
TCGv_i32 t0 = tcg_const_i32(sprn); |
1400 |
gen_helper_booke_setpid(cpu_env, t0, cpu_gpr[gprn]); |
1401 |
tcg_temp_free_i32(t0); |
1402 |
} |
1403 |
#endif
|
1404 |
|
1405 |
static void gen_spr_usprgh (CPUPPCState *env) |
1406 |
{ |
1407 |
spr_register(env, SPR_USPRG4, "USPRG4",
|
1408 |
&spr_read_ureg, SPR_NOACCESS, |
1409 |
&spr_read_ureg, SPR_NOACCESS, |
1410 |
0x00000000);
|
1411 |
spr_register(env, SPR_USPRG5, "USPRG5",
|
1412 |
&spr_read_ureg, SPR_NOACCESS, |
1413 |
&spr_read_ureg, SPR_NOACCESS, |
1414 |
0x00000000);
|
1415 |
spr_register(env, SPR_USPRG6, "USPRG6",
|
1416 |
&spr_read_ureg, SPR_NOACCESS, |
1417 |
&spr_read_ureg, SPR_NOACCESS, |
1418 |
0x00000000);
|
1419 |
spr_register(env, SPR_USPRG7, "USPRG7",
|
1420 |
&spr_read_ureg, SPR_NOACCESS, |
1421 |
&spr_read_ureg, SPR_NOACCESS, |
1422 |
0x00000000);
|
1423 |
} |
1424 |
|
1425 |
/* PowerPC BookE SPR */
|
1426 |
static void gen_spr_BookE (CPUPPCState *env, uint64_t ivor_mask) |
1427 |
{ |
1428 |
const char *ivor_names[64] = { |
1429 |
"IVOR0", "IVOR1", "IVOR2", "IVOR3", |
1430 |
"IVOR4", "IVOR5", "IVOR6", "IVOR7", |
1431 |
"IVOR8", "IVOR9", "IVOR10", "IVOR11", |
1432 |
"IVOR12", "IVOR13", "IVOR14", "IVOR15", |
1433 |
"IVOR16", "IVOR17", "IVOR18", "IVOR19", |
1434 |
"IVOR20", "IVOR21", "IVOR22", "IVOR23", |
1435 |
"IVOR24", "IVOR25", "IVOR26", "IVOR27", |
1436 |
"IVOR28", "IVOR29", "IVOR30", "IVOR31", |
1437 |
"IVOR32", "IVOR33", "IVOR34", "IVOR35", |
1438 |
"IVOR36", "IVOR37", "IVOR38", "IVOR39", |
1439 |
"IVOR40", "IVOR41", "IVOR42", "IVOR43", |
1440 |
"IVOR44", "IVOR45", "IVOR46", "IVOR47", |
1441 |
"IVOR48", "IVOR49", "IVOR50", "IVOR51", |
1442 |
"IVOR52", "IVOR53", "IVOR54", "IVOR55", |
1443 |
"IVOR56", "IVOR57", "IVOR58", "IVOR59", |
1444 |
"IVOR60", "IVOR61", "IVOR62", "IVOR63", |
1445 |
}; |
1446 |
#define SPR_BOOKE_IVORxx (-1) |
1447 |
int ivor_sprn[64] = { |
1448 |
SPR_BOOKE_IVOR0, SPR_BOOKE_IVOR1, SPR_BOOKE_IVOR2, SPR_BOOKE_IVOR3, |
1449 |
SPR_BOOKE_IVOR4, SPR_BOOKE_IVOR5, SPR_BOOKE_IVOR6, SPR_BOOKE_IVOR7, |
1450 |
SPR_BOOKE_IVOR8, SPR_BOOKE_IVOR9, SPR_BOOKE_IVOR10, SPR_BOOKE_IVOR11, |
1451 |
SPR_BOOKE_IVOR12, SPR_BOOKE_IVOR13, SPR_BOOKE_IVOR14, SPR_BOOKE_IVOR15, |
1452 |
SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, |
1453 |
SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, |
1454 |
SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, |
1455 |
SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, |
1456 |
SPR_BOOKE_IVOR32, SPR_BOOKE_IVOR33, SPR_BOOKE_IVOR34, SPR_BOOKE_IVOR35, |
1457 |
SPR_BOOKE_IVOR36, SPR_BOOKE_IVOR37, SPR_BOOKE_IVOR38, SPR_BOOKE_IVOR39, |
1458 |
SPR_BOOKE_IVOR40, SPR_BOOKE_IVOR41, SPR_BOOKE_IVOR42, SPR_BOOKE_IVORxx, |
1459 |
SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, |
1460 |
SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, |
1461 |
SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, |
1462 |
SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, |
1463 |
SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, |
1464 |
}; |
1465 |
int i;
|
1466 |
|
1467 |
/* Interrupt processing */
|
1468 |
spr_register(env, SPR_BOOKE_CSRR0, "CSRR0",
|
1469 |
SPR_NOACCESS, SPR_NOACCESS, |
1470 |
&spr_read_generic, &spr_write_generic, |
1471 |
0x00000000);
|
1472 |
spr_register(env, SPR_BOOKE_CSRR1, "CSRR1",
|
1473 |
SPR_NOACCESS, SPR_NOACCESS, |
1474 |
&spr_read_generic, &spr_write_generic, |
1475 |
0x00000000);
|
1476 |
/* Debug */
|
1477 |
/* XXX : not implemented */
|
1478 |
spr_register(env, SPR_BOOKE_IAC1, "IAC1",
|
1479 |
SPR_NOACCESS, SPR_NOACCESS, |
1480 |
&spr_read_generic, &spr_write_generic, |
1481 |
0x00000000);
|
1482 |
/* XXX : not implemented */
|
1483 |
spr_register(env, SPR_BOOKE_IAC2, "IAC2",
|
1484 |
SPR_NOACCESS, SPR_NOACCESS, |
1485 |
&spr_read_generic, &spr_write_generic, |
1486 |
0x00000000);
|
1487 |
/* XXX : not implemented */
|
1488 |
spr_register(env, SPR_BOOKE_DAC1, "DAC1",
|
1489 |
SPR_NOACCESS, SPR_NOACCESS, |
1490 |
&spr_read_generic, &spr_write_generic, |
1491 |
0x00000000);
|
1492 |
/* XXX : not implemented */
|
1493 |
spr_register(env, SPR_BOOKE_DAC2, "DAC2",
|
1494 |
SPR_NOACCESS, SPR_NOACCESS, |
1495 |
&spr_read_generic, &spr_write_generic, |
1496 |
0x00000000);
|
1497 |
/* XXX : not implemented */
|
1498 |
spr_register(env, SPR_BOOKE_DBCR0, "DBCR0",
|
1499 |
SPR_NOACCESS, SPR_NOACCESS, |
1500 |
&spr_read_generic, &spr_write_generic, |
1501 |
0x00000000);
|
1502 |
/* XXX : not implemented */
|
1503 |
spr_register(env, SPR_BOOKE_DBCR1, "DBCR1",
|
1504 |
SPR_NOACCESS, SPR_NOACCESS, |
1505 |
&spr_read_generic, &spr_write_generic, |
1506 |
0x00000000);
|
1507 |
/* XXX : not implemented */
|
1508 |
spr_register(env, SPR_BOOKE_DBCR2, "DBCR2",
|
1509 |
SPR_NOACCESS, SPR_NOACCESS, |
1510 |
&spr_read_generic, &spr_write_generic, |
1511 |
0x00000000);
|
1512 |
/* XXX : not implemented */
|
1513 |
spr_register(env, SPR_BOOKE_DBSR, "DBSR",
|
1514 |
SPR_NOACCESS, SPR_NOACCESS, |
1515 |
&spr_read_generic, &spr_write_clear, |
1516 |
0x00000000);
|
1517 |
spr_register(env, SPR_BOOKE_DEAR, "DEAR",
|
1518 |
SPR_NOACCESS, SPR_NOACCESS, |
1519 |
&spr_read_generic, &spr_write_generic, |
1520 |
0x00000000);
|
1521 |
spr_register(env, SPR_BOOKE_ESR, "ESR",
|
1522 |
SPR_NOACCESS, SPR_NOACCESS, |
1523 |
&spr_read_generic, &spr_write_generic, |
1524 |
0x00000000);
|
1525 |
spr_register(env, SPR_BOOKE_IVPR, "IVPR",
|
1526 |
SPR_NOACCESS, SPR_NOACCESS, |
1527 |
&spr_read_generic, &spr_write_excp_prefix, |
1528 |
0x00000000);
|
1529 |
/* Exception vectors */
|
1530 |
for (i = 0; i < 64; i++) { |
1531 |
if (ivor_mask & (1ULL << i)) { |
1532 |
if (ivor_sprn[i] == SPR_BOOKE_IVORxx) {
|
1533 |
fprintf(stderr, "ERROR: IVOR %d SPR is not defined\n", i);
|
1534 |
exit(1);
|
1535 |
} |
1536 |
spr_register(env, ivor_sprn[i], ivor_names[i], |
1537 |
SPR_NOACCESS, SPR_NOACCESS, |
1538 |
&spr_read_generic, &spr_write_excp_vector, |
1539 |
0x00000000);
|
1540 |
} |
1541 |
} |
1542 |
spr_register(env, SPR_BOOKE_PID, "PID",
|
1543 |
SPR_NOACCESS, SPR_NOACCESS, |
1544 |
&spr_read_generic, &spr_write_booke_pid, |
1545 |
0x00000000);
|
1546 |
spr_register(env, SPR_BOOKE_TCR, "TCR",
|
1547 |
SPR_NOACCESS, SPR_NOACCESS, |
1548 |
&spr_read_generic, &spr_write_booke_tcr, |
1549 |
0x00000000);
|
1550 |
spr_register(env, SPR_BOOKE_TSR, "TSR",
|
1551 |
SPR_NOACCESS, SPR_NOACCESS, |
1552 |
&spr_read_generic, &spr_write_booke_tsr, |
1553 |
0x00000000);
|
1554 |
/* Timer */
|
1555 |
spr_register(env, SPR_DECR, "DECR",
|
1556 |
SPR_NOACCESS, SPR_NOACCESS, |
1557 |
&spr_read_decr, &spr_write_decr, |
1558 |
0x00000000);
|
1559 |
spr_register(env, SPR_BOOKE_DECAR, "DECAR",
|
1560 |
SPR_NOACCESS, SPR_NOACCESS, |
1561 |
SPR_NOACCESS, &spr_write_generic, |
1562 |
0x00000000);
|
1563 |
/* SPRGs */
|
1564 |
spr_register(env, SPR_USPRG0, "USPRG0",
|
1565 |
&spr_read_generic, &spr_write_generic, |
1566 |
&spr_read_generic, &spr_write_generic, |
1567 |
0x00000000);
|
1568 |
spr_register(env, SPR_SPRG4, "SPRG4",
|
1569 |
SPR_NOACCESS, SPR_NOACCESS, |
1570 |
&spr_read_generic, &spr_write_generic, |
1571 |
0x00000000);
|
1572 |
spr_register(env, SPR_SPRG5, "SPRG5",
|
1573 |
SPR_NOACCESS, SPR_NOACCESS, |
1574 |
&spr_read_generic, &spr_write_generic, |
1575 |
0x00000000);
|
1576 |
spr_register(env, SPR_SPRG6, "SPRG6",
|
1577 |
SPR_NOACCESS, SPR_NOACCESS, |
1578 |
&spr_read_generic, &spr_write_generic, |
1579 |
0x00000000);
|
1580 |
spr_register(env, SPR_SPRG7, "SPRG7",
|
1581 |
SPR_NOACCESS, SPR_NOACCESS, |
1582 |
&spr_read_generic, &spr_write_generic, |
1583 |
0x00000000);
|
1584 |
} |
1585 |
|
1586 |
static inline uint32_t gen_tlbncfg(uint32_t assoc, uint32_t minsize, |
1587 |
uint32_t maxsize, uint32_t flags, |
1588 |
uint32_t nentries) |
1589 |
{ |
1590 |
return (assoc << TLBnCFG_ASSOC_SHIFT) |
|
1591 |
(minsize << TLBnCFG_MINSIZE_SHIFT) | |
1592 |
(maxsize << TLBnCFG_MAXSIZE_SHIFT) | |
1593 |
flags | nentries; |
1594 |
} |
1595 |
|
1596 |
/* BookE 2.06 storage control registers */
|
1597 |
static void gen_spr_BookE206(CPUPPCState *env, uint32_t mas_mask, |
1598 |
uint32_t *tlbncfg) |
1599 |
{ |
1600 |
#if !defined(CONFIG_USER_ONLY)
|
1601 |
const char *mas_names[8] = { |
1602 |
"MAS0", "MAS1", "MAS2", "MAS3", "MAS4", "MAS5", "MAS6", "MAS7", |
1603 |
}; |
1604 |
int mas_sprn[8] = { |
1605 |
SPR_BOOKE_MAS0, SPR_BOOKE_MAS1, SPR_BOOKE_MAS2, SPR_BOOKE_MAS3, |
1606 |
SPR_BOOKE_MAS4, SPR_BOOKE_MAS5, SPR_BOOKE_MAS6, SPR_BOOKE_MAS7, |
1607 |
}; |
1608 |
int i;
|
1609 |
|
1610 |
/* TLB assist registers */
|
1611 |
/* XXX : not implemented */
|
1612 |
for (i = 0; i < 8; i++) { |
1613 |
void (*uea_write)(void *o, int sprn, int gprn) = &spr_write_generic32; |
1614 |
if (i == 2 && (mas_mask & (1 << i)) && (env->insns_flags & PPC_64B)) { |
1615 |
uea_write = &spr_write_generic; |
1616 |
} |
1617 |
if (mas_mask & (1 << i)) { |
1618 |
spr_register(env, mas_sprn[i], mas_names[i], |
1619 |
SPR_NOACCESS, SPR_NOACCESS, |
1620 |
&spr_read_generic, uea_write, |
1621 |
0x00000000);
|
1622 |
} |
1623 |
} |
1624 |
if (env->nb_pids > 1) { |
1625 |
/* XXX : not implemented */
|
1626 |
spr_register(env, SPR_BOOKE_PID1, "PID1",
|
1627 |
SPR_NOACCESS, SPR_NOACCESS, |
1628 |
&spr_read_generic, &spr_write_booke_pid, |
1629 |
0x00000000);
|
1630 |
} |
1631 |
if (env->nb_pids > 2) { |
1632 |
/* XXX : not implemented */
|
1633 |
spr_register(env, SPR_BOOKE_PID2, "PID2",
|
1634 |
SPR_NOACCESS, SPR_NOACCESS, |
1635 |
&spr_read_generic, &spr_write_booke_pid, |
1636 |
0x00000000);
|
1637 |
} |
1638 |
/* XXX : not implemented */
|
1639 |
spr_register(env, SPR_MMUCFG, "MMUCFG",
|
1640 |
SPR_NOACCESS, SPR_NOACCESS, |
1641 |
&spr_read_generic, SPR_NOACCESS, |
1642 |
0x00000000); /* TOFIX */ |
1643 |
switch (env->nb_ways) {
|
1644 |
case 4: |
1645 |
spr_register(env, SPR_BOOKE_TLB3CFG, "TLB3CFG",
|
1646 |
SPR_NOACCESS, SPR_NOACCESS, |
1647 |
&spr_read_generic, SPR_NOACCESS, |
1648 |
tlbncfg[3]);
|
1649 |
/* Fallthru */
|
1650 |
case 3: |
1651 |
spr_register(env, SPR_BOOKE_TLB2CFG, "TLB2CFG",
|
1652 |
SPR_NOACCESS, SPR_NOACCESS, |
1653 |
&spr_read_generic, SPR_NOACCESS, |
1654 |
tlbncfg[2]);
|
1655 |
/* Fallthru */
|
1656 |
case 2: |
1657 |
spr_register(env, SPR_BOOKE_TLB1CFG, "TLB1CFG",
|
1658 |
SPR_NOACCESS, SPR_NOACCESS, |
1659 |
&spr_read_generic, SPR_NOACCESS, |
1660 |
tlbncfg[1]);
|
1661 |
/* Fallthru */
|
1662 |
case 1: |
1663 |
spr_register(env, SPR_BOOKE_TLB0CFG, "TLB0CFG",
|
1664 |
SPR_NOACCESS, SPR_NOACCESS, |
1665 |
&spr_read_generic, SPR_NOACCESS, |
1666 |
tlbncfg[0]);
|
1667 |
/* Fallthru */
|
1668 |
case 0: |
1669 |
default:
|
1670 |
break;
|
1671 |
} |
1672 |
#endif
|
1673 |
|
1674 |
gen_spr_usprgh(env); |
1675 |
} |
1676 |
|
1677 |
/* SPR specific to PowerPC 440 implementation */
|
1678 |
static void gen_spr_440 (CPUPPCState *env) |
1679 |
{ |
1680 |
/* Cache control */
|
1681 |
/* XXX : not implemented */
|
1682 |
spr_register(env, SPR_440_DNV0, "DNV0",
|
1683 |
SPR_NOACCESS, SPR_NOACCESS, |
1684 |
&spr_read_generic, &spr_write_generic, |
1685 |
0x00000000);
|
1686 |
/* XXX : not implemented */
|
1687 |
spr_register(env, SPR_440_DNV1, "DNV1",
|
1688 |
SPR_NOACCESS, SPR_NOACCESS, |
1689 |
&spr_read_generic, &spr_write_generic, |
1690 |
0x00000000);
|
1691 |
/* XXX : not implemented */
|
1692 |
spr_register(env, SPR_440_DNV2, "DNV2",
|
1693 |
SPR_NOACCESS, SPR_NOACCESS, |
1694 |
&spr_read_generic, &spr_write_generic, |
1695 |
0x00000000);
|
1696 |
/* XXX : not implemented */
|
1697 |
spr_register(env, SPR_440_DNV3, "DNV3",
|
1698 |
SPR_NOACCESS, SPR_NOACCESS, |
1699 |
&spr_read_generic, &spr_write_generic, |
1700 |
0x00000000);
|
1701 |
/* XXX : not implemented */
|
1702 |
spr_register(env, SPR_440_DTV0, "DTV0",
|
1703 |
SPR_NOACCESS, SPR_NOACCESS, |
1704 |
&spr_read_generic, &spr_write_generic, |
1705 |
0x00000000);
|
1706 |
/* XXX : not implemented */
|
1707 |
spr_register(env, SPR_440_DTV1, "DTV1",
|
1708 |
SPR_NOACCESS, SPR_NOACCESS, |
1709 |
&spr_read_generic, &spr_write_generic, |
1710 |
0x00000000);
|
1711 |
/* XXX : not implemented */
|
1712 |
spr_register(env, SPR_440_DTV2, "DTV2",
|
1713 |
SPR_NOACCESS, SPR_NOACCESS, |
1714 |
&spr_read_generic, &spr_write_generic, |
1715 |
0x00000000);
|
1716 |
/* XXX : not implemented */
|
1717 |
spr_register(env, SPR_440_DTV3, "DTV3",
|
1718 |
SPR_NOACCESS, SPR_NOACCESS, |
1719 |
&spr_read_generic, &spr_write_generic, |
1720 |
0x00000000);
|
1721 |
/* XXX : not implemented */
|
1722 |
spr_register(env, SPR_440_DVLIM, "DVLIM",
|
1723 |
SPR_NOACCESS, SPR_NOACCESS, |
1724 |
&spr_read_generic, &spr_write_generic, |
1725 |
0x00000000);
|
1726 |
/* XXX : not implemented */
|
1727 |
spr_register(env, SPR_440_INV0, "INV0",
|
1728 |
SPR_NOACCESS, SPR_NOACCESS, |
1729 |
&spr_read_generic, &spr_write_generic, |
1730 |
0x00000000);
|
1731 |
/* XXX : not implemented */
|
1732 |
spr_register(env, SPR_440_INV1, "INV1",
|
1733 |
SPR_NOACCESS, SPR_NOACCESS, |
1734 |
&spr_read_generic, &spr_write_generic, |
1735 |
0x00000000);
|
1736 |
/* XXX : not implemented */
|
1737 |
spr_register(env, SPR_440_INV2, "INV2",
|
1738 |
SPR_NOACCESS, SPR_NOACCESS, |
1739 |
&spr_read_generic, &spr_write_generic, |
1740 |
0x00000000);
|
1741 |
/* XXX : not implemented */
|
1742 |
spr_register(env, SPR_440_INV3, "INV3",
|
1743 |
SPR_NOACCESS, SPR_NOACCESS, |
1744 |
&spr_read_generic, &spr_write_generic, |
1745 |
0x00000000);
|
1746 |
/* XXX : not implemented */
|
1747 |
spr_register(env, SPR_440_ITV0, "ITV0",
|
1748 |
SPR_NOACCESS, SPR_NOACCESS, |
1749 |
&spr_read_generic, &spr_write_generic, |
1750 |
0x00000000);
|
1751 |
/* XXX : not implemented */
|
1752 |
spr_register(env, SPR_440_ITV1, "ITV1",
|
1753 |
SPR_NOACCESS, SPR_NOACCESS, |
1754 |
&spr_read_generic, &spr_write_generic, |
1755 |
0x00000000);
|
1756 |
/* XXX : not implemented */
|
1757 |
spr_register(env, SPR_440_ITV2, "ITV2",
|
1758 |
SPR_NOACCESS, SPR_NOACCESS, |
1759 |
&spr_read_generic, &spr_write_generic, |
1760 |
0x00000000);
|
1761 |
/* XXX : not implemented */
|
1762 |
spr_register(env, SPR_440_ITV3, "ITV3",
|
1763 |
SPR_NOACCESS, SPR_NOACCESS, |
1764 |
&spr_read_generic, &spr_write_generic, |
1765 |
0x00000000);
|
1766 |
/* XXX : not implemented */
|
1767 |
spr_register(env, SPR_440_IVLIM, "IVLIM",
|
1768 |
SPR_NOACCESS, SPR_NOACCESS, |
1769 |
&spr_read_generic, &spr_write_generic, |
1770 |
0x00000000);
|
1771 |
/* Cache debug */
|
1772 |
/* XXX : not implemented */
|
1773 |
spr_register(env, SPR_BOOKE_DCDBTRH, "DCDBTRH",
|
1774 |
SPR_NOACCESS, SPR_NOACCESS, |
1775 |
&spr_read_generic, SPR_NOACCESS, |
1776 |
0x00000000);
|
1777 |
/* XXX : not implemented */
|
1778 |
spr_register(env, SPR_BOOKE_DCDBTRL, "DCDBTRL",
|
1779 |
SPR_NOACCESS, SPR_NOACCESS, |
1780 |
&spr_read_generic, SPR_NOACCESS, |
1781 |
0x00000000);
|
1782 |
/* XXX : not implemented */
|
1783 |
spr_register(env, SPR_BOOKE_ICDBDR, "ICDBDR",
|
1784 |
SPR_NOACCESS, SPR_NOACCESS, |
1785 |
&spr_read_generic, SPR_NOACCESS, |
1786 |
0x00000000);
|
1787 |
/* XXX : not implemented */
|
1788 |
spr_register(env, SPR_BOOKE_ICDBTRH, "ICDBTRH",
|
1789 |
SPR_NOACCESS, SPR_NOACCESS, |
1790 |
&spr_read_generic, SPR_NOACCESS, |
1791 |
0x00000000);
|
1792 |
/* XXX : not implemented */
|
1793 |
spr_register(env, SPR_BOOKE_ICDBTRL, "ICDBTRL",
|
1794 |
SPR_NOACCESS, SPR_NOACCESS, |
1795 |
&spr_read_generic, SPR_NOACCESS, |
1796 |
0x00000000);
|
1797 |
/* XXX : not implemented */
|
1798 |
spr_register(env, SPR_440_DBDR, "DBDR",
|
1799 |
SPR_NOACCESS, SPR_NOACCESS, |
1800 |
&spr_read_generic, &spr_write_generic, |
1801 |
0x00000000);
|
1802 |
/* Processor control */
|
1803 |
spr_register(env, SPR_4xx_CCR0, "CCR0",
|
1804 |
SPR_NOACCESS, SPR_NOACCESS, |
1805 |
&spr_read_generic, &spr_write_generic, |
1806 |
0x00000000);
|
1807 |
spr_register(env, SPR_440_RSTCFG, "RSTCFG",
|
1808 |
SPR_NOACCESS, SPR_NOACCESS, |
1809 |
&spr_read_generic, SPR_NOACCESS, |
1810 |
0x00000000);
|
1811 |
/* Storage control */
|
1812 |
spr_register(env, SPR_440_MMUCR, "MMUCR",
|
1813 |
SPR_NOACCESS, SPR_NOACCESS, |
1814 |
&spr_read_generic, &spr_write_generic, |
1815 |
0x00000000);
|
1816 |
} |
1817 |
|
1818 |
/* SPR shared between PowerPC 40x implementations */
|
1819 |
static void gen_spr_40x (CPUPPCState *env) |
1820 |
{ |
1821 |
/* Cache */
|
1822 |
/* not emulated, as QEMU do not emulate caches */
|
1823 |
spr_register(env, SPR_40x_DCCR, "DCCR",
|
1824 |
SPR_NOACCESS, SPR_NOACCESS, |
1825 |
&spr_read_generic, &spr_write_generic, |
1826 |
0x00000000);
|
1827 |
/* not emulated, as QEMU do not emulate caches */
|
1828 |
spr_register(env, SPR_40x_ICCR, "ICCR",
|
1829 |
SPR_NOACCESS, SPR_NOACCESS, |
1830 |
&spr_read_generic, &spr_write_generic, |
1831 |
0x00000000);
|
1832 |
/* not emulated, as QEMU do not emulate caches */
|
1833 |
spr_register(env, SPR_BOOKE_ICDBDR, "ICDBDR",
|
1834 |
SPR_NOACCESS, SPR_NOACCESS, |
1835 |
&spr_read_generic, SPR_NOACCESS, |
1836 |
0x00000000);
|
1837 |
/* Exception */
|
1838 |
spr_register(env, SPR_40x_DEAR, "DEAR",
|
1839 |
SPR_NOACCESS, SPR_NOACCESS, |
1840 |
&spr_read_generic, &spr_write_generic, |
1841 |
0x00000000);
|
1842 |
spr_register(env, SPR_40x_ESR, "ESR",
|
1843 |
SPR_NOACCESS, SPR_NOACCESS, |
1844 |
&spr_read_generic, &spr_write_generic, |
1845 |
0x00000000);
|
1846 |
spr_register(env, SPR_40x_EVPR, "EVPR",
|
1847 |
SPR_NOACCESS, SPR_NOACCESS, |
1848 |
&spr_read_generic, &spr_write_excp_prefix, |
1849 |
0x00000000);
|
1850 |
spr_register(env, SPR_40x_SRR2, "SRR2",
|
1851 |
&spr_read_generic, &spr_write_generic, |
1852 |
&spr_read_generic, &spr_write_generic, |
1853 |
0x00000000);
|
1854 |
spr_register(env, SPR_40x_SRR3, "SRR3",
|
1855 |
&spr_read_generic, &spr_write_generic, |
1856 |
&spr_read_generic, &spr_write_generic, |
1857 |
0x00000000);
|
1858 |
/* Timers */
|
1859 |
spr_register(env, SPR_40x_PIT, "PIT",
|
1860 |
SPR_NOACCESS, SPR_NOACCESS, |
1861 |
&spr_read_40x_pit, &spr_write_40x_pit, |
1862 |
0x00000000);
|
1863 |
spr_register(env, SPR_40x_TCR, "TCR",
|
1864 |
SPR_NOACCESS, SPR_NOACCESS, |
1865 |
&spr_read_generic, &spr_write_booke_tcr, |
1866 |
0x00000000);
|
1867 |
spr_register(env, SPR_40x_TSR, "TSR",
|
1868 |
SPR_NOACCESS, SPR_NOACCESS, |
1869 |
&spr_read_generic, &spr_write_booke_tsr, |
1870 |
0x00000000);
|
1871 |
} |
1872 |
|
1873 |
/* SPR specific to PowerPC 405 implementation */
|
1874 |
static void gen_spr_405 (CPUPPCState *env) |
1875 |
{ |
1876 |
/* MMU */
|
1877 |
spr_register(env, SPR_40x_PID, "PID",
|
1878 |
SPR_NOACCESS, SPR_NOACCESS, |
1879 |
&spr_read_generic, &spr_write_generic, |
1880 |
0x00000000);
|
1881 |
spr_register(env, SPR_4xx_CCR0, "CCR0",
|
1882 |
SPR_NOACCESS, SPR_NOACCESS, |
1883 |
&spr_read_generic, &spr_write_generic, |
1884 |
0x00700000);
|
1885 |
/* Debug interface */
|
1886 |
/* XXX : not implemented */
|
1887 |
spr_register(env, SPR_40x_DBCR0, "DBCR0",
|
1888 |
SPR_NOACCESS, SPR_NOACCESS, |
1889 |
&spr_read_generic, &spr_write_40x_dbcr0, |
1890 |
0x00000000);
|
1891 |
/* XXX : not implemented */
|
1892 |
spr_register(env, SPR_405_DBCR1, "DBCR1",
|
1893 |
SPR_NOACCESS, SPR_NOACCESS, |
1894 |
&spr_read_generic, &spr_write_generic, |
1895 |
0x00000000);
|
1896 |
/* XXX : not implemented */
|
1897 |
spr_register(env, SPR_40x_DBSR, "DBSR",
|
1898 |
SPR_NOACCESS, SPR_NOACCESS, |
1899 |
&spr_read_generic, &spr_write_clear, |
1900 |
/* Last reset was system reset */
|
1901 |
0x00000300);
|
1902 |
/* XXX : not implemented */
|
1903 |
spr_register(env, SPR_40x_DAC1, "DAC1",
|
1904 |
SPR_NOACCESS, SPR_NOACCESS, |
1905 |
&spr_read_generic, &spr_write_generic, |
1906 |
0x00000000);
|
1907 |
spr_register(env, SPR_40x_DAC2, "DAC2",
|
1908 |
SPR_NOACCESS, SPR_NOACCESS, |
1909 |
&spr_read_generic, &spr_write_generic, |
1910 |
0x00000000);
|
1911 |
/* XXX : not implemented */
|
1912 |
spr_register(env, SPR_405_DVC1, "DVC1",
|
1913 |
SPR_NOACCESS, SPR_NOACCESS, |
1914 |
&spr_read_generic, &spr_write_generic, |
1915 |
0x00000000);
|
1916 |
/* XXX : not implemented */
|
1917 |
spr_register(env, SPR_405_DVC2, "DVC2",
|
1918 |
SPR_NOACCESS, SPR_NOACCESS, |
1919 |
&spr_read_generic, &spr_write_generic, |
1920 |
0x00000000);
|
1921 |
/* XXX : not implemented */
|
1922 |
spr_register(env, SPR_40x_IAC1, "IAC1",
|
1923 |
SPR_NOACCESS, SPR_NOACCESS, |
1924 |
&spr_read_generic, &spr_write_generic, |
1925 |
0x00000000);
|
1926 |
spr_register(env, SPR_40x_IAC2, "IAC2",
|
1927 |
SPR_NOACCESS, SPR_NOACCESS, |
1928 |
&spr_read_generic, &spr_write_generic, |
1929 |
0x00000000);
|
1930 |
/* XXX : not implemented */
|
1931 |
spr_register(env, SPR_405_IAC3, "IAC3",
|
1932 |
SPR_NOACCESS, SPR_NOACCESS, |
1933 |
&spr_read_generic, &spr_write_generic, |
1934 |
0x00000000);
|
1935 |
/* XXX : not implemented */
|
1936 |
spr_register(env, SPR_405_IAC4, "IAC4",
|
1937 |
SPR_NOACCESS, SPR_NOACCESS, |
1938 |
&spr_read_generic, &spr_write_generic, |
1939 |
0x00000000);
|
1940 |
/* Storage control */
|
1941 |
/* XXX: TODO: not implemented */
|
1942 |
spr_register(env, SPR_405_SLER, "SLER",
|
1943 |
SPR_NOACCESS, SPR_NOACCESS, |
1944 |
&spr_read_generic, &spr_write_40x_sler, |
1945 |
0x00000000);
|
1946 |
spr_register(env, SPR_40x_ZPR, "ZPR",
|
1947 |
SPR_NOACCESS, SPR_NOACCESS, |
1948 |
&spr_read_generic, &spr_write_generic, |
1949 |
0x00000000);
|
1950 |
/* XXX : not implemented */
|
1951 |
spr_register(env, SPR_405_SU0R, "SU0R",
|
1952 |
SPR_NOACCESS, SPR_NOACCESS, |
1953 |
&spr_read_generic, &spr_write_generic, |
1954 |
0x00000000);
|
1955 |
/* SPRG */
|
1956 |
spr_register(env, SPR_USPRG0, "USPRG0",
|
1957 |
&spr_read_ureg, SPR_NOACCESS, |
1958 |
&spr_read_ureg, SPR_NOACCESS, |
1959 |
0x00000000);
|
1960 |
spr_register(env, SPR_SPRG4, "SPRG4",
|
1961 |
SPR_NOACCESS, SPR_NOACCESS, |
1962 |
&spr_read_generic, &spr_write_generic, |
1963 |
0x00000000);
|
1964 |
spr_register(env, SPR_SPRG5, "SPRG5",
|
1965 |
SPR_NOACCESS, SPR_NOACCESS, |
1966 |
spr_read_generic, &spr_write_generic, |
1967 |
0x00000000);
|
1968 |
spr_register(env, SPR_SPRG6, "SPRG6",
|
1969 |
SPR_NOACCESS, SPR_NOACCESS, |
1970 |
spr_read_generic, &spr_write_generic, |
1971 |
0x00000000);
|
1972 |
spr_register(env, SPR_SPRG7, "SPRG7",
|
1973 |
SPR_NOACCESS, SPR_NOACCESS, |
1974 |
spr_read_generic, &spr_write_generic, |
1975 |
0x00000000);
|
1976 |
gen_spr_usprgh(env); |
1977 |
} |
1978 |
|
1979 |
/* SPR shared between PowerPC 401 & 403 implementations */
|
1980 |
static void gen_spr_401_403 (CPUPPCState *env) |
1981 |
{ |
1982 |
/* Time base */
|
1983 |
spr_register(env, SPR_403_VTBL, "TBL",
|
1984 |
&spr_read_tbl, SPR_NOACCESS, |
1985 |
&spr_read_tbl, SPR_NOACCESS, |
1986 |
0x00000000);
|
1987 |
spr_register(env, SPR_403_TBL, "TBL",
|
1988 |
SPR_NOACCESS, SPR_NOACCESS, |
1989 |
SPR_NOACCESS, &spr_write_tbl, |
1990 |
0x00000000);
|
1991 |
spr_register(env, SPR_403_VTBU, "TBU",
|
1992 |
&spr_read_tbu, SPR_NOACCESS, |
1993 |
&spr_read_tbu, SPR_NOACCESS, |
1994 |
0x00000000);
|
1995 |
spr_register(env, SPR_403_TBU, "TBU",
|
1996 |
SPR_NOACCESS, SPR_NOACCESS, |
1997 |
SPR_NOACCESS, &spr_write_tbu, |
1998 |
0x00000000);
|
1999 |
/* Debug */
|
2000 |
/* not emulated, as QEMU do not emulate caches */
|
2001 |
spr_register(env, SPR_403_CDBCR, "CDBCR",
|
2002 |
SPR_NOACCESS, SPR_NOACCESS, |
2003 |
&spr_read_generic, &spr_write_generic, |
2004 |
0x00000000);
|
2005 |
} |
2006 |
|
2007 |
/* SPR specific to PowerPC 401 implementation */
|
2008 |
static void gen_spr_401 (CPUPPCState *env) |
2009 |
{ |
2010 |
/* Debug interface */
|
2011 |
/* XXX : not implemented */
|
2012 |
spr_register(env, SPR_40x_DBCR0, "DBCR",
|
2013 |
SPR_NOACCESS, SPR_NOACCESS, |
2014 |
&spr_read_generic, &spr_write_40x_dbcr0, |
2015 |
0x00000000);
|
2016 |
/* XXX : not implemented */
|
2017 |
spr_register(env, SPR_40x_DBSR, "DBSR",
|
2018 |
SPR_NOACCESS, SPR_NOACCESS, |
2019 |
&spr_read_generic, &spr_write_clear, |
2020 |
/* Last reset was system reset */
|
2021 |
0x00000300);
|
2022 |
/* XXX : not implemented */
|
2023 |
spr_register(env, SPR_40x_DAC1, "DAC",
|
2024 |
SPR_NOACCESS, SPR_NOACCESS, |
2025 |
&spr_read_generic, &spr_write_generic, |
2026 |
0x00000000);
|
2027 |
/* XXX : not implemented */
|
2028 |
spr_register(env, SPR_40x_IAC1, "IAC",
|
2029 |
SPR_NOACCESS, SPR_NOACCESS, |
2030 |
&spr_read_generic, &spr_write_generic, |
2031 |
0x00000000);
|
2032 |
/* Storage control */
|
2033 |
/* XXX: TODO: not implemented */
|
2034 |
spr_register(env, SPR_405_SLER, "SLER",
|
2035 |
SPR_NOACCESS, SPR_NOACCESS, |
2036 |
&spr_read_generic, &spr_write_40x_sler, |
2037 |
0x00000000);
|
2038 |
/* not emulated, as QEMU never does speculative access */
|
2039 |
spr_register(env, SPR_40x_SGR, "SGR",
|
2040 |
SPR_NOACCESS, SPR_NOACCESS, |
2041 |
&spr_read_generic, &spr_write_generic, |
2042 |
0xFFFFFFFF);
|
2043 |
/* not emulated, as QEMU do not emulate caches */
|
2044 |
spr_register(env, SPR_40x_DCWR, "DCWR",
|
2045 |
SPR_NOACCESS, SPR_NOACCESS, |
2046 |
&spr_read_generic, &spr_write_generic, |
2047 |
0x00000000);
|
2048 |
} |
2049 |
|
2050 |
static void gen_spr_401x2 (CPUPPCState *env) |
2051 |
{ |
2052 |
gen_spr_401(env); |
2053 |
spr_register(env, SPR_40x_PID, "PID",
|
2054 |
SPR_NOACCESS, SPR_NOACCESS, |
2055 |
&spr_read_generic, &spr_write_generic, |
2056 |
0x00000000);
|
2057 |
spr_register(env, SPR_40x_ZPR, "ZPR",
|
2058 |
SPR_NOACCESS, SPR_NOACCESS, |
2059 |
&spr_read_generic, &spr_write_generic, |
2060 |
0x00000000);
|
2061 |
} |
2062 |
|
2063 |
/* SPR specific to PowerPC 403 implementation */
|
2064 |
static void gen_spr_403 (CPUPPCState *env) |
2065 |
{ |
2066 |
/* Debug interface */
|
2067 |
/* XXX : not implemented */
|
2068 |
spr_register(env, SPR_40x_DBCR0, "DBCR0",
|
2069 |
SPR_NOACCESS, SPR_NOACCESS, |
2070 |
&spr_read_generic, &spr_write_40x_dbcr0, |
2071 |
0x00000000);
|
2072 |
/* XXX : not implemented */
|
2073 |
spr_register(env, SPR_40x_DBSR, "DBSR",
|
2074 |
SPR_NOACCESS, SPR_NOACCESS, |
2075 |
&spr_read_generic, &spr_write_clear, |
2076 |
/* Last reset was system reset */
|
2077 |
0x00000300);
|
2078 |
/* XXX : not implemented */
|
2079 |
spr_register(env, SPR_40x_DAC1, "DAC1",
|
2080 |
SPR_NOACCESS, SPR_NOACCESS, |
2081 |
&spr_read_generic, &spr_write_generic, |
2082 |
0x00000000);
|
2083 |
/* XXX : not implemented */
|
2084 |
spr_register(env, SPR_40x_DAC2, "DAC2",
|
2085 |
SPR_NOACCESS, SPR_NOACCESS, |
2086 |
&spr_read_generic, &spr_write_generic, |
2087 |
0x00000000);
|
2088 |
/* XXX : not implemented */
|
2089 |
spr_register(env, SPR_40x_IAC1, "IAC1",
|
2090 |
SPR_NOACCESS, SPR_NOACCESS, |
2091 |
&spr_read_generic, &spr_write_generic, |
2092 |
0x00000000);
|
2093 |
/* XXX : not implemented */
|
2094 |
spr_register(env, SPR_40x_IAC2, "IAC2",
|
2095 |
SPR_NOACCESS, SPR_NOACCESS, |
2096 |
&spr_read_generic, &spr_write_generic, |
2097 |
0x00000000);
|
2098 |
} |
2099 |
|
2100 |
static void gen_spr_403_real (CPUPPCState *env) |
2101 |
{ |
2102 |
spr_register(env, SPR_403_PBL1, "PBL1",
|
2103 |
SPR_NOACCESS, SPR_NOACCESS, |
2104 |
&spr_read_403_pbr, &spr_write_403_pbr, |
2105 |
0x00000000);
|
2106 |
spr_register(env, SPR_403_PBU1, "PBU1",
|
2107 |
SPR_NOACCESS, SPR_NOACCESS, |
2108 |
&spr_read_403_pbr, &spr_write_403_pbr, |
2109 |
0x00000000);
|
2110 |
spr_register(env, SPR_403_PBL2, "PBL2",
|
2111 |
SPR_NOACCESS, SPR_NOACCESS, |
2112 |
&spr_read_403_pbr, &spr_write_403_pbr, |
2113 |
0x00000000);
|
2114 |
spr_register(env, SPR_403_PBU2, "PBU2",
|
2115 |
SPR_NOACCESS, SPR_NOACCESS, |
2116 |
&spr_read_403_pbr, &spr_write_403_pbr, |
2117 |
0x00000000);
|
2118 |
} |
2119 |
|
2120 |
static void gen_spr_403_mmu (CPUPPCState *env) |
2121 |
{ |
2122 |
/* MMU */
|
2123 |
spr_register(env, SPR_40x_PID, "PID",
|
2124 |
SPR_NOACCESS, SPR_NOACCESS, |
2125 |
&spr_read_generic, &spr_write_generic, |
2126 |
0x00000000);
|
2127 |
spr_register(env, SPR_40x_ZPR, "ZPR",
|
2128 |
SPR_NOACCESS, SPR_NOACCESS, |
2129 |
&spr_read_generic, &spr_write_generic, |
2130 |
0x00000000);
|
2131 |
} |
2132 |
|
2133 |
/* SPR specific to PowerPC compression coprocessor extension */
|
2134 |
static void gen_spr_compress (CPUPPCState *env) |
2135 |
{ |
2136 |
/* XXX : not implemented */
|
2137 |
spr_register(env, SPR_401_SKR, "SKR",
|
2138 |
SPR_NOACCESS, SPR_NOACCESS, |
2139 |
&spr_read_generic, &spr_write_generic, |
2140 |
0x00000000);
|
2141 |
} |
2142 |
|
2143 |
#if defined (TARGET_PPC64)
|
2144 |
/* SPR specific to PowerPC 620 */
|
2145 |
static void gen_spr_620 (CPUPPCState *env) |
2146 |
{ |
2147 |
/* Processor identification */
|
2148 |
spr_register(env, SPR_PIR, "PIR",
|
2149 |
SPR_NOACCESS, SPR_NOACCESS, |
2150 |
&spr_read_generic, &spr_write_pir, |
2151 |
0x00000000);
|
2152 |
spr_register(env, SPR_ASR, "ASR",
|
2153 |
SPR_NOACCESS, SPR_NOACCESS, |
2154 |
&spr_read_asr, &spr_write_asr, |
2155 |
0x00000000);
|
2156 |
/* Breakpoints */
|
2157 |
/* XXX : not implemented */
|
2158 |
spr_register(env, SPR_IABR, "IABR",
|
2159 |
SPR_NOACCESS, SPR_NOACCESS, |
2160 |
&spr_read_generic, &spr_write_generic, |
2161 |
0x00000000);
|
2162 |
/* XXX : not implemented */
|
2163 |
spr_register(env, SPR_DABR, "DABR",
|
2164 |
SPR_NOACCESS, SPR_NOACCESS, |
2165 |
&spr_read_generic, &spr_write_generic, |
2166 |
0x00000000);
|
2167 |
/* XXX : not implemented */
|
2168 |
spr_register(env, SPR_SIAR, "SIAR",
|
2169 |
SPR_NOACCESS, SPR_NOACCESS, |
2170 |
&spr_read_generic, SPR_NOACCESS, |
2171 |
0x00000000);
|
2172 |
/* XXX : not implemented */
|
2173 |
spr_register(env, SPR_SDA, "SDA",
|
2174 |
SPR_NOACCESS, SPR_NOACCESS, |
2175 |
&spr_read_generic, SPR_NOACCESS, |
2176 |
0x00000000);
|
2177 |
/* XXX : not implemented */
|
2178 |
spr_register(env, SPR_620_PMC1R, "PMC1",
|
2179 |
SPR_NOACCESS, SPR_NOACCESS, |
2180 |
&spr_read_generic, SPR_NOACCESS, |
2181 |
0x00000000);
|
2182 |
spr_register(env, SPR_620_PMC1W, "PMC1",
|
2183 |
SPR_NOACCESS, SPR_NOACCESS, |
2184 |
SPR_NOACCESS, &spr_write_generic, |
2185 |
0x00000000);
|
2186 |
/* XXX : not implemented */
|
2187 |
spr_register(env, SPR_620_PMC2R, "PMC2",
|
2188 |
SPR_NOACCESS, SPR_NOACCESS, |
2189 |
&spr_read_generic, SPR_NOACCESS, |
2190 |
0x00000000);
|
2191 |
spr_register(env, SPR_620_PMC2W, "PMC2",
|
2192 |
SPR_NOACCESS, SPR_NOACCESS, |
2193 |
SPR_NOACCESS, &spr_write_generic, |
2194 |
0x00000000);
|
2195 |
/* XXX : not implemented */
|
2196 |
spr_register(env, SPR_620_MMCR0R, "MMCR0",
|
2197 |
SPR_NOACCESS, SPR_NOACCESS, |
2198 |
&spr_read_generic, SPR_NOACCESS, |
2199 |
0x00000000);
|
2200 |
spr_register(env, SPR_620_MMCR0W, "MMCR0",
|
2201 |
SPR_NOACCESS, SPR_NOACCESS, |
2202 |
SPR_NOACCESS, &spr_write_generic, |
2203 |
0x00000000);
|
2204 |
/* External access control */
|
2205 |
/* XXX : not implemented */
|
2206 |
spr_register(env, SPR_EAR, "EAR",
|
2207 |
SPR_NOACCESS, SPR_NOACCESS, |
2208 |
&spr_read_generic, &spr_write_generic, |
2209 |
0x00000000);
|
2210 |
#if 0 // XXX: check this
|
2211 |
/* XXX : not implemented */
|
2212 |
spr_register(env, SPR_620_PMR0, "PMR0",
|
2213 |
SPR_NOACCESS, SPR_NOACCESS,
|
2214 |
&spr_read_generic, &spr_write_generic,
|
2215 |
0x00000000);
|
2216 |
/* XXX : not implemented */
|
2217 |
spr_register(env, SPR_620_PMR1, "PMR1",
|
2218 |
SPR_NOACCESS, SPR_NOACCESS,
|
2219 |
&spr_read_generic, &spr_write_generic,
|
2220 |
0x00000000);
|
2221 |
/* XXX : not implemented */
|
2222 |
spr_register(env, SPR_620_PMR2, "PMR2",
|
2223 |
SPR_NOACCESS, SPR_NOACCESS,
|
2224 |
&spr_read_generic, &spr_write_generic,
|
2225 |
0x00000000);
|
2226 |
/* XXX : not implemented */
|
2227 |
spr_register(env, SPR_620_PMR3, "PMR3",
|
2228 |
SPR_NOACCESS, SPR_NOACCESS,
|
2229 |
&spr_read_generic, &spr_write_generic,
|
2230 |
0x00000000);
|
2231 |
/* XXX : not implemented */
|
2232 |
spr_register(env, SPR_620_PMR4, "PMR4",
|
2233 |
SPR_NOACCESS, SPR_NOACCESS,
|
2234 |
&spr_read_generic, &spr_write_generic,
|
2235 |
0x00000000);
|
2236 |
/* XXX : not implemented */
|
2237 |
spr_register(env, SPR_620_PMR5, "PMR5",
|
2238 |
SPR_NOACCESS, SPR_NOACCESS,
|
2239 |
&spr_read_generic, &spr_write_generic,
|
2240 |
0x00000000);
|
2241 |
/* XXX : not implemented */
|
2242 |
spr_register(env, SPR_620_PMR6, "PMR6",
|
2243 |
SPR_NOACCESS, SPR_NOACCESS,
|
2244 |
&spr_read_generic, &spr_write_generic,
|
2245 |
0x00000000);
|
2246 |
/* XXX : not implemented */
|
2247 |
spr_register(env, SPR_620_PMR7, "PMR7",
|
2248 |
SPR_NOACCESS, SPR_NOACCESS,
|
2249 |
&spr_read_generic, &spr_write_generic,
|
2250 |
0x00000000);
|
2251 |
/* XXX : not implemented */
|
2252 |
spr_register(env, SPR_620_PMR8, "PMR8",
|
2253 |
SPR_NOACCESS, SPR_NOACCESS,
|
2254 |
&spr_read_generic, &spr_write_generic,
|
2255 |
0x00000000);
|
2256 |
/* XXX : not implemented */
|
2257 |
spr_register(env, SPR_620_PMR9, "PMR9",
|
2258 |
SPR_NOACCESS, SPR_NOACCESS,
|
2259 |
&spr_read_generic, &spr_write_generic,
|
2260 |
0x00000000);
|
2261 |
/* XXX : not implemented */
|
2262 |
spr_register(env, SPR_620_PMRA, "PMR10",
|
2263 |
SPR_NOACCESS, SPR_NOACCESS,
|
2264 |
&spr_read_generic, &spr_write_generic,
|
2265 |
0x00000000);
|
2266 |
/* XXX : not implemented */
|
2267 |
spr_register(env, SPR_620_PMRB, "PMR11",
|
2268 |
SPR_NOACCESS, SPR_NOACCESS,
|
2269 |
&spr_read_generic, &spr_write_generic,
|
2270 |
0x00000000);
|
2271 |
/* XXX : not implemented */
|
2272 |
spr_register(env, SPR_620_PMRC, "PMR12",
|
2273 |
SPR_NOACCESS, SPR_NOACCESS,
|
2274 |
&spr_read_generic, &spr_write_generic,
|
2275 |
0x00000000);
|
2276 |
/* XXX : not implemented */
|
2277 |
spr_register(env, SPR_620_PMRD, "PMR13",
|
2278 |
SPR_NOACCESS, SPR_NOACCESS,
|
2279 |
&spr_read_generic, &spr_write_generic,
|
2280 |
0x00000000);
|
2281 |
/* XXX : not implemented */
|
2282 |
spr_register(env, SPR_620_PMRE, "PMR14",
|
2283 |
SPR_NOACCESS, SPR_NOACCESS,
|
2284 |
&spr_read_generic, &spr_write_generic,
|
2285 |
0x00000000);
|
2286 |
/* XXX : not implemented */
|
2287 |
spr_register(env, SPR_620_PMRF, "PMR15",
|
2288 |
SPR_NOACCESS, SPR_NOACCESS,
|
2289 |
&spr_read_generic, &spr_write_generic,
|
2290 |
0x00000000);
|
2291 |
#endif
|
2292 |
/* XXX : not implemented */
|
2293 |
spr_register(env, SPR_620_BUSCSR, "BUSCSR",
|
2294 |
SPR_NOACCESS, SPR_NOACCESS, |
2295 |
&spr_read_generic, &spr_write_generic, |
2296 |
0x00000000);
|
2297 |
/* XXX : not implemented */
|
2298 |
spr_register(env, SPR_620_L2CR, "L2CR",
|
2299 |
SPR_NOACCESS, SPR_NOACCESS, |
2300 |
&spr_read_generic, &spr_write_generic, |
2301 |
0x00000000);
|
2302 |
/* XXX : not implemented */
|
2303 |
spr_register(env, SPR_620_L2SR, "L2SR",
|
2304 |
SPR_NOACCESS, SPR_NOACCESS, |
2305 |
&spr_read_generic, &spr_write_generic, |
2306 |
0x00000000);
|
2307 |
} |
2308 |
#endif /* defined (TARGET_PPC64) */ |
2309 |
|
2310 |
static void gen_spr_5xx_8xx (CPUPPCState *env) |
2311 |
{ |
2312 |
/* Exception processing */
|
2313 |
spr_register(env, SPR_DSISR, "DSISR",
|
2314 |
SPR_NOACCESS, SPR_NOACCESS, |
2315 |
&spr_read_generic, &spr_write_generic, |
2316 |
0x00000000);
|
2317 |
spr_register(env, SPR_DAR, "DAR",
|
2318 |
SPR_NOACCESS, SPR_NOACCESS, |
2319 |
&spr_read_generic, &spr_write_generic, |
2320 |
0x00000000);
|
2321 |
/* Timer */
|
2322 |
spr_register(env, SPR_DECR, "DECR",
|
2323 |
SPR_NOACCESS, SPR_NOACCESS, |
2324 |
&spr_read_decr, &spr_write_decr, |
2325 |
0x00000000);
|
2326 |
/* XXX : not implemented */
|
2327 |
spr_register(env, SPR_MPC_EIE, "EIE",
|
2328 |
SPR_NOACCESS, SPR_NOACCESS, |
2329 |
&spr_read_generic, &spr_write_generic, |
2330 |
0x00000000);
|
2331 |
/* XXX : not implemented */
|
2332 |
spr_register(env, SPR_MPC_EID, "EID",
|
2333 |
SPR_NOACCESS, SPR_NOACCESS, |
2334 |
&spr_read_generic, &spr_write_generic, |
2335 |
0x00000000);
|
2336 |
/* XXX : not implemented */
|
2337 |
spr_register(env, SPR_MPC_NRI, "NRI",
|
2338 |
SPR_NOACCESS, SPR_NOACCESS, |
2339 |
&spr_read_generic, &spr_write_generic, |
2340 |
0x00000000);
|
2341 |
/* XXX : not implemented */
|
2342 |
spr_register(env, SPR_MPC_CMPA, "CMPA",
|
2343 |
SPR_NOACCESS, SPR_NOACCESS, |
2344 |
&spr_read_generic, &spr_write_generic, |
2345 |
0x00000000);
|
2346 |
/* XXX : not implemented */
|
2347 |
spr_register(env, SPR_MPC_CMPB, "CMPB",
|
2348 |
SPR_NOACCESS, SPR_NOACCESS, |
2349 |
&spr_read_generic, &spr_write_generic, |
2350 |
0x00000000);
|
2351 |
/* XXX : not implemented */
|
2352 |
spr_register(env, SPR_MPC_CMPC, "CMPC",
|
2353 |
SPR_NOACCESS, SPR_NOACCESS, |
2354 |
&spr_read_generic, &spr_write_generic, |
2355 |
0x00000000);
|
2356 |
/* XXX : not implemented */
|
2357 |
spr_register(env, SPR_MPC_CMPD, "CMPD",
|
2358 |
SPR_NOACCESS, SPR_NOACCESS, |
2359 |
&spr_read_generic, &spr_write_generic, |
2360 |
0x00000000);
|
2361 |
/* XXX : not implemented */
|
2362 |
spr_register(env, SPR_MPC_ECR, "ECR",
|
2363 |
SPR_NOACCESS, SPR_NOACCESS, |
2364 |
&spr_read_generic, &spr_write_generic, |
2365 |
0x00000000);
|
2366 |
/* XXX : not implemented */
|
2367 |
spr_register(env, SPR_MPC_DER, "DER",
|
2368 |
SPR_NOACCESS, SPR_NOACCESS, |
2369 |
&spr_read_generic, &spr_write_generic, |
2370 |
0x00000000);
|
2371 |
/* XXX : not implemented */
|
2372 |
spr_register(env, SPR_MPC_COUNTA, "COUNTA",
|
2373 |
SPR_NOACCESS, SPR_NOACCESS, |
2374 |
&spr_read_generic, &spr_write_generic, |
2375 |
0x00000000);
|
2376 |
/* XXX : not implemented */
|
2377 |
spr_register(env, SPR_MPC_COUNTB, "COUNTB",
|
2378 |
SPR_NOACCESS, SPR_NOACCESS, |
2379 |
&spr_read_generic, &spr_write_generic, |
2380 |
0x00000000);
|
2381 |
/* XXX : not implemented */
|
2382 |
spr_register(env, SPR_MPC_CMPE, "CMPE",
|
2383 |
SPR_NOACCESS, SPR_NOACCESS, |
2384 |
&spr_read_generic, &spr_write_generic, |
2385 |
0x00000000);
|
2386 |
/* XXX : not implemented */
|
2387 |
spr_register(env, SPR_MPC_CMPF, "CMPF",
|
2388 |
SPR_NOACCESS, SPR_NOACCESS, |
2389 |
&spr_read_generic, &spr_write_generic, |
2390 |
0x00000000);
|
2391 |
/* XXX : not implemented */
|
2392 |
spr_register(env, SPR_MPC_CMPG, "CMPG",
|
2393 |
SPR_NOACCESS, SPR_NOACCESS, |
2394 |
&spr_read_generic, &spr_write_generic, |
2395 |
0x00000000);
|
2396 |
/* XXX : not implemented */
|
2397 |
spr_register(env, SPR_MPC_CMPH, "CMPH",
|
2398 |
SPR_NOACCESS, SPR_NOACCESS, |
2399 |
&spr_read_generic, &spr_write_generic, |
2400 |
0x00000000);
|
2401 |
/* XXX : not implemented */
|
2402 |
spr_register(env, SPR_MPC_LCTRL1, "LCTRL1",
|
2403 |
SPR_NOACCESS, SPR_NOACCESS, |
2404 |
&spr_read_generic, &spr_write_generic, |
2405 |
0x00000000);
|
2406 |
/* XXX : not implemented */
|
2407 |
spr_register(env, SPR_MPC_LCTRL2, "LCTRL2",
|
2408 |
SPR_NOACCESS, SPR_NOACCESS, |
2409 |
&spr_read_generic, &spr_write_generic, |
2410 |
0x00000000);
|
2411 |
/* XXX : not implemented */
|
2412 |
spr_register(env, SPR_MPC_BAR, "BAR",
|
2413 |
SPR_NOACCESS, SPR_NOACCESS, |
2414 |
&spr_read_generic, &spr_write_generic, |
2415 |
0x00000000);
|
2416 |
/* XXX : not implemented */
|
2417 |
spr_register(env, SPR_MPC_DPDR, "DPDR",
|
2418 |
SPR_NOACCESS, SPR_NOACCESS, |
2419 |
&spr_read_generic, &spr_write_generic, |
2420 |
0x00000000);
|
2421 |
/* XXX : not implemented */
|
2422 |
spr_register(env, SPR_MPC_IMMR, "IMMR",
|
2423 |
SPR_NOACCESS, SPR_NOACCESS, |
2424 |
&spr_read_generic, &spr_write_generic, |
2425 |
0x00000000);
|
2426 |
} |
2427 |
|
2428 |
static void gen_spr_5xx (CPUPPCState *env) |
2429 |
{ |
2430 |
/* XXX : not implemented */
|
2431 |
spr_register(env, SPR_RCPU_MI_GRA, "MI_GRA",
|
2432 |
SPR_NOACCESS, SPR_NOACCESS, |
2433 |
&spr_read_generic, &spr_write_generic, |
2434 |
0x00000000);
|
2435 |
/* XXX : not implemented */
|
2436 |
spr_register(env, SPR_RCPU_L2U_GRA, "L2U_GRA",
|
2437 |
SPR_NOACCESS, SPR_NOACCESS, |
2438 |
&spr_read_generic, &spr_write_generic, |
2439 |
0x00000000);
|
2440 |
/* XXX : not implemented */
|
2441 |
spr_register(env, SPR_RPCU_BBCMCR, "L2U_BBCMCR",
|
2442 |
SPR_NOACCESS, SPR_NOACCESS, |
2443 |
&spr_read_generic, &spr_write_generic, |
2444 |
0x00000000);
|
2445 |
/* XXX : not implemented */
|
2446 |
spr_register(env, SPR_RCPU_L2U_MCR, "L2U_MCR",
|
2447 |
SPR_NOACCESS, SPR_NOACCESS, |
2448 |
&spr_read_generic, &spr_write_generic, |
2449 |
0x00000000);
|
2450 |
/* XXX : not implemented */
|
2451 |
spr_register(env, SPR_RCPU_MI_RBA0, "MI_RBA0",
|
2452 |
SPR_NOACCESS, SPR_NOACCESS, |
2453 |
&spr_read_generic, &spr_write_generic, |
2454 |
0x00000000);
|
2455 |
/* XXX : not implemented */
|
2456 |
spr_register(env, SPR_RCPU_MI_RBA1, "MI_RBA1",
|
2457 |
SPR_NOACCESS, SPR_NOACCESS, |
2458 |
&spr_read_generic, &spr_write_generic, |
2459 |
0x00000000);
|
2460 |
/* XXX : not implemented */
|
2461 |
spr_register(env, SPR_RCPU_MI_RBA2, "MI_RBA2",
|
2462 |
SPR_NOACCESS, SPR_NOACCESS, |
2463 |
&spr_read_generic, &spr_write_generic, |
2464 |
0x00000000);
|
2465 |
/* XXX : not implemented */
|
2466 |
spr_register(env, SPR_RCPU_MI_RBA3, "MI_RBA3",
|
2467 |
SPR_NOACCESS, SPR_NOACCESS, |
2468 |
&spr_read_generic, &spr_write_generic, |
2469 |
0x00000000);
|
2470 |
/* XXX : not implemented */
|
2471 |
spr_register(env, SPR_RCPU_L2U_RBA0, "L2U_RBA0",
|
2472 |
SPR_NOACCESS, SPR_NOACCESS, |
2473 |
&spr_read_generic, &spr_write_generic, |
2474 |
0x00000000);
|
2475 |
/* XXX : not implemented */
|
2476 |
spr_register(env, SPR_RCPU_L2U_RBA1, "L2U_RBA1",
|
2477 |
SPR_NOACCESS, SPR_NOACCESS, |
2478 |
&spr_read_generic, &spr_write_generic, |
2479 |
0x00000000);
|
2480 |
/* XXX : not implemented */
|
2481 |
spr_register(env, SPR_RCPU_L2U_RBA2, "L2U_RBA2",
|
2482 |
SPR_NOACCESS, SPR_NOACCESS, |
2483 |
&spr_read_generic, &spr_write_generic, |
2484 |
0x00000000);
|
2485 |
/* XXX : not implemented */
|
2486 |
spr_register(env, SPR_RCPU_L2U_RBA3, "L2U_RBA3",
|
2487 |
SPR_NOACCESS, SPR_NOACCESS, |
2488 |
&spr_read_generic, &spr_write_generic, |
2489 |
0x00000000);
|
2490 |
/* XXX : not implemented */
|
2491 |
spr_register(env, SPR_RCPU_MI_RA0, "MI_RA0",
|
2492 |
SPR_NOACCESS, SPR_NOACCESS, |
2493 |
&spr_read_generic, &spr_write_generic, |
2494 |
0x00000000);
|
2495 |
/* XXX : not implemented */
|
2496 |
spr_register(env, SPR_RCPU_MI_RA1, "MI_RA1",
|
2497 |
SPR_NOACCESS, SPR_NOACCESS, |
2498 |
&spr_read_generic, &spr_write_generic, |
2499 |
0x00000000);
|
2500 |
/* XXX : not implemented */
|
2501 |
spr_register(env, SPR_RCPU_MI_RA2, "MI_RA2",
|
2502 |
SPR_NOACCESS, SPR_NOACCESS, |
2503 |
&spr_read_generic, &spr_write_generic, |
2504 |
0x00000000);
|
2505 |
/* XXX : not implemented */
|
2506 |
spr_register(env, SPR_RCPU_MI_RA3, "MI_RA3",
|
2507 |
SPR_NOACCESS, SPR_NOACCESS, |
2508 |
&spr_read_generic, &spr_write_generic, |
2509 |
0x00000000);
|
2510 |
/* XXX : not implemented */
|
2511 |
spr_register(env, SPR_RCPU_L2U_RA0, "L2U_RA0",
|
2512 |
SPR_NOACCESS, SPR_NOACCESS, |
2513 |
&spr_read_generic, &spr_write_generic, |
2514 |
0x00000000);
|
2515 |
/* XXX : not implemented */
|
2516 |
spr_register(env, SPR_RCPU_L2U_RA1, "L2U_RA1",
|
2517 |
SPR_NOACCESS, SPR_NOACCESS, |
2518 |
&spr_read_generic, &spr_write_generic, |
2519 |
0x00000000);
|
2520 |
/* XXX : not implemented */
|
2521 |
spr_register(env, SPR_RCPU_L2U_RA2, "L2U_RA2",
|
2522 |
SPR_NOACCESS, SPR_NOACCESS, |
2523 |
&spr_read_generic, &spr_write_generic, |
2524 |
0x00000000);
|
2525 |
/* XXX : not implemented */
|
2526 |
spr_register(env, SPR_RCPU_L2U_RA3, "L2U_RA3",
|
2527 |
SPR_NOACCESS, SPR_NOACCESS, |
2528 |
&spr_read_generic, &spr_write_generic, |
2529 |
0x00000000);
|
2530 |
/* XXX : not implemented */
|
2531 |
spr_register(env, SPR_RCPU_FPECR, "FPECR",
|
2532 |
SPR_NOACCESS, SPR_NOACCESS, |
2533 |
&spr_read_generic, &spr_write_generic, |
2534 |
0x00000000);
|
2535 |
} |
2536 |
|
2537 |
static void gen_spr_8xx (CPUPPCState *env) |
2538 |
{ |
2539 |
/* XXX : not implemented */
|
2540 |
spr_register(env, SPR_MPC_IC_CST, "IC_CST",
|
2541 |
SPR_NOACCESS, SPR_NOACCESS, |
2542 |
&spr_read_generic, &spr_write_generic, |
2543 |
0x00000000);
|
2544 |
/* XXX : not implemented */
|
2545 |
spr_register(env, SPR_MPC_IC_ADR, "IC_ADR",
|
2546 |
SPR_NOACCESS, SPR_NOACCESS, |
2547 |
&spr_read_generic, &spr_write_generic, |
2548 |
0x00000000);
|
2549 |
/* XXX : not implemented */
|
2550 |
spr_register(env, SPR_MPC_IC_DAT, "IC_DAT",
|
2551 |
SPR_NOACCESS, SPR_NOACCESS, |
2552 |
&spr_read_generic, &spr_write_generic, |
2553 |
0x00000000);
|
2554 |
/* XXX : not implemented */
|
2555 |
spr_register(env, SPR_MPC_DC_CST, "DC_CST",
|
2556 |
SPR_NOACCESS, SPR_NOACCESS, |
2557 |
&spr_read_generic, &spr_write_generic, |
2558 |
0x00000000);
|
2559 |
/* XXX : not implemented */
|
2560 |
spr_register(env, SPR_MPC_DC_ADR, "DC_ADR",
|
2561 |
SPR_NOACCESS, SPR_NOACCESS, |
2562 |
&spr_read_generic, &spr_write_generic, |
2563 |
0x00000000);
|
2564 |
/* XXX : not implemented */
|
2565 |
spr_register(env, SPR_MPC_DC_DAT, "DC_DAT",
|
2566 |
SPR_NOACCESS, SPR_NOACCESS, |
2567 |
&spr_read_generic, &spr_write_generic, |
2568 |
0x00000000);
|
2569 |
/* XXX : not implemented */
|
2570 |
spr_register(env, SPR_MPC_MI_CTR, "MI_CTR",
|
2571 |
SPR_NOACCESS, SPR_NOACCESS, |
2572 |
&spr_read_generic, &spr_write_generic, |
2573 |
0x00000000);
|
2574 |
/* XXX : not implemented */
|
2575 |
spr_register(env, SPR_MPC_MI_AP, "MI_AP",
|
2576 |
SPR_NOACCESS, SPR_NOACCESS, |
2577 |
&spr_read_generic, &spr_write_generic, |
2578 |
0x00000000);
|
2579 |
/* XXX : not implemented */
|
2580 |
spr_register(env, SPR_MPC_MI_EPN, "MI_EPN",
|
2581 |
SPR_NOACCESS, SPR_NOACCESS, |
2582 |
&spr_read_generic, &spr_write_generic, |
2583 |
0x00000000);
|
2584 |
/* XXX : not implemented */
|
2585 |
spr_register(env, SPR_MPC_MI_TWC, "MI_TWC",
|
2586 |
SPR_NOACCESS, SPR_NOACCESS, |
2587 |
&spr_read_generic, &spr_write_generic, |
2588 |
0x00000000);
|
2589 |
/* XXX : not implemented */
|
2590 |
spr_register(env, SPR_MPC_MI_RPN, "MI_RPN",
|
2591 |
SPR_NOACCESS, SPR_NOACCESS, |
2592 |
&spr_read_generic, &spr_write_generic, |
2593 |
0x00000000);
|
2594 |
/* XXX : not implemented */
|
2595 |
spr_register(env, SPR_MPC_MI_DBCAM, "MI_DBCAM",
|
2596 |
SPR_NOACCESS, SPR_NOACCESS, |
2597 |
&spr_read_generic, &spr_write_generic, |
2598 |
0x00000000);
|
2599 |
/* XXX : not implemented */
|
2600 |
spr_register(env, SPR_MPC_MI_DBRAM0, "MI_DBRAM0",
|
2601 |
SPR_NOACCESS, SPR_NOACCESS, |
2602 |
&spr_read_generic, &spr_write_generic, |
2603 |
0x00000000);
|
2604 |
/* XXX : not implemented */
|
2605 |
spr_register(env, SPR_MPC_MI_DBRAM1, "MI_DBRAM1",
|
2606 |
SPR_NOACCESS, SPR_NOACCESS, |
2607 |
&spr_read_generic, &spr_write_generic, |
2608 |
0x00000000);
|
2609 |
/* XXX : not implemented */
|
2610 |
spr_register(env, SPR_MPC_MD_CTR, "MD_CTR",
|
2611 |
SPR_NOACCESS, SPR_NOACCESS, |
2612 |
&spr_read_generic, &spr_write_generic, |
2613 |
0x00000000);
|
2614 |
/* XXX : not implemented */
|
2615 |
spr_register(env, SPR_MPC_MD_CASID, "MD_CASID",
|
2616 |
SPR_NOACCESS, SPR_NOACCESS, |
2617 |
&spr_read_generic, &spr_write_generic, |
2618 |
0x00000000);
|
2619 |
/* XXX : not implemented */
|
2620 |
spr_register(env, SPR_MPC_MD_AP, "MD_AP",
|
2621 |
SPR_NOACCESS, SPR_NOACCESS, |
2622 |
&spr_read_generic, &spr_write_generic, |
2623 |
0x00000000);
|
2624 |
/* XXX : not implemented */
|
2625 |
spr_register(env, SPR_MPC_MD_EPN, "MD_EPN",
|
2626 |
SPR_NOACCESS, SPR_NOACCESS, |
2627 |
&spr_read_generic, &spr_write_generic, |
2628 |
0x00000000);
|
2629 |
/* XXX : not implemented */
|
2630 |
spr_register(env, SPR_MPC_MD_TWB, "MD_TWB",
|
2631 |
SPR_NOACCESS, SPR_NOACCESS, |
2632 |
&spr_read_generic, &spr_write_generic, |
2633 |
0x00000000);
|
2634 |
/* XXX : not implemented */
|
2635 |
spr_register(env, SPR_MPC_MD_TWC, "MD_TWC",
|
2636 |
SPR_NOACCESS, SPR_NOACCESS, |
2637 |
&spr_read_generic, &spr_write_generic, |
2638 |
0x00000000);
|
2639 |
/* XXX : not implemented */
|
2640 |
spr_register(env, SPR_MPC_MD_RPN, "MD_RPN",
|
2641 |
SPR_NOACCESS, SPR_NOACCESS, |
2642 |
&spr_read_generic, &spr_write_generic, |
2643 |
0x00000000);
|
2644 |
/* XXX : not implemented */
|
2645 |
spr_register(env, SPR_MPC_MD_TW, "MD_TW",
|
2646 |
SPR_NOACCESS, SPR_NOACCESS, |
2647 |
&spr_read_generic, &spr_write_generic, |
2648 |
0x00000000);
|
2649 |
/* XXX : not implemented */
|
2650 |
spr_register(env, SPR_MPC_MD_DBCAM, "MD_DBCAM",
|
2651 |
SPR_NOACCESS, SPR_NOACCESS, |
2652 |
&spr_read_generic, &spr_write_generic, |
2653 |
0x00000000);
|
2654 |
/* XXX : not implemented */
|
2655 |
spr_register(env, SPR_MPC_MD_DBRAM0, "MD_DBRAM0",
|
2656 |
SPR_NOACCESS, SPR_NOACCESS, |
2657 |
&spr_read_generic, &spr_write_generic, |
2658 |
0x00000000);
|
2659 |
/* XXX : not implemented */
|
2660 |
spr_register(env, SPR_MPC_MD_DBRAM1, "MD_DBRAM1",
|
2661 |
SPR_NOACCESS, SPR_NOACCESS, |
2662 |
&spr_read_generic, &spr_write_generic, |
2663 |
0x00000000);
|
2664 |
} |
2665 |
|
2666 |
// XXX: TODO
|
2667 |
/*
|
2668 |
* AMR => SPR 29 (Power 2.04)
|
2669 |
* CTRL => SPR 136 (Power 2.04)
|
2670 |
* CTRL => SPR 152 (Power 2.04)
|
2671 |
* SCOMC => SPR 276 (64 bits ?)
|
2672 |
* SCOMD => SPR 277 (64 bits ?)
|
2673 |
* TBU40 => SPR 286 (Power 2.04 hypv)
|
2674 |
* HSPRG0 => SPR 304 (Power 2.04 hypv)
|
2675 |
* HSPRG1 => SPR 305 (Power 2.04 hypv)
|
2676 |
* HDSISR => SPR 306 (Power 2.04 hypv)
|
2677 |
* HDAR => SPR 307 (Power 2.04 hypv)
|
2678 |
* PURR => SPR 309 (Power 2.04 hypv)
|
2679 |
* HDEC => SPR 310 (Power 2.04 hypv)
|
2680 |
* HIOR => SPR 311 (hypv)
|
2681 |
* RMOR => SPR 312 (970)
|
2682 |
* HRMOR => SPR 313 (Power 2.04 hypv)
|
2683 |
* HSRR0 => SPR 314 (Power 2.04 hypv)
|
2684 |
* HSRR1 => SPR 315 (Power 2.04 hypv)
|
2685 |
* LPCR => SPR 316 (970)
|
2686 |
* LPIDR => SPR 317 (970)
|
2687 |
* EPR => SPR 702 (Power 2.04 emb)
|
2688 |
* perf => 768-783 (Power 2.04)
|
2689 |
* perf => 784-799 (Power 2.04)
|
2690 |
* PPR => SPR 896 (Power 2.04)
|
2691 |
* EPLC => SPR 947 (Power 2.04 emb)
|
2692 |
* EPSC => SPR 948 (Power 2.04 emb)
|
2693 |
* DABRX => 1015 (Power 2.04 hypv)
|
2694 |
* FPECR => SPR 1022 (?)
|
2695 |
* ... and more (thermal management, performance counters, ...)
|
2696 |
*/
|
2697 |
|
2698 |
/*****************************************************************************/
|
2699 |
/* Exception vectors models */
|
2700 |
static void init_excp_4xx_real (CPUPPCState *env) |
2701 |
{ |
2702 |
#if !defined(CONFIG_USER_ONLY)
|
2703 |
env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000100;
|
2704 |
env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
|
2705 |
env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
|
2706 |
env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
|
2707 |
env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
|
2708 |
env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
|
2709 |
env->excp_vectors[POWERPC_EXCP_PIT] = 0x00001000;
|
2710 |
env->excp_vectors[POWERPC_EXCP_FIT] = 0x00001010;
|
2711 |
env->excp_vectors[POWERPC_EXCP_WDT] = 0x00001020;
|
2712 |
env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00002000;
|
2713 |
env->hreset_excp_prefix = 0x00000000UL;
|
2714 |
env->ivor_mask = 0x0000FFF0UL;
|
2715 |
env->ivpr_mask = 0xFFFF0000UL;
|
2716 |
/* Hardware reset vector */
|
2717 |
env->hreset_vector = 0xFFFFFFFCUL;
|
2718 |
#endif
|
2719 |
} |
2720 |
|
2721 |
static void init_excp_4xx_softmmu (CPUPPCState *env) |
2722 |
{ |
2723 |
#if !defined(CONFIG_USER_ONLY)
|
2724 |
env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000100;
|
2725 |
env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
|
2726 |
env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
|
2727 |
env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
|
2728 |
env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
|
2729 |
env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
|
2730 |
env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
|
2731 |
env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
|
2732 |
env->excp_vectors[POWERPC_EXCP_PIT] = 0x00001000;
|
2733 |
env->excp_vectors[POWERPC_EXCP_FIT] = 0x00001010;
|
2734 |
env->excp_vectors[POWERPC_EXCP_WDT] = 0x00001020;
|
2735 |
env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00001100;
|
2736 |
env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00001200;
|
2737 |
env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00002000;
|
2738 |
env->hreset_excp_prefix = 0x00000000UL;
|
2739 |
env->ivor_mask = 0x0000FFF0UL;
|
2740 |
env->ivpr_mask = 0xFFFF0000UL;
|
2741 |
/* Hardware reset vector */
|
2742 |
env->hreset_vector = 0xFFFFFFFCUL;
|
2743 |
#endif
|
2744 |
} |
2745 |
|
2746 |
static void init_excp_MPC5xx (CPUPPCState *env) |
2747 |
{ |
2748 |
#if !defined(CONFIG_USER_ONLY)
|
2749 |
env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
|
2750 |
env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
|
2751 |
env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
|
2752 |
env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
|
2753 |
env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
|
2754 |
env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000900;
|
2755 |
env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
|
2756 |
env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
|
2757 |
env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
|
2758 |
env->excp_vectors[POWERPC_EXCP_FPA] = 0x00000E00;
|
2759 |
env->excp_vectors[POWERPC_EXCP_EMUL] = 0x00001000;
|
2760 |
env->excp_vectors[POWERPC_EXCP_DABR] = 0x00001C00;
|
2761 |
env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001C00;
|
2762 |
env->excp_vectors[POWERPC_EXCP_MEXTBR] = 0x00001E00;
|
2763 |
env->excp_vectors[POWERPC_EXCP_NMEXTBR] = 0x00001F00;
|
2764 |
env->hreset_excp_prefix = 0x00000000UL;
|
2765 |
env->ivor_mask = 0x0000FFF0UL;
|
2766 |
env->ivpr_mask = 0xFFFF0000UL;
|
2767 |
/* Hardware reset vector */
|
2768 |
env->hreset_vector = 0xFFFFFFFCUL;
|
2769 |
#endif
|
2770 |
} |
2771 |
|
2772 |
static void init_excp_MPC8xx (CPUPPCState *env) |
2773 |
{ |
2774 |
#if !defined(CONFIG_USER_ONLY)
|
2775 |
env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
|
2776 |
env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
|
2777 |
env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
|
2778 |
env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
|
2779 |
env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
|
2780 |
env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
|
2781 |
env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
|
2782 |
env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000900;
|
2783 |
env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
|
2784 |
env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
|
2785 |
env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
|
2786 |
env->excp_vectors[POWERPC_EXCP_FPA] = 0x00000E00;
|
2787 |
env->excp_vectors[POWERPC_EXCP_EMUL] = 0x00001000;
|
2788 |
env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00001100;
|
2789 |
env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00001200;
|
2790 |
env->excp_vectors[POWERPC_EXCP_ITLBE] = 0x00001300;
|
2791 |
env->excp_vectors[POWERPC_EXCP_DTLBE] = 0x00001400;
|
2792 |
env->excp_vectors[POWERPC_EXCP_DABR] = 0x00001C00;
|
2793 |
env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001C00;
|
2794 |
env->excp_vectors[POWERPC_EXCP_MEXTBR] = 0x00001E00;
|
2795 |
env->excp_vectors[POWERPC_EXCP_NMEXTBR] = 0x00001F00;
|
2796 |
env->hreset_excp_prefix = 0x00000000UL;
|
2797 |
env->ivor_mask = 0x0000FFF0UL;
|
2798 |
env->ivpr_mask = 0xFFFF0000UL;
|
2799 |
/* Hardware reset vector */
|
2800 |
env->hreset_vector = 0xFFFFFFFCUL;
|
2801 |
#endif
|
2802 |
} |
2803 |
|
2804 |
static void init_excp_G2 (CPUPPCState *env) |
2805 |
{ |
2806 |
#if !defined(CONFIG_USER_ONLY)
|
2807 |
env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
|
2808 |
env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
|
2809 |
env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
|
2810 |
env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
|
2811 |
env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
|
2812 |
env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
|
2813 |
env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
|
2814 |
env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
|
2815 |
env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
|
2816 |
env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000A00;
|
2817 |
env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
|
2818 |
env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
|
2819 |
env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
|
2820 |
env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
|
2821 |
env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
|
2822 |
env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
|
2823 |
env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
|
2824 |
env->hreset_excp_prefix = 0x00000000UL;
|
2825 |
/* Hardware reset vector */
|
2826 |
env->hreset_vector = 0xFFFFFFFCUL;
|
2827 |
#endif
|
2828 |
} |
2829 |
|
2830 |
static void init_excp_e200(CPUPPCState *env, target_ulong ivpr_mask) |
2831 |
{ |
2832 |
#if !defined(CONFIG_USER_ONLY)
|
2833 |
env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000FFC;
|
2834 |
env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000000;
|
2835 |
env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000000;
|
2836 |
env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000000;
|
2837 |
env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000000;
|
2838 |
env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000000;
|
2839 |
env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000000;
|
2840 |
env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000000;
|
2841 |
env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000000;
|
2842 |
env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000000;
|
2843 |
env->excp_vectors[POWERPC_EXCP_APU] = 0x00000000;
|
2844 |
env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000000;
|
2845 |
env->excp_vectors[POWERPC_EXCP_FIT] = 0x00000000;
|
2846 |
env->excp_vectors[POWERPC_EXCP_WDT] = 0x00000000;
|
2847 |
env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00000000;
|
2848 |
env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00000000;
|
2849 |
env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00000000;
|
2850 |
env->excp_vectors[POWERPC_EXCP_SPEU] = 0x00000000;
|
2851 |
env->excp_vectors[POWERPC_EXCP_EFPDI] = 0x00000000;
|
2852 |
env->excp_vectors[POWERPC_EXCP_EFPRI] = 0x00000000;
|
2853 |
env->hreset_excp_prefix = 0x00000000UL;
|
2854 |
env->ivor_mask = 0x0000FFF7UL;
|
2855 |
env->ivpr_mask = ivpr_mask; |
2856 |
/* Hardware reset vector */
|
2857 |
env->hreset_vector = 0xFFFFFFFCUL;
|
2858 |
#endif
|
2859 |
} |
2860 |
|
2861 |
static void init_excp_BookE (CPUPPCState *env) |
2862 |
{ |
2863 |
#if !defined(CONFIG_USER_ONLY)
|
2864 |
env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000000;
|
2865 |
env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000000;
|
2866 |
env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000000;
|
2867 |
env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000000;
|
2868 |
env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000000;
|
2869 |
env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000000;
|
2870 |
env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000000;
|
2871 |
env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000000;
|
2872 |
env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000000;
|
2873 |
env->excp_vectors[POWERPC_EXCP_APU] = 0x00000000;
|
2874 |
env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000000;
|
2875 |
env->excp_vectors[POWERPC_EXCP_FIT] = 0x00000000;
|
2876 |
env->excp_vectors[POWERPC_EXCP_WDT] = 0x00000000;
|
2877 |
env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00000000;
|
2878 |
env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00000000;
|
2879 |
env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00000000;
|
2880 |
env->hreset_excp_prefix = 0x00000000UL;
|
2881 |
env->ivor_mask = 0x0000FFE0UL;
|
2882 |
env->ivpr_mask = 0xFFFF0000UL;
|
2883 |
/* Hardware reset vector */
|
2884 |
env->hreset_vector = 0xFFFFFFFCUL;
|
2885 |
#endif
|
2886 |
} |
2887 |
|
2888 |
static void init_excp_601 (CPUPPCState *env) |
2889 |
{ |
2890 |
#if !defined(CONFIG_USER_ONLY)
|
2891 |
env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
|
2892 |
env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
|
2893 |
env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
|
2894 |
env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
|
2895 |
env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
|
2896 |
env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
|
2897 |
env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
|
2898 |
env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
|
2899 |
env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
|
2900 |
env->excp_vectors[POWERPC_EXCP_IO] = 0x00000A00;
|
2901 |
env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
|
2902 |
env->excp_vectors[POWERPC_EXCP_RUNM] = 0x00002000;
|
2903 |
env->hreset_excp_prefix = 0xFFF00000UL;
|
2904 |
/* Hardware reset vector */
|
2905 |
env->hreset_vector = 0x00000100UL;
|
2906 |
#endif
|
2907 |
} |
2908 |
|
2909 |
static void init_excp_602 (CPUPPCState *env) |
2910 |
{ |
2911 |
#if !defined(CONFIG_USER_ONLY)
|
2912 |
/* XXX: exception prefix has a special behavior on 602 */
|
2913 |
env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
|
2914 |
env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
|
2915 |
env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
|
2916 |
env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
|
2917 |
env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
|
2918 |
env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
|
2919 |
env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
|
2920 |
env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
|
2921 |
env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
|
2922 |
env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
|
2923 |
env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
|
2924 |
env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
|
2925 |
env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
|
2926 |
env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
|
2927 |
env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
|
2928 |
env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
|
2929 |
env->excp_vectors[POWERPC_EXCP_WDT] = 0x00001500;
|
2930 |
env->excp_vectors[POWERPC_EXCP_EMUL] = 0x00001600;
|
2931 |
env->hreset_excp_prefix = 0xFFF00000UL;
|
2932 |
/* Hardware reset vector */
|
2933 |
env->hreset_vector = 0xFFFFFFFCUL;
|
2934 |
#endif
|
2935 |
} |
2936 |
|
2937 |
static void init_excp_603 (CPUPPCState *env) |
2938 |
{ |
2939 |
#if !defined(CONFIG_USER_ONLY)
|
2940 |
env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
|
2941 |
env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
|
2942 |
env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
|
2943 |
env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
|
2944 |
env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
|
2945 |
env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
|
2946 |
env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
|
2947 |
env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
|
2948 |
env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
|
2949 |
env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
|
2950 |
env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
|
2951 |
env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
|
2952 |
env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
|
2953 |
env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
|
2954 |
env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
|
2955 |
env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
|
2956 |
env->hreset_excp_prefix = 0x00000000UL;
|
2957 |
/* Hardware reset vector */
|
2958 |
env->hreset_vector = 0xFFFFFFFCUL;
|
2959 |
#endif
|
2960 |
} |
2961 |
|
2962 |
static void init_excp_604 (CPUPPCState *env) |
2963 |
{ |
2964 |
#if !defined(CONFIG_USER_ONLY)
|
2965 |
env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
|
2966 |
env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
|
2967 |
env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
|
2968 |
env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
|
2969 |
env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
|
2970 |
env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
|
2971 |
env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
|
2972 |
env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
|
2973 |
env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
|
2974 |
env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
|
2975 |
env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
|
2976 |
env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
|
2977 |
env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
|
2978 |
env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
|
2979 |
env->hreset_excp_prefix = 0xFFF00000UL;
|
2980 |
/* Hardware reset vector */
|
2981 |
env->hreset_vector = 0x00000100UL;
|
2982 |
#endif
|
2983 |
} |
2984 |
|
2985 |
#if defined(TARGET_PPC64)
|
2986 |
static void init_excp_620 (CPUPPCState *env) |
2987 |
{ |
2988 |
#if !defined(CONFIG_USER_ONLY)
|
2989 |
env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
|
2990 |
env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
|
2991 |
env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
|
2992 |
env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
|
2993 |
env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
|
2994 |
env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
|
2995 |
env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
|
2996 |
env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
|
2997 |
env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
|
2998 |
env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
|
2999 |
env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
|
3000 |
env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
|
3001 |
env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
|
3002 |
env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
|
3003 |
env->hreset_excp_prefix = 0xFFF00000UL;
|
3004 |
/* Hardware reset vector */
|
3005 |
env->hreset_vector = 0x0000000000000100ULL;
|
3006 |
#endif
|
3007 |
} |
3008 |
#endif /* defined(TARGET_PPC64) */ |
3009 |
|
3010 |
static void init_excp_7x0 (CPUPPCState *env) |
3011 |
{ |
3012 |
#if !defined(CONFIG_USER_ONLY)
|
3013 |
env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
|
3014 |
env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
|
3015 |
env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
|
3016 |
env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
|
3017 |
env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
|
3018 |
env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
|
3019 |
env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
|
3020 |
env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
|
3021 |
env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
|
3022 |
env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
|
3023 |
env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
|
3024 |
env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
|
3025 |
env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
|
3026 |
env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
|
3027 |
env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
|
3028 |
env->hreset_excp_prefix = 0x00000000UL;
|
3029 |
/* Hardware reset vector */
|
3030 |
env->hreset_vector = 0xFFFFFFFCUL;
|
3031 |
#endif
|
3032 |
} |
3033 |
|
3034 |
static void init_excp_750cl (CPUPPCState *env) |
3035 |
{ |
3036 |
#if !defined(CONFIG_USER_ONLY)
|
3037 |
env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
|
3038 |
env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
|
3039 |
env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
|
3040 |
env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
|
3041 |
env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
|
3042 |
env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
|
3043 |
env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
|
3044 |
env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
|
3045 |
env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
|
3046 |
env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
|
3047 |
env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
|
3048 |
env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
|
3049 |
env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
|
3050 |
env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
|
3051 |
env->hreset_excp_prefix = 0x00000000UL;
|
3052 |
/* Hardware reset vector */
|
3053 |
env->hreset_vector = 0xFFFFFFFCUL;
|
3054 |
#endif
|
3055 |
} |
3056 |
|
3057 |
static void init_excp_750cx (CPUPPCState *env) |
3058 |
{ |
3059 |
#if !defined(CONFIG_USER_ONLY)
|
3060 |
env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
|
3061 |
env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
|
3062 |
env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
|
3063 |
env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
|
3064 |
env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
|
3065 |
env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
|
3066 |
env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
|
3067 |
env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
|
3068 |
env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
|
3069 |
env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
|
3070 |
env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
|
3071 |
env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
|
3072 |
env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
|
3073 |
env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
|
3074 |
env->hreset_excp_prefix = 0x00000000UL;
|
3075 |
/* Hardware reset vector */
|
3076 |
env->hreset_vector = 0xFFFFFFFCUL;
|
3077 |
#endif
|
3078 |
} |
3079 |
|
3080 |
/* XXX: Check if this is correct */
|
3081 |
static void init_excp_7x5 (CPUPPCState *env) |
3082 |
{ |
3083 |
#if !defined(CONFIG_USER_ONLY)
|
3084 |
env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
|
3085 |
env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
|
3086 |
env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
|
3087 |
env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
|
3088 |
env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
|
3089 |
env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
|
3090 |
env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
|
3091 |
env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
|
3092 |
env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
|
3093 |
env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
|
3094 |
env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
|
3095 |
env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
|
3096 |
env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
|
3097 |
env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
|
3098 |
env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
|
3099 |
env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
|
3100 |
env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
|
3101 |
env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
|
3102 |
env->hreset_excp_prefix = 0x00000000UL;
|
3103 |
/* Hardware reset vector */
|
3104 |
env->hreset_vector = 0xFFFFFFFCUL;
|
3105 |
#endif
|
3106 |
} |
3107 |
|
3108 |
static void init_excp_7400 (CPUPPCState *env) |
3109 |
{ |
3110 |
#if !defined(CONFIG_USER_ONLY)
|
3111 |
env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
|
3112 |
env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
|
3113 |
env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
|
3114 |
env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
|
3115 |
env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
|
3116 |
env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
|
3117 |
env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
|
3118 |
env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
|
3119 |
env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
|
3120 |
env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
|
3121 |
env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
|
3122 |
env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
|
3123 |
env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20;
|
3124 |
env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
|
3125 |
env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
|
3126 |
env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001600;
|
3127 |
env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
|
3128 |
env->hreset_excp_prefix = 0x00000000UL;
|
3129 |
/* Hardware reset vector */
|
3130 |
env->hreset_vector = 0xFFFFFFFCUL;
|
3131 |
#endif
|
3132 |
} |
3133 |
|
3134 |
static void init_excp_7450 (CPUPPCState *env) |
3135 |
{ |
3136 |
#if !defined(CONFIG_USER_ONLY)
|
3137 |
env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
|
3138 |
env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
|
3139 |
env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
|
3140 |
env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
|
3141 |
env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
|
3142 |
env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
|
3143 |
env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
|
3144 |
env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
|
3145 |
env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
|
3146 |
env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
|
3147 |
env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
|
3148 |
env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
|
3149 |
env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20;
|
3150 |
env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
|
3151 |
env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
|
3152 |
env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
|
3153 |
env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
|
3154 |
env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
|
3155 |
env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001600;
|
3156 |
env->hreset_excp_prefix = 0x00000000UL;
|
3157 |
/* Hardware reset vector */
|
3158 |
env->hreset_vector = 0xFFFFFFFCUL;
|
3159 |
#endif
|
3160 |
} |
3161 |
|
3162 |
#if defined (TARGET_PPC64)
|
3163 |
static void init_excp_970 (CPUPPCState *env) |
3164 |
{ |
3165 |
#if !defined(CONFIG_USER_ONLY)
|
3166 |
env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
|
3167 |
env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
|
3168 |
env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
|
3169 |
env->excp_vectors[POWERPC_EXCP_DSEG] = 0x00000380;
|
3170 |
env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
|
3171 |
env->excp_vectors[POWERPC_EXCP_ISEG] = 0x00000480;
|
3172 |
env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
|
3173 |
env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
|
3174 |
env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
|
3175 |
env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
|
3176 |
env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
|
3177 |
env->excp_vectors[POWERPC_EXCP_HDECR] = 0x00000980;
|
3178 |
env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
|
3179 |
env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
|
3180 |
env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
|
3181 |
env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20;
|
3182 |
env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
|
3183 |
env->excp_vectors[POWERPC_EXCP_MAINT] = 0x00001600;
|
3184 |
env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001700;
|
3185 |
env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001800;
|
3186 |
env->hreset_excp_prefix = 0x00000000FFF00000ULL;
|
3187 |
/* Hardware reset vector */
|
3188 |
env->hreset_vector = 0x0000000000000100ULL;
|
3189 |
#endif
|
3190 |
} |
3191 |
|
3192 |
static void init_excp_POWER7 (CPUPPCState *env) |
3193 |
{ |
3194 |
#if !defined(CONFIG_USER_ONLY)
|
3195 |
env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
|
3196 |
env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
|
3197 |
env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
|
3198 |
env->excp_vectors[POWERPC_EXCP_DSEG] = 0x00000380;
|
3199 |
env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
|
3200 |
env->excp_vectors[POWERPC_EXCP_ISEG] = 0x00000480;
|
3201 |
env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
|
3202 |
env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
|
3203 |
env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
|
3204 |
env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
|
3205 |
env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
|
3206 |
env->excp_vectors[POWERPC_EXCP_HDECR] = 0x00000980;
|
3207 |
env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
|
3208 |
env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
|
3209 |
env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
|
3210 |
env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20;
|
3211 |
env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
|
3212 |
env->excp_vectors[POWERPC_EXCP_MAINT] = 0x00001600;
|
3213 |
env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001700;
|
3214 |
env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001800;
|
3215 |
env->hreset_excp_prefix = 0;
|
3216 |
/* Hardware reset vector */
|
3217 |
env->hreset_vector = 0x0000000000000100ULL;
|
3218 |
#endif
|
3219 |
} |
3220 |
#endif
|
3221 |
|
3222 |
/*****************************************************************************/
|
3223 |
/* Power management enable checks */
|
3224 |
static int check_pow_none (CPUPPCState *env) |
3225 |
{ |
3226 |
return 0; |
3227 |
} |
3228 |
|
3229 |
static int check_pow_nocheck (CPUPPCState *env) |
3230 |
{ |
3231 |
return 1; |
3232 |
} |
3233 |
|
3234 |
static int check_pow_hid0 (CPUPPCState *env) |
3235 |
{ |
3236 |
if (env->spr[SPR_HID0] & 0x00E00000) |
3237 |
return 1; |
3238 |
|
3239 |
return 0; |
3240 |
} |
3241 |
|
3242 |
static int check_pow_hid0_74xx (CPUPPCState *env) |
3243 |
{ |
3244 |
if (env->spr[SPR_HID0] & 0x00600000) |
3245 |
return 1; |
3246 |
|
3247 |
return 0; |
3248 |
} |
3249 |
|
3250 |
/*****************************************************************************/
|
3251 |
/* PowerPC implementations definitions */
|
3252 |
|
3253 |
/* PowerPC 401 */
|
3254 |
#define POWERPC_INSNS_401 (PPC_INSNS_BASE | PPC_STRING | \
|
3255 |
PPC_WRTEE | PPC_DCR | \ |
3256 |
PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT | \ |
3257 |
PPC_CACHE_DCBZ | \ |
3258 |
PPC_MEM_SYNC | PPC_MEM_EIEIO | \ |
3259 |
PPC_4xx_COMMON | PPC_40x_EXCP) |
3260 |
#define POWERPC_INSNS2_401 (PPC_NONE)
|
3261 |
#define POWERPC_MSRM_401 (0x00000000000FD201ULL) |
3262 |
#define POWERPC_MMU_401 (POWERPC_MMU_REAL)
|
3263 |
#define POWERPC_EXCP_401 (POWERPC_EXCP_40x)
|
3264 |
#define POWERPC_INPUT_401 (PPC_FLAGS_INPUT_401)
|
3265 |
#define POWERPC_BFDM_401 (bfd_mach_ppc_403)
|
3266 |
#define POWERPC_FLAG_401 (POWERPC_FLAG_CE | POWERPC_FLAG_DE | \
|
3267 |
POWERPC_FLAG_BUS_CLK) |
3268 |
#define check_pow_401 check_pow_nocheck
|
3269 |
|
3270 |
static void init_proc_401 (CPUPPCState *env) |
3271 |
{ |
3272 |
gen_spr_40x(env); |
3273 |
gen_spr_401_403(env); |
3274 |
gen_spr_401(env); |
3275 |
init_excp_4xx_real(env); |
3276 |
env->dcache_line_size = 32;
|
3277 |
env->icache_line_size = 32;
|
3278 |
/* Allocate hardware IRQ controller */
|
3279 |
ppc40x_irq_init(env); |
3280 |
|
3281 |
SET_FIT_PERIOD(12, 16, 20, 24); |
3282 |
SET_WDT_PERIOD(16, 20, 24, 28); |
3283 |
} |
3284 |
|
3285 |
/* PowerPC 401x2 */
|
3286 |
#define POWERPC_INSNS_401x2 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
|
3287 |
PPC_DCR | PPC_WRTEE | \ |
3288 |
PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT | \ |
3289 |
PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \ |
3290 |
PPC_MEM_SYNC | PPC_MEM_EIEIO | \ |
3291 |
PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \ |
3292 |
PPC_4xx_COMMON | PPC_40x_EXCP) |
3293 |
#define POWERPC_INSNS2_401x2 (PPC_NONE)
|
3294 |
#define POWERPC_MSRM_401x2 (0x00000000001FD231ULL) |
3295 |
#define POWERPC_MMU_401x2 (POWERPC_MMU_SOFT_4xx_Z)
|
3296 |
#define POWERPC_EXCP_401x2 (POWERPC_EXCP_40x)
|
3297 |
#define POWERPC_INPUT_401x2 (PPC_FLAGS_INPUT_401)
|
3298 |
#define POWERPC_BFDM_401x2 (bfd_mach_ppc_403)
|
3299 |
#define POWERPC_FLAG_401x2 (POWERPC_FLAG_CE | POWERPC_FLAG_DE | \
|
3300 |
POWERPC_FLAG_BUS_CLK) |
3301 |
#define check_pow_401x2 check_pow_nocheck
|
3302 |
|
3303 |
static void init_proc_401x2 (CPUPPCState *env) |
3304 |
{ |
3305 |
gen_spr_40x(env); |
3306 |
gen_spr_401_403(env); |
3307 |
gen_spr_401x2(env); |
3308 |
gen_spr_compress(env); |
3309 |
/* Memory management */
|
3310 |
#if !defined(CONFIG_USER_ONLY)
|
3311 |
env->nb_tlb = 64;
|
3312 |
env->nb_ways = 1;
|
3313 |
env->id_tlbs = 0;
|
3314 |
env->tlb_type = TLB_EMB; |
3315 |
#endif
|
3316 |
init_excp_4xx_softmmu(env); |
3317 |
env->dcache_line_size = 32;
|
3318 |
env->icache_line_size = 32;
|
3319 |
/* Allocate hardware IRQ controller */
|
3320 |
ppc40x_irq_init(env); |
3321 |
|
3322 |
SET_FIT_PERIOD(12, 16, 20, 24); |
3323 |
SET_WDT_PERIOD(16, 20, 24, 28); |
3324 |
} |
3325 |
|
3326 |
/* PowerPC 401x3 */
|
3327 |
#define POWERPC_INSNS_401x3 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
|
3328 |
PPC_DCR | PPC_WRTEE | \ |
3329 |
PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT | \ |
3330 |
PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \ |
3331 |
PPC_MEM_SYNC | PPC_MEM_EIEIO | \ |
3332 |
PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \ |
3333 |
PPC_4xx_COMMON | PPC_40x_EXCP) |
3334 |
#define POWERPC_INSNS2_401x3 (PPC_NONE)
|
3335 |
#define POWERPC_MSRM_401x3 (0x00000000001FD631ULL) |
3336 |
#define POWERPC_MMU_401x3 (POWERPC_MMU_SOFT_4xx_Z)
|
3337 |
#define POWERPC_EXCP_401x3 (POWERPC_EXCP_40x)
|
3338 |
#define POWERPC_INPUT_401x3 (PPC_FLAGS_INPUT_401)
|
3339 |
#define POWERPC_BFDM_401x3 (bfd_mach_ppc_403)
|
3340 |
#define POWERPC_FLAG_401x3 (POWERPC_FLAG_CE | POWERPC_FLAG_DE | \
|
3341 |
POWERPC_FLAG_BUS_CLK) |
3342 |
#define check_pow_401x3 check_pow_nocheck
|
3343 |
|
3344 |
__attribute__ (( unused )) |
3345 |
static void init_proc_401x3 (CPUPPCState *env) |
3346 |
{ |
3347 |
gen_spr_40x(env); |
3348 |
gen_spr_401_403(env); |
3349 |
gen_spr_401(env); |
3350 |
gen_spr_401x2(env); |
3351 |
gen_spr_compress(env); |
3352 |
init_excp_4xx_softmmu(env); |
3353 |
env->dcache_line_size = 32;
|
3354 |
env->icache_line_size = 32;
|
3355 |
/* Allocate hardware IRQ controller */
|
3356 |
ppc40x_irq_init(env); |
3357 |
|
3358 |
SET_FIT_PERIOD(12, 16, 20, 24); |
3359 |
SET_WDT_PERIOD(16, 20, 24, 28); |
3360 |
} |
3361 |
|
3362 |
/* IOP480 */
|
3363 |
#define POWERPC_INSNS_IOP480 (PPC_INSNS_BASE | PPC_STRING | \
|
3364 |
PPC_DCR | PPC_WRTEE | \ |
3365 |
PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT | \ |
3366 |
PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \ |
3367 |
PPC_MEM_SYNC | PPC_MEM_EIEIO | \ |
3368 |
PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \ |
3369 |
PPC_4xx_COMMON | PPC_40x_EXCP) |
3370 |
#define POWERPC_INSNS2_IOP480 (PPC_NONE)
|
3371 |
#define POWERPC_MSRM_IOP480 (0x00000000001FD231ULL) |
3372 |
#define POWERPC_MMU_IOP480 (POWERPC_MMU_SOFT_4xx_Z)
|
3373 |
#define POWERPC_EXCP_IOP480 (POWERPC_EXCP_40x)
|
3374 |
#define POWERPC_INPUT_IOP480 (PPC_FLAGS_INPUT_401)
|
3375 |
#define POWERPC_BFDM_IOP480 (bfd_mach_ppc_403)
|
3376 |
#define POWERPC_FLAG_IOP480 (POWERPC_FLAG_CE | POWERPC_FLAG_DE | \
|
3377 |
POWERPC_FLAG_BUS_CLK) |
3378 |
#define check_pow_IOP480 check_pow_nocheck
|
3379 |
|
3380 |
static void init_proc_IOP480 (CPUPPCState *env) |
3381 |
{ |
3382 |
gen_spr_40x(env); |
3383 |
gen_spr_401_403(env); |
3384 |
gen_spr_401x2(env); |
3385 |
gen_spr_compress(env); |
3386 |
/* Memory management */
|
3387 |
#if !defined(CONFIG_USER_ONLY)
|
3388 |
env->nb_tlb = 64;
|
3389 |
env->nb_ways = 1;
|
3390 |
env->id_tlbs = 0;
|
3391 |
env->tlb_type = TLB_EMB; |
3392 |
#endif
|
3393 |
init_excp_4xx_softmmu(env); |
3394 |
env->dcache_line_size = 32;
|
3395 |
env->icache_line_size = 32;
|
3396 |
/* Allocate hardware IRQ controller */
|
3397 |
ppc40x_irq_init(env); |
3398 |
|
3399 |
SET_FIT_PERIOD(8, 12, 16, 20); |
3400 |
SET_WDT_PERIOD(16, 20, 24, 28); |
3401 |
} |
3402 |
|
3403 |
/* PowerPC 403 */
|
3404 |
#define POWERPC_INSNS_403 (PPC_INSNS_BASE | PPC_STRING | \
|
3405 |
PPC_DCR | PPC_WRTEE | \ |
3406 |
PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT | \ |
3407 |
PPC_CACHE_DCBZ | \ |
3408 |
PPC_MEM_SYNC | PPC_MEM_EIEIO | \ |
3409 |
PPC_4xx_COMMON | PPC_40x_EXCP) |
3410 |
#define POWERPC_INSNS2_403 (PPC_NONE)
|
3411 |
#define POWERPC_MSRM_403 (0x000000000007D00DULL) |
3412 |
#define POWERPC_MMU_403 (POWERPC_MMU_REAL)
|
3413 |
#define POWERPC_EXCP_403 (POWERPC_EXCP_40x)
|
3414 |
#define POWERPC_INPUT_403 (PPC_FLAGS_INPUT_401)
|
3415 |
#define POWERPC_BFDM_403 (bfd_mach_ppc_403)
|
3416 |
#define POWERPC_FLAG_403 (POWERPC_FLAG_CE | POWERPC_FLAG_PX | \
|
3417 |
POWERPC_FLAG_BUS_CLK) |
3418 |
#define check_pow_403 check_pow_nocheck
|
3419 |
|
3420 |
static void init_proc_403 (CPUPPCState *env) |
3421 |
{ |
3422 |
gen_spr_40x(env); |
3423 |
gen_spr_401_403(env); |
3424 |
gen_spr_403(env); |
3425 |
gen_spr_403_real(env); |
3426 |
init_excp_4xx_real(env); |
3427 |
env->dcache_line_size = 32;
|
3428 |
env->icache_line_size = 32;
|
3429 |
/* Allocate hardware IRQ controller */
|
3430 |
ppc40x_irq_init(env); |
3431 |
|
3432 |
SET_FIT_PERIOD(8, 12, 16, 20); |
3433 |
SET_WDT_PERIOD(16, 20, 24, 28); |
3434 |
} |
3435 |
|
3436 |
/* PowerPC 403 GCX */
|
3437 |
#define POWERPC_INSNS_403GCX (PPC_INSNS_BASE | PPC_STRING | \
|
3438 |
PPC_DCR | PPC_WRTEE | \ |
3439 |
PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT | \ |
3440 |
PPC_CACHE_DCBZ | \ |
3441 |
PPC_MEM_SYNC | PPC_MEM_EIEIO | \ |
3442 |
PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \ |
3443 |
PPC_4xx_COMMON | PPC_40x_EXCP) |
3444 |
#define POWERPC_INSNS2_403GCX (PPC_NONE)
|
3445 |
#define POWERPC_MSRM_403GCX (0x000000000007D00DULL) |
3446 |
#define POWERPC_MMU_403GCX (POWERPC_MMU_SOFT_4xx_Z)
|
3447 |
#define POWERPC_EXCP_403GCX (POWERPC_EXCP_40x)
|
3448 |
#define POWERPC_INPUT_403GCX (PPC_FLAGS_INPUT_401)
|
3449 |
#define POWERPC_BFDM_403GCX (bfd_mach_ppc_403)
|
3450 |
#define POWERPC_FLAG_403GCX (POWERPC_FLAG_CE | POWERPC_FLAG_PX | \
|
3451 |
POWERPC_FLAG_BUS_CLK) |
3452 |
#define check_pow_403GCX check_pow_nocheck
|
3453 |
|
3454 |
static void init_proc_403GCX (CPUPPCState *env) |
3455 |
{ |
3456 |
gen_spr_40x(env); |
3457 |
gen_spr_401_403(env); |
3458 |
gen_spr_403(env); |
3459 |
gen_spr_403_real(env); |
3460 |
gen_spr_403_mmu(env); |
3461 |
/* Bus access control */
|
3462 |
/* not emulated, as QEMU never does speculative access */
|
3463 |
spr_register(env, SPR_40x_SGR, "SGR",
|
3464 |
SPR_NOACCESS, SPR_NOACCESS, |
3465 |
&spr_read_generic, &spr_write_generic, |
3466 |
0xFFFFFFFF);
|
3467 |
/* not emulated, as QEMU do not emulate caches */
|
3468 |
spr_register(env, SPR_40x_DCWR, "DCWR",
|
3469 |
SPR_NOACCESS, SPR_NOACCESS, |
3470 |
&spr_read_generic, &spr_write_generic, |
3471 |
0x00000000);
|
3472 |
/* Memory management */
|
3473 |
#if !defined(CONFIG_USER_ONLY)
|
3474 |
env->nb_tlb = 64;
|
3475 |
env->nb_ways = 1;
|
3476 |
env->id_tlbs = 0;
|
3477 |
env->tlb_type = TLB_EMB; |
3478 |
#endif
|
3479 |
init_excp_4xx_softmmu(env); |
3480 |
env->dcache_line_size = 32;
|
3481 |
env->icache_line_size = 32;
|
3482 |
/* Allocate hardware IRQ controller */
|
3483 |
ppc40x_irq_init(env); |
3484 |
|
3485 |
SET_FIT_PERIOD(8, 12, 16, 20); |
3486 |
SET_WDT_PERIOD(16, 20, 24, 28); |
3487 |
} |
3488 |
|
3489 |
/* PowerPC 405 */
|
3490 |
#define POWERPC_INSNS_405 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
|
3491 |
PPC_DCR | PPC_WRTEE | \ |
3492 |
PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT | \ |
3493 |
PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \ |
3494 |
PPC_MEM_SYNC | PPC_MEM_EIEIO | \ |
3495 |
PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \ |
3496 |
PPC_4xx_COMMON | PPC_405_MAC | PPC_40x_EXCP) |
3497 |
#define POWERPC_INSNS2_405 (PPC_NONE)
|
3498 |
#define POWERPC_MSRM_405 (0x000000000006E630ULL) |
3499 |
#define POWERPC_MMU_405 (POWERPC_MMU_SOFT_4xx)
|
3500 |
#define POWERPC_EXCP_405 (POWERPC_EXCP_40x)
|
3501 |
#define POWERPC_INPUT_405 (PPC_FLAGS_INPUT_405)
|
3502 |
#define POWERPC_BFDM_405 (bfd_mach_ppc_403)
|
3503 |
#define POWERPC_FLAG_405 (POWERPC_FLAG_CE | POWERPC_FLAG_DWE | \
|
3504 |
POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK) |
3505 |
#define check_pow_405 check_pow_nocheck
|
3506 |
|
3507 |
static void init_proc_405 (CPUPPCState *env) |
3508 |
{ |
3509 |
/* Time base */
|
3510 |
gen_tbl(env); |
3511 |
gen_spr_40x(env); |
3512 |
gen_spr_405(env); |
3513 |
/* Bus access control */
|
3514 |
/* not emulated, as QEMU never does speculative access */
|
3515 |
spr_register(env, SPR_40x_SGR, "SGR",
|
3516 |
SPR_NOACCESS, SPR_NOACCESS, |
3517 |
&spr_read_generic, &spr_write_generic, |
3518 |
0xFFFFFFFF);
|
3519 |
/* not emulated, as QEMU do not emulate caches */
|
3520 |
spr_register(env, SPR_40x_DCWR, "DCWR",
|
3521 |
SPR_NOACCESS, SPR_NOACCESS, |
3522 |
&spr_read_generic, &spr_write_generic, |
3523 |
0x00000000);
|
3524 |
/* Memory management */
|
3525 |
#if !defined(CONFIG_USER_ONLY)
|
3526 |
env->nb_tlb = 64;
|
3527 |
env->nb_ways = 1;
|
3528 |
env->id_tlbs = 0;
|
3529 |
env->tlb_type = TLB_EMB; |
3530 |
#endif
|
3531 |
init_excp_4xx_softmmu(env); |
3532 |
env->dcache_line_size = 32;
|
3533 |
env->icache_line_size = 32;
|
3534 |
/* Allocate hardware IRQ controller */
|
3535 |
ppc40x_irq_init(env); |
3536 |
|
3537 |
SET_FIT_PERIOD(8, 12, 16, 20); |
3538 |
SET_WDT_PERIOD(16, 20, 24, 28); |
3539 |
} |
3540 |
|
3541 |
/* PowerPC 440 EP */
|
3542 |
#define POWERPC_INSNS_440EP (PPC_INSNS_BASE | PPC_STRING | \
|
3543 |
PPC_FLOAT | PPC_FLOAT_FRES | PPC_FLOAT_FSEL | \ |
3544 |
PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \ |
3545 |
PPC_FLOAT_STFIWX | \ |
3546 |
PPC_DCR | PPC_WRTEE | PPC_RFMCI | \ |
3547 |
PPC_CACHE | PPC_CACHE_ICBI | \ |
3548 |
PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \ |
3549 |
PPC_MEM_TLBSYNC | PPC_MFTB | \ |
3550 |
PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | \ |
3551 |
PPC_440_SPEC) |
3552 |
#define POWERPC_INSNS2_440EP (PPC_NONE)
|
3553 |
#define POWERPC_MSRM_440EP (0x000000000006FF30ULL) |
3554 |
#define POWERPC_MMU_440EP (POWERPC_MMU_BOOKE)
|
3555 |
#define POWERPC_EXCP_440EP (POWERPC_EXCP_BOOKE)
|
3556 |
#define POWERPC_INPUT_440EP (PPC_FLAGS_INPUT_BookE)
|
3557 |
#define POWERPC_BFDM_440EP (bfd_mach_ppc_403)
|
3558 |
#define POWERPC_FLAG_440EP (POWERPC_FLAG_CE | POWERPC_FLAG_DWE | \
|
3559 |
POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK) |
3560 |
#define check_pow_440EP check_pow_nocheck
|
3561 |
|
3562 |
static void init_proc_440EP (CPUPPCState *env) |
3563 |
{ |
3564 |
/* Time base */
|
3565 |
gen_tbl(env); |
3566 |
gen_spr_BookE(env, 0x000000000000FFFFULL);
|
3567 |
gen_spr_440(env); |
3568 |
gen_spr_usprgh(env); |
3569 |
/* Processor identification */
|
3570 |
spr_register(env, SPR_BOOKE_PIR, "PIR",
|
3571 |
SPR_NOACCESS, SPR_NOACCESS, |
3572 |
&spr_read_generic, &spr_write_pir, |
3573 |
0x00000000);
|
3574 |
/* XXX : not implemented */
|
3575 |
spr_register(env, SPR_BOOKE_IAC3, "IAC3",
|
3576 |
SPR_NOACCESS, SPR_NOACCESS, |
3577 |
&spr_read_generic, &spr_write_generic, |
3578 |
0x00000000);
|
3579 |
/* XXX : not implemented */
|
3580 |
spr_register(env, SPR_BOOKE_IAC4, "IAC4",
|
3581 |
SPR_NOACCESS, SPR_NOACCESS, |
3582 |
&spr_read_generic, &spr_write_generic, |
3583 |
0x00000000);
|
3584 |
/* XXX : not implemented */
|
3585 |
spr_register(env, SPR_BOOKE_DVC1, "DVC1",
|
3586 |
SPR_NOACCESS, SPR_NOACCESS, |
3587 |
&spr_read_generic, &spr_write_generic, |
3588 |
0x00000000);
|
3589 |
/* XXX : not implemented */
|
3590 |
spr_register(env, SPR_BOOKE_DVC2, "DVC2",
|
3591 |
SPR_NOACCESS, SPR_NOACCESS, |
3592 |
&spr_read_generic, &spr_write_generic, |
3593 |
0x00000000);
|
3594 |
/* XXX : not implemented */
|
3595 |
spr_register(env, SPR_BOOKE_MCSR, "MCSR",
|
3596 |
SPR_NOACCESS, SPR_NOACCESS, |
3597 |
&spr_read_generic, &spr_write_generic, |
3598 |
0x00000000);
|
3599 |
spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
|
3600 |
SPR_NOACCESS, SPR_NOACCESS, |
3601 |
&spr_read_generic, &spr_write_generic, |
3602 |
0x00000000);
|
3603 |
spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
|
3604 |
SPR_NOACCESS, SPR_NOACCESS, |
3605 |
&spr_read_generic, &spr_write_generic, |
3606 |
0x00000000);
|
3607 |
/* XXX : not implemented */
|
3608 |
spr_register(env, SPR_440_CCR1, "CCR1",
|
3609 |
SPR_NOACCESS, SPR_NOACCESS, |
3610 |
&spr_read_generic, &spr_write_generic, |
3611 |
0x00000000);
|
3612 |
/* Memory management */
|
3613 |
#if !defined(CONFIG_USER_ONLY)
|
3614 |
env->nb_tlb = 64;
|
3615 |
env->nb_ways = 1;
|
3616 |
env->id_tlbs = 0;
|
3617 |
env->tlb_type = TLB_EMB; |
3618 |
#endif
|
3619 |
init_excp_BookE(env); |
3620 |
env->dcache_line_size = 32;
|
3621 |
env->icache_line_size = 32;
|
3622 |
ppc40x_irq_init(env); |
3623 |
|
3624 |
SET_FIT_PERIOD(12, 16, 20, 24); |
3625 |
SET_WDT_PERIOD(20, 24, 28, 32); |
3626 |
} |
3627 |
|
3628 |
/* PowerPC 440 GP */
|
3629 |
#define POWERPC_INSNS_440GP (PPC_INSNS_BASE | PPC_STRING | \
|
3630 |
PPC_DCR | PPC_DCRX | PPC_WRTEE | PPC_MFAPIDI | \ |
3631 |
PPC_CACHE | PPC_CACHE_ICBI | \ |
3632 |
PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \ |
3633 |
PPC_MEM_TLBSYNC | PPC_TLBIVA | PPC_MFTB | \ |
3634 |
PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | \ |
3635 |
PPC_440_SPEC) |
3636 |
#define POWERPC_INSNS2_440GP (PPC_NONE)
|
3637 |
#define POWERPC_MSRM_440GP (0x000000000006FF30ULL) |
3638 |
#define POWERPC_MMU_440GP (POWERPC_MMU_BOOKE)
|
3639 |
#define POWERPC_EXCP_440GP (POWERPC_EXCP_BOOKE)
|
3640 |
#define POWERPC_INPUT_440GP (PPC_FLAGS_INPUT_BookE)
|
3641 |
#define POWERPC_BFDM_440GP (bfd_mach_ppc_403)
|
3642 |
#define POWERPC_FLAG_440GP (POWERPC_FLAG_CE | POWERPC_FLAG_DWE | \
|
3643 |
POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK) |
3644 |
#define check_pow_440GP check_pow_nocheck
|
3645 |
|
3646 |
__attribute__ (( unused )) |
3647 |
static void init_proc_440GP (CPUPPCState *env) |
3648 |
{ |
3649 |
/* Time base */
|
3650 |
gen_tbl(env); |
3651 |
gen_spr_BookE(env, 0x000000000000FFFFULL);
|
3652 |
gen_spr_440(env); |
3653 |
gen_spr_usprgh(env); |
3654 |
/* Processor identification */
|
3655 |
spr_register(env, SPR_BOOKE_PIR, "PIR",
|
3656 |
SPR_NOACCESS, SPR_NOACCESS, |
3657 |
&spr_read_generic, &spr_write_pir, |
3658 |
0x00000000);
|
3659 |
/* XXX : not implemented */
|
3660 |
spr_register(env, SPR_BOOKE_IAC3, "IAC3",
|
3661 |
SPR_NOACCESS, SPR_NOACCESS, |
3662 |
&spr_read_generic, &spr_write_generic, |
3663 |
0x00000000);
|
3664 |
/* XXX : not implemented */
|
3665 |
spr_register(env, SPR_BOOKE_IAC4, "IAC4",
|
3666 |
SPR_NOACCESS, SPR_NOACCESS, |
3667 |
&spr_read_generic, &spr_write_generic, |
3668 |
0x00000000);
|
3669 |
/* XXX : not implemented */
|
3670 |
spr_register(env, SPR_BOOKE_DVC1, "DVC1",
|
3671 |
SPR_NOACCESS, SPR_NOACCESS, |
3672 |
&spr_read_generic, &spr_write_generic, |
3673 |
0x00000000);
|
3674 |
/* XXX : not implemented */
|
3675 |
spr_register(env, SPR_BOOKE_DVC2, "DVC2",
|
3676 |
SPR_NOACCESS, SPR_NOACCESS, |
3677 |
&spr_read_generic, &spr_write_generic, |
3678 |
0x00000000);
|
3679 |
/* Memory management */
|
3680 |
#if !defined(CONFIG_USER_ONLY)
|
3681 |
env->nb_tlb = 64;
|
3682 |
env->nb_ways = 1;
|
3683 |
env->id_tlbs = 0;
|
3684 |
env->tlb_type = TLB_EMB; |
3685 |
#endif
|
3686 |
init_excp_BookE(env); |
3687 |
env->dcache_line_size = 32;
|
3688 |
env->icache_line_size = 32;
|
3689 |
/* XXX: TODO: allocate internal IRQ controller */
|
3690 |
|
3691 |
SET_FIT_PERIOD(12, 16, 20, 24); |
3692 |
SET_WDT_PERIOD(20, 24, 28, 32); |
3693 |
} |
3694 |
|
3695 |
/* PowerPC 440x4 */
|
3696 |
#define POWERPC_INSNS_440x4 (PPC_INSNS_BASE | PPC_STRING | \
|
3697 |
PPC_DCR | PPC_WRTEE | \ |
3698 |
PPC_CACHE | PPC_CACHE_ICBI | \ |
3699 |
PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \ |
3700 |
PPC_MEM_TLBSYNC | PPC_MFTB | \ |
3701 |
PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | \ |
3702 |
PPC_440_SPEC) |
3703 |
#define POWERPC_INSNS2_440x4 (PPC_NONE)
|
3704 |
#define POWERPC_MSRM_440x4 (0x000000000006FF30ULL) |
3705 |
#define POWERPC_MMU_440x4 (POWERPC_MMU_BOOKE)
|
3706 |
#define POWERPC_EXCP_440x4 (POWERPC_EXCP_BOOKE)
|
3707 |
#define POWERPC_INPUT_440x4 (PPC_FLAGS_INPUT_BookE)
|
3708 |
#define POWERPC_BFDM_440x4 (bfd_mach_ppc_403)
|
3709 |
#define POWERPC_FLAG_440x4 (POWERPC_FLAG_CE | POWERPC_FLAG_DWE | \
|
3710 |
POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK) |
3711 |
#define check_pow_440x4 check_pow_nocheck
|
3712 |
|
3713 |
__attribute__ (( unused )) |
3714 |
static void init_proc_440x4 (CPUPPCState *env) |
3715 |
{ |
3716 |
/* Time base */
|
3717 |
gen_tbl(env); |
3718 |
gen_spr_BookE(env, 0x000000000000FFFFULL);
|
3719 |
gen_spr_440(env); |
3720 |
gen_spr_usprgh(env); |
3721 |
/* Processor identification */
|
3722 |
spr_register(env, SPR_BOOKE_PIR, "PIR",
|
3723 |
SPR_NOACCESS, SPR_NOACCESS, |
3724 |
&spr_read_generic, &spr_write_pir, |
3725 |
0x00000000);
|
3726 |
/* XXX : not implemented */
|
3727 |
spr_register(env, SPR_BOOKE_IAC3, "IAC3",
|
3728 |
SPR_NOACCESS, SPR_NOACCESS, |
3729 |
&spr_read_generic, &spr_write_generic, |
3730 |
0x00000000);
|
3731 |
/* XXX : not implemented */
|
3732 |
spr_register(env, SPR_BOOKE_IAC4, "IAC4",
|
3733 |
SPR_NOACCESS, SPR_NOACCESS, |
3734 |
&spr_read_generic, &spr_write_generic, |
3735 |
0x00000000);
|
3736 |
/* XXX : not implemented */
|
3737 |
spr_register(env, SPR_BOOKE_DVC1, "DVC1",
|
3738 |
SPR_NOACCESS, SPR_NOACCESS, |
3739 |
&spr_read_generic, &spr_write_generic, |
3740 |
0x00000000);
|
3741 |
/* XXX : not implemented */
|
3742 |
spr_register(env, SPR_BOOKE_DVC2, "DVC2",
|
3743 |
SPR_NOACCESS, SPR_NOACCESS, |
3744 |
&spr_read_generic, &spr_write_generic, |
3745 |
0x00000000);
|
3746 |
/* Memory management */
|
3747 |
#if !defined(CONFIG_USER_ONLY)
|
3748 |
env->nb_tlb = 64;
|
3749 |
env->nb_ways = 1;
|
3750 |
env->id_tlbs = 0;
|
3751 |
env->tlb_type = TLB_EMB; |
3752 |
#endif
|
3753 |
init_excp_BookE(env); |
3754 |
env->dcache_line_size = 32;
|
3755 |
env->icache_line_size = 32;
|
3756 |
/* XXX: TODO: allocate internal IRQ controller */
|
3757 |
|
3758 |
SET_FIT_PERIOD(12, 16, 20, 24); |
3759 |
SET_WDT_PERIOD(20, 24, 28, 32); |
3760 |
} |
3761 |
|
3762 |
/* PowerPC 440x5 */
|
3763 |
#define POWERPC_INSNS_440x5 (PPC_INSNS_BASE | PPC_STRING | \
|
3764 |
PPC_DCR | PPC_WRTEE | PPC_RFMCI | \ |
3765 |
PPC_CACHE | PPC_CACHE_ICBI | \ |
3766 |
PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \ |
3767 |
PPC_MEM_TLBSYNC | PPC_MFTB | \ |
3768 |
PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | \ |
3769 |
PPC_440_SPEC) |
3770 |
#define POWERPC_INSNS2_440x5 (PPC_NONE)
|
3771 |
#define POWERPC_MSRM_440x5 (0x000000000006FF30ULL) |
3772 |
#define POWERPC_MMU_440x5 (POWERPC_MMU_BOOKE)
|
3773 |
#define POWERPC_EXCP_440x5 (POWERPC_EXCP_BOOKE)
|
3774 |
#define POWERPC_INPUT_440x5 (PPC_FLAGS_INPUT_BookE)
|
3775 |
#define POWERPC_BFDM_440x5 (bfd_mach_ppc_403)
|
3776 |
#define POWERPC_FLAG_440x5 (POWERPC_FLAG_CE | POWERPC_FLAG_DWE | \
|
3777 |
POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK) |
3778 |
#define check_pow_440x5 check_pow_nocheck
|
3779 |
|
3780 |
static void init_proc_440x5 (CPUPPCState *env) |
3781 |
{ |
3782 |
/* Time base */
|
3783 |
gen_tbl(env); |
3784 |
gen_spr_BookE(env, 0x000000000000FFFFULL);
|
3785 |
gen_spr_440(env); |
3786 |
gen_spr_usprgh(env); |
3787 |
/* Processor identification */
|
3788 |
spr_register(env, SPR_BOOKE_PIR, "PIR",
|
3789 |
SPR_NOACCESS, SPR_NOACCESS, |
3790 |
&spr_read_generic, &spr_write_pir, |
3791 |
0x00000000);
|
3792 |
/* XXX : not implemented */
|
3793 |
spr_register(env, SPR_BOOKE_IAC3, "IAC3",
|
3794 |
SPR_NOACCESS, SPR_NOACCESS, |
3795 |
&spr_read_generic, &spr_write_generic, |
3796 |
0x00000000);
|
3797 |
/* XXX : not implemented */
|
3798 |
spr_register(env, SPR_BOOKE_IAC4, "IAC4",
|
3799 |
SPR_NOACCESS, SPR_NOACCESS, |
3800 |
&spr_read_generic, &spr_write_generic, |
3801 |
0x00000000);
|
3802 |
/* XXX : not implemented */
|
3803 |
spr_register(env, SPR_BOOKE_DVC1, "DVC1",
|
3804 |
SPR_NOACCESS, SPR_NOACCESS, |
3805 |
&spr_read_generic, &spr_write_generic, |
3806 |
0x00000000);
|
3807 |
/* XXX : not implemented */
|
3808 |
spr_register(env, SPR_BOOKE_DVC2, "DVC2",
|
3809 |
SPR_NOACCESS, SPR_NOACCESS, |
3810 |
&spr_read_generic, &spr_write_generic, |
3811 |
0x00000000);
|
3812 |
/* XXX : not implemented */
|
3813 |
spr_register(env, SPR_BOOKE_MCSR, "MCSR",
|
3814 |
SPR_NOACCESS, SPR_NOACCESS, |
3815 |
&spr_read_generic, &spr_write_generic, |
3816 |
0x00000000);
|
3817 |
spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
|
3818 |
SPR_NOACCESS, SPR_NOACCESS, |
3819 |
&spr_read_generic, &spr_write_generic, |
3820 |
0x00000000);
|
3821 |
spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
|
3822 |
SPR_NOACCESS, SPR_NOACCESS, |
3823 |
&spr_read_generic, &spr_write_generic, |
3824 |
0x00000000);
|
3825 |
/* XXX : not implemented */
|
3826 |
spr_register(env, SPR_440_CCR1, "CCR1",
|
3827 |
SPR_NOACCESS, SPR_NOACCESS, |
3828 |
&spr_read_generic, &spr_write_generic, |
3829 |
0x00000000);
|
3830 |
/* Memory management */
|
3831 |
#if !defined(CONFIG_USER_ONLY)
|
3832 |
env->nb_tlb = 64;
|
3833 |
env->nb_ways = 1;
|
3834 |
env->id_tlbs = 0;
|
3835 |
env->tlb_type = TLB_EMB; |
3836 |
#endif
|
3837 |
init_excp_BookE(env); |
3838 |
env->dcache_line_size = 32;
|
3839 |
env->icache_line_size = 32;
|
3840 |
ppc40x_irq_init(env); |
3841 |
|
3842 |
SET_FIT_PERIOD(12, 16, 20, 24); |
3843 |
SET_WDT_PERIOD(20, 24, 28, 32); |
3844 |
} |
3845 |
|
3846 |
/* PowerPC 460 (guessed) */
|
3847 |
#define POWERPC_INSNS_460 (PPC_INSNS_BASE | PPC_STRING | \
|
3848 |
PPC_DCR | PPC_DCRX | PPC_DCRUX | \ |
3849 |
PPC_WRTEE | PPC_MFAPIDI | PPC_MFTB | \ |
3850 |
PPC_CACHE | PPC_CACHE_ICBI | \ |
3851 |
PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \ |
3852 |
PPC_MEM_TLBSYNC | PPC_TLBIVA | \ |
3853 |
PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | \ |
3854 |
PPC_440_SPEC) |
3855 |
#define POWERPC_INSNS2_460 (PPC_NONE)
|
3856 |
#define POWERPC_MSRM_460 (0x000000000006FF30ULL) |
3857 |
#define POWERPC_MMU_460 (POWERPC_MMU_BOOKE)
|
3858 |
#define POWERPC_EXCP_460 (POWERPC_EXCP_BOOKE)
|
3859 |
#define POWERPC_INPUT_460 (PPC_FLAGS_INPUT_BookE)
|
3860 |
#define POWERPC_BFDM_460 (bfd_mach_ppc_403)
|
3861 |
#define POWERPC_FLAG_460 (POWERPC_FLAG_CE | POWERPC_FLAG_DWE | \
|
3862 |
POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK) |
3863 |
#define check_pow_460 check_pow_nocheck
|
3864 |
|
3865 |
__attribute__ (( unused )) |
3866 |
static void init_proc_460 (CPUPPCState *env) |
3867 |
{ |
3868 |
/* Time base */
|
3869 |
gen_tbl(env); |
3870 |
gen_spr_BookE(env, 0x000000000000FFFFULL);
|
3871 |
gen_spr_440(env); |
3872 |
gen_spr_usprgh(env); |
3873 |
/* Processor identification */
|
3874 |
spr_register(env, SPR_BOOKE_PIR, "PIR",
|
3875 |
SPR_NOACCESS, SPR_NOACCESS, |
3876 |
&spr_read_generic, &spr_write_pir, |
3877 |
0x00000000);
|
3878 |
/* XXX : not implemented */
|
3879 |
spr_register(env, SPR_BOOKE_IAC3, "IAC3",
|
3880 |
SPR_NOACCESS, SPR_NOACCESS, |
3881 |
&spr_read_generic, &spr_write_generic, |
3882 |
0x00000000);
|
3883 |
/* XXX : not implemented */
|
3884 |
spr_register(env, SPR_BOOKE_IAC4, "IAC4",
|
3885 |
SPR_NOACCESS, SPR_NOACCESS, |
3886 |
&spr_read_generic, &spr_write_generic, |
3887 |
0x00000000);
|
3888 |
/* XXX : not implemented */
|
3889 |
spr_register(env, SPR_BOOKE_DVC1, "DVC1",
|
3890 |
SPR_NOACCESS, SPR_NOACCESS, |
3891 |
&spr_read_generic, &spr_write_generic, |
3892 |
0x00000000);
|
3893 |
/* XXX : not implemented */
|
3894 |
spr_register(env, SPR_BOOKE_DVC2, "DVC2",
|
3895 |
SPR_NOACCESS, SPR_NOACCESS, |
3896 |
&spr_read_generic, &spr_write_generic, |
3897 |
0x00000000);
|
3898 |
/* XXX : not implemented */
|
3899 |
spr_register(env, SPR_BOOKE_MCSR, "MCSR",
|
3900 |
SPR_NOACCESS, SPR_NOACCESS, |
3901 |
&spr_read_generic, &spr_write_generic, |
3902 |
0x00000000);
|
3903 |
spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
|
3904 |
SPR_NOACCESS, SPR_NOACCESS, |
3905 |
&spr_read_generic, &spr_write_generic, |
3906 |
0x00000000);
|
3907 |
spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
|
3908 |
SPR_NOACCESS, SPR_NOACCESS, |
3909 |
&spr_read_generic, &spr_write_generic, |
3910 |
0x00000000);
|
3911 |
/* XXX : not implemented */
|
3912 |
spr_register(env, SPR_440_CCR1, "CCR1",
|
3913 |
SPR_NOACCESS, SPR_NOACCESS, |
3914 |
&spr_read_generic, &spr_write_generic, |
3915 |
0x00000000);
|
3916 |
/* XXX : not implemented */
|
3917 |
spr_register(env, SPR_DCRIPR, "SPR_DCRIPR",
|
3918 |
&spr_read_generic, &spr_write_generic, |
3919 |
&spr_read_generic, &spr_write_generic, |
3920 |
0x00000000);
|
3921 |
/* Memory management */
|
3922 |
#if !defined(CONFIG_USER_ONLY)
|
3923 |
env->nb_tlb = 64;
|
3924 |
env->nb_ways = 1;
|
3925 |
env->id_tlbs = 0;
|
3926 |
env->tlb_type = TLB_EMB; |
3927 |
#endif
|
3928 |
init_excp_BookE(env); |
3929 |
env->dcache_line_size = 32;
|
3930 |
env->icache_line_size = 32;
|
3931 |
/* XXX: TODO: allocate internal IRQ controller */
|
3932 |
|
3933 |
SET_FIT_PERIOD(12, 16, 20, 24); |
3934 |
SET_WDT_PERIOD(20, 24, 28, 32); |
3935 |
} |
3936 |
|
3937 |
/* PowerPC 460F (guessed) */
|
3938 |
#define POWERPC_INSNS_460F (PPC_INSNS_BASE | PPC_STRING | \
|
3939 |
PPC_FLOAT | PPC_FLOAT_FRES | PPC_FLOAT_FSEL | \ |
3940 |
PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \ |
3941 |
PPC_FLOAT_STFIWX | PPC_MFTB | \ |
3942 |
PPC_DCR | PPC_DCRX | PPC_DCRUX | \ |
3943 |
PPC_WRTEE | PPC_MFAPIDI | \ |
3944 |
PPC_CACHE | PPC_CACHE_ICBI | \ |
3945 |
PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \ |
3946 |
PPC_MEM_TLBSYNC | PPC_TLBIVA | \ |
3947 |
PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | \ |
3948 |
PPC_440_SPEC) |
3949 |
#define POWERPC_INSNS2_460F (PPC_NONE)
|
3950 |
#define POWERPC_MSRM_460 (0x000000000006FF30ULL) |
3951 |
#define POWERPC_MMU_460F (POWERPC_MMU_BOOKE)
|
3952 |
#define POWERPC_EXCP_460F (POWERPC_EXCP_BOOKE)
|
3953 |
#define POWERPC_INPUT_460F (PPC_FLAGS_INPUT_BookE)
|
3954 |
#define POWERPC_BFDM_460F (bfd_mach_ppc_403)
|
3955 |
#define POWERPC_FLAG_460F (POWERPC_FLAG_CE | POWERPC_FLAG_DWE | \
|
3956 |
POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK) |
3957 |
#define check_pow_460F check_pow_nocheck
|
3958 |
|
3959 |
__attribute__ (( unused )) |
3960 |
static void init_proc_460F (CPUPPCState *env) |
3961 |
{ |
3962 |
/* Time base */
|
3963 |
gen_tbl(env); |
3964 |
gen_spr_BookE(env, 0x000000000000FFFFULL);
|
3965 |
gen_spr_440(env); |
3966 |
gen_spr_usprgh(env); |
3967 |
/* Processor identification */
|
3968 |
spr_register(env, SPR_BOOKE_PIR, "PIR",
|
3969 |
SPR_NOACCESS, SPR_NOACCESS, |
3970 |
&spr_read_generic, &spr_write_pir, |
3971 |
0x00000000);
|
3972 |
/* XXX : not implemented */
|
3973 |
spr_register(env, SPR_BOOKE_IAC3, "IAC3",
|
3974 |
SPR_NOACCESS, SPR_NOACCESS, |
3975 |
&spr_read_generic, &spr_write_generic, |
3976 |
0x00000000);
|
3977 |
/* XXX : not implemented */
|
3978 |
spr_register(env, SPR_BOOKE_IAC4, "IAC4",
|
3979 |
SPR_NOACCESS, SPR_NOACCESS, |
3980 |
&spr_read_generic, &spr_write_generic, |
3981 |
0x00000000);
|
3982 |
/* XXX : not implemented */
|
3983 |
spr_register(env, SPR_BOOKE_DVC1, "DVC1",
|
3984 |
SPR_NOACCESS, SPR_NOACCESS, |
3985 |
&spr_read_generic, &spr_write_generic, |
3986 |
0x00000000);
|
3987 |
/* XXX : not implemented */
|
3988 |
spr_register(env, SPR_BOOKE_DVC2, "DVC2",
|
3989 |
SPR_NOACCESS, SPR_NOACCESS, |
3990 |
&spr_read_generic, &spr_write_generic, |
3991 |
0x00000000);
|
3992 |
/* XXX : not implemented */
|
3993 |
spr_register(env, SPR_BOOKE_MCSR, "MCSR",
|
3994 |
SPR_NOACCESS, SPR_NOACCESS, |
3995 |
&spr_read_generic, &spr_write_generic, |
3996 |
0x00000000);
|
3997 |
spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
|
3998 |
SPR_NOACCESS, SPR_NOACCESS, |
3999 |
&spr_read_generic, &spr_write_generic, |
4000 |
0x00000000);
|
4001 |
spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
|
4002 |
SPR_NOACCESS, SPR_NOACCESS, |
4003 |
&spr_read_generic, &spr_write_generic, |
4004 |
0x00000000);
|
4005 |
/* XXX : not implemented */
|
4006 |
spr_register(env, SPR_440_CCR1, "CCR1",
|
4007 |
SPR_NOACCESS, SPR_NOACCESS, |
4008 |
&spr_read_generic, &spr_write_generic, |
4009 |
0x00000000);
|
4010 |
/* XXX : not implemented */
|
4011 |
spr_register(env, SPR_DCRIPR, "SPR_DCRIPR",
|
4012 |
&spr_read_generic, &spr_write_generic, |
4013 |
&spr_read_generic, &spr_write_generic, |
4014 |
0x00000000);
|
4015 |
/* Memory management */
|
4016 |
#if !defined(CONFIG_USER_ONLY)
|
4017 |
env->nb_tlb = 64;
|
4018 |
env->nb_ways = 1;
|
4019 |
env->id_tlbs = 0;
|
4020 |
env->tlb_type = TLB_EMB; |
4021 |
#endif
|
4022 |
init_excp_BookE(env); |
4023 |
env->dcache_line_size = 32;
|
4024 |
env->icache_line_size = 32;
|
4025 |
/* XXX: TODO: allocate internal IRQ controller */
|
4026 |
|
4027 |
SET_FIT_PERIOD(12, 16, 20, 24); |
4028 |
SET_WDT_PERIOD(20, 24, 28, 32); |
4029 |
} |
4030 |
|
4031 |
/* Freescale 5xx cores (aka RCPU) */
|
4032 |
#define POWERPC_INSNS_MPC5xx (PPC_INSNS_BASE | PPC_STRING | \
|
4033 |
PPC_MEM_EIEIO | PPC_MEM_SYNC | \ |
4034 |
PPC_CACHE_ICBI | PPC_FLOAT | PPC_FLOAT_STFIWX | \ |
4035 |
PPC_MFTB) |
4036 |
#define POWERPC_INSNS2_MPC5xx (PPC_NONE)
|
4037 |
#define POWERPC_MSRM_MPC5xx (0x000000000001FF43ULL) |
4038 |
#define POWERPC_MMU_MPC5xx (POWERPC_MMU_REAL)
|
4039 |
#define POWERPC_EXCP_MPC5xx (POWERPC_EXCP_603)
|
4040 |
#define POWERPC_INPUT_MPC5xx (PPC_FLAGS_INPUT_RCPU)
|
4041 |
#define POWERPC_BFDM_MPC5xx (bfd_mach_ppc_505)
|
4042 |
#define POWERPC_FLAG_MPC5xx (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
|
4043 |
POWERPC_FLAG_BUS_CLK) |
4044 |
#define check_pow_MPC5xx check_pow_none
|
4045 |
|
4046 |
__attribute__ (( unused )) |
4047 |
static void init_proc_MPC5xx (CPUPPCState *env) |
4048 |
{ |
4049 |
/* Time base */
|
4050 |
gen_tbl(env); |
4051 |
gen_spr_5xx_8xx(env); |
4052 |
gen_spr_5xx(env); |
4053 |
init_excp_MPC5xx(env); |
4054 |
env->dcache_line_size = 32;
|
4055 |
env->icache_line_size = 32;
|
4056 |
/* XXX: TODO: allocate internal IRQ controller */
|
4057 |
} |
4058 |
|
4059 |
/* Freescale 8xx cores (aka PowerQUICC) */
|
4060 |
#define POWERPC_INSNS_MPC8xx (PPC_INSNS_BASE | PPC_STRING | \
|
4061 |
PPC_MEM_EIEIO | PPC_MEM_SYNC | \ |
4062 |
PPC_CACHE_ICBI | PPC_MFTB) |
4063 |
#define POWERPC_INSNS2_MPC8xx (PPC_NONE)
|
4064 |
#define POWERPC_MSRM_MPC8xx (0x000000000001F673ULL) |
4065 |
#define POWERPC_MMU_MPC8xx (POWERPC_MMU_MPC8xx)
|
4066 |
#define POWERPC_EXCP_MPC8xx (POWERPC_EXCP_603)
|
4067 |
#define POWERPC_INPUT_MPC8xx (PPC_FLAGS_INPUT_RCPU)
|
4068 |
#define POWERPC_BFDM_MPC8xx (bfd_mach_ppc_860)
|
4069 |
#define POWERPC_FLAG_MPC8xx (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
|
4070 |
POWERPC_FLAG_BUS_CLK) |
4071 |
#define check_pow_MPC8xx check_pow_none
|
4072 |
|
4073 |
__attribute__ (( unused )) |
4074 |
static void init_proc_MPC8xx (CPUPPCState *env) |
4075 |
{ |
4076 |
/* Time base */
|
4077 |
gen_tbl(env); |
4078 |
gen_spr_5xx_8xx(env); |
4079 |
gen_spr_8xx(env); |
4080 |
init_excp_MPC8xx(env); |
4081 |
env->dcache_line_size = 32;
|
4082 |
env->icache_line_size = 32;
|
4083 |
/* XXX: TODO: allocate internal IRQ controller */
|
4084 |
} |
4085 |
|
4086 |
/* Freescale 82xx cores (aka PowerQUICC-II) */
|
4087 |
/* PowerPC G2 */
|
4088 |
#define POWERPC_INSNS_G2 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
|
4089 |
PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \ |
4090 |
PPC_FLOAT_STFIWX | \ |
4091 |
PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \ |
4092 |
PPC_MEM_SYNC | PPC_MEM_EIEIO | \ |
4093 |
PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | \ |
4094 |
PPC_SEGMENT | PPC_EXTERN) |
4095 |
#define POWERPC_INSNS2_G2 (PPC_NONE)
|
4096 |
#define POWERPC_MSRM_G2 (0x000000000006FFF2ULL) |
4097 |
#define POWERPC_MMU_G2 (POWERPC_MMU_SOFT_6xx)
|
4098 |
//#define POWERPC_EXCP_G2 (POWERPC_EXCP_G2)
|
4099 |
#define POWERPC_INPUT_G2 (PPC_FLAGS_INPUT_6xx)
|
4100 |
#define POWERPC_BFDM_G2 (bfd_mach_ppc_ec603e)
|
4101 |
#define POWERPC_FLAG_G2 (POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | \
|
4102 |
POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK) |
4103 |
#define check_pow_G2 check_pow_hid0
|
4104 |
|
4105 |
static void init_proc_G2 (CPUPPCState *env) |
4106 |
{ |
4107 |
gen_spr_ne_601(env); |
4108 |
gen_spr_G2_755(env); |
4109 |
gen_spr_G2(env); |
4110 |
/* Time base */
|
4111 |
gen_tbl(env); |
4112 |
/* External access control */
|
4113 |
/* XXX : not implemented */
|
4114 |
spr_register(env, SPR_EAR, "EAR",
|
4115 |
SPR_NOACCESS, SPR_NOACCESS, |
4116 |
&spr_read_generic, &spr_write_generic, |
4117 |
0x00000000);
|
4118 |
/* Hardware implementation register */
|
4119 |
/* XXX : not implemented */
|
4120 |
spr_register(env, SPR_HID0, "HID0",
|
4121 |
SPR_NOACCESS, SPR_NOACCESS, |
4122 |
&spr_read_generic, &spr_write_generic, |
4123 |
0x00000000);
|
4124 |
/* XXX : not implemented */
|
4125 |
spr_register(env, SPR_HID1, "HID1",
|
4126 |
SPR_NOACCESS, SPR_NOACCESS, |
4127 |
&spr_read_generic, &spr_write_generic, |
4128 |
0x00000000);
|
4129 |
/* XXX : not implemented */
|
4130 |
spr_register(env, SPR_HID2, "HID2",
|
4131 |
SPR_NOACCESS, SPR_NOACCESS, |
4132 |
&spr_read_generic, &spr_write_generic, |
4133 |
0x00000000);
|
4134 |
/* Memory management */
|
4135 |
gen_low_BATs(env); |
4136 |
gen_high_BATs(env); |
4137 |
gen_6xx_7xx_soft_tlb(env, 64, 2); |
4138 |
init_excp_G2(env); |
4139 |
env->dcache_line_size = 32;
|
4140 |
env->icache_line_size = 32;
|
4141 |
/* Allocate hardware IRQ controller */
|
4142 |
ppc6xx_irq_init(env); |
4143 |
} |
4144 |
|
4145 |
/* PowerPC G2LE */
|
4146 |
#define POWERPC_INSNS_G2LE (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
|
4147 |
PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \ |
4148 |
PPC_FLOAT_STFIWX | \ |
4149 |
PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \ |
4150 |
PPC_MEM_SYNC | PPC_MEM_EIEIO | \ |
4151 |
PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | \ |
4152 |
PPC_SEGMENT | PPC_EXTERN) |
4153 |
#define POWERPC_INSNS2_G2LE (PPC_NONE)
|
4154 |
#define POWERPC_MSRM_G2LE (0x000000000007FFF3ULL) |
4155 |
#define POWERPC_MMU_G2LE (POWERPC_MMU_SOFT_6xx)
|
4156 |
#define POWERPC_EXCP_G2LE (POWERPC_EXCP_G2)
|
4157 |
#define POWERPC_INPUT_G2LE (PPC_FLAGS_INPUT_6xx)
|
4158 |
#define POWERPC_BFDM_G2LE (bfd_mach_ppc_ec603e)
|
4159 |
#define POWERPC_FLAG_G2LE (POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | \
|
4160 |
POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK) |
4161 |
#define check_pow_G2LE check_pow_hid0
|
4162 |
|
4163 |
static void init_proc_G2LE (CPUPPCState *env) |
4164 |
{ |
4165 |
gen_spr_ne_601(env); |
4166 |
gen_spr_G2_755(env); |
4167 |
gen_spr_G2(env); |
4168 |
/* Time base */
|
4169 |
gen_tbl(env); |
4170 |
/* External access control */
|
4171 |
/* XXX : not implemented */
|
4172 |
spr_register(env, SPR_EAR, "EAR",
|
4173 |
SPR_NOACCESS, SPR_NOACCESS, |
4174 |
&spr_read_generic, &spr_write_generic, |
4175 |
0x00000000);
|
4176 |
/* Hardware implementation register */
|
4177 |
/* XXX : not implemented */
|
4178 |
spr_register(env, SPR_HID0, "HID0",
|
4179 |
SPR_NOACCESS, SPR_NOACCESS, |
4180 |
&spr_read_generic, &spr_write_generic, |
4181 |
0x00000000);
|
4182 |
/* XXX : not implemented */
|
4183 |
spr_register(env, SPR_HID1, "HID1",
|
4184 |
SPR_NOACCESS, SPR_NOACCESS, |
4185 |
&spr_read_generic, &spr_write_generic, |
4186 |
0x00000000);
|
4187 |
/* XXX : not implemented */
|
4188 |
spr_register(env, SPR_HID2, "HID2",
|
4189 |
SPR_NOACCESS, SPR_NOACCESS, |
4190 |
&spr_read_generic, &spr_write_generic, |
4191 |
0x00000000);
|
4192 |
/* Memory management */
|
4193 |
gen_low_BATs(env); |
4194 |
gen_high_BATs(env); |
4195 |
gen_6xx_7xx_soft_tlb(env, 64, 2); |
4196 |
init_excp_G2(env); |
4197 |
env->dcache_line_size = 32;
|
4198 |
env->icache_line_size = 32;
|
4199 |
/* Allocate hardware IRQ controller */
|
4200 |
ppc6xx_irq_init(env); |
4201 |
} |
4202 |
|
4203 |
/* e200 core */
|
4204 |
/* XXX: unimplemented instructions:
|
4205 |
* dcblc
|
4206 |
* dcbtlst
|
4207 |
* dcbtstls
|
4208 |
* icblc
|
4209 |
* icbtls
|
4210 |
* tlbivax
|
4211 |
* all SPE multiply-accumulate instructions
|
4212 |
*/
|
4213 |
#define POWERPC_INSNS_e200 (PPC_INSNS_BASE | PPC_ISEL | \
|
4214 |
PPC_SPE | PPC_SPE_SINGLE | \ |
4215 |
PPC_WRTEE | PPC_RFDI | \ |
4216 |
PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | \ |
4217 |
PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \ |
4218 |
PPC_MEM_TLBSYNC | PPC_TLBIVAX | \ |
4219 |
PPC_BOOKE) |
4220 |
#define POWERPC_INSNS2_e200 (PPC_NONE)
|
4221 |
#define POWERPC_MSRM_e200 (0x000000000606FF30ULL) |
4222 |
#define POWERPC_MMU_e200 (POWERPC_MMU_BOOKE206)
|
4223 |
#define POWERPC_EXCP_e200 (POWERPC_EXCP_BOOKE)
|
4224 |
#define POWERPC_INPUT_e200 (PPC_FLAGS_INPUT_BookE)
|
4225 |
#define POWERPC_BFDM_e200 (bfd_mach_ppc_860)
|
4226 |
#define POWERPC_FLAG_e200 (POWERPC_FLAG_SPE | POWERPC_FLAG_CE | \
|
4227 |
POWERPC_FLAG_UBLE | POWERPC_FLAG_DE | \ |
4228 |
POWERPC_FLAG_BUS_CLK) |
4229 |
#define check_pow_e200 check_pow_hid0
|
4230 |
|
4231 |
__attribute__ (( unused )) |
4232 |
static void init_proc_e200 (CPUPPCState *env) |
4233 |
{ |
4234 |
/* Time base */
|
4235 |
gen_tbl(env); |
4236 |
gen_spr_BookE(env, 0x000000070000FFFFULL);
|
4237 |
/* XXX : not implemented */
|
4238 |
spr_register(env, SPR_BOOKE_SPEFSCR, "SPEFSCR",
|
4239 |
&spr_read_spefscr, &spr_write_spefscr, |
4240 |
&spr_read_spefscr, &spr_write_spefscr, |
4241 |
0x00000000);
|
4242 |
/* Memory management */
|
4243 |
gen_spr_BookE206(env, 0x0000005D, NULL); |
4244 |
/* XXX : not implemented */
|
4245 |
spr_register(env, SPR_HID0, "HID0",
|
4246 |
SPR_NOACCESS, SPR_NOACCESS, |
4247 |
&spr_read_generic, &spr_write_generic, |
4248 |
0x00000000);
|
4249 |
/* XXX : not implemented */
|
4250 |
spr_register(env, SPR_HID1, "HID1",
|
4251 |
SPR_NOACCESS, SPR_NOACCESS, |
4252 |
&spr_read_generic, &spr_write_generic, |
4253 |
0x00000000);
|
4254 |
/* XXX : not implemented */
|
4255 |
spr_register(env, SPR_Exxx_ALTCTXCR, "ALTCTXCR",
|
4256 |
SPR_NOACCESS, SPR_NOACCESS, |
4257 |
&spr_read_generic, &spr_write_generic, |
4258 |
0x00000000);
|
4259 |
/* XXX : not implemented */
|
4260 |
spr_register(env, SPR_Exxx_BUCSR, "BUCSR",
|
4261 |
SPR_NOACCESS, SPR_NOACCESS, |
4262 |
&spr_read_generic, &spr_write_generic, |
4263 |
0x00000000);
|
4264 |
/* XXX : not implemented */
|
4265 |
spr_register(env, SPR_Exxx_CTXCR, "CTXCR",
|
4266 |
SPR_NOACCESS, SPR_NOACCESS, |
4267 |
&spr_read_generic, &spr_write_generic, |
4268 |
0x00000000);
|
4269 |
/* XXX : not implemented */
|
4270 |
spr_register(env, SPR_Exxx_DBCNT, "DBCNT",
|
4271 |
SPR_NOACCESS, SPR_NOACCESS, |
4272 |
&spr_read_generic, &spr_write_generic, |
4273 |
0x00000000);
|
4274 |
/* XXX : not implemented */
|
4275 |
spr_register(env, SPR_Exxx_DBCR3, "DBCR3",
|
4276 |
SPR_NOACCESS, SPR_NOACCESS, |
4277 |
&spr_read_generic, &spr_write_generic, |
4278 |
0x00000000);
|
4279 |
/* XXX : not implemented */
|
4280 |
spr_register(env, SPR_Exxx_L1CFG0, "L1CFG0",
|
4281 |
SPR_NOACCESS, SPR_NOACCESS, |
4282 |
&spr_read_generic, &spr_write_generic, |
4283 |
0x00000000);
|
4284 |
/* XXX : not implemented */
|
4285 |
spr_register(env, SPR_Exxx_L1CSR0, "L1CSR0",
|
4286 |
SPR_NOACCESS, SPR_NOACCESS, |
4287 |
&spr_read_generic, &spr_write_generic, |
4288 |
0x00000000);
|
4289 |
/* XXX : not implemented */
|
4290 |
spr_register(env, SPR_Exxx_L1FINV0, "L1FINV0",
|
4291 |
SPR_NOACCESS, SPR_NOACCESS, |
4292 |
&spr_read_generic, &spr_write_generic, |
4293 |
0x00000000);
|
4294 |
/* XXX : not implemented */
|
4295 |
spr_register(env, SPR_BOOKE_TLB0CFG, "TLB0CFG",
|
4296 |
SPR_NOACCESS, SPR_NOACCESS, |
4297 |
&spr_read_generic, &spr_write_generic, |
4298 |
0x00000000);
|
4299 |
/* XXX : not implemented */
|
4300 |
spr_register(env, SPR_BOOKE_TLB1CFG, "TLB1CFG",
|
4301 |
SPR_NOACCESS, SPR_NOACCESS, |
4302 |
&spr_read_generic, &spr_write_generic, |
4303 |
0x00000000);
|
4304 |
/* XXX : not implemented */
|
4305 |
spr_register(env, SPR_BOOKE_IAC3, "IAC3",
|
4306 |
SPR_NOACCESS, SPR_NOACCESS, |
4307 |
&spr_read_generic, &spr_write_generic, |
4308 |
0x00000000);
|
4309 |
/* XXX : not implemented */
|
4310 |
spr_register(env, SPR_BOOKE_IAC4, "IAC4",
|
4311 |
SPR_NOACCESS, SPR_NOACCESS, |
4312 |
&spr_read_generic, &spr_write_generic, |
4313 |
0x00000000);
|
4314 |
/* XXX : not implemented */
|
4315 |
spr_register(env, SPR_MMUCSR0, "MMUCSR0",
|
4316 |
SPR_NOACCESS, SPR_NOACCESS, |
4317 |
&spr_read_generic, &spr_write_generic, |
4318 |
0x00000000); /* TOFIX */ |
4319 |
spr_register(env, SPR_BOOKE_DSRR0, "DSRR0",
|
4320 |
SPR_NOACCESS, SPR_NOACCESS, |
4321 |
&spr_read_generic, &spr_write_generic, |
4322 |
0x00000000);
|
4323 |
spr_register(env, SPR_BOOKE_DSRR1, "DSRR1",
|
4324 |
SPR_NOACCESS, SPR_NOACCESS, |
4325 |
&spr_read_generic, &spr_write_generic, |
4326 |
0x00000000);
|
4327 |
#if !defined(CONFIG_USER_ONLY)
|
4328 |
env->nb_tlb = 64;
|
4329 |
env->nb_ways = 1;
|
4330 |
env->id_tlbs = 0;
|
4331 |
env->tlb_type = TLB_EMB; |
4332 |
#endif
|
4333 |
init_excp_e200(env, 0xFFFF0000UL);
|
4334 |
env->dcache_line_size = 32;
|
4335 |
env->icache_line_size = 32;
|
4336 |
/* XXX: TODO: allocate internal IRQ controller */
|
4337 |
} |
4338 |
|
4339 |
/* e300 core */
|
4340 |
#define POWERPC_INSNS_e300 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
|
4341 |
PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \ |
4342 |
PPC_FLOAT_STFIWX | \ |
4343 |
PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \ |
4344 |
PPC_MEM_SYNC | PPC_MEM_EIEIO | \ |
4345 |
PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | \ |
4346 |
PPC_SEGMENT | PPC_EXTERN) |
4347 |
#define POWERPC_INSNS2_e300 (PPC_NONE)
|
4348 |
#define POWERPC_MSRM_e300 (0x000000000007FFF3ULL) |
4349 |
#define POWERPC_MMU_e300 (POWERPC_MMU_SOFT_6xx)
|
4350 |
#define POWERPC_EXCP_e300 (POWERPC_EXCP_603)
|
4351 |
#define POWERPC_INPUT_e300 (PPC_FLAGS_INPUT_6xx)
|
4352 |
#define POWERPC_BFDM_e300 (bfd_mach_ppc_603)
|
4353 |
#define POWERPC_FLAG_e300 (POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | \
|
4354 |
POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK) |
4355 |
#define check_pow_e300 check_pow_hid0
|
4356 |
|
4357 |
__attribute__ (( unused )) |
4358 |
static void init_proc_e300 (CPUPPCState *env) |
4359 |
{ |
4360 |
gen_spr_ne_601(env); |
4361 |
gen_spr_603(env); |
4362 |
/* Time base */
|
4363 |
gen_tbl(env); |
4364 |
/* hardware implementation registers */
|
4365 |
/* XXX : not implemented */
|
4366 |
spr_register(env, SPR_HID0, "HID0",
|
4367 |
SPR_NOACCESS, SPR_NOACCESS, |
4368 |
&spr_read_generic, &spr_write_generic, |
4369 |
0x00000000);
|
4370 |
/* XXX : not implemented */
|
4371 |
spr_register(env, SPR_HID1, "HID1",
|
4372 |
SPR_NOACCESS, SPR_NOACCESS, |
4373 |
&spr_read_generic, &spr_write_generic, |
4374 |
0x00000000);
|
4375 |
/* XXX : not implemented */
|
4376 |
spr_register(env, SPR_HID2, "HID2",
|
4377 |
SPR_NOACCESS, SPR_NOACCESS, |
4378 |
&spr_read_generic, &spr_write_generic, |
4379 |
0x00000000);
|
4380 |
/* Memory management */
|
4381 |
gen_low_BATs(env); |
4382 |
gen_high_BATs(env); |
4383 |
gen_6xx_7xx_soft_tlb(env, 64, 2); |
4384 |
init_excp_603(env); |
4385 |
env->dcache_line_size = 32;
|
4386 |
env->icache_line_size = 32;
|
4387 |
/* Allocate hardware IRQ controller */
|
4388 |
ppc6xx_irq_init(env); |
4389 |
} |
4390 |
|
4391 |
/* e500v1 core */
|
4392 |
#define POWERPC_INSNS_e500v1 (PPC_INSNS_BASE | PPC_ISEL | \
|
4393 |
PPC_SPE | PPC_SPE_SINGLE | \ |
4394 |
PPC_WRTEE | PPC_RFDI | \ |
4395 |
PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | \ |
4396 |
PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \ |
4397 |
PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC) |
4398 |
#define POWERPC_INSNS2_e500v1 (PPC2_BOOKE206)
|
4399 |
#define POWERPC_MSRM_e500v1 (0x000000000606FF30ULL) |
4400 |
#define POWERPC_MMU_e500v1 (POWERPC_MMU_BOOKE206)
|
4401 |
#define POWERPC_EXCP_e500v1 (POWERPC_EXCP_BOOKE)
|
4402 |
#define POWERPC_INPUT_e500v1 (PPC_FLAGS_INPUT_BookE)
|
4403 |
#define POWERPC_BFDM_e500v1 (bfd_mach_ppc_860)
|
4404 |
#define POWERPC_FLAG_e500v1 (POWERPC_FLAG_SPE | POWERPC_FLAG_CE | \
|
4405 |
POWERPC_FLAG_UBLE | POWERPC_FLAG_DE | \ |
4406 |
POWERPC_FLAG_BUS_CLK) |
4407 |
#define check_pow_e500v1 check_pow_hid0
|
4408 |
#define init_proc_e500v1 init_proc_e500v1
|
4409 |
|
4410 |
/* e500v2 core */
|
4411 |
#define POWERPC_INSNS_e500v2 (PPC_INSNS_BASE | PPC_ISEL | \
|
4412 |
PPC_SPE | PPC_SPE_SINGLE | PPC_SPE_DOUBLE | \ |
4413 |
PPC_WRTEE | PPC_RFDI | \ |
4414 |
PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | \ |
4415 |
PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \ |
4416 |
PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC) |
4417 |
#define POWERPC_INSNS2_e500v2 (PPC2_BOOKE206)
|
4418 |
#define POWERPC_MSRM_e500v2 (0x000000000606FF30ULL) |
4419 |
#define POWERPC_MMU_e500v2 (POWERPC_MMU_BOOKE206)
|
4420 |
#define POWERPC_EXCP_e500v2 (POWERPC_EXCP_BOOKE)
|
4421 |
#define POWERPC_INPUT_e500v2 (PPC_FLAGS_INPUT_BookE)
|
4422 |
#define POWERPC_BFDM_e500v2 (bfd_mach_ppc_860)
|
4423 |
#define POWERPC_FLAG_e500v2 (POWERPC_FLAG_SPE | POWERPC_FLAG_CE | \
|
4424 |
POWERPC_FLAG_UBLE | POWERPC_FLAG_DE | \ |
4425 |
POWERPC_FLAG_BUS_CLK) |
4426 |
#define check_pow_e500v2 check_pow_hid0
|
4427 |
#define init_proc_e500v2 init_proc_e500v2
|
4428 |
|
4429 |
/* e500mc core */
|
4430 |
#define POWERPC_INSNS_e500mc (PPC_INSNS_BASE | PPC_ISEL | \
|
4431 |
PPC_WRTEE | PPC_RFDI | PPC_RFMCI | \ |
4432 |
PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | \ |
4433 |
PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \ |
4434 |
PPC_FLOAT | PPC_FLOAT_FRES | \ |
4435 |
PPC_FLOAT_FRSQRTE | PPC_FLOAT_FSEL | \ |
4436 |
PPC_FLOAT_STFIWX | PPC_WAIT | \ |
4437 |
PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC) |
4438 |
#define POWERPC_INSNS2_e500mc (PPC2_BOOKE206 | PPC2_PRCNTL)
|
4439 |
#define POWERPC_MSRM_e500mc (0x000000001402FB36ULL) |
4440 |
#define POWERPC_MMU_e500mc (POWERPC_MMU_BOOKE206)
|
4441 |
#define POWERPC_EXCP_e500mc (POWERPC_EXCP_BOOKE)
|
4442 |
#define POWERPC_INPUT_e500mc (PPC_FLAGS_INPUT_BookE)
|
4443 |
/* Fixme: figure out the correct flag for e500mc */
|
4444 |
#define POWERPC_BFDM_e500mc (bfd_mach_ppc_e500)
|
4445 |
#define POWERPC_FLAG_e500mc (POWERPC_FLAG_CE | POWERPC_FLAG_DE | \
|
4446 |
POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK) |
4447 |
#define check_pow_e500mc check_pow_none
|
4448 |
#define init_proc_e500mc init_proc_e500mc
|
4449 |
|
4450 |
/* e5500 core */
|
4451 |
#define POWERPC_INSNS_e5500 (PPC_INSNS_BASE | PPC_ISEL | \
|
4452 |
PPC_WRTEE | PPC_RFDI | PPC_RFMCI | \ |
4453 |
PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | \ |
4454 |
PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \ |
4455 |
PPC_FLOAT | PPC_FLOAT_FRES | \ |
4456 |
PPC_FLOAT_FRSQRTE | PPC_FLOAT_FSEL | \ |
4457 |
PPC_FLOAT_STFIWX | PPC_WAIT | \ |
4458 |
PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC | \ |
4459 |
PPC_64B | PPC_POPCNTB | PPC_POPCNTWD) |
4460 |
#define POWERPC_INSNS2_e5500 (PPC2_BOOKE206 | PPC2_PRCNTL)
|
4461 |
#define POWERPC_MSRM_e5500 (0x000000009402FB36ULL) |
4462 |
#define POWERPC_MMU_e5500 (POWERPC_MMU_BOOKE206)
|
4463 |
#define POWERPC_EXCP_e5500 (POWERPC_EXCP_BOOKE)
|
4464 |
#define POWERPC_INPUT_e5500 (PPC_FLAGS_INPUT_BookE)
|
4465 |
/* Fixme: figure out the correct flag for e5500 */
|
4466 |
#define POWERPC_BFDM_e5500 (bfd_mach_ppc_e500)
|
4467 |
#define POWERPC_FLAG_e5500 (POWERPC_FLAG_CE | POWERPC_FLAG_DE | \
|
4468 |
POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK) |
4469 |
#define check_pow_e5500 check_pow_none
|
4470 |
#define init_proc_e5500 init_proc_e5500
|
4471 |
|
4472 |
#if !defined(CONFIG_USER_ONLY)
|
4473 |
static void spr_write_mas73(void *opaque, int sprn, int gprn) |
4474 |
{ |
4475 |
TCGv val = tcg_temp_new(); |
4476 |
tcg_gen_ext32u_tl(val, cpu_gpr[gprn]); |
4477 |
gen_store_spr(SPR_BOOKE_MAS3, val); |
4478 |
tcg_gen_shri_tl(val, cpu_gpr[gprn], 32);
|
4479 |
gen_store_spr(SPR_BOOKE_MAS7, val); |
4480 |
tcg_temp_free(val); |
4481 |
} |
4482 |
|
4483 |
static void spr_read_mas73(void *opaque, int gprn, int sprn) |
4484 |
{ |
4485 |
TCGv mas7 = tcg_temp_new(); |
4486 |
TCGv mas3 = tcg_temp_new(); |
4487 |
gen_load_spr(mas7, SPR_BOOKE_MAS7); |
4488 |
tcg_gen_shli_tl(mas7, mas7, 32);
|
4489 |
gen_load_spr(mas3, SPR_BOOKE_MAS3); |
4490 |
tcg_gen_or_tl(cpu_gpr[gprn], mas3, mas7); |
4491 |
tcg_temp_free(mas3); |
4492 |
tcg_temp_free(mas7); |
4493 |
} |
4494 |
|
4495 |
static void spr_load_epr(void *opaque, int gprn, int sprn) |
4496 |
{ |
4497 |
gen_helper_load_epr(cpu_gpr[gprn], cpu_env); |
4498 |
} |
4499 |
|
4500 |
#endif
|
4501 |
|
4502 |
enum fsl_e500_version {
|
4503 |
fsl_e500v1, |
4504 |
fsl_e500v2, |
4505 |
fsl_e500mc, |
4506 |
fsl_e5500, |
4507 |
}; |
4508 |
|
4509 |
static void init_proc_e500 (CPUPPCState *env, int version) |
4510 |
{ |
4511 |
uint32_t tlbncfg[2];
|
4512 |
uint64_t ivor_mask; |
4513 |
uint64_t ivpr_mask = 0xFFFF0000ULL;
|
4514 |
uint32_t l1cfg0 = 0x3800 /* 8 ways */ |
4515 |
| 0x0020; /* 32 kb */ |
4516 |
#if !defined(CONFIG_USER_ONLY)
|
4517 |
int i;
|
4518 |
#endif
|
4519 |
|
4520 |
/* Time base */
|
4521 |
gen_tbl(env); |
4522 |
/*
|
4523 |
* XXX The e500 doesn't implement IVOR7 and IVOR9, but doesn't
|
4524 |
* complain when accessing them.
|
4525 |
* gen_spr_BookE(env, 0x0000000F0000FD7FULL);
|
4526 |
*/
|
4527 |
switch (version) {
|
4528 |
case fsl_e500v1:
|
4529 |
case fsl_e500v2:
|
4530 |
default:
|
4531 |
ivor_mask = 0x0000000F0000FFFFULL;
|
4532 |
break;
|
4533 |
case fsl_e500mc:
|
4534 |
case fsl_e5500:
|
4535 |
ivor_mask = 0x000003FE0000FFFFULL;
|
4536 |
break;
|
4537 |
} |
4538 |
gen_spr_BookE(env, ivor_mask); |
4539 |
/* Processor identification */
|
4540 |
spr_register(env, SPR_BOOKE_PIR, "PIR",
|
4541 |
SPR_NOACCESS, SPR_NOACCESS, |
4542 |
&spr_read_generic, &spr_write_pir, |
4543 |
0x00000000);
|
4544 |
/* XXX : not implemented */
|
4545 |
spr_register(env, SPR_BOOKE_SPEFSCR, "SPEFSCR",
|
4546 |
&spr_read_spefscr, &spr_write_spefscr, |
4547 |
&spr_read_spefscr, &spr_write_spefscr, |
4548 |
0x00000000);
|
4549 |
#if !defined(CONFIG_USER_ONLY)
|
4550 |
/* Memory management */
|
4551 |
env->nb_pids = 3;
|
4552 |
env->nb_ways = 2;
|
4553 |
env->id_tlbs = 0;
|
4554 |
switch (version) {
|
4555 |
case fsl_e500v1:
|
4556 |
tlbncfg[0] = gen_tlbncfg(2, 1, 1, 0, 256); |
4557 |
tlbncfg[1] = gen_tlbncfg(16, 1, 9, TLBnCFG_AVAIL | TLBnCFG_IPROT, 16); |
4558 |
break;
|
4559 |
case fsl_e500v2:
|
4560 |
tlbncfg[0] = gen_tlbncfg(4, 1, 1, 0, 512); |
4561 |
tlbncfg[1] = gen_tlbncfg(16, 1, 12, TLBnCFG_AVAIL | TLBnCFG_IPROT, 16); |
4562 |
break;
|
4563 |
case fsl_e500mc:
|
4564 |
case fsl_e5500:
|
4565 |
tlbncfg[0] = gen_tlbncfg(4, 1, 1, 0, 512); |
4566 |
tlbncfg[1] = gen_tlbncfg(64, 1, 12, TLBnCFG_AVAIL | TLBnCFG_IPROT, 64); |
4567 |
break;
|
4568 |
default:
|
4569 |
cpu_abort(env, "Unknown CPU: " TARGET_FMT_lx "\n", env->spr[SPR_PVR]); |
4570 |
} |
4571 |
#endif
|
4572 |
/* Cache sizes */
|
4573 |
switch (version) {
|
4574 |
case fsl_e500v1:
|
4575 |
case fsl_e500v2:
|
4576 |
env->dcache_line_size = 32;
|
4577 |
env->icache_line_size = 32;
|
4578 |
break;
|
4579 |
case fsl_e500mc:
|
4580 |
case fsl_e5500:
|
4581 |
env->dcache_line_size = 64;
|
4582 |
env->icache_line_size = 64;
|
4583 |
l1cfg0 |= 0x1000000; /* 64 byte cache block size */ |
4584 |
break;
|
4585 |
default:
|
4586 |
cpu_abort(env, "Unknown CPU: " TARGET_FMT_lx "\n", env->spr[SPR_PVR]); |
4587 |
} |
4588 |
gen_spr_BookE206(env, 0x000000DF, tlbncfg);
|
4589 |
/* XXX : not implemented */
|
4590 |
spr_register(env, SPR_HID0, "HID0",
|
4591 |
SPR_NOACCESS, SPR_NOACCESS, |
4592 |
&spr_read_generic, &spr_write_generic, |
4593 |
0x00000000);
|
4594 |
/* XXX : not implemented */
|
4595 |
spr_register(env, SPR_HID1, "HID1",
|
4596 |
SPR_NOACCESS, SPR_NOACCESS, |
4597 |
&spr_read_generic, &spr_write_generic, |
4598 |
0x00000000);
|
4599 |
/* XXX : not implemented */
|
4600 |
spr_register(env, SPR_Exxx_BBEAR, "BBEAR",
|
4601 |
SPR_NOACCESS, SPR_NOACCESS, |
4602 |
&spr_read_generic, &spr_write_generic, |
4603 |
0x00000000);
|
4604 |
/* XXX : not implemented */
|
4605 |
spr_register(env, SPR_Exxx_BBTAR, "BBTAR",
|
4606 |
SPR_NOACCESS, SPR_NOACCESS, |
4607 |
&spr_read_generic, &spr_write_generic, |
4608 |
0x00000000);
|
4609 |
/* XXX : not implemented */
|
4610 |
spr_register(env, SPR_Exxx_MCAR, "MCAR",
|
4611 |
SPR_NOACCESS, SPR_NOACCESS, |
4612 |
&spr_read_generic, &spr_write_generic, |
4613 |
0x00000000);
|
4614 |
/* XXX : not implemented */
|
4615 |
spr_register(env, SPR_BOOKE_MCSR, "MCSR",
|
4616 |
SPR_NOACCESS, SPR_NOACCESS, |
4617 |
&spr_read_generic, &spr_write_generic, |
4618 |
0x00000000);
|
4619 |
/* XXX : not implemented */
|
4620 |
spr_register(env, SPR_Exxx_NPIDR, "NPIDR",
|
4621 |
SPR_NOACCESS, SPR_NOACCESS, |
4622 |
&spr_read_generic, &spr_write_generic, |
4623 |
0x00000000);
|
4624 |
/* XXX : not implemented */
|
4625 |
spr_register(env, SPR_Exxx_BUCSR, "BUCSR",
|
4626 |
SPR_NOACCESS, SPR_NOACCESS, |
4627 |
&spr_read_generic, &spr_write_generic, |
4628 |
0x00000000);
|
4629 |
/* XXX : not implemented */
|
4630 |
spr_register(env, SPR_Exxx_L1CFG0, "L1CFG0",
|
4631 |
SPR_NOACCESS, SPR_NOACCESS, |
4632 |
&spr_read_generic, &spr_write_generic, |
4633 |
l1cfg0); |
4634 |
/* XXX : not implemented */
|
4635 |
spr_register(env, SPR_Exxx_L1CSR0, "L1CSR0",
|
4636 |
SPR_NOACCESS, SPR_NOACCESS, |
4637 |
&spr_read_generic, &spr_write_e500_l1csr0, |
4638 |
0x00000000);
|
4639 |
/* XXX : not implemented */
|
4640 |
spr_register(env, SPR_Exxx_L1CSR1, "L1CSR1",
|
4641 |
SPR_NOACCESS, SPR_NOACCESS, |
4642 |
&spr_read_generic, &spr_write_generic, |
4643 |
0x00000000);
|
4644 |
spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
|
4645 |
SPR_NOACCESS, SPR_NOACCESS, |
4646 |
&spr_read_generic, &spr_write_generic, |
4647 |
0x00000000);
|
4648 |
spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
|
4649 |
SPR_NOACCESS, SPR_NOACCESS, |
4650 |
&spr_read_generic, &spr_write_generic, |
4651 |
0x00000000);
|
4652 |
spr_register(env, SPR_MMUCSR0, "MMUCSR0",
|
4653 |
SPR_NOACCESS, SPR_NOACCESS, |
4654 |
&spr_read_generic, &spr_write_booke206_mmucsr0, |
4655 |
0x00000000);
|
4656 |
spr_register(env, SPR_BOOKE_EPR, "EPR",
|
4657 |
SPR_NOACCESS, SPR_NOACCESS, |
4658 |
&spr_load_epr, SPR_NOACCESS, |
4659 |
0x00000000);
|
4660 |
/* XXX better abstract into Emb.xxx features */
|
4661 |
if (version == fsl_e5500) {
|
4662 |
spr_register(env, SPR_BOOKE_EPCR, "EPCR",
|
4663 |
SPR_NOACCESS, SPR_NOACCESS, |
4664 |
&spr_read_generic, &spr_write_generic, |
4665 |
0x00000000);
|
4666 |
spr_register(env, SPR_BOOKE_MAS7_MAS3, "MAS7_MAS3",
|
4667 |
SPR_NOACCESS, SPR_NOACCESS, |
4668 |
&spr_read_mas73, &spr_write_mas73, |
4669 |
0x00000000);
|
4670 |
ivpr_mask = (target_ulong)~0xFFFFULL;
|
4671 |
} |
4672 |
|
4673 |
#if !defined(CONFIG_USER_ONLY)
|
4674 |
env->nb_tlb = 0;
|
4675 |
env->tlb_type = TLB_MAS; |
4676 |
for (i = 0; i < BOOKE206_MAX_TLBN; i++) { |
4677 |
env->nb_tlb += booke206_tlb_size(env, i); |
4678 |
} |
4679 |
#endif
|
4680 |
|
4681 |
init_excp_e200(env, ivpr_mask); |
4682 |
/* Allocate hardware IRQ controller */
|
4683 |
ppce500_irq_init(env); |
4684 |
} |
4685 |
|
4686 |
static void init_proc_e500v1(CPUPPCState *env) |
4687 |
{ |
4688 |
init_proc_e500(env, fsl_e500v1); |
4689 |
} |
4690 |
|
4691 |
static void init_proc_e500v2(CPUPPCState *env) |
4692 |
{ |
4693 |
init_proc_e500(env, fsl_e500v2); |
4694 |
} |
4695 |
|
4696 |
static void init_proc_e500mc(CPUPPCState *env) |
4697 |
{ |
4698 |
init_proc_e500(env, fsl_e500mc); |
4699 |
} |
4700 |
|
4701 |
#ifdef TARGET_PPC64
|
4702 |
static void init_proc_e5500(CPUPPCState *env) |
4703 |
{ |
4704 |
init_proc_e500(env, fsl_e5500); |
4705 |
} |
4706 |
#endif
|
4707 |
|
4708 |
/* Non-embedded PowerPC */
|
4709 |
|
4710 |
/* POWER : same as 601, without mfmsr, mfsr */
|
4711 |
#if defined(TODO)
|
4712 |
#define POWERPC_INSNS_POWER (XXX_TODO)
|
4713 |
/* POWER RSC (from RAD6000) */
|
4714 |
#define POWERPC_MSRM_POWER (0x00000000FEF0ULL) |
4715 |
#endif /* TODO */ |
4716 |
|
4717 |
/* PowerPC 601 */
|
4718 |
#define POWERPC_INSNS_601 (PPC_INSNS_BASE | PPC_STRING | PPC_POWER_BR | \
|
4719 |
PPC_FLOAT | \ |
4720 |
PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \ |
4721 |
PPC_MEM_SYNC | PPC_MEM_EIEIO | PPC_MEM_TLBIE | \ |
4722 |
PPC_SEGMENT | PPC_EXTERN) |
4723 |
#define POWERPC_INSNS2_601 (PPC_NONE)
|
4724 |
#define POWERPC_MSRM_601 (0x000000000000FD70ULL) |
4725 |
#define POWERPC_MSRR_601 (0x0000000000001040ULL) |
4726 |
//#define POWERPC_MMU_601 (POWERPC_MMU_601)
|
4727 |
//#define POWERPC_EXCP_601 (POWERPC_EXCP_601)
|
4728 |
#define POWERPC_INPUT_601 (PPC_FLAGS_INPUT_6xx)
|
4729 |
#define POWERPC_BFDM_601 (bfd_mach_ppc_601)
|
4730 |
#define POWERPC_FLAG_601 (POWERPC_FLAG_SE | POWERPC_FLAG_RTC_CLK)
|
4731 |
#define check_pow_601 check_pow_none
|
4732 |
|
4733 |
static void init_proc_601 (CPUPPCState *env) |
4734 |
{ |
4735 |
gen_spr_ne_601(env); |
4736 |
gen_spr_601(env); |
4737 |
/* Hardware implementation registers */
|
4738 |
/* XXX : not implemented */
|
4739 |
spr_register(env, SPR_HID0, "HID0",
|
4740 |
SPR_NOACCESS, SPR_NOACCESS, |
4741 |
&spr_read_generic, &spr_write_hid0_601, |
4742 |
0x80010080);
|
4743 |
/* XXX : not implemented */
|
4744 |
spr_register(env, SPR_HID1, "HID1",
|
4745 |
SPR_NOACCESS, SPR_NOACCESS, |
4746 |
&spr_read_generic, &spr_write_generic, |
4747 |
0x00000000);
|
4748 |
/* XXX : not implemented */
|
4749 |
spr_register(env, SPR_601_HID2, "HID2",
|
4750 |
SPR_NOACCESS, SPR_NOACCESS, |
4751 |
&spr_read_generic, &spr_write_generic, |
4752 |
0x00000000);
|
4753 |
/* XXX : not implemented */
|
4754 |
spr_register(env, SPR_601_HID5, "HID5",
|
4755 |
SPR_NOACCESS, SPR_NOACCESS, |
4756 |
&spr_read_generic, &spr_write_generic, |
4757 |
0x00000000);
|
4758 |
/* Memory management */
|
4759 |
init_excp_601(env); |
4760 |
/* XXX: beware that dcache line size is 64
|
4761 |
* but dcbz uses 32 bytes "sectors"
|
4762 |
* XXX: this breaks clcs instruction !
|
4763 |
*/
|
4764 |
env->dcache_line_size = 32;
|
4765 |
env->icache_line_size = 64;
|
4766 |
/* Allocate hardware IRQ controller */
|
4767 |
ppc6xx_irq_init(env); |
4768 |
} |
4769 |
|
4770 |
/* PowerPC 601v */
|
4771 |
#define POWERPC_INSNS_601v (PPC_INSNS_BASE | PPC_STRING | PPC_POWER_BR | \
|
4772 |
PPC_FLOAT | \ |
4773 |
PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \ |
4774 |
PPC_MEM_SYNC | PPC_MEM_EIEIO | PPC_MEM_TLBIE | \ |
4775 |
PPC_SEGMENT | PPC_EXTERN) |
4776 |
#define POWERPC_INSNS2_601v (PPC_NONE)
|
4777 |
#define POWERPC_MSRM_601v (0x000000000000FD70ULL) |
4778 |
#define POWERPC_MSRR_601v (0x0000000000001040ULL) |
4779 |
#define POWERPC_MMU_601v (POWERPC_MMU_601)
|
4780 |
#define POWERPC_EXCP_601v (POWERPC_EXCP_601)
|
4781 |
#define POWERPC_INPUT_601v (PPC_FLAGS_INPUT_6xx)
|
4782 |
#define POWERPC_BFDM_601v (bfd_mach_ppc_601)
|
4783 |
#define POWERPC_FLAG_601v (POWERPC_FLAG_SE | POWERPC_FLAG_RTC_CLK)
|
4784 |
#define check_pow_601v check_pow_none
|
4785 |
|
4786 |
static void init_proc_601v (CPUPPCState *env) |
4787 |
{ |
4788 |
init_proc_601(env); |
4789 |
/* XXX : not implemented */
|
4790 |
spr_register(env, SPR_601_HID15, "HID15",
|
4791 |
SPR_NOACCESS, SPR_NOACCESS, |
4792 |
&spr_read_generic, &spr_write_generic, |
4793 |
0x00000000);
|
4794 |
} |
4795 |
|
4796 |
/* PowerPC 602 */
|
4797 |
#define POWERPC_INSNS_602 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
|
4798 |
PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \ |
4799 |
PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \ |
4800 |
PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \ |
4801 |
PPC_MEM_SYNC | PPC_MEM_EIEIO | \ |
4802 |
PPC_MEM_TLBIE | PPC_6xx_TLB | PPC_MEM_TLBSYNC | \ |
4803 |
PPC_SEGMENT | PPC_602_SPEC) |
4804 |
#define POWERPC_INSNS2_602 (PPC_NONE)
|
4805 |
#define POWERPC_MSRM_602 (0x0000000000C7FF73ULL) |
4806 |
/* XXX: 602 MMU is quite specific. Should add a special case */
|
4807 |
#define POWERPC_MMU_602 (POWERPC_MMU_SOFT_6xx)
|
4808 |
//#define POWERPC_EXCP_602 (POWERPC_EXCP_602)
|
4809 |
#define POWERPC_INPUT_602 (PPC_FLAGS_INPUT_6xx)
|
4810 |
#define POWERPC_BFDM_602 (bfd_mach_ppc_602)
|
4811 |
#define POWERPC_FLAG_602 (POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | \
|
4812 |
POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK) |
4813 |
#define check_pow_602 check_pow_hid0
|
4814 |
|
4815 |
static void init_proc_602 (CPUPPCState *env) |
4816 |
{ |
4817 |
gen_spr_ne_601(env); |
4818 |
gen_spr_602(env); |
4819 |
/* Time base */
|
4820 |
gen_tbl(env); |
4821 |
/* hardware implementation registers */
|
4822 |
/* XXX : not implemented */
|
4823 |
spr_register(env, SPR_HID0, "HID0",
|
4824 |
SPR_NOACCESS, SPR_NOACCESS, |
4825 |
&spr_read_generic, &spr_write_generic, |
4826 |
0x00000000);
|
4827 |
/* XXX : not implemented */
|
4828 |
spr_register(env, SPR_HID1, "HID1",
|
4829 |
SPR_NOACCESS, SPR_NOACCESS, |
4830 |
&spr_read_generic, &spr_write_generic, |
4831 |
0x00000000);
|
4832 |
/* Memory management */
|
4833 |
gen_low_BATs(env); |
4834 |
gen_6xx_7xx_soft_tlb(env, 64, 2); |
4835 |
init_excp_602(env); |
4836 |
env->dcache_line_size = 32;
|
4837 |
env->icache_line_size = 32;
|
4838 |
/* Allocate hardware IRQ controller */
|
4839 |
ppc6xx_irq_init(env); |
4840 |
} |
4841 |
|
4842 |
/* PowerPC 603 */
|
4843 |
#define POWERPC_INSNS_603 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
|
4844 |
PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \ |
4845 |
PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \ |
4846 |
PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \ |
4847 |
PPC_MEM_SYNC | PPC_MEM_EIEIO | \ |
4848 |
PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | \ |
4849 |
PPC_SEGMENT | PPC_EXTERN) |
4850 |
#define POWERPC_INSNS2_603 (PPC_NONE)
|
4851 |
#define POWERPC_MSRM_603 (0x000000000007FF73ULL) |
4852 |
#define POWERPC_MMU_603 (POWERPC_MMU_SOFT_6xx)
|
4853 |
//#define POWERPC_EXCP_603 (POWERPC_EXCP_603)
|
4854 |
#define POWERPC_INPUT_603 (PPC_FLAGS_INPUT_6xx)
|
4855 |
#define POWERPC_BFDM_603 (bfd_mach_ppc_603)
|
4856 |
#define POWERPC_FLAG_603 (POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | \
|
4857 |
POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK) |
4858 |
#define check_pow_603 check_pow_hid0
|
4859 |
|
4860 |
static void init_proc_603 (CPUPPCState *env) |
4861 |
{ |
4862 |
gen_spr_ne_601(env); |
4863 |
gen_spr_603(env); |
4864 |
/* Time base */
|
4865 |
gen_tbl(env); |
4866 |
/* hardware implementation registers */
|
4867 |
/* XXX : not implemented */
|
4868 |
spr_register(env, SPR_HID0, "HID0",
|
4869 |
SPR_NOACCESS, SPR_NOACCESS, |
4870 |
&spr_read_generic, &spr_write_generic, |
4871 |
0x00000000);
|
4872 |
/* XXX : not implemented */
|
4873 |
spr_register(env, SPR_HID1, "HID1",
|
4874 |
SPR_NOACCESS, SPR_NOACCESS, |
4875 |
&spr_read_generic, &spr_write_generic, |
4876 |
0x00000000);
|
4877 |
/* Memory management */
|
4878 |
gen_low_BATs(env); |
4879 |
gen_6xx_7xx_soft_tlb(env, 64, 2); |
4880 |
init_excp_603(env); |
4881 |
env->dcache_line_size = 32;
|
4882 |
env->icache_line_size = 32;
|
4883 |
/* Allocate hardware IRQ controller */
|
4884 |
ppc6xx_irq_init(env); |
4885 |
} |
4886 |
|
4887 |
/* PowerPC 603e */
|
4888 |
#define POWERPC_INSNS_603E (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
|
4889 |
PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \ |
4890 |
PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \ |
4891 |
PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \ |
4892 |
PPC_MEM_SYNC | PPC_MEM_EIEIO | \ |
4893 |
PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | \ |
4894 |
PPC_SEGMENT | PPC_EXTERN) |
4895 |
#define POWERPC_INSNS2_603E (PPC_NONE)
|
4896 |
#define POWERPC_MSRM_603E (0x000000000007FF73ULL) |
4897 |
#define POWERPC_MMU_603E (POWERPC_MMU_SOFT_6xx)
|
4898 |
//#define POWERPC_EXCP_603E (POWERPC_EXCP_603E)
|
4899 |
#define POWERPC_INPUT_603E (PPC_FLAGS_INPUT_6xx)
|
4900 |
#define POWERPC_BFDM_603E (bfd_mach_ppc_ec603e)
|
4901 |
#define POWERPC_FLAG_603E (POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | \
|
4902 |
POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK) |
4903 |
#define check_pow_603E check_pow_hid0
|
4904 |
|
4905 |
static void init_proc_603E (CPUPPCState *env) |
4906 |
{ |
4907 |
gen_spr_ne_601(env); |
4908 |
gen_spr_603(env); |
4909 |
/* Time base */
|
4910 |
gen_tbl(env); |
4911 |
/* hardware implementation registers */
|
4912 |
/* XXX : not implemented */
|
4913 |
spr_register(env, SPR_HID0, "HID0",
|
4914 |
SPR_NOACCESS, SPR_NOACCESS, |
4915 |
&spr_read_generic, &spr_write_generic, |
4916 |
0x00000000);
|
4917 |
/* XXX : not implemented */
|
4918 |
spr_register(env, SPR_HID1, "HID1",
|
4919 |
SPR_NOACCESS, SPR_NOACCESS, |
4920 |
&spr_read_generic, &spr_write_generic, |
4921 |
0x00000000);
|
4922 |
/* XXX : not implemented */
|
4923 |
spr_register(env, SPR_IABR, "IABR",
|
4924 |
SPR_NOACCESS, SPR_NOACCESS, |
4925 |
&spr_read_generic, &spr_write_generic, |
4926 |
0x00000000);
|
4927 |
/* Memory management */
|
4928 |
gen_low_BATs(env); |
4929 |
gen_6xx_7xx_soft_tlb(env, 64, 2); |
4930 |
init_excp_603(env); |
4931 |
env->dcache_line_size = 32;
|
4932 |
env->icache_line_size = 32;
|
4933 |
/* Allocate hardware IRQ controller */
|
4934 |
ppc6xx_irq_init(env); |
4935 |
} |
4936 |
|
4937 |
/* PowerPC 604 */
|
4938 |
#define POWERPC_INSNS_604 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
|
4939 |
PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \ |
4940 |
PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \ |
4941 |
PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \ |
4942 |
PPC_MEM_SYNC | PPC_MEM_EIEIO | \ |
4943 |
PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \ |
4944 |
PPC_SEGMENT | PPC_EXTERN) |
4945 |
#define POWERPC_INSNS2_604 (PPC_NONE)
|
4946 |
#define POWERPC_MSRM_604 (0x000000000005FF77ULL) |
4947 |
#define POWERPC_MMU_604 (POWERPC_MMU_32B)
|
4948 |
//#define POWERPC_EXCP_604 (POWERPC_EXCP_604)
|
4949 |
#define POWERPC_INPUT_604 (PPC_FLAGS_INPUT_6xx)
|
4950 |
#define POWERPC_BFDM_604 (bfd_mach_ppc_604)
|
4951 |
#define POWERPC_FLAG_604 (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
|
4952 |
POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK) |
4953 |
#define check_pow_604 check_pow_nocheck
|
4954 |
|
4955 |
static void init_proc_604 (CPUPPCState *env) |
4956 |
{ |
4957 |
gen_spr_ne_601(env); |
4958 |
gen_spr_604(env); |
4959 |
/* Time base */
|
4960 |
gen_tbl(env); |
4961 |
/* Hardware implementation registers */
|
4962 |
/* XXX : not implemented */
|
4963 |
spr_register(env, SPR_HID0, "HID0",
|
4964 |
SPR_NOACCESS, SPR_NOACCESS, |
4965 |
&spr_read_generic, &spr_write_generic, |
4966 |
0x00000000);
|
4967 |
/* Memory management */
|
4968 |
gen_low_BATs(env); |
4969 |
init_excp_604(env); |
4970 |
env->dcache_line_size = 32;
|
4971 |
env->icache_line_size = 32;
|
4972 |
/* Allocate hardware IRQ controller */
|
4973 |
ppc6xx_irq_init(env); |
4974 |
} |
4975 |
|
4976 |
/* PowerPC 604E */
|
4977 |
#define POWERPC_INSNS_604E (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
|
4978 |
PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \ |
4979 |
PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \ |
4980 |
PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \ |
4981 |
PPC_MEM_SYNC | PPC_MEM_EIEIO | \ |
4982 |
PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \ |
4983 |
PPC_SEGMENT | PPC_EXTERN) |
4984 |
#define POWERPC_INSNS2_604E (PPC_NONE)
|
4985 |
#define POWERPC_MSRM_604E (0x000000000005FF77ULL) |
4986 |
#define POWERPC_MMU_604E (POWERPC_MMU_32B)
|
4987 |
#define POWERPC_EXCP_604E (POWERPC_EXCP_604)
|
4988 |
#define POWERPC_INPUT_604E (PPC_FLAGS_INPUT_6xx)
|
4989 |
#define POWERPC_BFDM_604E (bfd_mach_ppc_604)
|
4990 |
#define POWERPC_FLAG_604E (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
|
4991 |
POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK) |
4992 |
#define check_pow_604E check_pow_nocheck
|
4993 |
|
4994 |
static void init_proc_604E (CPUPPCState *env) |
4995 |
{ |
4996 |
gen_spr_ne_601(env); |
4997 |
gen_spr_604(env); |
4998 |
/* XXX : not implemented */
|
4999 |
spr_register(env, SPR_MMCR1, "MMCR1",
|
5000 |
SPR_NOACCESS, SPR_NOACCESS, |
5001 |
&spr_read_generic, &spr_write_generic, |
5002 |
0x00000000);
|
5003 |
/* XXX : not implemented */
|
5004 |
spr_register(env, SPR_PMC3, "PMC3",
|
5005 |
SPR_NOACCESS, SPR_NOACCESS, |
5006 |
&spr_read_generic, &spr_write_generic, |
5007 |
0x00000000);
|
5008 |
/* XXX : not implemented */
|
5009 |
spr_register(env, SPR_PMC4, "PMC4",
|
5010 |
SPR_NOACCESS, SPR_NOACCESS, |
5011 |
&spr_read_generic, &spr_write_generic, |
5012 |
0x00000000);
|
5013 |
/* Time base */
|
5014 |
gen_tbl(env); |
5015 |
/* Hardware implementation registers */
|
5016 |
/* XXX : not implemented */
|
5017 |
spr_register(env, SPR_HID0, "HID0",
|
5018 |
SPR_NOACCESS, SPR_NOACCESS, |
5019 |
&spr_read_generic, &spr_write_generic, |
5020 |
0x00000000);
|
5021 |
/* XXX : not implemented */
|
5022 |
spr_register(env, SPR_HID1, "HID1",
|
5023 |
SPR_NOACCESS, SPR_NOACCESS, |
5024 |
&spr_read_generic, &spr_write_generic, |
5025 |
0x00000000);
|
5026 |
/* Memory management */
|
5027 |
gen_low_BATs(env); |
5028 |
init_excp_604(env); |
5029 |
env->dcache_line_size = 32;
|
5030 |
env->icache_line_size = 32;
|
5031 |
/* Allocate hardware IRQ controller */
|
5032 |
ppc6xx_irq_init(env); |
5033 |
} |
5034 |
|
5035 |
/* PowerPC 740 */
|
5036 |
#define POWERPC_INSNS_740 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
|
5037 |
PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \ |
5038 |
PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \ |
5039 |
PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \ |
5040 |
PPC_MEM_SYNC | PPC_MEM_EIEIO | \ |
5041 |
PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \ |
5042 |
PPC_SEGMENT | PPC_EXTERN) |
5043 |
#define POWERPC_INSNS2_740 (PPC_NONE)
|
5044 |
#define POWERPC_MSRM_740 (0x000000000005FF77ULL) |
5045 |
#define POWERPC_MMU_740 (POWERPC_MMU_32B)
|
5046 |
#define POWERPC_EXCP_740 (POWERPC_EXCP_7x0)
|
5047 |
#define POWERPC_INPUT_740 (PPC_FLAGS_INPUT_6xx)
|
5048 |
#define POWERPC_BFDM_740 (bfd_mach_ppc_750)
|
5049 |
#define POWERPC_FLAG_740 (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
|
5050 |
POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK) |
5051 |
#define check_pow_740 check_pow_hid0
|
5052 |
|
5053 |
static void init_proc_740 (CPUPPCState *env) |
5054 |
{ |
5055 |
gen_spr_ne_601(env); |
5056 |
gen_spr_7xx(env); |
5057 |
/* Time base */
|
5058 |
gen_tbl(env); |
5059 |
/* Thermal management */
|
5060 |
gen_spr_thrm(env); |
5061 |
/* Hardware implementation registers */
|
5062 |
/* XXX : not implemented */
|
5063 |
spr_register(env, SPR_HID0, "HID0",
|
5064 |
SPR_NOACCESS, SPR_NOACCESS, |
5065 |
&spr_read_generic, &spr_write_generic, |
5066 |
0x00000000);
|
5067 |
/* XXX : not implemented */
|
5068 |
spr_register(env, SPR_HID1, "HID1",
|
5069 |
SPR_NOACCESS, SPR_NOACCESS, |
5070 |
&spr_read_generic, &spr_write_generic, |
5071 |
0x00000000);
|
5072 |
/* Memory management */
|
5073 |
gen_low_BATs(env); |
5074 |
init_excp_7x0(env); |
5075 |
env->dcache_line_size = 32;
|
5076 |
env->icache_line_size = 32;
|
5077 |
/* Allocate hardware IRQ controller */
|
5078 |
ppc6xx_irq_init(env); |
5079 |
} |
5080 |
|
5081 |
/* PowerPC 750 */
|
5082 |
#define POWERPC_INSNS_750 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
|
5083 |
PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \ |
5084 |
PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \ |
5085 |
PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \ |
5086 |
PPC_MEM_SYNC | PPC_MEM_EIEIO | \ |
5087 |
PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \ |
5088 |
PPC_SEGMENT | PPC_EXTERN) |
5089 |
#define POWERPC_INSNS2_750 (PPC_NONE)
|
5090 |
#define POWERPC_MSRM_750 (0x000000000005FF77ULL) |
5091 |
#define POWERPC_MMU_750 (POWERPC_MMU_32B)
|
5092 |
#define POWERPC_EXCP_750 (POWERPC_EXCP_7x0)
|
5093 |
#define POWERPC_INPUT_750 (PPC_FLAGS_INPUT_6xx)
|
5094 |
#define POWERPC_BFDM_750 (bfd_mach_ppc_750)
|
5095 |
#define POWERPC_FLAG_750 (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
|
5096 |
POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK) |
5097 |
#define check_pow_750 check_pow_hid0
|
5098 |
|
5099 |
static void init_proc_750 (CPUPPCState *env) |
5100 |
{ |
5101 |
gen_spr_ne_601(env); |
5102 |
gen_spr_7xx(env); |
5103 |
/* XXX : not implemented */
|
5104 |
spr_register(env, SPR_L2CR, "L2CR",
|
5105 |
SPR_NOACCESS, SPR_NOACCESS, |
5106 |
&spr_read_generic, &spr_write_generic, |
5107 |
0x00000000);
|
5108 |
/* Time base */
|
5109 |
gen_tbl(env); |
5110 |
/* Thermal management */
|
5111 |
gen_spr_thrm(env); |
5112 |
/* Hardware implementation registers */
|
5113 |
/* XXX : not implemented */
|
5114 |
spr_register(env, SPR_HID0, "HID0",
|
5115 |
SPR_NOACCESS, SPR_NOACCESS, |
5116 |
&spr_read_generic, &spr_write_generic, |
5117 |
0x00000000);
|
5118 |
/* XXX : not implemented */
|
5119 |
spr_register(env, SPR_HID1, "HID1",
|
5120 |
SPR_NOACCESS, SPR_NOACCESS, |
5121 |
&spr_read_generic, &spr_write_generic, |
5122 |
0x00000000);
|
5123 |
/* Memory management */
|
5124 |
gen_low_BATs(env); |
5125 |
/* XXX: high BATs are also present but are known to be bugged on
|
5126 |
* die version 1.x
|
5127 |
*/
|
5128 |
init_excp_7x0(env); |
5129 |
env->dcache_line_size = 32;
|
5130 |
env->icache_line_size = 32;
|
5131 |
/* Allocate hardware IRQ controller */
|
5132 |
ppc6xx_irq_init(env); |
5133 |
} |
5134 |
|
5135 |
/* PowerPC 750 CL */
|
5136 |
/* XXX: not implemented:
|
5137 |
* cache lock instructions:
|
5138 |
* dcbz_l
|
5139 |
* floating point paired instructions
|
5140 |
* psq_lux
|
5141 |
* psq_lx
|
5142 |
* psq_stux
|
5143 |
* psq_stx
|
5144 |
* ps_abs
|
5145 |
* ps_add
|
5146 |
* ps_cmpo0
|
5147 |
* ps_cmpo1
|
5148 |
* ps_cmpu0
|
5149 |
* ps_cmpu1
|
5150 |
* ps_div
|
5151 |
* ps_madd
|
5152 |
* ps_madds0
|
5153 |
* ps_madds1
|
5154 |
* ps_merge00
|
5155 |
* ps_merge01
|
5156 |
* ps_merge10
|
5157 |
* ps_merge11
|
5158 |
* ps_mr
|
5159 |
* ps_msub
|
5160 |
* ps_mul
|
5161 |
* ps_muls0
|
5162 |
* ps_muls1
|
5163 |
* ps_nabs
|
5164 |
* ps_neg
|
5165 |
* ps_nmadd
|
5166 |
* ps_nmsub
|
5167 |
* ps_res
|
5168 |
* ps_rsqrte
|
5169 |
* ps_sel
|
5170 |
* ps_sub
|
5171 |
* ps_sum0
|
5172 |
* ps_sum1
|
5173 |
*/
|
5174 |
#define POWERPC_INSNS_750cl (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
|
5175 |
PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \ |
5176 |
PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \ |
5177 |
PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \ |
5178 |
PPC_MEM_SYNC | PPC_MEM_EIEIO | \ |
5179 |
PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \ |
5180 |
PPC_SEGMENT | PPC_EXTERN) |
5181 |
#define POWERPC_INSNS2_750cl (PPC_NONE)
|
5182 |
#define POWERPC_MSRM_750cl (0x000000000005FF77ULL) |
5183 |
#define POWERPC_MMU_750cl (POWERPC_MMU_32B)
|
5184 |
#define POWERPC_EXCP_750cl (POWERPC_EXCP_7x0)
|
5185 |
#define POWERPC_INPUT_750cl (PPC_FLAGS_INPUT_6xx)
|
5186 |
#define POWERPC_BFDM_750cl (bfd_mach_ppc_750)
|
5187 |
#define POWERPC_FLAG_750cl (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
|
5188 |
POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK) |
5189 |
#define check_pow_750cl check_pow_hid0
|
5190 |
|
5191 |
static void init_proc_750cl (CPUPPCState *env) |
5192 |
{ |
5193 |
gen_spr_ne_601(env); |
5194 |
gen_spr_7xx(env); |
5195 |
/* XXX : not implemented */
|
5196 |
spr_register(env, SPR_L2CR, "L2CR",
|
5197 |
SPR_NOACCESS, SPR_NOACCESS, |
5198 |
&spr_read_generic, &spr_write_generic, |
5199 |
0x00000000);
|
5200 |
/* Time base */
|
5201 |
gen_tbl(env); |
5202 |
/* Thermal management */
|
5203 |
/* Those registers are fake on 750CL */
|
5204 |
spr_register(env, SPR_THRM1, "THRM1",
|
5205 |
SPR_NOACCESS, SPR_NOACCESS, |
5206 |
&spr_read_generic, &spr_write_generic, |
5207 |
0x00000000);
|
5208 |
spr_register(env, SPR_THRM2, "THRM2",
|
5209 |
SPR_NOACCESS, SPR_NOACCESS, |
5210 |
&spr_read_generic, &spr_write_generic, |
5211 |
0x00000000);
|
5212 |
spr_register(env, SPR_THRM3, "THRM3",
|
5213 |
SPR_NOACCESS, SPR_NOACCESS, |
5214 |
&spr_read_generic, &spr_write_generic, |
5215 |
0x00000000);
|
5216 |
/* XXX: not implemented */
|
5217 |
spr_register(env, SPR_750_TDCL, "TDCL",
|
5218 |
SPR_NOACCESS, SPR_NOACCESS, |
5219 |
&spr_read_generic, &spr_write_generic, |
5220 |
0x00000000);
|
5221 |
spr_register(env, SPR_750_TDCH, "TDCH",
|
5222 |
SPR_NOACCESS, SPR_NOACCESS, |
5223 |
&spr_read_generic, &spr_write_generic, |
5224 |
0x00000000);
|
5225 |
/* DMA */
|
5226 |
/* XXX : not implemented */
|
5227 |
spr_register(env, SPR_750_WPAR, "WPAR",
|
5228 |
SPR_NOACCESS, SPR_NOACCESS, |
5229 |
&spr_read_generic, &spr_write_generic, |
5230 |
0x00000000);
|
5231 |
spr_register(env, SPR_750_DMAL, "DMAL",
|
5232 |
SPR_NOACCESS, SPR_NOACCESS, |
5233 |
&spr_read_generic, &spr_write_generic, |
5234 |
0x00000000);
|
5235 |
spr_register(env, SPR_750_DMAU, "DMAU",
|
5236 |
SPR_NOACCESS, SPR_NOACCESS, |
5237 |
&spr_read_generic, &spr_write_generic, |
5238 |
0x00000000);
|
5239 |
/* Hardware implementation registers */
|
5240 |
/* XXX : not implemented */
|
5241 |
spr_register(env, SPR_HID0, "HID0",
|
5242 |
SPR_NOACCESS, SPR_NOACCESS, |
5243 |
&spr_read_generic, &spr_write_generic, |
5244 |
0x00000000);
|
5245 |
/* XXX : not implemented */
|
5246 |
spr_register(env, SPR_HID1, "HID1",
|
5247 |
SPR_NOACCESS, SPR_NOACCESS, |
5248 |
&spr_read_generic, &spr_write_generic, |
5249 |
0x00000000);
|
5250 |
/* XXX : not implemented */
|
5251 |
spr_register(env, SPR_750CL_HID2, "HID2",
|
5252 |
SPR_NOACCESS, SPR_NOACCESS, |
5253 |
&spr_read_generic, &spr_write_generic, |
5254 |
0x00000000);
|
5255 |
/* XXX : not implemented */
|
5256 |
spr_register(env, SPR_750CL_HID4, "HID4",
|
5257 |
SPR_NOACCESS, SPR_NOACCESS, |
5258 |
&spr_read_generic, &spr_write_generic, |
5259 |
0x00000000);
|
5260 |
/* Quantization registers */
|
5261 |
/* XXX : not implemented */
|
5262 |
spr_register(env, SPR_750_GQR0, "GQR0",
|
5263 |
SPR_NOACCESS, SPR_NOACCESS, |
5264 |
&spr_read_generic, &spr_write_generic, |
5265 |
0x00000000);
|
5266 |
/* XXX : not implemented */
|
5267 |
spr_register(env, SPR_750_GQR1, "GQR1",
|
5268 |
SPR_NOACCESS, SPR_NOACCESS, |
5269 |
&spr_read_generic, &spr_write_generic, |
5270 |
0x00000000);
|
5271 |
/* XXX : not implemented */
|
5272 |
spr_register(env, SPR_750_GQR2, "GQR2",
|
5273 |
SPR_NOACCESS, SPR_NOACCESS, |
5274 |
&spr_read_generic, &spr_write_generic, |
5275 |
0x00000000);
|
5276 |
/* XXX : not implemented */
|
5277 |
spr_register(env, SPR_750_GQR3, "GQR3",
|
5278 |
SPR_NOACCESS, SPR_NOACCESS, |
5279 |
&spr_read_generic, &spr_write_generic, |
5280 |
0x00000000);
|
5281 |
/* XXX : not implemented */
|
5282 |
spr_register(env, SPR_750_GQR4, "GQR4",
|
5283 |
SPR_NOACCESS, SPR_NOACCESS, |
5284 |
&spr_read_generic, &spr_write_generic, |
5285 |
0x00000000);
|
5286 |
/* XXX : not implemented */
|
5287 |
spr_register(env, SPR_750_GQR5, "GQR5",
|
5288 |
SPR_NOACCESS, SPR_NOACCESS, |
5289 |
&spr_read_generic, &spr_write_generic, |
5290 |
0x00000000);
|
5291 |
/* XXX : not implemented */
|
5292 |
spr_register(env, SPR_750_GQR6, "GQR6",
|
5293 |
SPR_NOACCESS, SPR_NOACCESS, |
5294 |
&spr_read_generic, &spr_write_generic, |
5295 |
0x00000000);
|
5296 |
/* XXX : not implemented */
|
5297 |
spr_register(env, SPR_750_GQR7, "GQR7",
|
5298 |
SPR_NOACCESS, SPR_NOACCESS, |
5299 |
&spr_read_generic, &spr_write_generic, |
5300 |
0x00000000);
|
5301 |
/* Memory management */
|
5302 |
gen_low_BATs(env); |
5303 |
/* PowerPC 750cl has 8 DBATs and 8 IBATs */
|
5304 |
gen_high_BATs(env); |
5305 |
init_excp_750cl(env); |
5306 |
env->dcache_line_size = 32;
|
5307 |
env->icache_line_size = 32;
|
5308 |
/* Allocate hardware IRQ controller */
|
5309 |
ppc6xx_irq_init(env); |
5310 |
} |
5311 |
|
5312 |
/* PowerPC 750CX */
|
5313 |
#define POWERPC_INSNS_750cx (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
|
5314 |
PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \ |
5315 |
PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \ |
5316 |
PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \ |
5317 |
PPC_MEM_SYNC | PPC_MEM_EIEIO | \ |
5318 |
PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \ |
5319 |
PPC_SEGMENT | PPC_EXTERN) |
5320 |
#define POWERPC_INSNS2_750cx (PPC_NONE)
|
5321 |
#define POWERPC_MSRM_750cx (0x000000000005FF77ULL) |
5322 |
#define POWERPC_MMU_750cx (POWERPC_MMU_32B)
|
5323 |
#define POWERPC_EXCP_750cx (POWERPC_EXCP_7x0)
|
5324 |
#define POWERPC_INPUT_750cx (PPC_FLAGS_INPUT_6xx)
|
5325 |
#define POWERPC_BFDM_750cx (bfd_mach_ppc_750)
|
5326 |
#define POWERPC_FLAG_750cx (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
|
5327 |
POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK) |
5328 |
#define check_pow_750cx check_pow_hid0
|
5329 |
|
5330 |
static void init_proc_750cx (CPUPPCState *env) |
5331 |
{ |
5332 |
gen_spr_ne_601(env); |
5333 |
gen_spr_7xx(env); |
5334 |
/* XXX : not implemented */
|
5335 |
spr_register(env, SPR_L2CR, "L2CR",
|
5336 |
SPR_NOACCESS, SPR_NOACCESS, |
5337 |
&spr_read_generic, &spr_write_generic, |
5338 |
0x00000000);
|
5339 |
/* Time base */
|
5340 |
gen_tbl(env); |
5341 |
/* Thermal management */
|
5342 |
gen_spr_thrm(env); |
5343 |
/* This register is not implemented but is present for compatibility */
|
5344 |
spr_register(env, SPR_SDA, "SDA",
|
5345 |
SPR_NOACCESS, SPR_NOACCESS, |
5346 |
&spr_read_generic, &spr_write_generic, |
5347 |
0x00000000);
|
5348 |
/* Hardware implementation registers */
|
5349 |
/* XXX : not implemented */
|
5350 |
spr_register(env, SPR_HID0, "HID0",
|
5351 |
SPR_NOACCESS, SPR_NOACCESS, |
5352 |
&spr_read_generic, &spr_write_generic, |
5353 |
0x00000000);
|
5354 |
/* XXX : not implemented */
|
5355 |
spr_register(env, SPR_HID1, "HID1",
|
5356 |
SPR_NOACCESS, SPR_NOACCESS, |
5357 |
&spr_read_generic, &spr_write_generic, |
5358 |
0x00000000);
|
5359 |
/* Memory management */
|
5360 |
gen_low_BATs(env); |
5361 |
/* PowerPC 750cx has 8 DBATs and 8 IBATs */
|
5362 |
gen_high_BATs(env); |
5363 |
init_excp_750cx(env); |
5364 |
env->dcache_line_size = 32;
|
5365 |
env->icache_line_size = 32;
|
5366 |
/* Allocate hardware IRQ controller */
|
5367 |
ppc6xx_irq_init(env); |
5368 |
} |
5369 |
|
5370 |
/* PowerPC 750FX */
|
5371 |
#define POWERPC_INSNS_750fx (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
|
5372 |
PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \ |
5373 |
PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \ |
5374 |
PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \ |
5375 |
PPC_MEM_SYNC | PPC_MEM_EIEIO | \ |
5376 |
PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \ |
5377 |
PPC_SEGMENT | PPC_EXTERN) |
5378 |
#define POWERPC_INSNS2_750fx (PPC_NONE)
|
5379 |
#define POWERPC_MSRM_750fx (0x000000000005FF77ULL) |
5380 |
#define POWERPC_MMU_750fx (POWERPC_MMU_32B)
|
5381 |
#define POWERPC_EXCP_750fx (POWERPC_EXCP_7x0)
|
5382 |
#define POWERPC_INPUT_750fx (PPC_FLAGS_INPUT_6xx)
|
5383 |
#define POWERPC_BFDM_750fx (bfd_mach_ppc_750)
|
5384 |
#define POWERPC_FLAG_750fx (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
|
5385 |
POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK) |
5386 |
#define check_pow_750fx check_pow_hid0
|
5387 |
|
5388 |
static void init_proc_750fx (CPUPPCState *env) |
5389 |
{ |
5390 |
gen_spr_ne_601(env); |
5391 |
gen_spr_7xx(env); |
5392 |
/* XXX : not implemented */
|
5393 |
spr_register(env, SPR_L2CR, "L2CR",
|
5394 |
SPR_NOACCESS, SPR_NOACCESS, |
5395 |
&spr_read_generic, &spr_write_generic, |
5396 |
0x00000000);
|
5397 |
/* Time base */
|
5398 |
gen_tbl(env); |
5399 |
/* Thermal management */
|
5400 |
gen_spr_thrm(env); |
5401 |
/* XXX : not implemented */
|
5402 |
spr_register(env, SPR_750_THRM4, "THRM4",
|
5403 |
SPR_NOACCESS, SPR_NOACCESS, |
5404 |
&spr_read_generic, &spr_write_generic, |
5405 |
0x00000000);
|
5406 |
/* Hardware implementation registers */
|
5407 |
/* XXX : not implemented */
|
5408 |
spr_register(env, SPR_HID0, "HID0",
|
5409 |
SPR_NOACCESS, SPR_NOACCESS, |
5410 |
&spr_read_generic, &spr_write_generic, |
5411 |
0x00000000);
|
5412 |
/* XXX : not implemented */
|
5413 |
spr_register(env, SPR_HID1, "HID1",
|
5414 |
SPR_NOACCESS, SPR_NOACCESS, |
5415 |
&spr_read_generic, &spr_write_generic, |
5416 |
0x00000000);
|
5417 |
/* XXX : not implemented */
|
5418 |
spr_register(env, SPR_750FX_HID2, "HID2",
|
5419 |
SPR_NOACCESS, SPR_NOACCESS, |
5420 |
&spr_read_generic, &spr_write_generic, |
5421 |
0x00000000);
|
5422 |
/* Memory management */
|
5423 |
gen_low_BATs(env); |
5424 |
/* PowerPC 750fx & 750gx has 8 DBATs and 8 IBATs */
|
5425 |
gen_high_BATs(env); |
5426 |
init_excp_7x0(env); |
5427 |
env->dcache_line_size = 32;
|
5428 |
env->icache_line_size = 32;
|
5429 |
/* Allocate hardware IRQ controller */
|
5430 |
ppc6xx_irq_init(env); |
5431 |
} |
5432 |
|
5433 |
/* PowerPC 750GX */
|
5434 |
#define POWERPC_INSNS_750gx (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
|
5435 |
PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \ |
5436 |
PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \ |
5437 |
PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \ |
5438 |
PPC_MEM_SYNC | PPC_MEM_EIEIO | \ |
5439 |
PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \ |
5440 |
PPC_SEGMENT | PPC_EXTERN) |
5441 |
#define POWERPC_INSNS2_750gx (PPC_NONE)
|
5442 |
#define POWERPC_MSRM_750gx (0x000000000005FF77ULL) |
5443 |
#define POWERPC_MMU_750gx (POWERPC_MMU_32B)
|
5444 |
#define POWERPC_EXCP_750gx (POWERPC_EXCP_7x0)
|
5445 |
#define POWERPC_INPUT_750gx (PPC_FLAGS_INPUT_6xx)
|
5446 |
#define POWERPC_BFDM_750gx (bfd_mach_ppc_750)
|
5447 |
#define POWERPC_FLAG_750gx (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
|
5448 |
POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK) |
5449 |
#define check_pow_750gx check_pow_hid0
|
5450 |
|
5451 |
static void init_proc_750gx (CPUPPCState *env) |
5452 |
{ |
5453 |
gen_spr_ne_601(env); |
5454 |
gen_spr_7xx(env); |
5455 |
/* XXX : not implemented (XXX: different from 750fx) */
|
5456 |
spr_register(env, SPR_L2CR, "L2CR",
|
5457 |
SPR_NOACCESS, SPR_NOACCESS, |
5458 |
&spr_read_generic, &spr_write_generic, |
5459 |
0x00000000);
|
5460 |
/* Time base */
|
5461 |
gen_tbl(env); |
5462 |
/* Thermal management */
|
5463 |
gen_spr_thrm(env); |
5464 |
/* XXX : not implemented */
|
5465 |
spr_register(env, SPR_750_THRM4, "THRM4",
|
5466 |
SPR_NOACCESS, SPR_NOACCESS, |
5467 |
&spr_read_generic, &spr_write_generic, |
5468 |
0x00000000);
|
5469 |
/* Hardware implementation registers */
|
5470 |
/* XXX : not implemented (XXX: different from 750fx) */
|
5471 |
spr_register(env, SPR_HID0, "HID0",
|
5472 |
SPR_NOACCESS, SPR_NOACCESS, |
5473 |
&spr_read_generic, &spr_write_generic, |
5474 |
0x00000000);
|
5475 |
/* XXX : not implemented */
|
5476 |
spr_register(env, SPR_HID1, "HID1",
|
5477 |
SPR_NOACCESS, SPR_NOACCESS, |
5478 |
&spr_read_generic, &spr_write_generic, |
5479 |
0x00000000);
|
5480 |
/* XXX : not implemented (XXX: different from 750fx) */
|
5481 |
spr_register(env, SPR_750FX_HID2, "HID2",
|
5482 |
SPR_NOACCESS, SPR_NOACCESS, |
5483 |
&spr_read_generic, &spr_write_generic, |
5484 |
0x00000000);
|
5485 |
/* Memory management */
|
5486 |
gen_low_BATs(env); |
5487 |
/* PowerPC 750fx & 750gx has 8 DBATs and 8 IBATs */
|
5488 |
gen_high_BATs(env); |
5489 |
init_excp_7x0(env); |
5490 |
env->dcache_line_size = 32;
|
5491 |
env->icache_line_size = 32;
|
5492 |
/* Allocate hardware IRQ controller */
|
5493 |
ppc6xx_irq_init(env); |
5494 |
} |
5495 |
|
5496 |
/* PowerPC 745 */
|
5497 |
#define POWERPC_INSNS_745 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
|
5498 |
PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \ |
5499 |
PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \ |
5500 |
PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \ |
5501 |
PPC_MEM_SYNC | PPC_MEM_EIEIO | \ |
5502 |
PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | \ |
5503 |
PPC_SEGMENT | PPC_EXTERN) |
5504 |
#define POWERPC_INSNS2_745 (PPC_NONE)
|
5505 |
#define POWERPC_MSRM_745 (0x000000000005FF77ULL) |
5506 |
#define POWERPC_MMU_745 (POWERPC_MMU_SOFT_6xx)
|
5507 |
#define POWERPC_EXCP_745 (POWERPC_EXCP_7x5)
|
5508 |
#define POWERPC_INPUT_745 (PPC_FLAGS_INPUT_6xx)
|
5509 |
#define POWERPC_BFDM_745 (bfd_mach_ppc_750)
|
5510 |
#define POWERPC_FLAG_745 (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
|
5511 |
POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK) |
5512 |
#define check_pow_745 check_pow_hid0
|
5513 |
|
5514 |
static void init_proc_745 (CPUPPCState *env) |
5515 |
{ |
5516 |
gen_spr_ne_601(env); |
5517 |
gen_spr_7xx(env); |
5518 |
gen_spr_G2_755(env); |
5519 |
/* Time base */
|
5520 |
gen_tbl(env); |
5521 |
/* Thermal management */
|
5522 |
gen_spr_thrm(env); |
5523 |
/* Hardware implementation registers */
|
5524 |
/* XXX : not implemented */
|
5525 |
spr_register(env, SPR_HID0, "HID0",
|
5526 |
SPR_NOACCESS, SPR_NOACCESS, |
5527 |
&spr_read_generic, &spr_write_generic, |
5528 |
0x00000000);
|
5529 |
/* XXX : not implemented */
|
5530 |
spr_register(env, SPR_HID1, "HID1",
|
5531 |
SPR_NOACCESS, SPR_NOACCESS, |
5532 |
&spr_read_generic, &spr_write_generic, |
5533 |
0x00000000);
|
5534 |
/* XXX : not implemented */
|
5535 |
spr_register(env, SPR_HID2, "HID2",
|
5536 |
SPR_NOACCESS, SPR_NOACCESS, |
5537 |
&spr_read_generic, &spr_write_generic, |
5538 |
0x00000000);
|
5539 |
/* Memory management */
|
5540 |
gen_low_BATs(env); |
5541 |
gen_high_BATs(env); |
5542 |
gen_6xx_7xx_soft_tlb(env, 64, 2); |
5543 |
init_excp_7x5(env); |
5544 |
env->dcache_line_size = 32;
|
5545 |
env->icache_line_size = 32;
|
5546 |
/* Allocate hardware IRQ controller */
|
5547 |
ppc6xx_irq_init(env); |
5548 |
} |
5549 |
|
5550 |
/* PowerPC 755 */
|
5551 |
#define POWERPC_INSNS_755 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
|
5552 |
PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \ |
5553 |
PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \ |
5554 |
PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \ |
5555 |
PPC_MEM_SYNC | PPC_MEM_EIEIO | \ |
5556 |
PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | \ |
5557 |
PPC_SEGMENT | PPC_EXTERN) |
5558 |
#define POWERPC_INSNS2_755 (PPC_NONE)
|
5559 |
#define POWERPC_MSRM_755 (0x000000000005FF77ULL) |
5560 |
#define POWERPC_MMU_755 (POWERPC_MMU_SOFT_6xx)
|
5561 |
#define POWERPC_EXCP_755 (POWERPC_EXCP_7x5)
|
5562 |
#define POWERPC_INPUT_755 (PPC_FLAGS_INPUT_6xx)
|
5563 |
#define POWERPC_BFDM_755 (bfd_mach_ppc_750)
|
5564 |
#define POWERPC_FLAG_755 (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
|
5565 |
POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK) |
5566 |
#define check_pow_755 check_pow_hid0
|
5567 |
|
5568 |
static void init_proc_755 (CPUPPCState *env) |
5569 |
{ |
5570 |
gen_spr_ne_601(env); |
5571 |
gen_spr_7xx(env); |
5572 |
gen_spr_G2_755(env); |
5573 |
/* Time base */
|
5574 |
gen_tbl(env); |
5575 |
/* L2 cache control */
|
5576 |
/* XXX : not implemented */
|
5577 |
spr_register(env, SPR_L2CR, "L2CR",
|
5578 |
SPR_NOACCESS, SPR_NOACCESS, |
5579 |
&spr_read_generic, &spr_write_generic, |
5580 |
0x00000000);
|
5581 |
/* XXX : not implemented */
|
5582 |
spr_register(env, SPR_L2PMCR, "L2PMCR",
|
5583 |
SPR_NOACCESS, SPR_NOACCESS, |
5584 |
&spr_read_generic, &spr_write_generic, |
5585 |
0x00000000);
|
5586 |
/* Thermal management */
|
5587 |
gen_spr_thrm(env); |
5588 |
/* Hardware implementation registers */
|
5589 |
/* XXX : not implemented */
|
5590 |
spr_register(env, SPR_HID0, "HID0",
|
5591 |
SPR_NOACCESS, SPR_NOACCESS, |
5592 |
&spr_read_generic, &spr_write_generic, |
5593 |
0x00000000);
|
5594 |
/* XXX : not implemented */
|
5595 |
spr_register(env, SPR_HID1, "HID1",
|
5596 |
SPR_NOACCESS, SPR_NOACCESS, |
5597 |
&spr_read_generic, &spr_write_generic, |
5598 |
0x00000000);
|
5599 |
/* XXX : not implemented */
|
5600 |
spr_register(env, SPR_HID2, "HID2",
|
5601 |
SPR_NOACCESS, SPR_NOACCESS, |
5602 |
&spr_read_generic, &spr_write_generic, |
5603 |
0x00000000);
|
5604 |
/* Memory management */
|
5605 |
gen_low_BATs(env); |
5606 |
gen_high_BATs(env); |
5607 |
gen_6xx_7xx_soft_tlb(env, 64, 2); |
5608 |
init_excp_7x5(env); |
5609 |
env->dcache_line_size = 32;
|
5610 |
env->icache_line_size = 32;
|
5611 |
/* Allocate hardware IRQ controller */
|
5612 |
ppc6xx_irq_init(env); |
5613 |
} |
5614 |
|
5615 |
/* PowerPC 7400 (aka G4) */
|
5616 |
#define POWERPC_INSNS_7400 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
|
5617 |
PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \ |
5618 |
PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \ |
5619 |
PPC_FLOAT_STFIWX | \ |
5620 |
PPC_CACHE | PPC_CACHE_ICBI | \ |
5621 |
PPC_CACHE_DCBA | PPC_CACHE_DCBZ | \ |
5622 |
PPC_MEM_SYNC | PPC_MEM_EIEIO | \ |
5623 |
PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \ |
5624 |
PPC_MEM_TLBIA | \ |
5625 |
PPC_SEGMENT | PPC_EXTERN | \ |
5626 |
PPC_ALTIVEC) |
5627 |
#define POWERPC_INSNS2_7400 (PPC_NONE)
|
5628 |
#define POWERPC_MSRM_7400 (0x000000000205FF77ULL) |
5629 |
#define POWERPC_MMU_7400 (POWERPC_MMU_32B)
|
5630 |
#define POWERPC_EXCP_7400 (POWERPC_EXCP_74xx)
|
5631 |
#define POWERPC_INPUT_7400 (PPC_FLAGS_INPUT_6xx)
|
5632 |
#define POWERPC_BFDM_7400 (bfd_mach_ppc_7400)
|
5633 |
#define POWERPC_FLAG_7400 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
|
5634 |
POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \ |
5635 |
POWERPC_FLAG_BUS_CLK) |
5636 |
#define check_pow_7400 check_pow_hid0
|
5637 |
|
5638 |
static void init_proc_7400 (CPUPPCState *env) |
5639 |
{ |
5640 |
gen_spr_ne_601(env); |
5641 |
gen_spr_7xx(env); |
5642 |
/* Time base */
|
5643 |
gen_tbl(env); |
5644 |
/* 74xx specific SPR */
|
5645 |
gen_spr_74xx(env); |
5646 |
/* XXX : not implemented */
|
5647 |
spr_register(env, SPR_UBAMR, "UBAMR",
|
5648 |
&spr_read_ureg, SPR_NOACCESS, |
5649 |
&spr_read_ureg, SPR_NOACCESS, |
5650 |
0x00000000);
|
5651 |
/* XXX: this seems not implemented on all revisions. */
|
5652 |
/* XXX : not implemented */
|
5653 |
spr_register(env, SPR_MSSCR1, "MSSCR1",
|
5654 |
SPR_NOACCESS, SPR_NOACCESS, |
5655 |
&spr_read_generic, &spr_write_generic, |
5656 |
0x00000000);
|
5657 |
/* Thermal management */
|
5658 |
gen_spr_thrm(env); |
5659 |
/* Memory management */
|
5660 |
gen_low_BATs(env); |
5661 |
init_excp_7400(env); |
5662 |
env->dcache_line_size = 32;
|
5663 |
env->icache_line_size = 32;
|
5664 |
/* Allocate hardware IRQ controller */
|
5665 |
ppc6xx_irq_init(env); |
5666 |
} |
5667 |
|
5668 |
/* PowerPC 7410 (aka G4) */
|
5669 |
#define POWERPC_INSNS_7410 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
|
5670 |
PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \ |
5671 |
PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \ |
5672 |
PPC_FLOAT_STFIWX | \ |
5673 |
PPC_CACHE | PPC_CACHE_ICBI | \ |
5674 |
PPC_CACHE_DCBA | PPC_CACHE_DCBZ | \ |
5675 |
PPC_MEM_SYNC | PPC_MEM_EIEIO | \ |
5676 |
PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \ |
5677 |
PPC_MEM_TLBIA | \ |
5678 |
PPC_SEGMENT | PPC_EXTERN | \ |
5679 |
PPC_ALTIVEC) |
5680 |
#define POWERPC_INSNS2_7410 (PPC_NONE)
|
5681 |
#define POWERPC_MSRM_7410 (0x000000000205FF77ULL) |
5682 |
#define POWERPC_MMU_7410 (POWERPC_MMU_32B)
|
5683 |
#define POWERPC_EXCP_7410 (POWERPC_EXCP_74xx)
|
5684 |
#define POWERPC_INPUT_7410 (PPC_FLAGS_INPUT_6xx)
|
5685 |
#define POWERPC_BFDM_7410 (bfd_mach_ppc_7400)
|
5686 |
#define POWERPC_FLAG_7410 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
|
5687 |
POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \ |
5688 |
POWERPC_FLAG_BUS_CLK) |
5689 |
#define check_pow_7410 check_pow_hid0
|
5690 |
|
5691 |
static void init_proc_7410 (CPUPPCState *env) |
5692 |
{ |
5693 |
gen_spr_ne_601(env); |
5694 |
gen_spr_7xx(env); |
5695 |
/* Time base */
|
5696 |
gen_tbl(env); |
5697 |
/* 74xx specific SPR */
|
5698 |
gen_spr_74xx(env); |
5699 |
/* XXX : not implemented */
|
5700 |
spr_register(env, SPR_UBAMR, "UBAMR",
|
5701 |
&spr_read_ureg, SPR_NOACCESS, |
5702 |
&spr_read_ureg, SPR_NOACCESS, |
5703 |
0x00000000);
|
5704 |
/* Thermal management */
|
5705 |
gen_spr_thrm(env); |
5706 |
/* L2PMCR */
|
5707 |
/* XXX : not implemented */
|
5708 |
spr_register(env, SPR_L2PMCR, "L2PMCR",
|
5709 |
SPR_NOACCESS, SPR_NOACCESS, |
5710 |
&spr_read_generic, &spr_write_generic, |
5711 |
0x00000000);
|
5712 |
/* LDSTDB */
|
5713 |
/* XXX : not implemented */
|
5714 |
spr_register(env, SPR_LDSTDB, "LDSTDB",
|
5715 |
SPR_NOACCESS, SPR_NOACCESS, |
5716 |
&spr_read_generic, &spr_write_generic, |
5717 |
0x00000000);
|
5718 |
/* Memory management */
|
5719 |
gen_low_BATs(env); |
5720 |
init_excp_7400(env); |
5721 |
env->dcache_line_size = 32;
|
5722 |
env->icache_line_size = 32;
|
5723 |
/* Allocate hardware IRQ controller */
|
5724 |
ppc6xx_irq_init(env); |
5725 |
} |
5726 |
|
5727 |
/* PowerPC 7440 (aka G4) */
|
5728 |
#define POWERPC_INSNS_7440 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
|
5729 |
PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \ |
5730 |
PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \ |
5731 |
PPC_FLOAT_STFIWX | \ |
5732 |
PPC_CACHE | PPC_CACHE_ICBI | \ |
5733 |
PPC_CACHE_DCBA | PPC_CACHE_DCBZ | \ |
5734 |
PPC_MEM_SYNC | PPC_MEM_EIEIO | \ |
5735 |
PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \ |
5736 |
PPC_MEM_TLBIA | PPC_74xx_TLB | \ |
5737 |
PPC_SEGMENT | PPC_EXTERN | \ |
5738 |
PPC_ALTIVEC) |
5739 |
#define POWERPC_INSNS2_7440 (PPC_NONE)
|
5740 |
#define POWERPC_MSRM_7440 (0x000000000205FF77ULL) |
5741 |
#define POWERPC_MMU_7440 (POWERPC_MMU_SOFT_74xx)
|
5742 |
#define POWERPC_EXCP_7440 (POWERPC_EXCP_74xx)
|
5743 |
#define POWERPC_INPUT_7440 (PPC_FLAGS_INPUT_6xx)
|
5744 |
#define POWERPC_BFDM_7440 (bfd_mach_ppc_7400)
|
5745 |
#define POWERPC_FLAG_7440 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
|
5746 |
POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \ |
5747 |
POWERPC_FLAG_BUS_CLK) |
5748 |
#define check_pow_7440 check_pow_hid0_74xx
|
5749 |
|
5750 |
__attribute__ (( unused )) |
5751 |
static void init_proc_7440 (CPUPPCState *env) |
5752 |
{ |
5753 |
gen_spr_ne_601(env); |
5754 |
gen_spr_7xx(env); |
5755 |
/* Time base */
|
5756 |
gen_tbl(env); |
5757 |
/* 74xx specific SPR */
|
5758 |
gen_spr_74xx(env); |
5759 |
/* XXX : not implemented */
|
5760 |
spr_register(env, SPR_UBAMR, "UBAMR",
|
5761 |
&spr_read_ureg, SPR_NOACCESS, |
5762 |
&spr_read_ureg, SPR_NOACCESS, |
5763 |
0x00000000);
|
5764 |
/* LDSTCR */
|
5765 |
/* XXX : not implemented */
|
5766 |
spr_register(env, SPR_LDSTCR, "LDSTCR",
|
5767 |
SPR_NOACCESS, SPR_NOACCESS, |
5768 |
&spr_read_generic, &spr_write_generic, |
5769 |
0x00000000);
|
5770 |
/* ICTRL */
|
5771 |
/* XXX : not implemented */
|
5772 |
spr_register(env, SPR_ICTRL, "ICTRL",
|
5773 |
SPR_NOACCESS, SPR_NOACCESS, |
5774 |
&spr_read_generic, &spr_write_generic, |
5775 |
0x00000000);
|
5776 |
/* MSSSR0 */
|
5777 |
/* XXX : not implemented */
|
5778 |
spr_register(env, SPR_MSSSR0, "MSSSR0",
|
5779 |
SPR_NOACCESS, SPR_NOACCESS, |
5780 |
&spr_read_generic, &spr_write_generic, |
5781 |
0x00000000);
|
5782 |
/* PMC */
|
5783 |
/* XXX : not implemented */
|
5784 |
spr_register(env, SPR_PMC5, "PMC5",
|
5785 |
SPR_NOACCESS, SPR_NOACCESS, |
5786 |
&spr_read_generic, &spr_write_generic, |
5787 |
0x00000000);
|
5788 |
/* XXX : not implemented */
|
5789 |
spr_register(env, SPR_UPMC5, "UPMC5",
|
5790 |
&spr_read_ureg, SPR_NOACCESS, |
5791 |
&spr_read_ureg, SPR_NOACCESS, |
5792 |
0x00000000);
|
5793 |
/* XXX : not implemented */
|
5794 |
spr_register(env, SPR_PMC6, "PMC6",
|
5795 |
SPR_NOACCESS, SPR_NOACCESS, |
5796 |
&spr_read_generic, &spr_write_generic, |
5797 |
0x00000000);
|
5798 |
/* XXX : not implemented */
|
5799 |
spr_register(env, SPR_UPMC6, "UPMC6",
|
5800 |
&spr_read_ureg, SPR_NOACCESS, |
5801 |
&spr_read_ureg, SPR_NOACCESS, |
5802 |
0x00000000);
|
5803 |
/* Memory management */
|
5804 |
gen_low_BATs(env); |
5805 |
gen_74xx_soft_tlb(env, 128, 2); |
5806 |
init_excp_7450(env); |
5807 |
env->dcache_line_size = 32;
|
5808 |
env->icache_line_size = 32;
|
5809 |
/* Allocate hardware IRQ controller */
|
5810 |
ppc6xx_irq_init(env); |
5811 |
} |
5812 |
|
5813 |
/* PowerPC 7450 (aka G4) */
|
5814 |
#define POWERPC_INSNS_7450 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
|
5815 |
PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \ |
5816 |
PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \ |
5817 |
PPC_FLOAT_STFIWX | \ |
5818 |
PPC_CACHE | PPC_CACHE_ICBI | \ |
5819 |
PPC_CACHE_DCBA | PPC_CACHE_DCBZ | \ |
5820 |
PPC_MEM_SYNC | PPC_MEM_EIEIO | \ |
5821 |
PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \ |
5822 |
PPC_MEM_TLBIA | PPC_74xx_TLB | \ |
5823 |
PPC_SEGMENT | PPC_EXTERN | \ |
5824 |
PPC_ALTIVEC) |
5825 |
#define POWERPC_INSNS2_7450 (PPC_NONE)
|
5826 |
#define POWERPC_MSRM_7450 (0x000000000205FF77ULL) |
5827 |
#define POWERPC_MMU_7450 (POWERPC_MMU_SOFT_74xx)
|
5828 |
#define POWERPC_EXCP_7450 (POWERPC_EXCP_74xx)
|
5829 |
#define POWERPC_INPUT_7450 (PPC_FLAGS_INPUT_6xx)
|
5830 |
#define POWERPC_BFDM_7450 (bfd_mach_ppc_7400)
|
5831 |
#define POWERPC_FLAG_7450 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
|
5832 |
POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \ |
5833 |
POWERPC_FLAG_BUS_CLK) |
5834 |
#define check_pow_7450 check_pow_hid0_74xx
|
5835 |
|
5836 |
__attribute__ (( unused )) |
5837 |
static void init_proc_7450 (CPUPPCState *env) |
5838 |
{ |
5839 |
gen_spr_ne_601(env); |
5840 |
gen_spr_7xx(env); |
5841 |
/* Time base */
|
5842 |
gen_tbl(env); |
5843 |
/* 74xx specific SPR */
|
5844 |
gen_spr_74xx(env); |
5845 |
/* Level 3 cache control */
|
5846 |
gen_l3_ctrl(env); |
5847 |
/* L3ITCR1 */
|
5848 |
/* XXX : not implemented */
|
5849 |
spr_register(env, SPR_L3ITCR1, "L3ITCR1",
|
5850 |
SPR_NOACCESS, SPR_NOACCESS, |
5851 |
&spr_read_generic, &spr_write_generic, |
5852 |
0x00000000);
|
5853 |
/* L3ITCR2 */
|
5854 |
/* XXX : not implemented */
|
5855 |
spr_register(env, SPR_L3ITCR2, "L3ITCR2",
|
5856 |
SPR_NOACCESS, SPR_NOACCESS, |
5857 |
&spr_read_generic, &spr_write_generic, |
5858 |
0x00000000);
|
5859 |
/* L3ITCR3 */
|
5860 |
/* XXX : not implemented */
|
5861 |
spr_register(env, SPR_L3ITCR3, "L3ITCR3",
|
5862 |
SPR_NOACCESS, SPR_NOACCESS, |
5863 |
&spr_read_generic, &spr_write_generic, |
5864 |
0x00000000);
|
5865 |
/* L3OHCR */
|
5866 |
/* XXX : not implemented */
|
5867 |
spr_register(env, SPR_L3OHCR, "L3OHCR",
|
5868 |
SPR_NOACCESS, SPR_NOACCESS, |
5869 |
&spr_read_generic, &spr_write_generic, |
5870 |
0x00000000);
|
5871 |
/* XXX : not implemented */
|
5872 |
spr_register(env, SPR_UBAMR, "UBAMR",
|
5873 |
&spr_read_ureg, SPR_NOACCESS, |
5874 |
&spr_read_ureg, SPR_NOACCESS, |
5875 |
0x00000000);
|
5876 |
/* LDSTCR */
|
5877 |
/* XXX : not implemented */
|
5878 |
spr_register(env, SPR_LDSTCR, "LDSTCR",
|
5879 |
SPR_NOACCESS, SPR_NOACCESS, |
5880 |
&spr_read_generic, &spr_write_generic, |
5881 |
0x00000000);
|
5882 |
/* ICTRL */
|
5883 |
/* XXX : not implemented */
|
5884 |
spr_register(env, SPR_ICTRL, "ICTRL",
|
5885 |
SPR_NOACCESS, SPR_NOACCESS, |
5886 |
&spr_read_generic, &spr_write_generic, |
5887 |
0x00000000);
|
5888 |
/* MSSSR0 */
|
5889 |
/* XXX : not implemented */
|
5890 |
spr_register(env, SPR_MSSSR0, "MSSSR0",
|
5891 |
SPR_NOACCESS, SPR_NOACCESS, |
5892 |
&spr_read_generic, &spr_write_generic, |
5893 |
0x00000000);
|
5894 |
/* PMC */
|
5895 |
/* XXX : not implemented */
|
5896 |
spr_register(env, SPR_PMC5, "PMC5",
|
5897 |
SPR_NOACCESS, SPR_NOACCESS, |
5898 |
&spr_read_generic, &spr_write_generic, |
5899 |
0x00000000);
|
5900 |
/* XXX : not implemented */
|
5901 |
spr_register(env, SPR_UPMC5, "UPMC5",
|
5902 |
&spr_read_ureg, SPR_NOACCESS, |
5903 |
&spr_read_ureg, SPR_NOACCESS, |
5904 |
0x00000000);
|
5905 |
/* XXX : not implemented */
|
5906 |
spr_register(env, SPR_PMC6, "PMC6",
|
5907 |
SPR_NOACCESS, SPR_NOACCESS, |
5908 |
&spr_read_generic, &spr_write_generic, |
5909 |
0x00000000);
|
5910 |
/* XXX : not implemented */
|
5911 |
spr_register(env, SPR_UPMC6, "UPMC6",
|
5912 |
&spr_read_ureg, SPR_NOACCESS, |
5913 |
&spr_read_ureg, SPR_NOACCESS, |
5914 |
0x00000000);
|
5915 |
/* Memory management */
|
5916 |
gen_low_BATs(env); |
5917 |
gen_74xx_soft_tlb(env, 128, 2); |
5918 |
init_excp_7450(env); |
5919 |
env->dcache_line_size = 32;
|
5920 |
env->icache_line_size = 32;
|
5921 |
/* Allocate hardware IRQ controller */
|
5922 |
ppc6xx_irq_init(env); |
5923 |
} |
5924 |
|
5925 |
/* PowerPC 7445 (aka G4) */
|
5926 |
#define POWERPC_INSNS_7445 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
|
5927 |
PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \ |
5928 |
PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \ |
5929 |
PPC_FLOAT_STFIWX | \ |
5930 |
PPC_CACHE | PPC_CACHE_ICBI | \ |
5931 |
PPC_CACHE_DCBA | PPC_CACHE_DCBZ | \ |
5932 |
PPC_MEM_SYNC | PPC_MEM_EIEIO | \ |
5933 |
PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \ |
5934 |
PPC_MEM_TLBIA | PPC_74xx_TLB | \ |
5935 |
PPC_SEGMENT | PPC_EXTERN | \ |
5936 |
PPC_ALTIVEC) |
5937 |
#define POWERPC_INSNS2_7445 (PPC_NONE)
|
5938 |
#define POWERPC_MSRM_7445 (0x000000000205FF77ULL) |
5939 |
#define POWERPC_MMU_7445 (POWERPC_MMU_SOFT_74xx)
|
5940 |
#define POWERPC_EXCP_7445 (POWERPC_EXCP_74xx)
|
5941 |
#define POWERPC_INPUT_7445 (PPC_FLAGS_INPUT_6xx)
|
5942 |
#define POWERPC_BFDM_7445 (bfd_mach_ppc_7400)
|
5943 |
#define POWERPC_FLAG_7445 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
|
5944 |
POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \ |
5945 |
POWERPC_FLAG_BUS_CLK) |
5946 |
#define check_pow_7445 check_pow_hid0_74xx
|
5947 |
|
5948 |
__attribute__ (( unused )) |
5949 |
static void init_proc_7445 (CPUPPCState *env) |
5950 |
{ |
5951 |
gen_spr_ne_601(env); |
5952 |
gen_spr_7xx(env); |
5953 |
/* Time base */
|
5954 |
gen_tbl(env); |
5955 |
/* 74xx specific SPR */
|
5956 |
gen_spr_74xx(env); |
5957 |
/* LDSTCR */
|
5958 |
/* XXX : not implemented */
|
5959 |
spr_register(env, SPR_LDSTCR, "LDSTCR",
|
5960 |
SPR_NOACCESS, SPR_NOACCESS, |
5961 |
&spr_read_generic, &spr_write_generic, |
5962 |
0x00000000);
|
5963 |
/* ICTRL */
|
5964 |
/* XXX : not implemented */
|
5965 |
spr_register(env, SPR_ICTRL, "ICTRL",
|
5966 |
SPR_NOACCESS, SPR_NOACCESS, |
5967 |
&spr_read_generic, &spr_write_generic, |
5968 |
0x00000000);
|
5969 |
/* MSSSR0 */
|
5970 |
/* XXX : not implemented */
|
5971 |
spr_register(env, SPR_MSSSR0, "MSSSR0",
|
5972 |
SPR_NOACCESS, SPR_NOACCESS, |
5973 |
&spr_read_generic, &spr_write_generic, |
5974 |
0x00000000);
|
5975 |
/* PMC */
|
5976 |
/* XXX : not implemented */
|
5977 |
spr_register(env, SPR_PMC5, "PMC5",
|
5978 |
SPR_NOACCESS, SPR_NOACCESS, |
5979 |
&spr_read_generic, &spr_write_generic, |
5980 |
0x00000000);
|
5981 |
/* XXX : not implemented */
|
5982 |
spr_register(env, SPR_UPMC5, "UPMC5",
|
5983 |
&spr_read_ureg, SPR_NOACCESS, |
5984 |
&spr_read_ureg, SPR_NOACCESS, |
5985 |
0x00000000);
|
5986 |
/* XXX : not implemented */
|
5987 |
spr_register(env, SPR_PMC6, "PMC6",
|
5988 |
SPR_NOACCESS, SPR_NOACCESS, |
5989 |
&spr_read_generic, &spr_write_generic, |
5990 |
0x00000000);
|
5991 |
/* XXX : not implemented */
|
5992 |
spr_register(env, SPR_UPMC6, "UPMC6",
|
5993 |
&spr_read_ureg, SPR_NOACCESS, |
5994 |
&spr_read_ureg, SPR_NOACCESS, |
5995 |
0x00000000);
|
5996 |
/* SPRGs */
|
5997 |
spr_register(env, SPR_SPRG4, "SPRG4",
|
5998 |
SPR_NOACCESS, SPR_NOACCESS, |
5999 |
&spr_read_generic, &spr_write_generic, |
6000 |
0x00000000);
|
6001 |
spr_register(env, SPR_USPRG4, "USPRG4",
|
6002 |
&spr_read_ureg, SPR_NOACCESS, |
6003 |
&spr_read_ureg, SPR_NOACCESS, |
6004 |
0x00000000);
|
6005 |
spr_register(env, SPR_SPRG5, "SPRG5",
|
6006 |
SPR_NOACCESS, SPR_NOACCESS, |
6007 |
&spr_read_generic, &spr_write_generic, |
6008 |
0x00000000);
|
6009 |
spr_register(env, SPR_USPRG5, "USPRG5",
|
6010 |
&spr_read_ureg, SPR_NOACCESS, |
6011 |
&spr_read_ureg, SPR_NOACCESS, |
6012 |
0x00000000);
|
6013 |
spr_register(env, SPR_SPRG6, "SPRG6",
|
6014 |
SPR_NOACCESS, SPR_NOACCESS, |
6015 |
&spr_read_generic, &spr_write_generic, |
6016 |
0x00000000);
|
6017 |
spr_register(env, SPR_USPRG6, "USPRG6",
|
6018 |
&spr_read_ureg, SPR_NOACCESS, |
6019 |
&spr_read_ureg, SPR_NOACCESS, |
6020 |
0x00000000);
|
6021 |
spr_register(env, SPR_SPRG7, "SPRG7",
|
6022 |
SPR_NOACCESS, SPR_NOACCESS, |
6023 |
&spr_read_generic, &spr_write_generic, |
6024 |
0x00000000);
|
6025 |
spr_register(env, SPR_USPRG7, "USPRG7",
|
6026 |
&spr_read_ureg, SPR_NOACCESS, |
6027 |
&spr_read_ureg, SPR_NOACCESS, |
6028 |
0x00000000);
|
6029 |
/* Memory management */
|
6030 |
gen_low_BATs(env); |
6031 |
gen_high_BATs(env); |
6032 |
gen_74xx_soft_tlb(env, 128, 2); |
6033 |
init_excp_7450(env); |
6034 |
env->dcache_line_size = 32;
|
6035 |
env->icache_line_size = 32;
|
6036 |
/* Allocate hardware IRQ controller */
|
6037 |
ppc6xx_irq_init(env); |
6038 |
} |
6039 |
|
6040 |
/* PowerPC 7455 (aka G4) */
|
6041 |
#define POWERPC_INSNS_7455 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
|
6042 |
PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \ |
6043 |
PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \ |
6044 |
PPC_FLOAT_STFIWX | \ |
6045 |
PPC_CACHE | PPC_CACHE_ICBI | \ |
6046 |
PPC_CACHE_DCBA | PPC_CACHE_DCBZ | \ |
6047 |
PPC_MEM_SYNC | PPC_MEM_EIEIO | \ |
6048 |
PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \ |
6049 |
PPC_MEM_TLBIA | PPC_74xx_TLB | \ |
6050 |
PPC_SEGMENT | PPC_EXTERN | \ |
6051 |
PPC_ALTIVEC) |
6052 |
#define POWERPC_INSNS2_7455 (PPC_NONE)
|
6053 |
#define POWERPC_MSRM_7455 (0x000000000205FF77ULL) |
6054 |
#define POWERPC_MMU_7455 (POWERPC_MMU_SOFT_74xx)
|
6055 |
#define POWERPC_EXCP_7455 (POWERPC_EXCP_74xx)
|
6056 |
#define POWERPC_INPUT_7455 (PPC_FLAGS_INPUT_6xx)
|
6057 |
#define POWERPC_BFDM_7455 (bfd_mach_ppc_7400)
|
6058 |
#define POWERPC_FLAG_7455 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
|
6059 |
POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \ |
6060 |
POWERPC_FLAG_BUS_CLK) |
6061 |
#define check_pow_7455 check_pow_hid0_74xx
|
6062 |
|
6063 |
__attribute__ (( unused )) |
6064 |
static void init_proc_7455 (CPUPPCState *env) |
6065 |
{ |
6066 |
gen_spr_ne_601(env); |
6067 |
gen_spr_7xx(env); |
6068 |
/* Time base */
|
6069 |
gen_tbl(env); |
6070 |
/* 74xx specific SPR */
|
6071 |
gen_spr_74xx(env); |
6072 |
/* Level 3 cache control */
|
6073 |
gen_l3_ctrl(env); |
6074 |
/* LDSTCR */
|
6075 |
/* XXX : not implemented */
|
6076 |
spr_register(env, SPR_LDSTCR, "LDSTCR",
|
6077 |
SPR_NOACCESS, SPR_NOACCESS, |
6078 |
&spr_read_generic, &spr_write_generic, |
6079 |
0x00000000);
|
6080 |
/* ICTRL */
|
6081 |
/* XXX : not implemented */
|
6082 |
spr_register(env, SPR_ICTRL, "ICTRL",
|
6083 |
SPR_NOACCESS, SPR_NOACCESS, |
6084 |
&spr_read_generic, &spr_write_generic, |
6085 |
0x00000000);
|
6086 |
/* MSSSR0 */
|
6087 |
/* XXX : not implemented */
|
6088 |
spr_register(env, SPR_MSSSR0, "MSSSR0",
|
6089 |
SPR_NOACCESS, SPR_NOACCESS, |
6090 |
&spr_read_generic, &spr_write_generic, |
6091 |
0x00000000);
|
6092 |
/* PMC */
|
6093 |
/* XXX : not implemented */
|
6094 |
spr_register(env, SPR_PMC5, "PMC5",
|
6095 |
SPR_NOACCESS, SPR_NOACCESS, |
6096 |
&spr_read_generic, &spr_write_generic, |
6097 |
0x00000000);
|
6098 |
/* XXX : not implemented */
|
6099 |
spr_register(env, SPR_UPMC5, "UPMC5",
|
6100 |
&spr_read_ureg, SPR_NOACCESS, |
6101 |
&spr_read_ureg, SPR_NOACCESS, |
6102 |
0x00000000);
|
6103 |
/* XXX : not implemented */
|
6104 |
spr_register(env, SPR_PMC6, "PMC6",
|
6105 |
SPR_NOACCESS, SPR_NOACCESS, |
6106 |
&spr_read_generic, &spr_write_generic, |
6107 |
0x00000000);
|
6108 |
/* XXX : not implemented */
|
6109 |
spr_register(env, SPR_UPMC6, "UPMC6",
|
6110 |
&spr_read_ureg, SPR_NOACCESS, |
6111 |
&spr_read_ureg, SPR_NOACCESS, |
6112 |
0x00000000);
|
6113 |
/* SPRGs */
|
6114 |
spr_register(env, SPR_SPRG4, "SPRG4",
|
6115 |
SPR_NOACCESS, SPR_NOACCESS, |
6116 |
&spr_read_generic, &spr_write_generic, |
6117 |
0x00000000);
|
6118 |
spr_register(env, SPR_USPRG4, "USPRG4",
|
6119 |
&spr_read_ureg, SPR_NOACCESS, |
6120 |
&spr_read_ureg, SPR_NOACCESS, |
6121 |
0x00000000);
|
6122 |
spr_register(env, SPR_SPRG5, "SPRG5",
|
6123 |
SPR_NOACCESS, SPR_NOACCESS, |
6124 |
&spr_read_generic, &spr_write_generic, |
6125 |
0x00000000);
|
6126 |
spr_register(env, SPR_USPRG5, "USPRG5",
|
6127 |
&spr_read_ureg, SPR_NOACCESS, |
6128 |
&spr_read_ureg, SPR_NOACCESS, |
6129 |
0x00000000);
|
6130 |
spr_register(env, SPR_SPRG6, "SPRG6",
|
6131 |
SPR_NOACCESS, SPR_NOACCESS, |
6132 |
&spr_read_generic, &spr_write_generic, |
6133 |
0x00000000);
|
6134 |
spr_register(env, SPR_USPRG6, "USPRG6",
|
6135 |
&spr_read_ureg, SPR_NOACCESS, |
6136 |
&spr_read_ureg, SPR_NOACCESS, |
6137 |
0x00000000);
|
6138 |
spr_register(env, SPR_SPRG7, "SPRG7",
|
6139 |
SPR_NOACCESS, SPR_NOACCESS, |
6140 |
&spr_read_generic, &spr_write_generic, |
6141 |
0x00000000);
|
6142 |
spr_register(env, SPR_USPRG7, "USPRG7",
|
6143 |
&spr_read_ureg, SPR_NOACCESS, |
6144 |
&spr_read_ureg, SPR_NOACCESS, |
6145 |
0x00000000);
|
6146 |
/* Memory management */
|
6147 |
gen_low_BATs(env); |
6148 |
gen_high_BATs(env); |
6149 |
gen_74xx_soft_tlb(env, 128, 2); |
6150 |
init_excp_7450(env); |
6151 |
env->dcache_line_size = 32;
|
6152 |
env->icache_line_size = 32;
|
6153 |
/* Allocate hardware IRQ controller */
|
6154 |
ppc6xx_irq_init(env); |
6155 |
} |
6156 |
|
6157 |
/* PowerPC 7457 (aka G4) */
|
6158 |
#define POWERPC_INSNS_7457 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
|
6159 |
PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \ |
6160 |
PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \ |
6161 |
PPC_FLOAT_STFIWX | \ |
6162 |
PPC_CACHE | PPC_CACHE_ICBI | \ |
6163 |
PPC_CACHE_DCBA | PPC_CACHE_DCBZ | \ |
6164 |
PPC_MEM_SYNC | PPC_MEM_EIEIO | \ |
6165 |
PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \ |
6166 |
PPC_MEM_TLBIA | PPC_74xx_TLB | \ |
6167 |
PPC_SEGMENT | PPC_EXTERN | \ |
6168 |
PPC_ALTIVEC) |
6169 |
#define POWERPC_INSNS2_7457 (PPC_NONE)
|
6170 |
#define POWERPC_MSRM_7457 (0x000000000205FF77ULL) |
6171 |
#define POWERPC_MMU_7457 (POWERPC_MMU_SOFT_74xx)
|
6172 |
#define POWERPC_EXCP_7457 (POWERPC_EXCP_74xx)
|
6173 |
#define POWERPC_INPUT_7457 (PPC_FLAGS_INPUT_6xx)
|
6174 |
#define POWERPC_BFDM_7457 (bfd_mach_ppc_7400)
|
6175 |
#define POWERPC_FLAG_7457 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
|
6176 |
POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \ |
6177 |
POWERPC_FLAG_BUS_CLK) |
6178 |
#define check_pow_7457 check_pow_hid0_74xx
|
6179 |
|
6180 |
__attribute__ (( unused )) |
6181 |
static void init_proc_7457 (CPUPPCState *env) |
6182 |
{ |
6183 |
gen_spr_ne_601(env); |
6184 |
gen_spr_7xx(env); |
6185 |
/* Time base */
|
6186 |
gen_tbl(env); |
6187 |
/* 74xx specific SPR */
|
6188 |
gen_spr_74xx(env); |
6189 |
/* Level 3 cache control */
|
6190 |
gen_l3_ctrl(env); |
6191 |
/* L3ITCR1 */
|
6192 |
/* XXX : not implemented */
|
6193 |
spr_register(env, SPR_L3ITCR1, "L3ITCR1",
|
6194 |
SPR_NOACCESS, SPR_NOACCESS, |
6195 |
&spr_read_generic, &spr_write_generic, |
6196 |
0x00000000);
|
6197 |
/* L3ITCR2 */
|
6198 |
/* XXX : not implemented */
|
6199 |
spr_register(env, SPR_L3ITCR2, "L3ITCR2",
|
6200 |
SPR_NOACCESS, SPR_NOACCESS, |
6201 |
&spr_read_generic, &spr_write_generic, |
6202 |
0x00000000);
|
6203 |
/* L3ITCR3 */
|
6204 |
/* XXX : not implemented */
|
6205 |
spr_register(env, SPR_L3ITCR3, "L3ITCR3",
|
6206 |
SPR_NOACCESS, SPR_NOACCESS, |
6207 |
&spr_read_generic, &spr_write_generic, |
6208 |
0x00000000);
|
6209 |
/* L3OHCR */
|
6210 |
/* XXX : not implemented */
|
6211 |
spr_register(env, SPR_L3OHCR, "L3OHCR",
|
6212 |
SPR_NOACCESS, SPR_NOACCESS, |
6213 |
&spr_read_generic, &spr_write_generic, |
6214 |
0x00000000);
|
6215 |
/* LDSTCR */
|
6216 |
/* XXX : not implemented */
|
6217 |
spr_register(env, SPR_LDSTCR, "LDSTCR",
|
6218 |
SPR_NOACCESS, SPR_NOACCESS, |
6219 |
&spr_read_generic, &spr_write_generic, |
6220 |
0x00000000);
|
6221 |
/* ICTRL */
|
6222 |
/* XXX : not implemented */
|
6223 |
spr_register(env, SPR_ICTRL, "ICTRL",
|
6224 |
SPR_NOACCESS, SPR_NOACCESS, |
6225 |
&spr_read_generic, &spr_write_generic, |
6226 |
0x00000000);
|
6227 |
/* MSSSR0 */
|
6228 |
/* XXX : not implemented */
|
6229 |
spr_register(env, SPR_MSSSR0, "MSSSR0",
|
6230 |
SPR_NOACCESS, SPR_NOACCESS, |
6231 |
&spr_read_generic, &spr_write_generic, |
6232 |
0x00000000);
|
6233 |
/* PMC */
|
6234 |
/* XXX : not implemented */
|
6235 |
spr_register(env, SPR_PMC5, "PMC5",
|
6236 |
SPR_NOACCESS, SPR_NOACCESS, |
6237 |
&spr_read_generic, &spr_write_generic, |
6238 |
0x00000000);
|
6239 |
/* XXX : not implemented */
|
6240 |
spr_register(env, SPR_UPMC5, "UPMC5",
|
6241 |
&spr_read_ureg, SPR_NOACCESS, |
6242 |
&spr_read_ureg, SPR_NOACCESS, |
6243 |
0x00000000);
|
6244 |
/* XXX : not implemented */
|
6245 |
spr_register(env, SPR_PMC6, "PMC6",
|
6246 |
SPR_NOACCESS, SPR_NOACCESS, |
6247 |
&spr_read_generic, &spr_write_generic, |
6248 |
0x00000000);
|
6249 |
/* XXX : not implemented */
|
6250 |
spr_register(env, SPR_UPMC6, "UPMC6",
|
6251 |
&spr_read_ureg, SPR_NOACCESS, |
6252 |
&spr_read_ureg, SPR_NOACCESS, |
6253 |
0x00000000);
|
6254 |
/* SPRGs */
|
6255 |
spr_register(env, SPR_SPRG4, "SPRG4",
|
6256 |
SPR_NOACCESS, SPR_NOACCESS, |
6257 |
&spr_read_generic, &spr_write_generic, |
6258 |
0x00000000);
|
6259 |
spr_register(env, SPR_USPRG4, "USPRG4",
|
6260 |
&spr_read_ureg, SPR_NOACCESS, |
6261 |
&spr_read_ureg, SPR_NOACCESS, |
6262 |
0x00000000);
|
6263 |
spr_register(env, SPR_SPRG5, "SPRG5",
|
6264 |
SPR_NOACCESS, SPR_NOACCESS, |
6265 |
&spr_read_generic, &spr_write_generic, |
6266 |
0x00000000);
|
6267 |
spr_register(env, SPR_USPRG5, "USPRG5",
|
6268 |
&spr_read_ureg, SPR_NOACCESS, |
6269 |
&spr_read_ureg, SPR_NOACCESS, |
6270 |
0x00000000);
|
6271 |
spr_register(env, SPR_SPRG6, "SPRG6",
|
6272 |
SPR_NOACCESS, SPR_NOACCESS, |
6273 |
&spr_read_generic, &spr_write_generic, |
6274 |
0x00000000);
|
6275 |
spr_register(env, SPR_USPRG6, "USPRG6",
|
6276 |
&spr_read_ureg, SPR_NOACCESS, |
6277 |
&spr_read_ureg, SPR_NOACCESS, |
6278 |
0x00000000);
|
6279 |
spr_register(env, SPR_SPRG7, "SPRG7",
|
6280 |
SPR_NOACCESS, SPR_NOACCESS, |
6281 |
&spr_read_generic, &spr_write_generic, |
6282 |
0x00000000);
|
6283 |
spr_register(env, SPR_USPRG7, "USPRG7",
|
6284 |
&spr_read_ureg, SPR_NOACCESS, |
6285 |
&spr_read_ureg, SPR_NOACCESS, |
6286 |
0x00000000);
|
6287 |
/* Memory management */
|
6288 |
gen_low_BATs(env); |
6289 |
gen_high_BATs(env); |
6290 |
gen_74xx_soft_tlb(env, 128, 2); |
6291 |
init_excp_7450(env); |
6292 |
env->dcache_line_size = 32;
|
6293 |
env->icache_line_size = 32;
|
6294 |
/* Allocate hardware IRQ controller */
|
6295 |
ppc6xx_irq_init(env); |
6296 |
} |
6297 |
|
6298 |
#if defined (TARGET_PPC64)
|
6299 |
/* PowerPC 970 */
|
6300 |
#define POWERPC_INSNS_970 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
|
6301 |
PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \ |
6302 |
PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \ |
6303 |
PPC_FLOAT_STFIWX | \ |
6304 |
PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZT | \ |
6305 |
PPC_MEM_SYNC | PPC_MEM_EIEIO | \ |
6306 |
PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \ |
6307 |
PPC_64B | PPC_ALTIVEC | \ |
6308 |
PPC_SEGMENT_64B | PPC_SLBI) |
6309 |
#define POWERPC_INSNS2_970 (PPC_NONE)
|
6310 |
#define POWERPC_MSRM_970 (0x900000000204FF36ULL) |
6311 |
#define POWERPC_MMU_970 (POWERPC_MMU_64B)
|
6312 |
//#define POWERPC_EXCP_970 (POWERPC_EXCP_970)
|
6313 |
#define POWERPC_INPUT_970 (PPC_FLAGS_INPUT_970)
|
6314 |
#define POWERPC_BFDM_970 (bfd_mach_ppc64)
|
6315 |
#define POWERPC_FLAG_970 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
|
6316 |
POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \ |
6317 |
POWERPC_FLAG_BUS_CLK) |
6318 |
|
6319 |
#if defined(CONFIG_USER_ONLY)
|
6320 |
#define POWERPC970_HID5_INIT 0x00000080 |
6321 |
#else
|
6322 |
#define POWERPC970_HID5_INIT 0x00000000 |
6323 |
#endif
|
6324 |
|
6325 |
static int check_pow_970 (CPUPPCState *env) |
6326 |
{ |
6327 |
if (env->spr[SPR_HID0] & 0x00600000) |
6328 |
return 1; |
6329 |
|
6330 |
return 0; |
6331 |
} |
6332 |
|
6333 |
static void init_proc_970 (CPUPPCState *env) |
6334 |
{ |
6335 |
gen_spr_ne_601(env); |
6336 |
gen_spr_7xx(env); |
6337 |
/* Time base */
|
6338 |
gen_tbl(env); |
6339 |
/* Hardware implementation registers */
|
6340 |
/* XXX : not implemented */
|
6341 |
spr_register(env, SPR_HID0, "HID0",
|
6342 |
SPR_NOACCESS, SPR_NOACCESS, |
6343 |
&spr_read_generic, &spr_write_clear, |
6344 |
0x60000000);
|
6345 |
/* XXX : not implemented */
|
6346 |
spr_register(env, SPR_HID1, "HID1",
|
6347 |
SPR_NOACCESS, SPR_NOACCESS, |
6348 |
&spr_read_generic, &spr_write_generic, |
6349 |
0x00000000);
|
6350 |
/* XXX : not implemented */
|
6351 |
spr_register(env, SPR_750FX_HID2, "HID2",
|
6352 |
SPR_NOACCESS, SPR_NOACCESS, |
6353 |
&spr_read_generic, &spr_write_generic, |
6354 |
0x00000000);
|
6355 |
/* XXX : not implemented */
|
6356 |
spr_register(env, SPR_970_HID5, "HID5",
|
6357 |
SPR_NOACCESS, SPR_NOACCESS, |
6358 |
&spr_read_generic, &spr_write_generic, |
6359 |
POWERPC970_HID5_INIT); |
6360 |
/* XXX : not implemented */
|
6361 |
spr_register(env, SPR_L2CR, "L2CR",
|
6362 |
SPR_NOACCESS, SPR_NOACCESS, |
6363 |
&spr_read_generic, &spr_write_generic, |
6364 |
0x00000000);
|
6365 |
/* Memory management */
|
6366 |
/* XXX: not correct */
|
6367 |
gen_low_BATs(env); |
6368 |
/* XXX : not implemented */
|
6369 |
spr_register(env, SPR_MMUCFG, "MMUCFG",
|
6370 |
SPR_NOACCESS, SPR_NOACCESS, |
6371 |
&spr_read_generic, SPR_NOACCESS, |
6372 |
0x00000000); /* TOFIX */ |
6373 |
/* XXX : not implemented */
|
6374 |
spr_register(env, SPR_MMUCSR0, "MMUCSR0",
|
6375 |
SPR_NOACCESS, SPR_NOACCESS, |
6376 |
&spr_read_generic, &spr_write_generic, |
6377 |
0x00000000); /* TOFIX */ |
6378 |
spr_register(env, SPR_HIOR, "SPR_HIOR",
|
6379 |
SPR_NOACCESS, SPR_NOACCESS, |
6380 |
&spr_read_hior, &spr_write_hior, |
6381 |
0x00000000);
|
6382 |
#if !defined(CONFIG_USER_ONLY)
|
6383 |
env->slb_nr = 32;
|
6384 |
#endif
|
6385 |
init_excp_970(env); |
6386 |
env->dcache_line_size = 128;
|
6387 |
env->icache_line_size = 128;
|
6388 |
/* Allocate hardware IRQ controller */
|
6389 |
ppc970_irq_init(env); |
6390 |
/* Can't find information on what this should be on reset. This
|
6391 |
* value is the one used by 74xx processors. */
|
6392 |
vscr_init(env, 0x00010000);
|
6393 |
} |
6394 |
|
6395 |
/* PowerPC 970FX (aka G5) */
|
6396 |
#define POWERPC_INSNS_970FX (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
|
6397 |
PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \ |
6398 |
PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \ |
6399 |
PPC_FLOAT_STFIWX | \ |
6400 |
PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZT | \ |
6401 |
PPC_MEM_SYNC | PPC_MEM_EIEIO | \ |
6402 |
PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \ |
6403 |
PPC_64B | PPC_ALTIVEC | \ |
6404 |
PPC_SEGMENT_64B | PPC_SLBI) |
6405 |
#define POWERPC_INSNS2_970FX (PPC_NONE)
|
6406 |
#define POWERPC_MSRM_970FX (0x800000000204FF36ULL) |
6407 |
#define POWERPC_MMU_970FX (POWERPC_MMU_64B)
|
6408 |
#define POWERPC_EXCP_970FX (POWERPC_EXCP_970)
|
6409 |
#define POWERPC_INPUT_970FX (PPC_FLAGS_INPUT_970)
|
6410 |
#define POWERPC_BFDM_970FX (bfd_mach_ppc64)
|
6411 |
#define POWERPC_FLAG_970FX (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
|
6412 |
POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \ |
6413 |
POWERPC_FLAG_BUS_CLK) |
6414 |
|
6415 |
static int check_pow_970FX (CPUPPCState *env) |
6416 |
{ |
6417 |
if (env->spr[SPR_HID0] & 0x00600000) |
6418 |
return 1; |
6419 |
|
6420 |
return 0; |
6421 |
} |
6422 |
|
6423 |
static void init_proc_970FX (CPUPPCState *env) |
6424 |
{ |
6425 |
gen_spr_ne_601(env); |
6426 |
gen_spr_7xx(env); |
6427 |
/* Time base */
|
6428 |
gen_tbl(env); |
6429 |
/* Hardware implementation registers */
|
6430 |
/* XXX : not implemented */
|
6431 |
spr_register(env, SPR_HID0, "HID0",
|
6432 |
SPR_NOACCESS, SPR_NOACCESS, |
6433 |
&spr_read_generic, &spr_write_clear, |
6434 |
0x60000000);
|
6435 |
/* XXX : not implemented */
|
6436 |
spr_register(env, SPR_HID1, "HID1",
|
6437 |
SPR_NOACCESS, SPR_NOACCESS, |
6438 |
&spr_read_generic, &spr_write_generic, |
6439 |
0x00000000);
|
6440 |
/* XXX : not implemented */
|
6441 |
spr_register(env, SPR_750FX_HID2, "HID2",
|
6442 |
SPR_NOACCESS, SPR_NOACCESS, |
6443 |
&spr_read_generic, &spr_write_generic, |
6444 |
0x00000000);
|
6445 |
/* XXX : not implemented */
|
6446 |
spr_register(env, SPR_970_HID5, "HID5",
|
6447 |
SPR_NOACCESS, SPR_NOACCESS, |
6448 |
&spr_read_generic, &spr_write_generic, |
6449 |
POWERPC970_HID5_INIT); |
6450 |
/* XXX : not implemented */
|
6451 |
spr_register(env, SPR_L2CR, "L2CR",
|
6452 |
SPR_NOACCESS, SPR_NOACCESS, |
6453 |
&spr_read_generic, &spr_write_generic, |
6454 |
0x00000000);
|
6455 |
/* Memory management */
|
6456 |
/* XXX: not correct */
|
6457 |
gen_low_BATs(env); |
6458 |
/* XXX : not implemented */
|
6459 |
spr_register(env, SPR_MMUCFG, "MMUCFG",
|
6460 |
SPR_NOACCESS, SPR_NOACCESS, |
6461 |
&spr_read_generic, SPR_NOACCESS, |
6462 |
0x00000000); /* TOFIX */ |
6463 |
/* XXX : not implemented */
|
6464 |
spr_register(env, SPR_MMUCSR0, "MMUCSR0",
|
6465 |
SPR_NOACCESS, SPR_NOACCESS, |
6466 |
&spr_read_generic, &spr_write_generic, |
6467 |
0x00000000); /* TOFIX */ |
6468 |
spr_register(env, SPR_HIOR, "SPR_HIOR",
|
6469 |
SPR_NOACCESS, SPR_NOACCESS, |
6470 |
&spr_read_hior, &spr_write_hior, |
6471 |
0x00000000);
|
6472 |
spr_register(env, SPR_CTRL, "SPR_CTRL",
|
6473 |
SPR_NOACCESS, SPR_NOACCESS, |
6474 |
&spr_read_generic, &spr_write_generic, |
6475 |
0x00000000);
|
6476 |
spr_register(env, SPR_UCTRL, "SPR_UCTRL",
|
6477 |
SPR_NOACCESS, SPR_NOACCESS, |
6478 |
&spr_read_generic, &spr_write_generic, |
6479 |
0x00000000);
|
6480 |
spr_register(env, SPR_VRSAVE, "SPR_VRSAVE",
|
6481 |
&spr_read_generic, &spr_write_generic, |
6482 |
&spr_read_generic, &spr_write_generic, |
6483 |
0x00000000);
|
6484 |
#if !defined(CONFIG_USER_ONLY)
|
6485 |
env->slb_nr = 64;
|
6486 |
#endif
|
6487 |
init_excp_970(env); |
6488 |
env->dcache_line_size = 128;
|
6489 |
env->icache_line_size = 128;
|
6490 |
/* Allocate hardware IRQ controller */
|
6491 |
ppc970_irq_init(env); |
6492 |
/* Can't find information on what this should be on reset. This
|
6493 |
* value is the one used by 74xx processors. */
|
6494 |
vscr_init(env, 0x00010000);
|
6495 |
} |
6496 |
|
6497 |
/* PowerPC 970 GX */
|
6498 |
#define POWERPC_INSNS_970GX (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
|
6499 |
PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \ |
6500 |
PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \ |
6501 |
PPC_FLOAT_STFIWX | \ |
6502 |
PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZT | \ |
6503 |
PPC_MEM_SYNC | PPC_MEM_EIEIO | \ |
6504 |
PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \ |
6505 |
PPC_64B | PPC_ALTIVEC | \ |
6506 |
PPC_SEGMENT_64B | PPC_SLBI) |
6507 |
#define POWERPC_INSNS2_970GX (PPC_NONE)
|
6508 |
#define POWERPC_MSRM_970GX (0x800000000204FF36ULL) |
6509 |
#define POWERPC_MMU_970GX (POWERPC_MMU_64B)
|
6510 |
#define POWERPC_EXCP_970GX (POWERPC_EXCP_970)
|
6511 |
#define POWERPC_INPUT_970GX (PPC_FLAGS_INPUT_970)
|
6512 |
#define POWERPC_BFDM_970GX (bfd_mach_ppc64)
|
6513 |
#define POWERPC_FLAG_970GX (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
|
6514 |
POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \ |
6515 |
POWERPC_FLAG_BUS_CLK) |
6516 |
|
6517 |
static int check_pow_970GX (CPUPPCState *env) |
6518 |
{ |
6519 |
if (env->spr[SPR_HID0] & 0x00600000) |
6520 |
return 1; |
6521 |
|
6522 |
return 0; |
6523 |
} |
6524 |
|
6525 |
static void init_proc_970GX (CPUPPCState *env) |
6526 |
{ |
6527 |
gen_spr_ne_601(env); |
6528 |
gen_spr_7xx(env); |
6529 |
/* Time base */
|
6530 |
gen_tbl(env); |
6531 |
/* Hardware implementation registers */
|
6532 |
/* XXX : not implemented */
|
6533 |
spr_register(env, SPR_HID0, "HID0",
|
6534 |
SPR_NOACCESS, SPR_NOACCESS, |
6535 |
&spr_read_generic, &spr_write_clear, |
6536 |
0x60000000);
|
6537 |
/* XXX : not implemented */
|
6538 |
spr_register(env, SPR_HID1, "HID1",
|
6539 |
SPR_NOACCESS, SPR_NOACCESS, |
6540 |
&spr_read_generic, &spr_write_generic, |
6541 |
0x00000000);
|
6542 |
/* XXX : not implemented */
|
6543 |
spr_register(env, SPR_750FX_HID2, "HID2",
|
6544 |
SPR_NOACCESS, SPR_NOACCESS, |
6545 |
&spr_read_generic, &spr_write_generic, |
6546 |
0x00000000);
|
6547 |
/* XXX : not implemented */
|
6548 |
spr_register(env, SPR_970_HID5, "HID5",
|
6549 |
SPR_NOACCESS, SPR_NOACCESS, |
6550 |
&spr_read_generic, &spr_write_generic, |
6551 |
POWERPC970_HID5_INIT); |
6552 |
/* XXX : not implemented */
|
6553 |
spr_register(env, SPR_L2CR, "L2CR",
|
6554 |
SPR_NOACCESS, SPR_NOACCESS, |
6555 |
&spr_read_generic, &spr_write_generic, |
6556 |
0x00000000);
|
6557 |
/* Memory management */
|
6558 |
/* XXX: not correct */
|
6559 |
gen_low_BATs(env); |
6560 |
/* XXX : not implemented */
|
6561 |
spr_register(env, SPR_MMUCFG, "MMUCFG",
|
6562 |
SPR_NOACCESS, SPR_NOACCESS, |
6563 |
&spr_read_generic, SPR_NOACCESS, |
6564 |
0x00000000); /* TOFIX */ |
6565 |
/* XXX : not implemented */
|
6566 |
spr_register(env, SPR_MMUCSR0, "MMUCSR0",
|
6567 |
SPR_NOACCESS, SPR_NOACCESS, |
6568 |
&spr_read_generic, &spr_write_generic, |
6569 |
0x00000000); /* TOFIX */ |
6570 |
spr_register(env, SPR_HIOR, "SPR_HIOR",
|
6571 |
SPR_NOACCESS, SPR_NOACCESS, |
6572 |
&spr_read_hior, &spr_write_hior, |
6573 |
0x00000000);
|
6574 |
#if !defined(CONFIG_USER_ONLY)
|
6575 |
env->slb_nr = 32;
|
6576 |
#endif
|
6577 |
init_excp_970(env); |
6578 |
env->dcache_line_size = 128;
|
6579 |
env->icache_line_size = 128;
|
6580 |
/* Allocate hardware IRQ controller */
|
6581 |
ppc970_irq_init(env); |
6582 |
/* Can't find information on what this should be on reset. This
|
6583 |
* value is the one used by 74xx processors. */
|
6584 |
vscr_init(env, 0x00010000);
|
6585 |
} |
6586 |
|
6587 |
/* PowerPC 970 MP */
|
6588 |
#define POWERPC_INSNS_970MP (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
|
6589 |
PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \ |
6590 |
PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \ |
6591 |
PPC_FLOAT_STFIWX | \ |
6592 |
PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZT | \ |
6593 |
PPC_MEM_SYNC | PPC_MEM_EIEIO | \ |
6594 |
PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \ |
6595 |
PPC_64B | PPC_ALTIVEC | \ |
6596 |
PPC_SEGMENT_64B | PPC_SLBI) |
6597 |
#define POWERPC_INSNS2_970MP (PPC_NONE)
|
6598 |
#define POWERPC_MSRM_970MP (0x900000000204FF36ULL) |
6599 |
#define POWERPC_MMU_970MP (POWERPC_MMU_64B)
|
6600 |
#define POWERPC_EXCP_970MP (POWERPC_EXCP_970)
|
6601 |
#define POWERPC_INPUT_970MP (PPC_FLAGS_INPUT_970)
|
6602 |
#define POWERPC_BFDM_970MP (bfd_mach_ppc64)
|
6603 |
#define POWERPC_FLAG_970MP (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
|
6604 |
POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \ |
6605 |
POWERPC_FLAG_BUS_CLK) |
6606 |
|
6607 |
static int check_pow_970MP (CPUPPCState *env) |
6608 |
{ |
6609 |
if (env->spr[SPR_HID0] & 0x01C00000) |
6610 |
return 1; |
6611 |
|
6612 |
return 0; |
6613 |
} |
6614 |
|
6615 |
static void init_proc_970MP (CPUPPCState *env) |
6616 |
{ |
6617 |
gen_spr_ne_601(env); |
6618 |
gen_spr_7xx(env); |
6619 |
/* Time base */
|
6620 |
gen_tbl(env); |
6621 |
/* Hardware implementation registers */
|
6622 |
/* XXX : not implemented */
|
6623 |
spr_register(env, SPR_HID0, "HID0",
|
6624 |
SPR_NOACCESS, SPR_NOACCESS, |
6625 |
&spr_read_generic, &spr_write_clear, |
6626 |
0x60000000);
|
6627 |
/* XXX : not implemented */
|
6628 |
spr_register(env, SPR_HID1, "HID1",
|
6629 |
SPR_NOACCESS, SPR_NOACCESS, |
6630 |
&spr_read_generic, &spr_write_generic, |
6631 |
0x00000000);
|
6632 |
/* XXX : not implemented */
|
6633 |
spr_register(env, SPR_750FX_HID2, "HID2",
|
6634 |
SPR_NOACCESS, SPR_NOACCESS, |
6635 |
&spr_read_generic, &spr_write_generic, |
6636 |
0x00000000);
|
6637 |
/* XXX : not implemented */
|
6638 |
spr_register(env, SPR_970_HID5, "HID5",
|
6639 |
SPR_NOACCESS, SPR_NOACCESS, |
6640 |
&spr_read_generic, &spr_write_generic, |
6641 |
POWERPC970_HID5_INIT); |
6642 |
/* XXX : not implemented */
|
6643 |
spr_register(env, SPR_L2CR, "L2CR",
|
6644 |
SPR_NOACCESS, SPR_NOACCESS, |
6645 |
&spr_read_generic, &spr_write_generic, |
6646 |
0x00000000);
|
6647 |
/* Memory management */
|
6648 |
/* XXX: not correct */
|
6649 |
gen_low_BATs(env); |
6650 |
/* XXX : not implemented */
|
6651 |
spr_register(env, SPR_MMUCFG, "MMUCFG",
|
6652 |
SPR_NOACCESS, SPR_NOACCESS, |
6653 |
&spr_read_generic, SPR_NOACCESS, |
6654 |
0x00000000); /* TOFIX */ |
6655 |
/* XXX : not implemented */
|
6656 |
spr_register(env, SPR_MMUCSR0, "MMUCSR0",
|
6657 |
SPR_NOACCESS, SPR_NOACCESS, |
6658 |
&spr_read_generic, &spr_write_generic, |
6659 |
0x00000000); /* TOFIX */ |
6660 |
spr_register(env, SPR_HIOR, "SPR_HIOR",
|
6661 |
SPR_NOACCESS, SPR_NOACCESS, |
6662 |
&spr_read_hior, &spr_write_hior, |
6663 |
0x00000000);
|
6664 |
#if !defined(CONFIG_USER_ONLY)
|
6665 |
env->slb_nr = 32;
|
6666 |
#endif
|
6667 |
init_excp_970(env); |
6668 |
env->dcache_line_size = 128;
|
6669 |
env->icache_line_size = 128;
|
6670 |
/* Allocate hardware IRQ controller */
|
6671 |
ppc970_irq_init(env); |
6672 |
/* Can't find information on what this should be on reset. This
|
6673 |
* value is the one used by 74xx processors. */
|
6674 |
vscr_init(env, 0x00010000);
|
6675 |
} |
6676 |
|
6677 |
#if defined(TARGET_PPC64)
|
6678 |
/* POWER7 */
|
6679 |
#define POWERPC_INSNS_POWER7 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
|
6680 |
PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \ |
6681 |
PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \ |
6682 |
PPC_FLOAT_STFIWX | \ |
6683 |
PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZT | \ |
6684 |
PPC_MEM_SYNC | PPC_MEM_EIEIO | \ |
6685 |
PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \ |
6686 |
PPC_64B | PPC_ALTIVEC | \ |
6687 |
PPC_SEGMENT_64B | PPC_SLBI | \ |
6688 |
PPC_POPCNTB | PPC_POPCNTWD) |
6689 |
#define POWERPC_INSNS2_POWER7 (PPC2_VSX | PPC2_DFP | PPC2_DBRX)
|
6690 |
#define POWERPC_MSRM_POWER7 (0x800000000204FF36ULL) |
6691 |
#define POWERPC_MMU_POWER7 (POWERPC_MMU_2_06)
|
6692 |
#define POWERPC_EXCP_POWER7 (POWERPC_EXCP_POWER7)
|
6693 |
#define POWERPC_INPUT_POWER7 (PPC_FLAGS_INPUT_POWER7)
|
6694 |
#define POWERPC_BFDM_POWER7 (bfd_mach_ppc64)
|
6695 |
#define POWERPC_FLAG_POWER7 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
|
6696 |
POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \ |
6697 |
POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_CFAR) |
6698 |
#define check_pow_POWER7 check_pow_nocheck
|
6699 |
|
6700 |
static void init_proc_POWER7 (CPUPPCState *env) |
6701 |
{ |
6702 |
gen_spr_ne_601(env); |
6703 |
gen_spr_7xx(env); |
6704 |
/* Time base */
|
6705 |
gen_tbl(env); |
6706 |
/* Processor identification */
|
6707 |
spr_register(env, SPR_PIR, "PIR",
|
6708 |
SPR_NOACCESS, SPR_NOACCESS, |
6709 |
&spr_read_generic, &spr_write_pir, |
6710 |
0x00000000);
|
6711 |
#if !defined(CONFIG_USER_ONLY)
|
6712 |
/* PURR & SPURR: Hack - treat these as aliases for the TB for now */
|
6713 |
spr_register(env, SPR_PURR, "PURR",
|
6714 |
&spr_read_purr, SPR_NOACCESS, |
6715 |
&spr_read_purr, SPR_NOACCESS, |
6716 |
0x00000000);
|
6717 |
spr_register(env, SPR_SPURR, "SPURR",
|
6718 |
&spr_read_purr, SPR_NOACCESS, |
6719 |
&spr_read_purr, SPR_NOACCESS, |
6720 |
0x00000000);
|
6721 |
spr_register(env, SPR_CFAR, "SPR_CFAR",
|
6722 |
SPR_NOACCESS, SPR_NOACCESS, |
6723 |
&spr_read_cfar, &spr_write_cfar, |
6724 |
0x00000000);
|
6725 |
spr_register(env, SPR_DSCR, "SPR_DSCR",
|
6726 |
SPR_NOACCESS, SPR_NOACCESS, |
6727 |
&spr_read_generic, &spr_write_generic, |
6728 |
0x00000000);
|
6729 |
#endif /* !CONFIG_USER_ONLY */ |
6730 |
/* Memory management */
|
6731 |
/* XXX : not implemented */
|
6732 |
spr_register(env, SPR_MMUCFG, "MMUCFG",
|
6733 |
SPR_NOACCESS, SPR_NOACCESS, |
6734 |
&spr_read_generic, SPR_NOACCESS, |
6735 |
0x00000000); /* TOFIX */ |
6736 |
/* XXX : not implemented */
|
6737 |
spr_register(env, SPR_CTRL, "SPR_CTRLT",
|
6738 |
SPR_NOACCESS, SPR_NOACCESS, |
6739 |
&spr_read_generic, &spr_write_generic, |
6740 |
0x80800000);
|
6741 |
spr_register(env, SPR_UCTRL, "SPR_CTRLF",
|
6742 |
SPR_NOACCESS, SPR_NOACCESS, |
6743 |
&spr_read_generic, &spr_write_generic, |
6744 |
0x80800000);
|
6745 |
spr_register(env, SPR_VRSAVE, "SPR_VRSAVE",
|
6746 |
&spr_read_generic, &spr_write_generic, |
6747 |
&spr_read_generic, &spr_write_generic, |
6748 |
0x00000000);
|
6749 |
#if !defined(CONFIG_USER_ONLY)
|
6750 |
env->slb_nr = 32;
|
6751 |
#endif
|
6752 |
init_excp_POWER7(env); |
6753 |
env->dcache_line_size = 128;
|
6754 |
env->icache_line_size = 128;
|
6755 |
/* Allocate hardware IRQ controller */
|
6756 |
ppcPOWER7_irq_init(env); |
6757 |
/* Can't find information on what this should be on reset. This
|
6758 |
* value is the one used by 74xx processors. */
|
6759 |
vscr_init(env, 0x00010000);
|
6760 |
} |
6761 |
#endif /* TARGET_PPC64 */ |
6762 |
|
6763 |
/* PowerPC 620 */
|
6764 |
#define POWERPC_INSNS_620 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
|
6765 |
PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \ |
6766 |
PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \ |
6767 |
PPC_FLOAT_STFIWX | \ |
6768 |
PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \ |
6769 |
PPC_MEM_SYNC | PPC_MEM_EIEIO | \ |
6770 |
PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \ |
6771 |
PPC_SEGMENT | PPC_EXTERN | \ |
6772 |
PPC_64B | PPC_SLBI) |
6773 |
#define POWERPC_INSNS2_620 (PPC_NONE)
|
6774 |
#define POWERPC_MSRM_620 (0x800000000005FF77ULL) |
6775 |
//#define POWERPC_MMU_620 (POWERPC_MMU_620)
|
6776 |
#define POWERPC_EXCP_620 (POWERPC_EXCP_970)
|
6777 |
#define POWERPC_INPUT_620 (PPC_FLAGS_INPUT_6xx)
|
6778 |
#define POWERPC_BFDM_620 (bfd_mach_ppc64)
|
6779 |
#define POWERPC_FLAG_620 (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
|
6780 |
POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK) |
6781 |
#define check_pow_620 check_pow_nocheck /* Check this */ |
6782 |
|
6783 |
__attribute__ (( unused )) |
6784 |
static void init_proc_620 (CPUPPCState *env) |
6785 |
{ |
6786 |
gen_spr_ne_601(env); |
6787 |
gen_spr_620(env); |
6788 |
/* Time base */
|
6789 |
gen_tbl(env); |
6790 |
/* Hardware implementation registers */
|
6791 |
/* XXX : not implemented */
|
6792 |
spr_register(env, SPR_HID0, "HID0",
|
6793 |
SPR_NOACCESS, SPR_NOACCESS, |
6794 |
&spr_read_generic, &spr_write_generic, |
6795 |
0x00000000);
|
6796 |
/* Memory management */
|
6797 |
gen_low_BATs(env); |
6798 |
init_excp_620(env); |
6799 |
env->dcache_line_size = 64;
|
6800 |
env->icache_line_size = 64;
|
6801 |
/* Allocate hardware IRQ controller */
|
6802 |
ppc6xx_irq_init(env); |
6803 |
} |
6804 |
#endif /* defined (TARGET_PPC64) */ |
6805 |
|
6806 |
/* Default 32 bits PowerPC target will be 604 */
|
6807 |
#define CPU_POWERPC_PPC32 CPU_POWERPC_604
|
6808 |
#define POWERPC_INSNS_PPC32 POWERPC_INSNS_604
|
6809 |
#define POWERPC_INSNS2_PPC32 POWERPC_INSNS2_604
|
6810 |
#define POWERPC_MSRM_PPC32 POWERPC_MSRM_604
|
6811 |
#define POWERPC_MMU_PPC32 POWERPC_MMU_604
|
6812 |
#define POWERPC_EXCP_PPC32 POWERPC_EXCP_604
|
6813 |
#define POWERPC_INPUT_PPC32 POWERPC_INPUT_604
|
6814 |
#define POWERPC_BFDM_PPC32 POWERPC_BFDM_604
|
6815 |
#define POWERPC_FLAG_PPC32 POWERPC_FLAG_604
|
6816 |
#define check_pow_PPC32 check_pow_604
|
6817 |
#define init_proc_PPC32 init_proc_604
|
6818 |
|
6819 |
/* Default 64 bits PowerPC target will be 970 FX */
|
6820 |
#define CPU_POWERPC_PPC64 CPU_POWERPC_970FX
|
6821 |
#define POWERPC_INSNS_PPC64 POWERPC_INSNS_970FX
|
6822 |
#define POWERPC_INSNS2_PPC64 POWERPC_INSNS2_970FX
|
6823 |
#define POWERPC_MSRM_PPC64 POWERPC_MSRM_970FX
|
6824 |
#define POWERPC_MMU_PPC64 POWERPC_MMU_970FX
|
6825 |
#define POWERPC_EXCP_PPC64 POWERPC_EXCP_970FX
|
6826 |
#define POWERPC_INPUT_PPC64 POWERPC_INPUT_970FX
|
6827 |
#define POWERPC_BFDM_PPC64 POWERPC_BFDM_970FX
|
6828 |
#define POWERPC_FLAG_PPC64 POWERPC_FLAG_970FX
|
6829 |
#define check_pow_PPC64 check_pow_970FX
|
6830 |
#define init_proc_PPC64 init_proc_970FX
|
6831 |
|
6832 |
/* Default PowerPC target will be PowerPC 32 */
|
6833 |
#if defined (TARGET_PPC64) && 0 // XXX: TODO |
6834 |
#define CPU_POWERPC_DEFAULT CPU_POWERPC_PPC64
|
6835 |
#define POWERPC_INSNS_DEFAULT POWERPC_INSNS_PPC64
|
6836 |
#define POWERPC_INSNS2_DEFAULT POWERPC_INSNS2_PPC64
|
6837 |
#define POWERPC_MSRM_DEFAULT POWERPC_MSRM_PPC64
|
6838 |
#define POWERPC_MMU_DEFAULT POWERPC_MMU_PPC64
|
6839 |
#define POWERPC_EXCP_DEFAULT POWERPC_EXCP_PPC64
|
6840 |
#define POWERPC_INPUT_DEFAULT POWERPC_INPUT_PPC64
|
6841 |
#define POWERPC_BFDM_DEFAULT POWERPC_BFDM_PPC64
|
6842 |
#define POWERPC_FLAG_DEFAULT POWERPC_FLAG_PPC64
|
6843 |
#define check_pow_DEFAULT check_pow_PPC64
|
6844 |
#define init_proc_DEFAULT init_proc_PPC64
|
6845 |
#else
|
6846 |
#define CPU_POWERPC_DEFAULT CPU_POWERPC_PPC32
|
6847 |
#define POWERPC_INSNS_DEFAULT POWERPC_INSNS_PPC32
|
6848 |
#define POWERPC_INSNS2_DEFAULT POWERPC_INSNS2_PPC32
|
6849 |
#define POWERPC_MSRM_DEFAULT POWERPC_MSRM_PPC32
|
6850 |
#define POWERPC_MMU_DEFAULT POWERPC_MMU_PPC32
|
6851 |
#define POWERPC_EXCP_DEFAULT POWERPC_EXCP_PPC32
|
6852 |
#define POWERPC_INPUT_DEFAULT POWERPC_INPUT_PPC32
|
6853 |
#define POWERPC_BFDM_DEFAULT POWERPC_BFDM_PPC32
|
6854 |
#define POWERPC_FLAG_DEFAULT POWERPC_FLAG_PPC32
|
6855 |
#define check_pow_DEFAULT check_pow_PPC32
|
6856 |
#define init_proc_DEFAULT init_proc_PPC32
|
6857 |
#endif
|
6858 |
|
6859 |
/*****************************************************************************/
|
6860 |
/* PVR definitions for most known PowerPC */
|
6861 |
enum {
|
6862 |
/* PowerPC 401 family */
|
6863 |
/* Generic PowerPC 401 */
|
6864 |
#define CPU_POWERPC_401 CPU_POWERPC_401G2
|
6865 |
/* PowerPC 401 cores */
|
6866 |
CPU_POWERPC_401A1 = 0x00210000,
|
6867 |
CPU_POWERPC_401B2 = 0x00220000,
|
6868 |
#if 0
|
6869 |
CPU_POWERPC_401B3 = xxx,
|
6870 |
#endif
|
6871 |
CPU_POWERPC_401C2 = 0x00230000,
|
6872 |
CPU_POWERPC_401D2 = 0x00240000,
|
6873 |
CPU_POWERPC_401E2 = 0x00250000,
|
6874 |
CPU_POWERPC_401F2 = 0x00260000,
|
6875 |
CPU_POWERPC_401G2 = 0x00270000,
|
6876 |
/* PowerPC 401 microcontrolers */
|
6877 |
#if 0
|
6878 |
CPU_POWERPC_401GF = xxx,
|
6879 |
#endif
|
6880 |
#define CPU_POWERPC_IOP480 CPU_POWERPC_401B2
|
6881 |
/* IBM Processor for Network Resources */
|
6882 |
CPU_POWERPC_COBRA = 0x10100000, /* XXX: 405 ? */ |
6883 |
#if 0
|
6884 |
CPU_POWERPC_XIPCHIP = xxx,
|
6885 |
#endif
|
6886 |
/* PowerPC 403 family */
|
6887 |
/* Generic PowerPC 403 */
|
6888 |
#define CPU_POWERPC_403 CPU_POWERPC_403GC
|
6889 |
/* PowerPC 403 microcontrollers */
|
6890 |
CPU_POWERPC_403GA = 0x00200011,
|
6891 |
CPU_POWERPC_403GB = 0x00200100,
|
6892 |
CPU_POWERPC_403GC = 0x00200200,
|
6893 |
CPU_POWERPC_403GCX = 0x00201400,
|
6894 |
#if 0
|
6895 |
CPU_POWERPC_403GP = xxx,
|
6896 |
#endif
|
6897 |
/* PowerPC 405 family */
|
6898 |
/* Generic PowerPC 405 */
|
6899 |
#define CPU_POWERPC_405 CPU_POWERPC_405D4
|
6900 |
/* PowerPC 405 cores */
|
6901 |
#if 0
|
6902 |
CPU_POWERPC_405A3 = xxx,
|
6903 |
#endif
|
6904 |
#if 0
|
6905 |
CPU_POWERPC_405A4 = xxx,
|
6906 |
#endif
|
6907 |
#if 0
|
6908 |
CPU_POWERPC_405B3 = xxx,
|
6909 |
#endif
|
6910 |
#if 0
|
6911 |
CPU_POWERPC_405B4 = xxx,
|
6912 |
#endif
|
6913 |
#if 0
|
6914 |
CPU_POWERPC_405C3 = xxx,
|
6915 |
#endif
|
6916 |
#if 0
|
6917 |
CPU_POWERPC_405C4 = xxx,
|
6918 |
#endif
|
6919 |
CPU_POWERPC_405D2 = 0x20010000,
|
6920 |
#if 0
|
6921 |
CPU_POWERPC_405D3 = xxx,
|
6922 |
#endif
|
6923 |
CPU_POWERPC_405D4 = 0x41810000,
|
6924 |
#if 0
|
6925 |
CPU_POWERPC_405D5 = xxx,
|
6926 |
#endif
|
6927 |
#if 0
|
6928 |
CPU_POWERPC_405E4 = xxx,
|
6929 |
#endif
|
6930 |
#if 0
|
6931 |
CPU_POWERPC_405F4 = xxx,
|
6932 |
#endif
|
6933 |
#if 0
|
6934 |
CPU_POWERPC_405F5 = xxx,
|
6935 |
#endif
|
6936 |
#if 0
|
6937 |
CPU_POWERPC_405F6 = xxx,
|
6938 |
#endif
|
6939 |
/* PowerPC 405 microcontrolers */
|
6940 |
/* XXX: missing 0x200108a0 */
|
6941 |
#define CPU_POWERPC_405CR CPU_POWERPC_405CRc
|
6942 |
CPU_POWERPC_405CRa = 0x40110041,
|
6943 |
CPU_POWERPC_405CRb = 0x401100C5,
|
6944 |
CPU_POWERPC_405CRc = 0x40110145,
|
6945 |
CPU_POWERPC_405EP = 0x51210950,
|
6946 |
#if 0
|
6947 |
CPU_POWERPC_405EXr = xxx,
|
6948 |
#endif
|
6949 |
CPU_POWERPC_405EZ = 0x41511460, /* 0x51210950 ? */ |
6950 |
#if 0
|
6951 |
CPU_POWERPC_405FX = xxx,
|
6952 |
#endif
|
6953 |
#define CPU_POWERPC_405GP CPU_POWERPC_405GPd
|
6954 |
CPU_POWERPC_405GPa = 0x40110000,
|
6955 |
CPU_POWERPC_405GPb = 0x40110040,
|
6956 |
CPU_POWERPC_405GPc = 0x40110082,
|
6957 |
CPU_POWERPC_405GPd = 0x401100C4,
|
6958 |
#define CPU_POWERPC_405GPe CPU_POWERPC_405CRc
|
6959 |
CPU_POWERPC_405GPR = 0x50910951,
|
6960 |
#if 0
|
6961 |
CPU_POWERPC_405H = xxx,
|
6962 |
#endif
|
6963 |
#if 0
|
6964 |
CPU_POWERPC_405L = xxx,
|
6965 |
#endif
|
6966 |
CPU_POWERPC_405LP = 0x41F10000,
|
6967 |
#if 0
|
6968 |
CPU_POWERPC_405PM = xxx,
|
6969 |
#endif
|
6970 |
#if 0
|
6971 |
CPU_POWERPC_405PS = xxx,
|
6972 |
#endif
|
6973 |
#if 0
|
6974 |
CPU_POWERPC_405S = xxx,
|
6975 |
#endif
|
6976 |
/* IBM network processors */
|
6977 |
CPU_POWERPC_NPE405H = 0x414100C0,
|
6978 |
CPU_POWERPC_NPE405H2 = 0x41410140,
|
6979 |
CPU_POWERPC_NPE405L = 0x416100C0,
|
6980 |
CPU_POWERPC_NPE4GS3 = 0x40B10000,
|
6981 |
#if 0
|
6982 |
CPU_POWERPC_NPCxx1 = xxx,
|
6983 |
#endif
|
6984 |
#if 0
|
6985 |
CPU_POWERPC_NPR161 = xxx,
|
6986 |
#endif
|
6987 |
#if 0
|
6988 |
CPU_POWERPC_LC77700 = xxx,
|
6989 |
#endif
|
6990 |
/* IBM STBxxx (PowerPC 401/403/405 core based microcontrollers) */
|
6991 |
#if 0
|
6992 |
CPU_POWERPC_STB01000 = xxx,
|
6993 |
#endif
|
6994 |
#if 0
|
6995 |
CPU_POWERPC_STB01010 = xxx,
|
6996 |
#endif
|
6997 |
#if 0
|
6998 |
CPU_POWERPC_STB0210 = xxx, /* 401B3 */
|
6999 |
#endif
|
7000 |
CPU_POWERPC_STB03 = 0x40310000, /* 0x40130000 ? */ |
7001 |
#if 0
|
7002 |
CPU_POWERPC_STB043 = xxx,
|
7003 |
#endif
|
7004 |
#if 0
|
7005 |
CPU_POWERPC_STB045 = xxx,
|
7006 |
#endif
|
7007 |
CPU_POWERPC_STB04 = 0x41810000,
|
7008 |
CPU_POWERPC_STB25 = 0x51510950,
|
7009 |
#if 0
|
7010 |
CPU_POWERPC_STB130 = xxx,
|
7011 |
#endif
|
7012 |
/* Xilinx cores */
|
7013 |
CPU_POWERPC_X2VP4 = 0x20010820,
|
7014 |
#define CPU_POWERPC_X2VP7 CPU_POWERPC_X2VP4
|
7015 |
CPU_POWERPC_X2VP20 = 0x20010860,
|
7016 |
#define CPU_POWERPC_X2VP50 CPU_POWERPC_X2VP20
|
7017 |
#if 0
|
7018 |
CPU_POWERPC_ZL10310 = xxx,
|
7019 |
#endif
|
7020 |
#if 0
|
7021 |
CPU_POWERPC_ZL10311 = xxx,
|
7022 |
#endif
|
7023 |
#if 0
|
7024 |
CPU_POWERPC_ZL10320 = xxx,
|
7025 |
#endif
|
7026 |
#if 0
|
7027 |
CPU_POWERPC_ZL10321 = xxx,
|
7028 |
#endif
|
7029 |
/* PowerPC 440 family */
|
7030 |
/* Generic PowerPC 440 */
|
7031 |
#define CPU_POWERPC_440 CPU_POWERPC_440GXf
|
7032 |
/* PowerPC 440 cores */
|
7033 |
#if 0
|
7034 |
CPU_POWERPC_440A4 = xxx,
|
7035 |
#endif
|
7036 |
CPU_POWERPC_440_XILINX = 0x7ff21910,
|
7037 |
#if 0
|
7038 |
CPU_POWERPC_440A5 = xxx,
|
7039 |
#endif
|
7040 |
#if 0
|
7041 |
CPU_POWERPC_440B4 = xxx,
|
7042 |
#endif
|
7043 |
#if 0
|
7044 |
CPU_POWERPC_440F5 = xxx,
|
7045 |
#endif
|
7046 |
#if 0
|
7047 |
CPU_POWERPC_440G5 = xxx,
|
7048 |
#endif
|
7049 |
#if 0
|
7050 |
CPU_POWERPC_440H4 = xxx,
|
7051 |
#endif
|
7052 |
#if 0
|
7053 |
CPU_POWERPC_440H6 = xxx,
|
7054 |
#endif
|
7055 |
/* PowerPC 440 microcontrolers */
|
7056 |
#define CPU_POWERPC_440EP CPU_POWERPC_440EPb
|
7057 |
CPU_POWERPC_440EPa = 0x42221850,
|
7058 |
CPU_POWERPC_440EPb = 0x422218D3,
|
7059 |
#define CPU_POWERPC_440GP CPU_POWERPC_440GPc
|
7060 |
CPU_POWERPC_440GPb = 0x40120440,
|
7061 |
CPU_POWERPC_440GPc = 0x40120481,
|
7062 |
#define CPU_POWERPC_440GR CPU_POWERPC_440GRa
|
7063 |
#define CPU_POWERPC_440GRa CPU_POWERPC_440EPb
|
7064 |
CPU_POWERPC_440GRX = 0x200008D0,
|
7065 |
#define CPU_POWERPC_440EPX CPU_POWERPC_440GRX
|
7066 |
#define CPU_POWERPC_440GX CPU_POWERPC_440GXf
|
7067 |
CPU_POWERPC_440GXa = 0x51B21850,
|
7068 |
CPU_POWERPC_440GXb = 0x51B21851,
|
7069 |
CPU_POWERPC_440GXc = 0x51B21892,
|
7070 |
CPU_POWERPC_440GXf = 0x51B21894,
|
7071 |
#if 0
|
7072 |
CPU_POWERPC_440S = xxx,
|
7073 |
#endif
|
7074 |
CPU_POWERPC_440SP = 0x53221850,
|
7075 |
CPU_POWERPC_440SP2 = 0x53221891,
|
7076 |
CPU_POWERPC_440SPE = 0x53421890,
|
7077 |
/* PowerPC 460 family */
|
7078 |
#if 0
|
7079 |
/* Generic PowerPC 464 */
|
7080 |
#define CPU_POWERPC_464 CPU_POWERPC_464H90
|
7081 |
#endif
|
7082 |
/* PowerPC 464 microcontrolers */
|
7083 |
#if 0
|
7084 |
CPU_POWERPC_464H90 = xxx,
|
7085 |
#endif
|
7086 |
#if 0
|
7087 |
CPU_POWERPC_464H90FP = xxx,
|
7088 |
#endif
|
7089 |
/* Freescale embedded PowerPC cores */
|
7090 |
/* PowerPC MPC 5xx cores (aka RCPU) */
|
7091 |
CPU_POWERPC_MPC5xx = 0x00020020,
|
7092 |
#define CPU_POWERPC_MGT560 CPU_POWERPC_MPC5xx
|
7093 |
#define CPU_POWERPC_MPC509 CPU_POWERPC_MPC5xx
|
7094 |
#define CPU_POWERPC_MPC533 CPU_POWERPC_MPC5xx
|
7095 |
#define CPU_POWERPC_MPC534 CPU_POWERPC_MPC5xx
|
7096 |
#define CPU_POWERPC_MPC555 CPU_POWERPC_MPC5xx
|
7097 |
#define CPU_POWERPC_MPC556 CPU_POWERPC_MPC5xx
|
7098 |
#define CPU_POWERPC_MPC560 CPU_POWERPC_MPC5xx
|
7099 |
#define CPU_POWERPC_MPC561 CPU_POWERPC_MPC5xx
|
7100 |
#define CPU_POWERPC_MPC562 CPU_POWERPC_MPC5xx
|
7101 |
#define CPU_POWERPC_MPC563 CPU_POWERPC_MPC5xx
|
7102 |
#define CPU_POWERPC_MPC564 CPU_POWERPC_MPC5xx
|
7103 |
#define CPU_POWERPC_MPC565 CPU_POWERPC_MPC5xx
|
7104 |
#define CPU_POWERPC_MPC566 CPU_POWERPC_MPC5xx
|
7105 |
/* PowerPC MPC 8xx cores (aka PowerQUICC) */
|
7106 |
CPU_POWERPC_MPC8xx = 0x00500000,
|
7107 |
#define CPU_POWERPC_MGT823 CPU_POWERPC_MPC8xx
|
7108 |
#define CPU_POWERPC_MPC821 CPU_POWERPC_MPC8xx
|
7109 |
#define CPU_POWERPC_MPC823 CPU_POWERPC_MPC8xx
|
7110 |
#define CPU_POWERPC_MPC850 CPU_POWERPC_MPC8xx
|
7111 |
#define CPU_POWERPC_MPC852T CPU_POWERPC_MPC8xx
|
7112 |
#define CPU_POWERPC_MPC855T CPU_POWERPC_MPC8xx
|
7113 |
#define CPU_POWERPC_MPC857 CPU_POWERPC_MPC8xx
|
7114 |
#define CPU_POWERPC_MPC859 CPU_POWERPC_MPC8xx
|
7115 |
#define CPU_POWERPC_MPC860 CPU_POWERPC_MPC8xx
|
7116 |
#define CPU_POWERPC_MPC862 CPU_POWERPC_MPC8xx
|
7117 |
#define CPU_POWERPC_MPC866 CPU_POWERPC_MPC8xx
|
7118 |
#define CPU_POWERPC_MPC870 CPU_POWERPC_MPC8xx
|
7119 |
#define CPU_POWERPC_MPC875 CPU_POWERPC_MPC8xx
|
7120 |
#define CPU_POWERPC_MPC880 CPU_POWERPC_MPC8xx
|
7121 |
#define CPU_POWERPC_MPC885 CPU_POWERPC_MPC8xx
|
7122 |
/* G2 cores (aka PowerQUICC-II) */
|
7123 |
CPU_POWERPC_G2 = 0x00810011,
|
7124 |
CPU_POWERPC_G2H4 = 0x80811010,
|
7125 |
CPU_POWERPC_G2gp = 0x80821010,
|
7126 |
CPU_POWERPC_G2ls = 0x90810010,
|
7127 |
CPU_POWERPC_MPC603 = 0x00810100,
|
7128 |
CPU_POWERPC_G2_HIP3 = 0x00810101,
|
7129 |
CPU_POWERPC_G2_HIP4 = 0x80811014,
|
7130 |
/* G2_LE core (aka PowerQUICC-II) */
|
7131 |
CPU_POWERPC_G2LE = 0x80820010,
|
7132 |
CPU_POWERPC_G2LEgp = 0x80822010,
|
7133 |
CPU_POWERPC_G2LEls = 0xA0822010,
|
7134 |
CPU_POWERPC_G2LEgp1 = 0x80822011,
|
7135 |
CPU_POWERPC_G2LEgp3 = 0x80822013,
|
7136 |
/* MPC52xx microcontrollers */
|
7137 |
/* XXX: MPC 5121 ? */
|
7138 |
#define CPU_POWERPC_MPC52xx CPU_POWERPC_MPC5200
|
7139 |
#define CPU_POWERPC_MPC5200 CPU_POWERPC_MPC5200_v12
|
7140 |
#define CPU_POWERPC_MPC5200_v10 CPU_POWERPC_G2LEgp1
|
7141 |
#define CPU_POWERPC_MPC5200_v11 CPU_POWERPC_G2LEgp1
|
7142 |
#define CPU_POWERPC_MPC5200_v12 CPU_POWERPC_G2LEgp1
|
7143 |
#define CPU_POWERPC_MPC5200B CPU_POWERPC_MPC5200B_v21
|
7144 |
#define CPU_POWERPC_MPC5200B_v20 CPU_POWERPC_G2LEgp1
|
7145 |
#define CPU_POWERPC_MPC5200B_v21 CPU_POWERPC_G2LEgp1
|
7146 |
/* MPC82xx microcontrollers */
|
7147 |
#define CPU_POWERPC_MPC82xx CPU_POWERPC_MPC8280
|
7148 |
#define CPU_POWERPC_MPC8240 CPU_POWERPC_MPC603
|
7149 |
#define CPU_POWERPC_MPC8241 CPU_POWERPC_G2_HIP4
|
7150 |
#define CPU_POWERPC_MPC8245 CPU_POWERPC_G2_HIP4
|
7151 |
#define CPU_POWERPC_MPC8247 CPU_POWERPC_G2LEgp3
|
7152 |
#define CPU_POWERPC_MPC8248 CPU_POWERPC_G2LEgp3
|
7153 |
#define CPU_POWERPC_MPC8250 CPU_POWERPC_MPC8250_HiP4
|
7154 |
#define CPU_POWERPC_MPC8250_HiP3 CPU_POWERPC_G2_HIP3
|
7155 |
#define CPU_POWERPC_MPC8250_HiP4 CPU_POWERPC_G2_HIP4
|
7156 |
#define CPU_POWERPC_MPC8255 CPU_POWERPC_MPC8255_HiP4
|
7157 |
#define CPU_POWERPC_MPC8255_HiP3 CPU_POWERPC_G2_HIP3
|
7158 |
#define CPU_POWERPC_MPC8255_HiP4 CPU_POWERPC_G2_HIP4
|
7159 |
#define CPU_POWERPC_MPC8260 CPU_POWERPC_MPC8260_HiP4
|
7160 |
#define CPU_POWERPC_MPC8260_HiP3 CPU_POWERPC_G2_HIP3
|
7161 |
#define CPU_POWERPC_MPC8260_HiP4 CPU_POWERPC_G2_HIP4
|
7162 |
#define CPU_POWERPC_MPC8264 CPU_POWERPC_MPC8264_HiP4
|
7163 |
#define CPU_POWERPC_MPC8264_HiP3 CPU_POWERPC_G2_HIP3
|
7164 |
#define CPU_POWERPC_MPC8264_HiP4 CPU_POWERPC_G2_HIP4
|
7165 |
#define CPU_POWERPC_MPC8265 CPU_POWERPC_MPC8265_HiP4
|
7166 |
#define CPU_POWERPC_MPC8265_HiP3 CPU_POWERPC_G2_HIP3
|
7167 |
#define CPU_POWERPC_MPC8265_HiP4 CPU_POWERPC_G2_HIP4
|
7168 |
#define CPU_POWERPC_MPC8266 CPU_POWERPC_MPC8266_HiP4
|
7169 |
#define CPU_POWERPC_MPC8266_HiP3 CPU_POWERPC_G2_HIP3
|
7170 |
#define CPU_POWERPC_MPC8266_HiP4 CPU_POWERPC_G2_HIP4
|
7171 |
#define CPU_POWERPC_MPC8270 CPU_POWERPC_G2LEgp3
|
7172 |
#define CPU_POWERPC_MPC8271 CPU_POWERPC_G2LEgp3
|
7173 |
#define CPU_POWERPC_MPC8272 CPU_POWERPC_G2LEgp3
|
7174 |
#define CPU_POWERPC_MPC8275 CPU_POWERPC_G2LEgp3
|
7175 |
#define CPU_POWERPC_MPC8280 CPU_POWERPC_G2LEgp3
|
7176 |
/* e200 family */
|
7177 |
/* e200 cores */
|
7178 |
#define CPU_POWERPC_e200 CPU_POWERPC_e200z6
|
7179 |
#if 0
|
7180 |
CPU_POWERPC_e200z0 = xxx,
|
7181 |
#endif
|
7182 |
#if 0
|
7183 |
CPU_POWERPC_e200z1 = xxx,
|
7184 |
#endif
|
7185 |
#if 0 /* ? */
|
7186 |
CPU_POWERPC_e200z3 = 0x81120000,
|
7187 |
#endif
|
7188 |
CPU_POWERPC_e200z5 = 0x81000000,
|
7189 |
CPU_POWERPC_e200z6 = 0x81120000,
|
7190 |
/* MPC55xx microcontrollers */
|
7191 |
#define CPU_POWERPC_MPC55xx CPU_POWERPC_MPC5567
|
7192 |
#if 0
|
7193 |
#define CPU_POWERPC_MPC5514E CPU_POWERPC_MPC5514E_v1
|
7194 |
#define CPU_POWERPC_MPC5514E_v0 CPU_POWERPC_e200z0
|
7195 |
#define CPU_POWERPC_MPC5514E_v1 CPU_POWERPC_e200z1
|
7196 |
#define CPU_POWERPC_MPC5514G CPU_POWERPC_MPC5514G_v1
|
7197 |
#define CPU_POWERPC_MPC5514G_v0 CPU_POWERPC_e200z0
|
7198 |
#define CPU_POWERPC_MPC5514G_v1 CPU_POWERPC_e200z1
|
7199 |
#define CPU_POWERPC_MPC5515S CPU_POWERPC_e200z1
|
7200 |
#define CPU_POWERPC_MPC5516E CPU_POWERPC_MPC5516E_v1
|
7201 |
#define CPU_POWERPC_MPC5516E_v0 CPU_POWERPC_e200z0
|
7202 |
#define CPU_POWERPC_MPC5516E_v1 CPU_POWERPC_e200z1
|
7203 |
#define CPU_POWERPC_MPC5516G CPU_POWERPC_MPC5516G_v1
|
7204 |
#define CPU_POWERPC_MPC5516G_v0 CPU_POWERPC_e200z0
|
7205 |
#define CPU_POWERPC_MPC5516G_v1 CPU_POWERPC_e200z1
|
7206 |
#define CPU_POWERPC_MPC5516S CPU_POWERPC_e200z1
|
7207 |
#endif
|
7208 |
#if 0
|
7209 |
#define CPU_POWERPC_MPC5533 CPU_POWERPC_e200z3
|
7210 |
#define CPU_POWERPC_MPC5534 CPU_POWERPC_e200z3
|
7211 |
#endif
|
7212 |
#define CPU_POWERPC_MPC5553 CPU_POWERPC_e200z6
|
7213 |
#define CPU_POWERPC_MPC5554 CPU_POWERPC_e200z6
|
7214 |
#define CPU_POWERPC_MPC5561 CPU_POWERPC_e200z6
|
7215 |
#define CPU_POWERPC_MPC5565 CPU_POWERPC_e200z6
|
7216 |
#define CPU_POWERPC_MPC5566 CPU_POWERPC_e200z6
|
7217 |
#define CPU_POWERPC_MPC5567 CPU_POWERPC_e200z6
|
7218 |
/* e300 family */
|
7219 |
/* e300 cores */
|
7220 |
#define CPU_POWERPC_e300 CPU_POWERPC_e300c3
|
7221 |
CPU_POWERPC_e300c1 = 0x00830010,
|
7222 |
CPU_POWERPC_e300c2 = 0x00840010,
|
7223 |
CPU_POWERPC_e300c3 = 0x00850010,
|
7224 |
CPU_POWERPC_e300c4 = 0x00860010,
|
7225 |
/* MPC83xx microcontrollers */
|
7226 |
#define CPU_POWERPC_MPC831x CPU_POWERPC_e300c3
|
7227 |
#define CPU_POWERPC_MPC832x CPU_POWERPC_e300c2
|
7228 |
#define CPU_POWERPC_MPC834x CPU_POWERPC_e300c1
|
7229 |
#define CPU_POWERPC_MPC835x CPU_POWERPC_e300c1
|
7230 |
#define CPU_POWERPC_MPC836x CPU_POWERPC_e300c1
|
7231 |
#define CPU_POWERPC_MPC837x CPU_POWERPC_e300c4
|
7232 |
/* e500 family */
|
7233 |
/* e500 cores */
|
7234 |
#define CPU_POWERPC_e500 CPU_POWERPC_e500v2_v22
|
7235 |
#define CPU_POWERPC_e500v1 CPU_POWERPC_e500v1_v20
|
7236 |
#define CPU_POWERPC_e500v2 CPU_POWERPC_e500v2_v22
|
7237 |
CPU_POWERPC_e500v1_v10 = 0x80200010,
|
7238 |
CPU_POWERPC_e500v1_v20 = 0x80200020,
|
7239 |
CPU_POWERPC_e500v2_v10 = 0x80210010,
|
7240 |
CPU_POWERPC_e500v2_v11 = 0x80210011,
|
7241 |
CPU_POWERPC_e500v2_v20 = 0x80210020,
|
7242 |
CPU_POWERPC_e500v2_v21 = 0x80210021,
|
7243 |
CPU_POWERPC_e500v2_v22 = 0x80210022,
|
7244 |
CPU_POWERPC_e500v2_v30 = 0x80210030,
|
7245 |
CPU_POWERPC_e500mc = 0x80230020,
|
7246 |
CPU_POWERPC_e5500 = 0x80240020,
|
7247 |
/* MPC85xx microcontrollers */
|
7248 |
#define CPU_POWERPC_MPC8533 CPU_POWERPC_MPC8533_v11
|
7249 |
#define CPU_POWERPC_MPC8533_v10 CPU_POWERPC_e500v2_v21
|
7250 |
#define CPU_POWERPC_MPC8533_v11 CPU_POWERPC_e500v2_v22
|
7251 |
#define CPU_POWERPC_MPC8533E CPU_POWERPC_MPC8533E_v11
|
7252 |
#define CPU_POWERPC_MPC8533E_v10 CPU_POWERPC_e500v2_v21
|
7253 |
#define CPU_POWERPC_MPC8533E_v11 CPU_POWERPC_e500v2_v22
|
7254 |
#define CPU_POWERPC_MPC8540 CPU_POWERPC_MPC8540_v21
|
7255 |
#define CPU_POWERPC_MPC8540_v10 CPU_POWERPC_e500v1_v10
|
7256 |
#define CPU_POWERPC_MPC8540_v20 CPU_POWERPC_e500v1_v20
|
7257 |
#define CPU_POWERPC_MPC8540_v21 CPU_POWERPC_e500v1_v20
|
7258 |
#define CPU_POWERPC_MPC8541 CPU_POWERPC_MPC8541_v11
|
7259 |
#define CPU_POWERPC_MPC8541_v10 CPU_POWERPC_e500v1_v20
|
7260 |
#define CPU_POWERPC_MPC8541_v11 CPU_POWERPC_e500v1_v20
|
7261 |
#define CPU_POWERPC_MPC8541E CPU_POWERPC_MPC8541E_v11
|
7262 |
#define CPU_POWERPC_MPC8541E_v10 CPU_POWERPC_e500v1_v20
|
7263 |
#define CPU_POWERPC_MPC8541E_v11 CPU_POWERPC_e500v1_v20
|
7264 |
#define CPU_POWERPC_MPC8543 CPU_POWERPC_MPC8543_v21
|
7265 |
#define CPU_POWERPC_MPC8543_v10 CPU_POWERPC_e500v2_v10
|
7266 |
#define CPU_POWERPC_MPC8543_v11 CPU_POWERPC_e500v2_v11
|
7267 |
#define CPU_POWERPC_MPC8543_v20 CPU_POWERPC_e500v2_v20
|
7268 |
#define CPU_POWERPC_MPC8543_v21 CPU_POWERPC_e500v2_v21
|
7269 |
#define CPU_POWERPC_MPC8543E CPU_POWERPC_MPC8543E_v21
|
7270 |
#define CPU_POWERPC_MPC8543E_v10 CPU_POWERPC_e500v2_v10
|
7271 |
#define CPU_POWERPC_MPC8543E_v11 CPU_POWERPC_e500v2_v11
|
7272 |
#define CPU_POWERPC_MPC8543E_v20 CPU_POWERPC_e500v2_v20
|
7273 |
#define CPU_POWERPC_MPC8543E_v21 CPU_POWERPC_e500v2_v21
|
7274 |
#define CPU_POWERPC_MPC8544 CPU_POWERPC_MPC8544_v11
|
7275 |
#define CPU_POWERPC_MPC8544_v10 CPU_POWERPC_e500v2_v21
|
7276 |
#define CPU_POWERPC_MPC8544_v11 CPU_POWERPC_e500v2_v22
|
7277 |
#define CPU_POWERPC_MPC8544E_v11 CPU_POWERPC_e500v2_v22
|
7278 |
#define CPU_POWERPC_MPC8544E CPU_POWERPC_MPC8544E_v11
|
7279 |
#define CPU_POWERPC_MPC8544E_v10 CPU_POWERPC_e500v2_v21
|
7280 |
#define CPU_POWERPC_MPC8545 CPU_POWERPC_MPC8545_v21
|
7281 |
#define CPU_POWERPC_MPC8545_v10 CPU_POWERPC_e500v2_v10
|
7282 |
#define CPU_POWERPC_MPC8545_v20 CPU_POWERPC_e500v2_v20
|
7283 |
#define CPU_POWERPC_MPC8545_v21 CPU_POWERPC_e500v2_v21
|
7284 |
#define CPU_POWERPC_MPC8545E CPU_POWERPC_MPC8545E_v21
|
7285 |
#define CPU_POWERPC_MPC8545E_v10 CPU_POWERPC_e500v2_v10
|
7286 |
#define CPU_POWERPC_MPC8545E_v20 CPU_POWERPC_e500v2_v20
|
7287 |
#define CPU_POWERPC_MPC8545E_v21 CPU_POWERPC_e500v2_v21
|
7288 |
#define CPU_POWERPC_MPC8547E CPU_POWERPC_MPC8545E_v21
|
7289 |
#define CPU_POWERPC_MPC8547E_v10 CPU_POWERPC_e500v2_v10
|
7290 |
#define CPU_POWERPC_MPC8547E_v20 CPU_POWERPC_e500v2_v20
|
7291 |
#define CPU_POWERPC_MPC8547E_v21 CPU_POWERPC_e500v2_v21
|
7292 |
#define CPU_POWERPC_MPC8548 CPU_POWERPC_MPC8548_v21
|
7293 |
#define CPU_POWERPC_MPC8548_v10 CPU_POWERPC_e500v2_v10
|
7294 |
#define CPU_POWERPC_MPC8548_v11 CPU_POWERPC_e500v2_v11
|
7295 |
#define CPU_POWERPC_MPC8548_v20 CPU_POWERPC_e500v2_v20
|
7296 |
#define CPU_POWERPC_MPC8548_v21 CPU_POWERPC_e500v2_v21
|
7297 |
#define CPU_POWERPC_MPC8548E CPU_POWERPC_MPC8548E_v21
|
7298 |
#define CPU_POWERPC_MPC8548E_v10 CPU_POWERPC_e500v2_v10
|
7299 |
#define CPU_POWERPC_MPC8548E_v11 CPU_POWERPC_e500v2_v11
|
7300 |
#define CPU_POWERPC_MPC8548E_v20 CPU_POWERPC_e500v2_v20
|
7301 |
#define CPU_POWERPC_MPC8548E_v21 CPU_POWERPC_e500v2_v21
|
7302 |
#define CPU_POWERPC_MPC8555 CPU_POWERPC_MPC8555_v11
|
7303 |
#define CPU_POWERPC_MPC8555_v10 CPU_POWERPC_e500v2_v10
|
7304 |
#define CPU_POWERPC_MPC8555_v11 CPU_POWERPC_e500v2_v11
|
7305 |
#define CPU_POWERPC_MPC8555E CPU_POWERPC_MPC8555E_v11
|
7306 |
#define CPU_POWERPC_MPC8555E_v10 CPU_POWERPC_e500v2_v10
|
7307 |
#define CPU_POWERPC_MPC8555E_v11 CPU_POWERPC_e500v2_v11
|
7308 |
#define CPU_POWERPC_MPC8560 CPU_POWERPC_MPC8560_v21
|
7309 |
#define CPU_POWERPC_MPC8560_v10 CPU_POWERPC_e500v2_v10
|
7310 |
#define CPU_POWERPC_MPC8560_v20 CPU_POWERPC_e500v2_v20
|
7311 |
#define CPU_POWERPC_MPC8560_v21 CPU_POWERPC_e500v2_v21
|
7312 |
#define CPU_POWERPC_MPC8567 CPU_POWERPC_e500v2_v22
|
7313 |
#define CPU_POWERPC_MPC8567E CPU_POWERPC_e500v2_v22
|
7314 |
#define CPU_POWERPC_MPC8568 CPU_POWERPC_e500v2_v22
|
7315 |
#define CPU_POWERPC_MPC8568E CPU_POWERPC_e500v2_v22
|
7316 |
#define CPU_POWERPC_MPC8572 CPU_POWERPC_e500v2_v30
|
7317 |
#define CPU_POWERPC_MPC8572E CPU_POWERPC_e500v2_v30
|
7318 |
/* e600 family */
|
7319 |
/* e600 cores */
|
7320 |
CPU_POWERPC_e600 = 0x80040010,
|
7321 |
/* MPC86xx microcontrollers */
|
7322 |
#define CPU_POWERPC_MPC8610 CPU_POWERPC_e600
|
7323 |
#define CPU_POWERPC_MPC8641 CPU_POWERPC_e600
|
7324 |
#define CPU_POWERPC_MPC8641D CPU_POWERPC_e600
|
7325 |
/* PowerPC 6xx cores */
|
7326 |
#define CPU_POWERPC_601 CPU_POWERPC_601_v2
|
7327 |
CPU_POWERPC_601_v0 = 0x00010001,
|
7328 |
CPU_POWERPC_601_v1 = 0x00010001,
|
7329 |
#define CPU_POWERPC_601v CPU_POWERPC_601_v2
|
7330 |
CPU_POWERPC_601_v2 = 0x00010002,
|
7331 |
CPU_POWERPC_602 = 0x00050100,
|
7332 |
CPU_POWERPC_603 = 0x00030100,
|
7333 |
#define CPU_POWERPC_603E CPU_POWERPC_603E_v41
|
7334 |
CPU_POWERPC_603E_v11 = 0x00060101,
|
7335 |
CPU_POWERPC_603E_v12 = 0x00060102,
|
7336 |
CPU_POWERPC_603E_v13 = 0x00060103,
|
7337 |
CPU_POWERPC_603E_v14 = 0x00060104,
|
7338 |
CPU_POWERPC_603E_v22 = 0x00060202,
|
7339 |
CPU_POWERPC_603E_v3 = 0x00060300,
|
7340 |
CPU_POWERPC_603E_v4 = 0x00060400,
|
7341 |
CPU_POWERPC_603E_v41 = 0x00060401,
|
7342 |
CPU_POWERPC_603E7t = 0x00071201,
|
7343 |
CPU_POWERPC_603E7v = 0x00070100,
|
7344 |
CPU_POWERPC_603E7v1 = 0x00070101,
|
7345 |
CPU_POWERPC_603E7v2 = 0x00070201,
|
7346 |
CPU_POWERPC_603E7 = 0x00070200,
|
7347 |
CPU_POWERPC_603P = 0x00070000,
|
7348 |
#define CPU_POWERPC_603R CPU_POWERPC_603E7t
|
7349 |
/* XXX: missing 0x00040303 (604) */
|
7350 |
CPU_POWERPC_604 = 0x00040103,
|
7351 |
#define CPU_POWERPC_604E CPU_POWERPC_604E_v24
|
7352 |
/* XXX: missing 0x00091203 */
|
7353 |
/* XXX: missing 0x00092110 */
|
7354 |
/* XXX: missing 0x00092120 */
|
7355 |
CPU_POWERPC_604E_v10 = 0x00090100,
|
7356 |
CPU_POWERPC_604E_v22 = 0x00090202,
|
7357 |
CPU_POWERPC_604E_v24 = 0x00090204,
|
7358 |
/* XXX: missing 0x000a0100 */
|
7359 |
/* XXX: missing 0x00093102 */
|
7360 |
CPU_POWERPC_604R = 0x000a0101,
|
7361 |
#if 0
|
7362 |
CPU_POWERPC_604EV = xxx, /* XXX: same as 604R ? */
|
7363 |
#endif
|
7364 |
/* PowerPC 740/750 cores (aka G3) */
|
7365 |
/* XXX: missing 0x00084202 */
|
7366 |
#define CPU_POWERPC_7x0 CPU_POWERPC_7x0_v31
|
7367 |
CPU_POWERPC_7x0_v10 = 0x00080100,
|
7368 |
CPU_POWERPC_7x0_v20 = 0x00080200,
|
7369 |
CPU_POWERPC_7x0_v21 = 0x00080201,
|
7370 |
CPU_POWERPC_7x0_v22 = 0x00080202,
|
7371 |
CPU_POWERPC_7x0_v30 = 0x00080300,
|
7372 |
CPU_POWERPC_7x0_v31 = 0x00080301,
|
7373 |
CPU_POWERPC_740E = 0x00080100,
|
7374 |
CPU_POWERPC_750E = 0x00080200,
|
7375 |
CPU_POWERPC_7x0P = 0x10080000,
|
7376 |
/* XXX: missing 0x00087010 (CL ?) */
|
7377 |
#define CPU_POWERPC_750CL CPU_POWERPC_750CL_v20
|
7378 |
CPU_POWERPC_750CL_v10 = 0x00087200,
|
7379 |
CPU_POWERPC_750CL_v20 = 0x00087210, /* aka rev E */ |
7380 |
#define CPU_POWERPC_750CX CPU_POWERPC_750CX_v22
|
7381 |
CPU_POWERPC_750CX_v10 = 0x00082100,
|
7382 |
CPU_POWERPC_750CX_v20 = 0x00082200,
|
7383 |
CPU_POWERPC_750CX_v21 = 0x00082201,
|
7384 |
CPU_POWERPC_750CX_v22 = 0x00082202,
|
7385 |
#define CPU_POWERPC_750CXE CPU_POWERPC_750CXE_v31b
|
7386 |
CPU_POWERPC_750CXE_v21 = 0x00082211,
|
7387 |
CPU_POWERPC_750CXE_v22 = 0x00082212,
|
7388 |
CPU_POWERPC_750CXE_v23 = 0x00082213,
|
7389 |
CPU_POWERPC_750CXE_v24 = 0x00082214,
|
7390 |
CPU_POWERPC_750CXE_v24b = 0x00083214,
|
7391 |
CPU_POWERPC_750CXE_v30 = 0x00082310,
|
7392 |
CPU_POWERPC_750CXE_v31 = 0x00082311,
|
7393 |
CPU_POWERPC_750CXE_v31b = 0x00083311,
|
7394 |
CPU_POWERPC_750CXR = 0x00083410,
|
7395 |
CPU_POWERPC_750FL = 0x70000203,
|
7396 |
#define CPU_POWERPC_750FX CPU_POWERPC_750FX_v23
|
7397 |
CPU_POWERPC_750FX_v10 = 0x70000100,
|
7398 |
CPU_POWERPC_750FX_v20 = 0x70000200,
|
7399 |
CPU_POWERPC_750FX_v21 = 0x70000201,
|
7400 |
CPU_POWERPC_750FX_v22 = 0x70000202,
|
7401 |
CPU_POWERPC_750FX_v23 = 0x70000203,
|
7402 |
CPU_POWERPC_750GL = 0x70020102,
|
7403 |
#define CPU_POWERPC_750GX CPU_POWERPC_750GX_v12
|
7404 |
CPU_POWERPC_750GX_v10 = 0x70020100,
|
7405 |
CPU_POWERPC_750GX_v11 = 0x70020101,
|
7406 |
CPU_POWERPC_750GX_v12 = 0x70020102,
|
7407 |
#define CPU_POWERPC_750L CPU_POWERPC_750L_v32 /* Aka LoneStar */ |
7408 |
CPU_POWERPC_750L_v20 = 0x00088200,
|
7409 |
CPU_POWERPC_750L_v21 = 0x00088201,
|
7410 |
CPU_POWERPC_750L_v22 = 0x00088202,
|
7411 |
CPU_POWERPC_750L_v30 = 0x00088300,
|
7412 |
CPU_POWERPC_750L_v32 = 0x00088302,
|
7413 |
/* PowerPC 745/755 cores */
|
7414 |
#define CPU_POWERPC_7x5 CPU_POWERPC_7x5_v28
|
7415 |
CPU_POWERPC_7x5_v10 = 0x00083100,
|
7416 |
CPU_POWERPC_7x5_v11 = 0x00083101,
|
7417 |
CPU_POWERPC_7x5_v20 = 0x00083200,
|
7418 |
CPU_POWERPC_7x5_v21 = 0x00083201,
|
7419 |
CPU_POWERPC_7x5_v22 = 0x00083202, /* aka D */ |
7420 |
CPU_POWERPC_7x5_v23 = 0x00083203, /* aka E */ |
7421 |
CPU_POWERPC_7x5_v24 = 0x00083204,
|
7422 |
CPU_POWERPC_7x5_v25 = 0x00083205,
|
7423 |
CPU_POWERPC_7x5_v26 = 0x00083206,
|
7424 |
CPU_POWERPC_7x5_v27 = 0x00083207,
|
7425 |
CPU_POWERPC_7x5_v28 = 0x00083208,
|
7426 |
#if 0
|
7427 |
CPU_POWERPC_7x5P = xxx,
|
7428 |
#endif
|
7429 |
/* PowerPC 74xx cores (aka G4) */
|
7430 |
/* XXX: missing 0x000C1101 */
|
7431 |
#define CPU_POWERPC_7400 CPU_POWERPC_7400_v29
|
7432 |
CPU_POWERPC_7400_v10 = 0x000C0100,
|
7433 |
CPU_POWERPC_7400_v11 = 0x000C0101,
|
7434 |
CPU_POWERPC_7400_v20 = 0x000C0200,
|
7435 |
CPU_POWERPC_7400_v21 = 0x000C0201,
|
7436 |
CPU_POWERPC_7400_v22 = 0x000C0202,
|
7437 |
CPU_POWERPC_7400_v26 = 0x000C0206,
|
7438 |
CPU_POWERPC_7400_v27 = 0x000C0207,
|
7439 |
CPU_POWERPC_7400_v28 = 0x000C0208,
|
7440 |
CPU_POWERPC_7400_v29 = 0x000C0209,
|
7441 |
#define CPU_POWERPC_7410 CPU_POWERPC_7410_v14
|
7442 |
CPU_POWERPC_7410_v10 = 0x800C1100,
|
7443 |
CPU_POWERPC_7410_v11 = 0x800C1101,
|
7444 |
CPU_POWERPC_7410_v12 = 0x800C1102, /* aka C */ |
7445 |
CPU_POWERPC_7410_v13 = 0x800C1103, /* aka D */ |
7446 |
CPU_POWERPC_7410_v14 = 0x800C1104, /* aka E */ |
7447 |
#define CPU_POWERPC_7448 CPU_POWERPC_7448_v21
|
7448 |
CPU_POWERPC_7448_v10 = 0x80040100,
|
7449 |
CPU_POWERPC_7448_v11 = 0x80040101,
|
7450 |
CPU_POWERPC_7448_v20 = 0x80040200,
|
7451 |
CPU_POWERPC_7448_v21 = 0x80040201,
|
7452 |
#define CPU_POWERPC_7450 CPU_POWERPC_7450_v21
|
7453 |
CPU_POWERPC_7450_v10 = 0x80000100,
|
7454 |
CPU_POWERPC_7450_v11 = 0x80000101,
|
7455 |
CPU_POWERPC_7450_v12 = 0x80000102,
|
7456 |
CPU_POWERPC_7450_v20 = 0x80000200, /* aka A, B, C, D: 2.04 */ |
7457 |
CPU_POWERPC_7450_v21 = 0x80000201, /* aka E */ |
7458 |
#define CPU_POWERPC_74x1 CPU_POWERPC_74x1_v23
|
7459 |
CPU_POWERPC_74x1_v23 = 0x80000203, /* aka G: 2.3 */ |
7460 |
/* XXX: this entry might be a bug in some documentation */
|
7461 |
CPU_POWERPC_74x1_v210 = 0x80000210, /* aka G: 2.3 ? */ |
7462 |
#define CPU_POWERPC_74x5 CPU_POWERPC_74x5_v32
|
7463 |
CPU_POWERPC_74x5_v10 = 0x80010100,
|
7464 |
/* XXX: missing 0x80010200 */
|
7465 |
CPU_POWERPC_74x5_v21 = 0x80010201, /* aka C: 2.1 */ |
7466 |
CPU_POWERPC_74x5_v32 = 0x80010302,
|
7467 |
CPU_POWERPC_74x5_v33 = 0x80010303, /* aka F: 3.3 */ |
7468 |
CPU_POWERPC_74x5_v34 = 0x80010304, /* aka G: 3.4 */ |
7469 |
#define CPU_POWERPC_74x7 CPU_POWERPC_74x7_v12
|
7470 |
CPU_POWERPC_74x7_v10 = 0x80020100, /* aka A: 1.0 */ |
7471 |
CPU_POWERPC_74x7_v11 = 0x80020101, /* aka B: 1.1 */ |
7472 |
CPU_POWERPC_74x7_v12 = 0x80020102, /* aka C: 1.2 */ |
7473 |
#define CPU_POWERPC_74x7A CPU_POWERPC_74x7A_v12
|
7474 |
CPU_POWERPC_74x7A_v10 = 0x80030100, /* aka A: 1.0 */ |
7475 |
CPU_POWERPC_74x7A_v11 = 0x80030101, /* aka B: 1.1 */ |
7476 |
CPU_POWERPC_74x7A_v12 = 0x80030102, /* aka C: 1.2 */ |
7477 |
/* 64 bits PowerPC */
|
7478 |
#if defined(TARGET_PPC64)
|
7479 |
CPU_POWERPC_620 = 0x00140000,
|
7480 |
CPU_POWERPC_630 = 0x00400000,
|
7481 |
CPU_POWERPC_631 = 0x00410104,
|
7482 |
CPU_POWERPC_POWER4 = 0x00350000,
|
7483 |
CPU_POWERPC_POWER4P = 0x00380000,
|
7484 |
/* XXX: missing 0x003A0201 */
|
7485 |
CPU_POWERPC_POWER5 = 0x003A0203,
|
7486 |
#define CPU_POWERPC_POWER5GR CPU_POWERPC_POWER5
|
7487 |
CPU_POWERPC_POWER5P = 0x003B0000,
|
7488 |
#define CPU_POWERPC_POWER5GS CPU_POWERPC_POWER5P
|
7489 |
CPU_POWERPC_POWER6 = 0x003E0000,
|
7490 |
CPU_POWERPC_POWER6_5 = 0x0F000001, /* POWER6 in POWER5 mode */ |
7491 |
CPU_POWERPC_POWER6A = 0x0F000002,
|
7492 |
#define CPU_POWERPC_POWER7 CPU_POWERPC_POWER7_v20
|
7493 |
CPU_POWERPC_POWER7_v20 = 0x003F0200,
|
7494 |
CPU_POWERPC_POWER7_v21 = 0x003F0201,
|
7495 |
CPU_POWERPC_POWER7_v23 = 0x003F0203,
|
7496 |
CPU_POWERPC_970 = 0x00390202,
|
7497 |
#define CPU_POWERPC_970FX CPU_POWERPC_970FX_v31
|
7498 |
CPU_POWERPC_970FX_v10 = 0x00391100,
|
7499 |
CPU_POWERPC_970FX_v20 = 0x003C0200,
|
7500 |
CPU_POWERPC_970FX_v21 = 0x003C0201,
|
7501 |
CPU_POWERPC_970FX_v30 = 0x003C0300,
|
7502 |
CPU_POWERPC_970FX_v31 = 0x003C0301,
|
7503 |
CPU_POWERPC_970GX = 0x00450000,
|
7504 |
#define CPU_POWERPC_970MP CPU_POWERPC_970MP_v11
|
7505 |
CPU_POWERPC_970MP_v10 = 0x00440100,
|
7506 |
CPU_POWERPC_970MP_v11 = 0x00440101,
|
7507 |
#define CPU_POWERPC_CELL CPU_POWERPC_CELL_v32
|
7508 |
CPU_POWERPC_CELL_v10 = 0x00700100,
|
7509 |
CPU_POWERPC_CELL_v20 = 0x00700400,
|
7510 |
CPU_POWERPC_CELL_v30 = 0x00700500,
|
7511 |
CPU_POWERPC_CELL_v31 = 0x00700501,
|
7512 |
#define CPU_POWERPC_CELL_v32 CPU_POWERPC_CELL_v31
|
7513 |
CPU_POWERPC_RS64 = 0x00330000,
|
7514 |
CPU_POWERPC_RS64II = 0x00340000,
|
7515 |
CPU_POWERPC_RS64III = 0x00360000,
|
7516 |
CPU_POWERPC_RS64IV = 0x00370000,
|
7517 |
#endif /* defined(TARGET_PPC64) */ |
7518 |
/* Original POWER */
|
7519 |
/* XXX: should be POWER (RIOS), RSC3308, RSC4608,
|
7520 |
* POWER2 (RIOS2) & RSC2 (P2SC) here
|
7521 |
*/
|
7522 |
#if 0
|
7523 |
CPU_POWER = xxx, /* 0x20000 ? 0x30000 for RSC ? */
|
7524 |
#endif
|
7525 |
#if 0
|
7526 |
CPU_POWER2 = xxx, /* 0x40000 ? */
|
7527 |
#endif
|
7528 |
/* PA Semi core */
|
7529 |
CPU_POWERPC_PA6T = 0x00900000,
|
7530 |
}; |
7531 |
|
7532 |
/* System version register (used on MPC 8xxx) */
|
7533 |
enum {
|
7534 |
POWERPC_SVR_NONE = 0x00000000,
|
7535 |
#define POWERPC_SVR_52xx POWERPC_SVR_5200
|
7536 |
#define POWERPC_SVR_5200 POWERPC_SVR_5200_v12
|
7537 |
POWERPC_SVR_5200_v10 = 0x80110010,
|
7538 |
POWERPC_SVR_5200_v11 = 0x80110011,
|
7539 |
POWERPC_SVR_5200_v12 = 0x80110012,
|
7540 |
#define POWERPC_SVR_5200B POWERPC_SVR_5200B_v21
|
7541 |
POWERPC_SVR_5200B_v20 = 0x80110020,
|
7542 |
POWERPC_SVR_5200B_v21 = 0x80110021,
|
7543 |
#define POWERPC_SVR_55xx POWERPC_SVR_5567
|
7544 |
#if 0
|
7545 |
POWERPC_SVR_5533 = xxx,
|
7546 |
#endif
|
7547 |
#if 0
|
7548 |
POWERPC_SVR_5534 = xxx,
|
7549 |
#endif
|
7550 |
#if 0
|
7551 |
POWERPC_SVR_5553 = xxx,
|
7552 |
#endif
|
7553 |
#if 0
|
7554 |
POWERPC_SVR_5554 = xxx,
|
7555 |
#endif
|
7556 |
#if 0
|
7557 |
POWERPC_SVR_5561 = xxx,
|
7558 |
#endif
|
7559 |
#if 0
|
7560 |
POWERPC_SVR_5565 = xxx,
|
7561 |
#endif
|
7562 |
#if 0
|
7563 |
POWERPC_SVR_5566 = xxx,
|
7564 |
#endif
|
7565 |
#if 0
|
7566 |
POWERPC_SVR_5567 = xxx,
|
7567 |
#endif
|
7568 |
#if 0
|
7569 |
POWERPC_SVR_8313 = xxx,
|
7570 |
#endif
|
7571 |
#if 0
|
7572 |
POWERPC_SVR_8313E = xxx,
|
7573 |
#endif
|
7574 |
#if 0
|
7575 |
POWERPC_SVR_8314 = xxx,
|
7576 |
#endif
|
7577 |
#if 0
|
7578 |
POWERPC_SVR_8314E = xxx,
|
7579 |
#endif
|
7580 |
#if 0
|
7581 |
POWERPC_SVR_8315 = xxx,
|
7582 |
#endif
|
7583 |
#if 0
|
7584 |
POWERPC_SVR_8315E = xxx,
|
7585 |
#endif
|
7586 |
#if 0
|
7587 |
POWERPC_SVR_8321 = xxx,
|
7588 |
#endif
|
7589 |
#if 0
|
7590 |
POWERPC_SVR_8321E = xxx,
|
7591 |
#endif
|
7592 |
#if 0
|
7593 |
POWERPC_SVR_8323 = xxx,
|
7594 |
#endif
|
7595 |
#if 0
|
7596 |
POWERPC_SVR_8323E = xxx,
|
7597 |
#endif
|
7598 |
POWERPC_SVR_8343 = 0x80570010,
|
7599 |
POWERPC_SVR_8343A = 0x80570030,
|
7600 |
POWERPC_SVR_8343E = 0x80560010,
|
7601 |
POWERPC_SVR_8343EA = 0x80560030,
|
7602 |
#define POWERPC_SVR_8347 POWERPC_SVR_8347T
|
7603 |
POWERPC_SVR_8347P = 0x80550010, /* PBGA package */ |
7604 |
POWERPC_SVR_8347T = 0x80530010, /* TBGA package */ |
7605 |
#define POWERPC_SVR_8347A POWERPC_SVR_8347AT
|
7606 |
POWERPC_SVR_8347AP = 0x80550030, /* PBGA package */ |
7607 |
POWERPC_SVR_8347AT = 0x80530030, /* TBGA package */ |
7608 |
#define POWERPC_SVR_8347E POWERPC_SVR_8347ET
|
7609 |
POWERPC_SVR_8347EP = 0x80540010, /* PBGA package */ |
7610 |
POWERPC_SVR_8347ET = 0x80520010, /* TBGA package */ |
7611 |
#define POWERPC_SVR_8347EA POWERPC_SVR_8347EAT
|
7612 |
POWERPC_SVR_8347EAP = 0x80540030, /* PBGA package */ |
7613 |
POWERPC_SVR_8347EAT = 0x80520030, /* TBGA package */ |
7614 |
POWERPC_SVR_8349 = 0x80510010,
|
7615 |
POWERPC_SVR_8349A = 0x80510030,
|
7616 |
POWERPC_SVR_8349E = 0x80500010,
|
7617 |
POWERPC_SVR_8349EA = 0x80500030,
|
7618 |
#if 0
|
7619 |
POWERPC_SVR_8358E = xxx,
|
7620 |
#endif
|
7621 |
#if 0
|
7622 |
POWERPC_SVR_8360E = xxx,
|
7623 |
#endif
|
7624 |
#define POWERPC_SVR_E500 0x40000000 |
7625 |
POWERPC_SVR_8377 = 0x80C70010 | POWERPC_SVR_E500,
|
7626 |
POWERPC_SVR_8377E = 0x80C60010 | POWERPC_SVR_E500,
|
7627 |
POWERPC_SVR_8378 = 0x80C50010 | POWERPC_SVR_E500,
|
7628 |
POWERPC_SVR_8378E = 0x80C40010 | POWERPC_SVR_E500,
|
7629 |
POWERPC_SVR_8379 = 0x80C30010 | POWERPC_SVR_E500,
|
7630 |
POWERPC_SVR_8379E = 0x80C00010 | POWERPC_SVR_E500,
|
7631 |
#define POWERPC_SVR_8533 POWERPC_SVR_8533_v11
|
7632 |
POWERPC_SVR_8533_v10 = 0x80340010 | POWERPC_SVR_E500,
|
7633 |
POWERPC_SVR_8533_v11 = 0x80340011 | POWERPC_SVR_E500,
|
7634 |
#define POWERPC_SVR_8533E POWERPC_SVR_8533E_v11
|
7635 |
POWERPC_SVR_8533E_v10 = 0x803C0010 | POWERPC_SVR_E500,
|
7636 |
POWERPC_SVR_8533E_v11 = 0x803C0011 | POWERPC_SVR_E500,
|
7637 |
#define POWERPC_SVR_8540 POWERPC_SVR_8540_v21
|
7638 |
POWERPC_SVR_8540_v10 = 0x80300010 | POWERPC_SVR_E500,
|
7639 |
POWERPC_SVR_8540_v20 = 0x80300020 | POWERPC_SVR_E500,
|
7640 |
POWERPC_SVR_8540_v21 = 0x80300021 | POWERPC_SVR_E500,
|
7641 |
#define POWERPC_SVR_8541 POWERPC_SVR_8541_v11
|
7642 |
POWERPC_SVR_8541_v10 = 0x80720010 | POWERPC_SVR_E500,
|
7643 |
POWERPC_SVR_8541_v11 = 0x80720011 | POWERPC_SVR_E500,
|
7644 |
#define POWERPC_SVR_8541E POWERPC_SVR_8541E_v11
|
7645 |
POWERPC_SVR_8541E_v10 = 0x807A0010 | POWERPC_SVR_E500,
|
7646 |
POWERPC_SVR_8541E_v11 = 0x807A0011 | POWERPC_SVR_E500,
|
7647 |
#define POWERPC_SVR_8543 POWERPC_SVR_8543_v21
|
7648 |
POWERPC_SVR_8543_v10 = 0x80320010 | POWERPC_SVR_E500,
|
7649 |
POWERPC_SVR_8543_v11 = 0x80320011 | POWERPC_SVR_E500,
|
7650 |
POWERPC_SVR_8543_v20 = 0x80320020 | POWERPC_SVR_E500,
|
7651 |
POWERPC_SVR_8543_v21 = 0x80320021 | POWERPC_SVR_E500,
|
7652 |
#define POWERPC_SVR_8543E POWERPC_SVR_8543E_v21
|
7653 |
POWERPC_SVR_8543E_v10 = 0x803A0010 | POWERPC_SVR_E500,
|
7654 |
POWERPC_SVR_8543E_v11 = 0x803A0011 | POWERPC_SVR_E500,
|
7655 |
POWERPC_SVR_8543E_v20 = 0x803A0020 | POWERPC_SVR_E500,
|
7656 |
POWERPC_SVR_8543E_v21 = 0x803A0021 | POWERPC_SVR_E500,
|
7657 |
#define POWERPC_SVR_8544 POWERPC_SVR_8544_v11
|
7658 |
POWERPC_SVR_8544_v10 = 0x80340110 | POWERPC_SVR_E500,
|
7659 |
POWERPC_SVR_8544_v11 = 0x80340111 | POWERPC_SVR_E500,
|
7660 |
#define POWERPC_SVR_8544E POWERPC_SVR_8544E_v11
|
7661 |
POWERPC_SVR_8544E_v10 = 0x803C0110 | POWERPC_SVR_E500,
|
7662 |
POWERPC_SVR_8544E_v11 = 0x803C0111 | POWERPC_SVR_E500,
|
7663 |
#define POWERPC_SVR_8545 POWERPC_SVR_8545_v21
|
7664 |
POWERPC_SVR_8545_v20 = 0x80310220 | POWERPC_SVR_E500,
|
7665 |
POWERPC_SVR_8545_v21 = 0x80310221 | POWERPC_SVR_E500,
|
7666 |
#define POWERPC_SVR_8545E POWERPC_SVR_8545E_v21
|
7667 |
POWERPC_SVR_8545E_v20 = 0x80390220 | POWERPC_SVR_E500,
|
7668 |
POWERPC_SVR_8545E_v21 = 0x80390221 | POWERPC_SVR_E500,
|
7669 |
#define POWERPC_SVR_8547E POWERPC_SVR_8547E_v21
|
7670 |
POWERPC_SVR_8547E_v20 = 0x80390120 | POWERPC_SVR_E500,
|
7671 |
POWERPC_SVR_8547E_v21 = 0x80390121 | POWERPC_SVR_E500,
|
7672 |
#define POWERPC_SVR_8548 POWERPC_SVR_8548_v21
|
7673 |
POWERPC_SVR_8548_v10 = 0x80310010 | POWERPC_SVR_E500,
|
7674 |
POWERPC_SVR_8548_v11 = 0x80310011 | POWERPC_SVR_E500,
|
7675 |
POWERPC_SVR_8548_v20 = 0x80310020 | POWERPC_SVR_E500,
|
7676 |
POWERPC_SVR_8548_v21 = 0x80310021 | POWERPC_SVR_E500,
|
7677 |
#define POWERPC_SVR_8548E POWERPC_SVR_8548E_v21
|
7678 |
POWERPC_SVR_8548E_v10 = 0x80390010 | POWERPC_SVR_E500,
|
7679 |
POWERPC_SVR_8548E_v11 = 0x80390011 | POWERPC_SVR_E500,
|
7680 |
POWERPC_SVR_8548E_v20 = 0x80390020 | POWERPC_SVR_E500,
|
7681 |
POWERPC_SVR_8548E_v21 = 0x80390021 | POWERPC_SVR_E500,
|
7682 |
#define POWERPC_SVR_8555 POWERPC_SVR_8555_v11
|
7683 |
POWERPC_SVR_8555_v10 = 0x80710010 | POWERPC_SVR_E500,
|
7684 |
POWERPC_SVR_8555_v11 = 0x80710011 | POWERPC_SVR_E500,
|
7685 |
#define POWERPC_SVR_8555E POWERPC_SVR_8555_v11
|
7686 |
POWERPC_SVR_8555E_v10 = 0x80790010 | POWERPC_SVR_E500,
|
7687 |
POWERPC_SVR_8555E_v11 = 0x80790011 | POWERPC_SVR_E500,
|
7688 |
#define POWERPC_SVR_8560 POWERPC_SVR_8560_v21
|
7689 |
POWERPC_SVR_8560_v10 = 0x80700010 | POWERPC_SVR_E500,
|
7690 |
POWERPC_SVR_8560_v20 = 0x80700020 | POWERPC_SVR_E500,
|
7691 |
POWERPC_SVR_8560_v21 = 0x80700021 | POWERPC_SVR_E500,
|
7692 |
POWERPC_SVR_8567 = 0x80750111 | POWERPC_SVR_E500,
|
7693 |
POWERPC_SVR_8567E = 0x807D0111 | POWERPC_SVR_E500,
|
7694 |
POWERPC_SVR_8568 = 0x80750011 | POWERPC_SVR_E500,
|
7695 |
POWERPC_SVR_8568E = 0x807D0011 | POWERPC_SVR_E500,
|
7696 |
POWERPC_SVR_8572 = 0x80E00010 | POWERPC_SVR_E500,
|
7697 |
POWERPC_SVR_8572E = 0x80E80010 | POWERPC_SVR_E500,
|
7698 |
#if 0
|
7699 |
POWERPC_SVR_8610 = xxx,
|
7700 |
#endif
|
7701 |
POWERPC_SVR_8641 = 0x80900021,
|
7702 |
POWERPC_SVR_8641D = 0x80900121,
|
7703 |
}; |
7704 |
|
7705 |
/*****************************************************************************/
|
7706 |
/* PowerPC CPU definitions */
|
7707 |
#define POWERPC_DEF_SVR(_name, _pvr, _svr, _type) \
|
7708 |
{ \ |
7709 |
.name = _name, \ |
7710 |
.pvr = _pvr, \ |
7711 |
.svr = _svr, \ |
7712 |
.insns_flags = glue(POWERPC_INSNS_,_type), \ |
7713 |
.insns_flags2 = glue(POWERPC_INSNS2_,_type), \ |
7714 |
.msr_mask = glue(POWERPC_MSRM_,_type), \ |
7715 |
.mmu_model = glue(POWERPC_MMU_,_type), \ |
7716 |
.excp_model = glue(POWERPC_EXCP_,_type), \ |
7717 |
.bus_model = glue(POWERPC_INPUT_,_type), \ |
7718 |
.bfd_mach = glue(POWERPC_BFDM_,_type), \ |
7719 |
.flags = glue(POWERPC_FLAG_,_type), \ |
7720 |
.init_proc = &glue(init_proc_,_type), \ |
7721 |
.check_pow = &glue(check_pow_,_type), \ |
7722 |
} |
7723 |
#define POWERPC_DEF(_name, _pvr, _type) \
|
7724 |
POWERPC_DEF_SVR(_name, _pvr, POWERPC_SVR_NONE, _type) |
7725 |
|
7726 |
static const ppc_def_t ppc_defs[] = { |
7727 |
/* Embedded PowerPC */
|
7728 |
/* PowerPC 401 family */
|
7729 |
/* Generic PowerPC 401 */
|
7730 |
POWERPC_DEF("401", CPU_POWERPC_401, 401), |
7731 |
/* PowerPC 401 cores */
|
7732 |
/* PowerPC 401A1 */
|
7733 |
POWERPC_DEF("401A1", CPU_POWERPC_401A1, 401), |
7734 |
/* PowerPC 401B2 */
|
7735 |
POWERPC_DEF("401B2", CPU_POWERPC_401B2, 401x2), |
7736 |
#if defined (TODO)
|
7737 |
/* PowerPC 401B3 */
|
7738 |
POWERPC_DEF("401B3", CPU_POWERPC_401B3, 401x3), |
7739 |
#endif
|
7740 |
/* PowerPC 401C2 */
|
7741 |
POWERPC_DEF("401C2", CPU_POWERPC_401C2, 401x2), |
7742 |
/* PowerPC 401D2 */
|
7743 |
POWERPC_DEF("401D2", CPU_POWERPC_401D2, 401x2), |
7744 |
/* PowerPC 401E2 */
|
7745 |
POWERPC_DEF("401E2", CPU_POWERPC_401E2, 401x2), |
7746 |
/* PowerPC 401F2 */
|
7747 |
POWERPC_DEF("401F2", CPU_POWERPC_401F2, 401x2), |
7748 |
/* PowerPC 401G2 */
|
7749 |
/* XXX: to be checked */
|
7750 |
POWERPC_DEF("401G2", CPU_POWERPC_401G2, 401x2), |
7751 |
/* PowerPC 401 microcontrolers */
|
7752 |
#if defined (TODO)
|
7753 |
/* PowerPC 401GF */
|
7754 |
POWERPC_DEF("401GF", CPU_POWERPC_401GF, 401), |
7755 |
#endif
|
7756 |
/* IOP480 (401 microcontroler) */
|
7757 |
POWERPC_DEF("IOP480", CPU_POWERPC_IOP480, IOP480),
|
7758 |
/* IBM Processor for Network Resources */
|
7759 |
POWERPC_DEF("Cobra", CPU_POWERPC_COBRA, 401), |
7760 |
#if defined (TODO)
|
7761 |
POWERPC_DEF("Xipchip", CPU_POWERPC_XIPCHIP, 401), |
7762 |
#endif
|
7763 |
/* PowerPC 403 family */
|
7764 |
/* Generic PowerPC 403 */
|
7765 |
POWERPC_DEF("403", CPU_POWERPC_403, 403), |
7766 |
/* PowerPC 403 microcontrolers */
|
7767 |
/* PowerPC 403 GA */
|
7768 |
POWERPC_DEF("403GA", CPU_POWERPC_403GA, 403), |
7769 |
/* PowerPC 403 GB */
|
7770 |
POWERPC_DEF("403GB", CPU_POWERPC_403GB, 403), |
7771 |
/* PowerPC 403 GC */
|
7772 |
POWERPC_DEF("403GC", CPU_POWERPC_403GC, 403), |
7773 |
/* PowerPC 403 GCX */
|
7774 |
POWERPC_DEF("403GCX", CPU_POWERPC_403GCX, 403GCX), |
7775 |
#if defined (TODO)
|
7776 |
/* PowerPC 403 GP */
|
7777 |
POWERPC_DEF("403GP", CPU_POWERPC_403GP, 403), |
7778 |
#endif
|
7779 |
/* PowerPC 405 family */
|
7780 |
/* Generic PowerPC 405 */
|
7781 |
POWERPC_DEF("405", CPU_POWERPC_405, 405), |
7782 |
/* PowerPC 405 cores */
|
7783 |
#if defined (TODO)
|
7784 |
/* PowerPC 405 A3 */
|
7785 |
POWERPC_DEF("405A3", CPU_POWERPC_405A3, 405), |
7786 |
#endif
|
7787 |
#if defined (TODO)
|
7788 |
/* PowerPC 405 A4 */
|
7789 |
POWERPC_DEF("405A4", CPU_POWERPC_405A4, 405), |
7790 |
#endif
|
7791 |
#if defined (TODO)
|
7792 |
/* PowerPC 405 B3 */
|
7793 |
POWERPC_DEF("405B3", CPU_POWERPC_405B3, 405), |
7794 |
#endif
|
7795 |
#if defined (TODO)
|
7796 |
/* PowerPC 405 B4 */
|
7797 |
POWERPC_DEF("405B4", CPU_POWERPC_405B4, 405), |
7798 |
#endif
|
7799 |
#if defined (TODO)
|
7800 |
/* PowerPC 405 C3 */
|
7801 |
POWERPC_DEF("405C3", CPU_POWERPC_405C3, 405), |
7802 |
#endif
|
7803 |
#if defined (TODO)
|
7804 |
/* PowerPC 405 C4 */
|
7805 |
POWERPC_DEF("405C4", CPU_POWERPC_405C4, 405), |
7806 |
#endif
|
7807 |
/* PowerPC 405 D2 */
|
7808 |
POWERPC_DEF("405D2", CPU_POWERPC_405D2, 405), |
7809 |
#if defined (TODO)
|
7810 |
/* PowerPC 405 D3 */
|
7811 |
POWERPC_DEF("405D3", CPU_POWERPC_405D3, 405), |
7812 |
#endif
|
7813 |
/* PowerPC 405 D4 */
|
7814 |
POWERPC_DEF("405D4", CPU_POWERPC_405D4, 405), |
7815 |
#if defined (TODO)
|
7816 |
/* PowerPC 405 D5 */
|
7817 |
POWERPC_DEF("405D5", CPU_POWERPC_405D5, 405), |
7818 |
#endif
|
7819 |
#if defined (TODO)
|
7820 |
/* PowerPC 405 E4 */
|
7821 |
POWERPC_DEF("405E4", CPU_POWERPC_405E4, 405), |
7822 |
#endif
|
7823 |
#if defined (TODO)
|
7824 |
/* PowerPC 405 F4 */
|
7825 |
POWERPC_DEF("405F4", CPU_POWERPC_405F4, 405), |
7826 |
#endif
|
7827 |
#if defined (TODO)
|
7828 |
/* PowerPC 405 F5 */
|
7829 |
POWERPC_DEF("405F5", CPU_POWERPC_405F5, 405), |
7830 |
#endif
|
7831 |
#if defined (TODO)
|
7832 |
/* PowerPC 405 F6 */
|
7833 |
POWERPC_DEF("405F6", CPU_POWERPC_405F6, 405), |
7834 |
#endif
|
7835 |
/* PowerPC 405 microcontrolers */
|
7836 |
/* PowerPC 405 CR */
|
7837 |
POWERPC_DEF("405CR", CPU_POWERPC_405CR, 405), |
7838 |
/* PowerPC 405 CRa */
|
7839 |
POWERPC_DEF("405CRa", CPU_POWERPC_405CRa, 405), |
7840 |
/* PowerPC 405 CRb */
|
7841 |
POWERPC_DEF("405CRb", CPU_POWERPC_405CRb, 405), |
7842 |
/* PowerPC 405 CRc */
|
7843 |
POWERPC_DEF("405CRc", CPU_POWERPC_405CRc, 405), |
7844 |
/* PowerPC 405 EP */
|
7845 |
POWERPC_DEF("405EP", CPU_POWERPC_405EP, 405), |
7846 |
#if defined(TODO)
|
7847 |
/* PowerPC 405 EXr */
|
7848 |
POWERPC_DEF("405EXr", CPU_POWERPC_405EXr, 405), |
7849 |
#endif
|
7850 |
/* PowerPC 405 EZ */
|
7851 |
POWERPC_DEF("405EZ", CPU_POWERPC_405EZ, 405), |
7852 |
#if defined(TODO)
|
7853 |
/* PowerPC 405 FX */
|
7854 |
POWERPC_DEF("405FX", CPU_POWERPC_405FX, 405), |
7855 |
#endif
|
7856 |
/* PowerPC 405 GP */
|
7857 |
POWERPC_DEF("405GP", CPU_POWERPC_405GP, 405), |
7858 |
/* PowerPC 405 GPa */
|
7859 |
POWERPC_DEF("405GPa", CPU_POWERPC_405GPa, 405), |
7860 |
/* PowerPC 405 GPb */
|
7861 |
POWERPC_DEF("405GPb", CPU_POWERPC_405GPb, 405), |
7862 |
/* PowerPC 405 GPc */
|
7863 |
POWERPC_DEF("405GPc", CPU_POWERPC_405GPc, 405), |
7864 |
/* PowerPC 405 GPd */
|
7865 |
POWERPC_DEF("405GPd", CPU_POWERPC_405GPd, 405), |
7866 |
/* PowerPC 405 GPe */
|
7867 |
POWERPC_DEF("405GPe", CPU_POWERPC_405GPe, 405), |
7868 |
/* PowerPC 405 GPR */
|
7869 |
POWERPC_DEF("405GPR", CPU_POWERPC_405GPR, 405), |
7870 |
#if defined(TODO)
|
7871 |
/* PowerPC 405 H */
|
7872 |
POWERPC_DEF("405H", CPU_POWERPC_405H, 405), |
7873 |
#endif
|
7874 |
#if defined(TODO)
|
7875 |
/* PowerPC 405 L */
|
7876 |
POWERPC_DEF("405L", CPU_POWERPC_405L, 405), |
7877 |
#endif
|
7878 |
/* PowerPC 405 LP */
|
7879 |
POWERPC_DEF("405LP", CPU_POWERPC_405LP, 405), |
7880 |
#if defined(TODO)
|
7881 |
/* PowerPC 405 PM */
|
7882 |
POWERPC_DEF("405PM", CPU_POWERPC_405PM, 405), |
7883 |
#endif
|
7884 |
#if defined(TODO)
|
7885 |
/* PowerPC 405 PS */
|
7886 |
POWERPC_DEF("405PS", CPU_POWERPC_405PS, 405), |
7887 |
#endif
|
7888 |
#if defined(TODO)
|
7889 |
/* PowerPC 405 S */
|
7890 |
POWERPC_DEF("405S", CPU_POWERPC_405S, 405), |
7891 |
#endif
|
7892 |
/* Npe405 H */
|
7893 |
POWERPC_DEF("Npe405H", CPU_POWERPC_NPE405H, 405), |
7894 |
/* Npe405 H2 */
|
7895 |
POWERPC_DEF("Npe405H2", CPU_POWERPC_NPE405H2, 405), |
7896 |
/* Npe405 L */
|
7897 |
POWERPC_DEF("Npe405L", CPU_POWERPC_NPE405L, 405), |
7898 |
/* Npe4GS3 */
|
7899 |
POWERPC_DEF("Npe4GS3", CPU_POWERPC_NPE4GS3, 405), |
7900 |
#if defined (TODO)
|
7901 |
POWERPC_DEF("Npcxx1", CPU_POWERPC_NPCxx1, 405), |
7902 |
#endif
|
7903 |
#if defined (TODO)
|
7904 |
POWERPC_DEF("Npr161", CPU_POWERPC_NPR161, 405), |
7905 |
#endif
|
7906 |
#if defined (TODO)
|
7907 |
/* PowerPC LC77700 (Sanyo) */
|
7908 |
POWERPC_DEF("LC77700", CPU_POWERPC_LC77700, 405), |
7909 |
#endif
|
7910 |
/* PowerPC 401/403/405 based set-top-box microcontrolers */
|
7911 |
#if defined (TODO)
|
7912 |
/* STB010000 */
|
7913 |
POWERPC_DEF("STB01000", CPU_POWERPC_STB01000, 401x2), |
7914 |
#endif
|
7915 |
#if defined (TODO)
|
7916 |
/* STB01010 */
|
7917 |
POWERPC_DEF("STB01010", CPU_POWERPC_STB01010, 401x2), |
7918 |
#endif
|
7919 |
#if defined (TODO)
|
7920 |
/* STB0210 */
|
7921 |
POWERPC_DEF("STB0210", CPU_POWERPC_STB0210, 401x3), |
7922 |
#endif
|
7923 |
/* STB03xx */
|
7924 |
POWERPC_DEF("STB03", CPU_POWERPC_STB03, 405), |
7925 |
#if defined (TODO)
|
7926 |
/* STB043x */
|
7927 |
POWERPC_DEF("STB043", CPU_POWERPC_STB043, 405), |
7928 |
#endif
|
7929 |
#if defined (TODO)
|
7930 |
/* STB045x */
|
7931 |
POWERPC_DEF("STB045", CPU_POWERPC_STB045, 405), |
7932 |
#endif
|
7933 |
/* STB04xx */
|
7934 |
POWERPC_DEF("STB04", CPU_POWERPC_STB04, 405), |
7935 |
/* STB25xx */
|
7936 |
POWERPC_DEF("STB25", CPU_POWERPC_STB25, 405), |
7937 |
#if defined (TODO)
|
7938 |
/* STB130 */
|
7939 |
POWERPC_DEF("STB130", CPU_POWERPC_STB130, 405), |
7940 |
#endif
|
7941 |
/* Xilinx PowerPC 405 cores */
|
7942 |
POWERPC_DEF("x2vp4", CPU_POWERPC_X2VP4, 405), |
7943 |
POWERPC_DEF("x2vp7", CPU_POWERPC_X2VP7, 405), |
7944 |
POWERPC_DEF("x2vp20", CPU_POWERPC_X2VP20, 405), |
7945 |
POWERPC_DEF("x2vp50", CPU_POWERPC_X2VP50, 405), |
7946 |
#if defined (TODO)
|
7947 |
/* Zarlink ZL10310 */
|
7948 |
POWERPC_DEF("zl10310", CPU_POWERPC_ZL10310, 405), |
7949 |
#endif
|
7950 |
#if defined (TODO)
|
7951 |
/* Zarlink ZL10311 */
|
7952 |
POWERPC_DEF("zl10311", CPU_POWERPC_ZL10311, 405), |
7953 |
#endif
|
7954 |
#if defined (TODO)
|
7955 |
/* Zarlink ZL10320 */
|
7956 |
POWERPC_DEF("zl10320", CPU_POWERPC_ZL10320, 405), |
7957 |
#endif
|
7958 |
#if defined (TODO)
|
7959 |
/* Zarlink ZL10321 */
|
7960 |
POWERPC_DEF("zl10321", CPU_POWERPC_ZL10321, 405), |
7961 |
#endif
|
7962 |
/* PowerPC 440 family */
|
7963 |
#if defined(TODO_USER_ONLY)
|
7964 |
/* Generic PowerPC 440 */
|
7965 |
POWERPC_DEF("440", CPU_POWERPC_440, 440GP), |
7966 |
#endif
|
7967 |
/* PowerPC 440 cores */
|
7968 |
#if defined (TODO)
|
7969 |
/* PowerPC 440 A4 */
|
7970 |
POWERPC_DEF("440A4", CPU_POWERPC_440A4, 440x4), |
7971 |
#endif
|
7972 |
/* PowerPC 440 Xilinx 5 */
|
7973 |
POWERPC_DEF("440-Xilinx", CPU_POWERPC_440_XILINX, 440x5), |
7974 |
#if defined (TODO)
|
7975 |
/* PowerPC 440 A5 */
|
7976 |
POWERPC_DEF("440A5", CPU_POWERPC_440A5, 440x5), |
7977 |
#endif
|
7978 |
#if defined (TODO)
|
7979 |
/* PowerPC 440 B4 */
|
7980 |
POWERPC_DEF("440B4", CPU_POWERPC_440B4, 440x4), |
7981 |
#endif
|
7982 |
#if defined (TODO)
|
7983 |
/* PowerPC 440 G4 */
|
7984 |
POWERPC_DEF("440G4", CPU_POWERPC_440G4, 440x4), |
7985 |
#endif
|
7986 |
#if defined (TODO)
|
7987 |
/* PowerPC 440 F5 */
|
7988 |
POWERPC_DEF("440F5", CPU_POWERPC_440F5, 440x5), |
7989 |
#endif
|
7990 |
#if defined (TODO)
|
7991 |
/* PowerPC 440 G5 */
|
7992 |
POWERPC_DEF("440G5", CPU_POWERPC_440G5, 440x5), |
7993 |
#endif
|
7994 |
#if defined (TODO)
|
7995 |
/* PowerPC 440H4 */
|
7996 |
POWERPC_DEF("440H4", CPU_POWERPC_440H4, 440x4), |
7997 |
#endif
|
7998 |
#if defined (TODO)
|
7999 |
/* PowerPC 440H6 */
|
8000 |
POWERPC_DEF("440H6", CPU_POWERPC_440H6, 440Gx5), |
8001 |
#endif
|
8002 |
/* PowerPC 440 microcontrolers */
|
8003 |
/* PowerPC 440 EP */
|
8004 |
POWERPC_DEF("440EP", CPU_POWERPC_440EP, 440EP), |
8005 |
/* PowerPC 440 EPa */
|
8006 |
POWERPC_DEF("440EPa", CPU_POWERPC_440EPa, 440EP), |
8007 |
/* PowerPC 440 EPb */
|
8008 |
POWERPC_DEF("440EPb", CPU_POWERPC_440EPb, 440EP), |
8009 |
/* PowerPC 440 EPX */
|
8010 |
POWERPC_DEF("440EPX", CPU_POWERPC_440EPX, 440EP), |
8011 |
#if defined(TODO_USER_ONLY)
|
8012 |
/* PowerPC 440 GP */
|
8013 |
POWERPC_DEF("440GP", CPU_POWERPC_440GP, 440GP), |
8014 |
#endif
|
8015 |
#if defined(TODO_USER_ONLY)
|
8016 |
/* PowerPC 440 GPb */
|
8017 |
POWERPC_DEF("440GPb", CPU_POWERPC_440GPb, 440GP), |
8018 |
#endif
|
8019 |
#if defined(TODO_USER_ONLY)
|
8020 |
/* PowerPC 440 GPc */
|
8021 |
POWERPC_DEF("440GPc", CPU_POWERPC_440GPc, 440GP), |
8022 |
#endif
|
8023 |
#if defined(TODO_USER_ONLY)
|
8024 |
/* PowerPC 440 GR */
|
8025 |
POWERPC_DEF("440GR", CPU_POWERPC_440GR, 440x5), |
8026 |
#endif
|
8027 |
#if defined(TODO_USER_ONLY)
|
8028 |
/* PowerPC 440 GRa */
|
8029 |
POWERPC_DEF("440GRa", CPU_POWERPC_440GRa, 440x5), |
8030 |
#endif
|
8031 |
#if defined(TODO_USER_ONLY)
|
8032 |
/* PowerPC 440 GRX */
|
8033 |
POWERPC_DEF("440GRX", CPU_POWERPC_440GRX, 440x5), |
8034 |
#endif
|
8035 |
#if defined(TODO_USER_ONLY)
|
8036 |
/* PowerPC 440 GX */
|
8037 |
POWERPC_DEF("440GX", CPU_POWERPC_440GX, 440EP), |
8038 |
#endif
|
8039 |
#if defined(TODO_USER_ONLY)
|
8040 |
/* PowerPC 440 GXa */
|
8041 |
POWERPC_DEF("440GXa", CPU_POWERPC_440GXa, 440EP), |
8042 |
#endif
|
8043 |
#if defined(TODO_USER_ONLY)
|
8044 |
/* PowerPC 440 GXb */
|
8045 |
POWERPC_DEF("440GXb", CPU_POWERPC_440GXb, 440EP), |
8046 |
#endif
|
8047 |
#if defined(TODO_USER_ONLY)
|
8048 |
/* PowerPC 440 GXc */
|
8049 |
POWERPC_DEF("440GXc", CPU_POWERPC_440GXc, 440EP), |
8050 |
#endif
|
8051 |
#if defined(TODO_USER_ONLY)
|
8052 |
/* PowerPC 440 GXf */
|
8053 |
POWERPC_DEF("440GXf", CPU_POWERPC_440GXf, 440EP), |
8054 |
#endif
|
8055 |
#if defined(TODO)
|
8056 |
/* PowerPC 440 S */
|
8057 |
POWERPC_DEF("440S", CPU_POWERPC_440S, 440), |
8058 |
#endif
|
8059 |
#if defined(TODO_USER_ONLY)
|
8060 |
/* PowerPC 440 SP */
|
8061 |
POWERPC_DEF("440SP", CPU_POWERPC_440SP, 440EP), |
8062 |
#endif
|
8063 |
#if defined(TODO_USER_ONLY)
|
8064 |
/* PowerPC 440 SP2 */
|
8065 |
POWERPC_DEF("440SP2", CPU_POWERPC_440SP2, 440EP), |
8066 |
#endif
|
8067 |
#if defined(TODO_USER_ONLY)
|
8068 |
/* PowerPC 440 SPE */
|
8069 |
POWERPC_DEF("440SPE", CPU_POWERPC_440SPE, 440EP), |
8070 |
#endif
|
8071 |
/* PowerPC 460 family */
|
8072 |
#if defined (TODO)
|
8073 |
/* Generic PowerPC 464 */
|
8074 |
POWERPC_DEF("464", CPU_POWERPC_464, 460), |
8075 |
#endif
|
8076 |
/* PowerPC 464 microcontrolers */
|
8077 |
#if defined (TODO)
|
8078 |
/* PowerPC 464H90 */
|
8079 |
POWERPC_DEF("464H90", CPU_POWERPC_464H90, 460), |
8080 |
#endif
|
8081 |
#if defined (TODO)
|
8082 |
/* PowerPC 464H90F */
|
8083 |
POWERPC_DEF("464H90F", CPU_POWERPC_464H90F, 460F), |
8084 |
#endif
|
8085 |
/* Freescale embedded PowerPC cores */
|
8086 |
/* MPC5xx family (aka RCPU) */
|
8087 |
#if defined(TODO_USER_ONLY)
|
8088 |
/* Generic MPC5xx core */
|
8089 |
POWERPC_DEF("MPC5xx", CPU_POWERPC_MPC5xx, MPC5xx),
|
8090 |
#endif
|
8091 |
#if defined(TODO_USER_ONLY)
|
8092 |
/* Codename for MPC5xx core */
|
8093 |
POWERPC_DEF("RCPU", CPU_POWERPC_MPC5xx, MPC5xx),
|
8094 |
#endif
|
8095 |
/* MPC5xx microcontrollers */
|
8096 |
#if defined(TODO_USER_ONLY)
|
8097 |
/* MGT560 */
|
8098 |
POWERPC_DEF("MGT560", CPU_POWERPC_MGT560, MPC5xx),
|
8099 |
#endif
|
8100 |
#if defined(TODO_USER_ONLY)
|
8101 |
/* MPC509 */
|
8102 |
POWERPC_DEF("MPC509", CPU_POWERPC_MPC509, MPC5xx),
|
8103 |
#endif
|
8104 |
#if defined(TODO_USER_ONLY)
|
8105 |
/* MPC533 */
|
8106 |
POWERPC_DEF("MPC533", CPU_POWERPC_MPC533, MPC5xx),
|
8107 |
#endif
|
8108 |
#if defined(TODO_USER_ONLY)
|
8109 |
/* MPC534 */
|
8110 |
POWERPC_DEF("MPC534", CPU_POWERPC_MPC534, MPC5xx),
|
8111 |
#endif
|
8112 |
#if defined(TODO_USER_ONLY)
|
8113 |
/* MPC555 */
|
8114 |
POWERPC_DEF("MPC555", CPU_POWERPC_MPC555, MPC5xx),
|
8115 |
#endif
|
8116 |
#if defined(TODO_USER_ONLY)
|
8117 |
/* MPC556 */
|
8118 |
POWERPC_DEF("MPC556", CPU_POWERPC_MPC556, MPC5xx),
|
8119 |
#endif
|
8120 |
#if defined(TODO_USER_ONLY)
|
8121 |
/* MPC560 */
|
8122 |
POWERPC_DEF("MPC560", CPU_POWERPC_MPC560, MPC5xx),
|
8123 |
#endif
|
8124 |
#if defined(TODO_USER_ONLY)
|
8125 |
/* MPC561 */
|
8126 |
POWERPC_DEF("MPC561", CPU_POWERPC_MPC561, MPC5xx),
|
8127 |
#endif
|
8128 |
#if defined(TODO_USER_ONLY)
|
8129 |
/* MPC562 */
|
8130 |
POWERPC_DEF("MPC562", CPU_POWERPC_MPC562, MPC5xx),
|
8131 |
#endif
|
8132 |
#if defined(TODO_USER_ONLY)
|
8133 |
/* MPC563 */
|
8134 |
POWERPC_DEF("MPC563", CPU_POWERPC_MPC563, MPC5xx),
|
8135 |
#endif
|
8136 |
#if defined(TODO_USER_ONLY)
|
8137 |
/* MPC564 */
|
8138 |
POWERPC_DEF("MPC564", CPU_POWERPC_MPC564, MPC5xx),
|
8139 |
#endif
|
8140 |
#if defined(TODO_USER_ONLY)
|
8141 |
/* MPC565 */
|
8142 |
POWERPC_DEF("MPC565", CPU_POWERPC_MPC565, MPC5xx),
|
8143 |
#endif
|
8144 |
#if defined(TODO_USER_ONLY)
|
8145 |
/* MPC566 */
|
8146 |
POWERPC_DEF("MPC566", CPU_POWERPC_MPC566, MPC5xx),
|
8147 |
#endif
|
8148 |
/* MPC8xx family (aka PowerQUICC) */
|
8149 |
#if defined(TODO_USER_ONLY)
|
8150 |
/* Generic MPC8xx core */
|
8151 |
POWERPC_DEF("MPC8xx", CPU_POWERPC_MPC8xx, MPC8xx),
|
8152 |
#endif
|
8153 |
#if defined(TODO_USER_ONLY)
|
8154 |
/* Codename for MPC8xx core */
|
8155 |
POWERPC_DEF("PowerQUICC", CPU_POWERPC_MPC8xx, MPC8xx),
|
8156 |
#endif
|
8157 |
/* MPC8xx microcontrollers */
|
8158 |
#if defined(TODO_USER_ONLY)
|
8159 |
/* MGT823 */
|
8160 |
POWERPC_DEF("MGT823", CPU_POWERPC_MGT823, MPC8xx),
|
8161 |
#endif
|
8162 |
#if defined(TODO_USER_ONLY)
|
8163 |
/* MPC821 */
|
8164 |
POWERPC_DEF("MPC821", CPU_POWERPC_MPC821, MPC8xx),
|
8165 |
#endif
|
8166 |
#if defined(TODO_USER_ONLY)
|
8167 |
/* MPC823 */
|
8168 |
POWERPC_DEF("MPC823", CPU_POWERPC_MPC823, MPC8xx),
|
8169 |
#endif
|
8170 |
#if defined(TODO_USER_ONLY)
|
8171 |
/* MPC850 */
|
8172 |
POWERPC_DEF("MPC850", CPU_POWERPC_MPC850, MPC8xx),
|
8173 |
#endif
|
8174 |
#if defined(TODO_USER_ONLY)
|
8175 |
/* MPC852T */
|
8176 |
POWERPC_DEF("MPC852T", CPU_POWERPC_MPC852T, MPC8xx),
|
8177 |
#endif
|
8178 |
#if defined(TODO_USER_ONLY)
|
8179 |
/* MPC855T */
|
8180 |
POWERPC_DEF("MPC855T", CPU_POWERPC_MPC855T, MPC8xx),
|
8181 |
#endif
|
8182 |
#if defined(TODO_USER_ONLY)
|
8183 |
/* MPC857 */
|
8184 |
POWERPC_DEF("MPC857", CPU_POWERPC_MPC857, MPC8xx),
|
8185 |
#endif
|
8186 |
#if defined(TODO_USER_ONLY)
|
8187 |
/* MPC859 */
|
8188 |
POWERPC_DEF("MPC859", CPU_POWERPC_MPC859, MPC8xx),
|
8189 |
#endif
|
8190 |
#if defined(TODO_USER_ONLY)
|
8191 |
/* MPC860 */
|
8192 |
POWERPC_DEF("MPC860", CPU_POWERPC_MPC860, MPC8xx),
|
8193 |
#endif
|
8194 |
#if defined(TODO_USER_ONLY)
|
8195 |
/* MPC862 */
|
8196 |
POWERPC_DEF("MPC862", CPU_POWERPC_MPC862, MPC8xx),
|
8197 |
#endif
|
8198 |
#if defined(TODO_USER_ONLY)
|
8199 |
/* MPC866 */
|
8200 |
POWERPC_DEF("MPC866", CPU_POWERPC_MPC866, MPC8xx),
|
8201 |
#endif
|
8202 |
#if defined(TODO_USER_ONLY)
|
8203 |
/* MPC870 */
|
8204 |
POWERPC_DEF("MPC870", CPU_POWERPC_MPC870, MPC8xx),
|
8205 |
#endif
|
8206 |
#if defined(TODO_USER_ONLY)
|
8207 |
/* MPC875 */
|
8208 |
POWERPC_DEF("MPC875", CPU_POWERPC_MPC875, MPC8xx),
|
8209 |
#endif
|
8210 |
#if defined(TODO_USER_ONLY)
|
8211 |
/* MPC880 */
|
8212 |
POWERPC_DEF("MPC880", CPU_POWERPC_MPC880, MPC8xx),
|
8213 |
#endif
|
8214 |
#if defined(TODO_USER_ONLY)
|
8215 |
/* MPC885 */
|
8216 |
POWERPC_DEF("MPC885", CPU_POWERPC_MPC885, MPC8xx),
|
8217 |
#endif
|
8218 |
/* MPC82xx family (aka PowerQUICC-II) */
|
8219 |
/* Generic MPC52xx core */
|
8220 |
POWERPC_DEF_SVR("MPC52xx",
|
8221 |
CPU_POWERPC_MPC52xx, POWERPC_SVR_52xx, G2LE), |
8222 |
/* Generic MPC82xx core */
|
8223 |
POWERPC_DEF("MPC82xx", CPU_POWERPC_MPC82xx, G2),
|
8224 |
/* Codename for MPC82xx */
|
8225 |
POWERPC_DEF("PowerQUICC-II", CPU_POWERPC_MPC82xx, G2),
|
8226 |
/* PowerPC G2 core */
|
8227 |
POWERPC_DEF("G2", CPU_POWERPC_G2, G2),
|
8228 |
/* PowerPC G2 H4 core */
|
8229 |
POWERPC_DEF("G2H4", CPU_POWERPC_G2H4, G2),
|
8230 |
/* PowerPC G2 GP core */
|
8231 |
POWERPC_DEF("G2GP", CPU_POWERPC_G2gp, G2),
|
8232 |
/* PowerPC G2 LS core */
|
8233 |
POWERPC_DEF("G2LS", CPU_POWERPC_G2ls, G2),
|
8234 |
/* PowerPC G2 HiP3 core */
|
8235 |
POWERPC_DEF("G2HiP3", CPU_POWERPC_G2_HIP3, G2),
|
8236 |
/* PowerPC G2 HiP4 core */
|
8237 |
POWERPC_DEF("G2HiP4", CPU_POWERPC_G2_HIP4, G2),
|
8238 |
/* PowerPC MPC603 core */
|
8239 |
POWERPC_DEF("MPC603", CPU_POWERPC_MPC603, 603E), |
8240 |
/* PowerPC G2le core (same as G2 plus little-endian mode support) */
|
8241 |
POWERPC_DEF("G2le", CPU_POWERPC_G2LE, G2LE),
|
8242 |
/* PowerPC G2LE GP core */
|
8243 |
POWERPC_DEF("G2leGP", CPU_POWERPC_G2LEgp, G2LE),
|
8244 |
/* PowerPC G2LE LS core */
|
8245 |
POWERPC_DEF("G2leLS", CPU_POWERPC_G2LEls, G2LE),
|
8246 |
/* PowerPC G2LE GP1 core */
|
8247 |
POWERPC_DEF("G2leGP1", CPU_POWERPC_G2LEgp1, G2LE),
|
8248 |
/* PowerPC G2LE GP3 core */
|
8249 |
POWERPC_DEF("G2leGP3", CPU_POWERPC_G2LEgp1, G2LE),
|
8250 |
/* PowerPC MPC603 microcontrollers */
|
8251 |
/* MPC8240 */
|
8252 |
POWERPC_DEF("MPC8240", CPU_POWERPC_MPC8240, 603E), |
8253 |
/* PowerPC G2 microcontrollers */
|
8254 |
#if defined(TODO)
|
8255 |
/* MPC5121 */
|
8256 |
POWERPC_DEF_SVR("MPC5121",
|
8257 |
CPU_POWERPC_MPC5121, POWERPC_SVR_5121, G2LE), |
8258 |
#endif
|
8259 |
/* MPC5200 */
|
8260 |
POWERPC_DEF_SVR("MPC5200",
|
8261 |
CPU_POWERPC_MPC5200, POWERPC_SVR_5200, G2LE), |
8262 |
/* MPC5200 v1.0 */
|
8263 |
POWERPC_DEF_SVR("MPC5200_v10",
|
8264 |
CPU_POWERPC_MPC5200_v10, POWERPC_SVR_5200_v10, G2LE), |
8265 |
/* MPC5200 v1.1 */
|
8266 |
POWERPC_DEF_SVR("MPC5200_v11",
|
8267 |
CPU_POWERPC_MPC5200_v11, POWERPC_SVR_5200_v11, G2LE), |
8268 |
/* MPC5200 v1.2 */
|
8269 |
POWERPC_DEF_SVR("MPC5200_v12",
|
8270 |
CPU_POWERPC_MPC5200_v12, POWERPC_SVR_5200_v12, G2LE), |
8271 |
/* MPC5200B */
|
8272 |
POWERPC_DEF_SVR("MPC5200B",
|
8273 |
CPU_POWERPC_MPC5200B, POWERPC_SVR_5200B, G2LE), |
8274 |
/* MPC5200B v2.0 */
|
8275 |
POWERPC_DEF_SVR("MPC5200B_v20",
|
8276 |
CPU_POWERPC_MPC5200B_v20, POWERPC_SVR_5200B_v20, G2LE), |
8277 |
/* MPC5200B v2.1 */
|
8278 |
POWERPC_DEF_SVR("MPC5200B_v21",
|
8279 |
CPU_POWERPC_MPC5200B_v21, POWERPC_SVR_5200B_v21, G2LE), |
8280 |
/* MPC8241 */
|
8281 |
POWERPC_DEF("MPC8241", CPU_POWERPC_MPC8241, G2),
|
8282 |
/* MPC8245 */
|
8283 |
POWERPC_DEF("MPC8245", CPU_POWERPC_MPC8245, G2),
|
8284 |
/* MPC8247 */
|
8285 |
POWERPC_DEF("MPC8247", CPU_POWERPC_MPC8247, G2LE),
|
8286 |
/* MPC8248 */
|
8287 |
POWERPC_DEF("MPC8248", CPU_POWERPC_MPC8248, G2LE),
|
8288 |
/* MPC8250 */
|
8289 |
POWERPC_DEF("MPC8250", CPU_POWERPC_MPC8250, G2),
|
8290 |
/* MPC8250 HiP3 */
|
8291 |
POWERPC_DEF("MPC8250_HiP3", CPU_POWERPC_MPC8250_HiP3, G2),
|
8292 |
/* MPC8250 HiP4 */
|
8293 |
POWERPC_DEF("MPC8250_HiP4", CPU_POWERPC_MPC8250_HiP4, G2),
|
8294 |
/* MPC8255 */
|
8295 |
POWERPC_DEF("MPC8255", CPU_POWERPC_MPC8255, G2),
|
8296 |
/* MPC8255 HiP3 */
|
8297 |
POWERPC_DEF("MPC8255_HiP3", CPU_POWERPC_MPC8255_HiP3, G2),
|
8298 |
/* MPC8255 HiP4 */
|
8299 |
POWERPC_DEF("MPC8255_HiP4", CPU_POWERPC_MPC8255_HiP4, G2),
|
8300 |
/* MPC8260 */
|
8301 |
POWERPC_DEF("MPC8260", CPU_POWERPC_MPC8260, G2),
|
8302 |
/* MPC8260 HiP3 */
|
8303 |
POWERPC_DEF("MPC8260_HiP3", CPU_POWERPC_MPC8260_HiP3, G2),
|
8304 |
/* MPC8260 HiP4 */
|
8305 |
POWERPC_DEF("MPC8260_HiP4", CPU_POWERPC_MPC8260_HiP4, G2),
|
8306 |
/* MPC8264 */
|
8307 |
POWERPC_DEF("MPC8264", CPU_POWERPC_MPC8264, G2),
|
8308 |
/* MPC8264 HiP3 */
|
8309 |
POWERPC_DEF("MPC8264_HiP3", CPU_POWERPC_MPC8264_HiP3, G2),
|
8310 |
/* MPC8264 HiP4 */
|
8311 |
POWERPC_DEF("MPC8264_HiP4", CPU_POWERPC_MPC8264_HiP4, G2),
|
8312 |
/* MPC8265 */
|
8313 |
POWERPC_DEF("MPC8265", CPU_POWERPC_MPC8265, G2),
|
8314 |
/* MPC8265 HiP3 */
|
8315 |
POWERPC_DEF("MPC8265_HiP3", CPU_POWERPC_MPC8265_HiP3, G2),
|
8316 |
/* MPC8265 HiP4 */
|
8317 |
POWERPC_DEF("MPC8265_HiP4", CPU_POWERPC_MPC8265_HiP4, G2),
|
8318 |
/* MPC8266 */
|
8319 |
POWERPC_DEF("MPC8266", CPU_POWERPC_MPC8266, G2),
|
8320 |
/* MPC8266 HiP3 */
|
8321 |
POWERPC_DEF("MPC8266_HiP3", CPU_POWERPC_MPC8266_HiP3, G2),
|
8322 |
/* MPC8266 HiP4 */
|
8323 |
POWERPC_DEF("MPC8266_HiP4", CPU_POWERPC_MPC8266_HiP4, G2),
|
8324 |
/* MPC8270 */
|
8325 |
POWERPC_DEF("MPC8270", CPU_POWERPC_MPC8270, G2LE),
|
8326 |
/* MPC8271 */
|
8327 |
POWERPC_DEF("MPC8271", CPU_POWERPC_MPC8271, G2LE),
|
8328 |
/* MPC8272 */
|
8329 |
POWERPC_DEF("MPC8272", CPU_POWERPC_MPC8272, G2LE),
|
8330 |
/* MPC8275 */
|
8331 |
POWERPC_DEF("MPC8275", CPU_POWERPC_MPC8275, G2LE),
|
8332 |
/* MPC8280 */
|
8333 |
POWERPC_DEF("MPC8280", CPU_POWERPC_MPC8280, G2LE),
|
8334 |
/* e200 family */
|
8335 |
/* Generic PowerPC e200 core */
|
8336 |
POWERPC_DEF("e200", CPU_POWERPC_e200, e200),
|
8337 |
/* Generic MPC55xx core */
|
8338 |
#if defined (TODO)
|
8339 |
POWERPC_DEF_SVR("MPC55xx",
|
8340 |
CPU_POWERPC_MPC55xx, POWERPC_SVR_55xx, e200), |
8341 |
#endif
|
8342 |
#if defined (TODO)
|
8343 |
/* PowerPC e200z0 core */
|
8344 |
POWERPC_DEF("e200z0", CPU_POWERPC_e200z0, e200),
|
8345 |
#endif
|
8346 |
#if defined (TODO)
|
8347 |
/* PowerPC e200z1 core */
|
8348 |
POWERPC_DEF("e200z1", CPU_POWERPC_e200z1, e200),
|
8349 |
#endif
|
8350 |
#if defined (TODO)
|
8351 |
/* PowerPC e200z3 core */
|
8352 |
POWERPC_DEF("e200z3", CPU_POWERPC_e200z3, e200),
|
8353 |
#endif
|
8354 |
/* PowerPC e200z5 core */
|
8355 |
POWERPC_DEF("e200z5", CPU_POWERPC_e200z5, e200),
|
8356 |
/* PowerPC e200z6 core */
|
8357 |
POWERPC_DEF("e200z6", CPU_POWERPC_e200z6, e200),
|
8358 |
/* PowerPC e200 microcontrollers */
|
8359 |
#if defined (TODO)
|
8360 |
/* MPC5514E */
|
8361 |
POWERPC_DEF_SVR("MPC5514E",
|
8362 |
CPU_POWERPC_MPC5514E, POWERPC_SVR_5514E, e200), |
8363 |
#endif
|
8364 |
#if defined (TODO)
|
8365 |
/* MPC5514E v0 */
|
8366 |
POWERPC_DEF_SVR("MPC5514E_v0",
|
8367 |
CPU_POWERPC_MPC5514E_v0, POWERPC_SVR_5514E_v0, e200), |
8368 |
#endif
|
8369 |
#if defined (TODO)
|
8370 |
/* MPC5514E v1 */
|
8371 |
POWERPC_DEF_SVR("MPC5514E_v1",
|
8372 |
CPU_POWERPC_MPC5514E_v1, POWERPC_SVR_5514E_v1, e200), |
8373 |
#endif
|
8374 |
#if defined (TODO)
|
8375 |
/* MPC5514G */
|
8376 |
POWERPC_DEF_SVR("MPC5514G",
|
8377 |
CPU_POWERPC_MPC5514G, POWERPC_SVR_5514G, e200), |
8378 |
#endif
|
8379 |
#if defined (TODO)
|
8380 |
/* MPC5514G v0 */
|
8381 |
POWERPC_DEF_SVR("MPC5514G_v0",
|
8382 |
CPU_POWERPC_MPC5514G_v0, POWERPC_SVR_5514G_v0, e200), |
8383 |
#endif
|
8384 |
#if defined (TODO)
|
8385 |
/* MPC5514G v1 */
|
8386 |
POWERPC_DEF_SVR("MPC5514G_v1",
|
8387 |
CPU_POWERPC_MPC5514G_v1, POWERPC_SVR_5514G_v1, e200), |
8388 |
#endif
|
8389 |
#if defined (TODO)
|
8390 |
/* MPC5515S */
|
8391 |
POWERPC_DEF_SVR("MPC5515S",
|
8392 |
CPU_POWERPC_MPC5515S, POWERPC_SVR_5515S, e200), |
8393 |
#endif
|
8394 |
#if defined (TODO)
|
8395 |
/* MPC5516E */
|
8396 |
POWERPC_DEF_SVR("MPC5516E",
|
8397 |
CPU_POWERPC_MPC5516E, POWERPC_SVR_5516E, e200), |
8398 |
#endif
|
8399 |
#if defined (TODO)
|
8400 |
/* MPC5516E v0 */
|
8401 |
POWERPC_DEF_SVR("MPC5516E_v0",
|
8402 |
CPU_POWERPC_MPC5516E_v0, POWERPC_SVR_5516E_v0, e200), |
8403 |
#endif
|
8404 |
#if defined (TODO)
|
8405 |
/* MPC5516E v1 */
|
8406 |
POWERPC_DEF_SVR("MPC5516E_v1",
|
8407 |
CPU_POWERPC_MPC5516E_v1, POWERPC_SVR_5516E_v1, e200), |
8408 |
#endif
|
8409 |
#if defined (TODO)
|
8410 |
/* MPC5516G */
|
8411 |
POWERPC_DEF_SVR("MPC5516G",
|
8412 |
CPU_POWERPC_MPC5516G, POWERPC_SVR_5516G, e200), |
8413 |
#endif
|
8414 |
#if defined (TODO)
|
8415 |
/* MPC5516G v0 */
|
8416 |
POWERPC_DEF_SVR("MPC5516G_v0",
|
8417 |
CPU_POWERPC_MPC5516G_v0, POWERPC_SVR_5516G_v0, e200), |
8418 |
#endif
|
8419 |
#if defined (TODO)
|
8420 |
/* MPC5516G v1 */
|
8421 |
POWERPC_DEF_SVR("MPC5516G_v1",
|
8422 |
CPU_POWERPC_MPC5516G_v1, POWERPC_SVR_5516G_v1, e200), |
8423 |
#endif
|
8424 |
#if defined (TODO)
|
8425 |
/* MPC5516S */
|
8426 |
POWERPC_DEF_SVR("MPC5516S",
|
8427 |
CPU_POWERPC_MPC5516S, POWERPC_SVR_5516S, e200), |
8428 |
#endif
|
8429 |
#if defined (TODO)
|
8430 |
/* MPC5533 */
|
8431 |
POWERPC_DEF_SVR("MPC5533",
|
8432 |
CPU_POWERPC_MPC5533, POWERPC_SVR_5533, e200), |
8433 |
#endif
|
8434 |
#if defined (TODO)
|
8435 |
/* MPC5534 */
|
8436 |
POWERPC_DEF_SVR("MPC5534",
|
8437 |
CPU_POWERPC_MPC5534, POWERPC_SVR_5534, e200), |
8438 |
#endif
|
8439 |
#if defined (TODO)
|
8440 |
/* MPC5553 */
|
8441 |
POWERPC_DEF_SVR("MPC5553",
|
8442 |
CPU_POWERPC_MPC5553, POWERPC_SVR_5553, e200), |
8443 |
#endif
|
8444 |
#if defined (TODO)
|
8445 |
/* MPC5554 */
|
8446 |
POWERPC_DEF_SVR("MPC5554",
|
8447 |
CPU_POWERPC_MPC5554, POWERPC_SVR_5554, e200), |
8448 |
#endif
|
8449 |
#if defined (TODO)
|
8450 |
/* MPC5561 */
|
8451 |
POWERPC_DEF_SVR("MPC5561",
|
8452 |
CPU_POWERPC_MPC5561, POWERPC_SVR_5561, e200), |
8453 |
#endif
|
8454 |
#if defined (TODO)
|
8455 |
/* MPC5565 */
|
8456 |
POWERPC_DEF_SVR("MPC5565",
|
8457 |
CPU_POWERPC_MPC5565, POWERPC_SVR_5565, e200), |
8458 |
#endif
|
8459 |
#if defined (TODO)
|
8460 |
/* MPC5566 */
|
8461 |
POWERPC_DEF_SVR("MPC5566",
|
8462 |
CPU_POWERPC_MPC5566, POWERPC_SVR_5566, e200), |
8463 |
#endif
|
8464 |
#if defined (TODO)
|
8465 |
/* MPC5567 */
|
8466 |
POWERPC_DEF_SVR("MPC5567",
|
8467 |
CPU_POWERPC_MPC5567, POWERPC_SVR_5567, e200), |
8468 |
#endif
|
8469 |
/* e300 family */
|
8470 |
/* Generic PowerPC e300 core */
|
8471 |
POWERPC_DEF("e300", CPU_POWERPC_e300, e300),
|
8472 |
/* PowerPC e300c1 core */
|
8473 |
POWERPC_DEF("e300c1", CPU_POWERPC_e300c1, e300),
|
8474 |
/* PowerPC e300c2 core */
|
8475 |
POWERPC_DEF("e300c2", CPU_POWERPC_e300c2, e300),
|
8476 |
/* PowerPC e300c3 core */
|
8477 |
POWERPC_DEF("e300c3", CPU_POWERPC_e300c3, e300),
|
8478 |
/* PowerPC e300c4 core */
|
8479 |
POWERPC_DEF("e300c4", CPU_POWERPC_e300c4, e300),
|
8480 |
/* PowerPC e300 microcontrollers */
|
8481 |
#if defined (TODO)
|
8482 |
/* MPC8313 */
|
8483 |
POWERPC_DEF_SVR("MPC8313",
|
8484 |
CPU_POWERPC_MPC831x, POWERPC_SVR_8313, e300), |
8485 |
#endif
|
8486 |
#if defined (TODO)
|
8487 |
/* MPC8313E */
|
8488 |
POWERPC_DEF_SVR("MPC8313E",
|
8489 |
CPU_POWERPC_MPC831x, POWERPC_SVR_8313E, e300), |
8490 |
#endif
|
8491 |
#if defined (TODO)
|
8492 |
/* MPC8314 */
|
8493 |
POWERPC_DEF_SVR("MPC8314",
|
8494 |
CPU_POWERPC_MPC831x, POWERPC_SVR_8314, e300), |
8495 |
#endif
|
8496 |
#if defined (TODO)
|
8497 |
/* MPC8314E */
|
8498 |
POWERPC_DEF_SVR("MPC8314E",
|
8499 |
CPU_POWERPC_MPC831x, POWERPC_SVR_8314E, e300), |
8500 |
#endif
|
8501 |
#if defined (TODO)
|
8502 |
/* MPC8315 */
|
8503 |
POWERPC_DEF_SVR("MPC8315",
|
8504 |
CPU_POWERPC_MPC831x, POWERPC_SVR_8315, e300), |
8505 |
#endif
|
8506 |
#if defined (TODO)
|
8507 |
/* MPC8315E */
|
8508 |
POWERPC_DEF_SVR("MPC8315E",
|
8509 |
CPU_POWERPC_MPC831x, POWERPC_SVR_8315E, e300), |
8510 |
#endif
|
8511 |
#if defined (TODO)
|
8512 |
/* MPC8321 */
|
8513 |
POWERPC_DEF_SVR("MPC8321",
|
8514 |
CPU_POWERPC_MPC832x, POWERPC_SVR_8321, e300), |
8515 |
#endif
|
8516 |
#if defined (TODO)
|
8517 |
/* MPC8321E */
|
8518 |
POWERPC_DEF_SVR("MPC8321E",
|
8519 |
CPU_POWERPC_MPC832x, POWERPC_SVR_8321E, e300), |
8520 |
#endif
|
8521 |
#if defined (TODO)
|
8522 |
/* MPC8323 */
|
8523 |
POWERPC_DEF_SVR("MPC8323",
|
8524 |
CPU_POWERPC_MPC832x, POWERPC_SVR_8323, e300), |
8525 |
#endif
|
8526 |
#if defined (TODO)
|
8527 |
/* MPC8323E */
|
8528 |
POWERPC_DEF_SVR("MPC8323E",
|
8529 |
CPU_POWERPC_MPC832x, POWERPC_SVR_8323E, e300), |
8530 |
#endif
|
8531 |
/* MPC8343 */
|
8532 |
POWERPC_DEF_SVR("MPC8343",
|
8533 |
CPU_POWERPC_MPC834x, POWERPC_SVR_8343, e300), |
8534 |
/* MPC8343A */
|
8535 |
POWERPC_DEF_SVR("MPC8343A",
|
8536 |
CPU_POWERPC_MPC834x, POWERPC_SVR_8343A, e300), |
8537 |
/* MPC8343E */
|
8538 |
POWERPC_DEF_SVR("MPC8343E",
|
8539 |
CPU_POWERPC_MPC834x, POWERPC_SVR_8343E, e300), |
8540 |
/* MPC8343EA */
|
8541 |
POWERPC_DEF_SVR("MPC8343EA",
|
8542 |
CPU_POWERPC_MPC834x, POWERPC_SVR_8343EA, e300), |
8543 |
/* MPC8347 */
|
8544 |
POWERPC_DEF_SVR("MPC8347",
|
8545 |
CPU_POWERPC_MPC834x, POWERPC_SVR_8347, e300), |
8546 |
/* MPC8347T */
|
8547 |
POWERPC_DEF_SVR("MPC8347T",
|
8548 |
CPU_POWERPC_MPC834x, POWERPC_SVR_8347T, e300), |
8549 |
/* MPC8347P */
|
8550 |
POWERPC_DEF_SVR("MPC8347P",
|
8551 |
CPU_POWERPC_MPC834x, POWERPC_SVR_8347P, e300), |
8552 |
/* MPC8347A */
|
8553 |
POWERPC_DEF_SVR("MPC8347A",
|
8554 |
CPU_POWERPC_MPC834x, POWERPC_SVR_8347A, e300), |
8555 |
/* MPC8347AT */
|
8556 |
POWERPC_DEF_SVR("MPC8347AT",
|
8557 |
CPU_POWERPC_MPC834x, POWERPC_SVR_8347AT, e300), |
8558 |
/* MPC8347AP */
|
8559 |
POWERPC_DEF_SVR("MPC8347AP",
|
8560 |
CPU_POWERPC_MPC834x, POWERPC_SVR_8347AP, e300), |
8561 |
/* MPC8347E */
|
8562 |
POWERPC_DEF_SVR("MPC8347E",
|
8563 |
CPU_POWERPC_MPC834x, POWERPC_SVR_8347E, e300), |
8564 |
/* MPC8347ET */
|
8565 |
POWERPC_DEF_SVR("MPC8347ET",
|
8566 |
CPU_POWERPC_MPC834x, POWERPC_SVR_8347ET, e300), |
8567 |
/* MPC8343EP */
|
8568 |
POWERPC_DEF_SVR("MPC8347EP",
|
8569 |
CPU_POWERPC_MPC834x, POWERPC_SVR_8347EP, e300), |
8570 |
/* MPC8347EA */
|
8571 |
POWERPC_DEF_SVR("MPC8347EA",
|
8572 |
CPU_POWERPC_MPC834x, POWERPC_SVR_8347EA, e300), |
8573 |
/* MPC8347EAT */
|
8574 |
POWERPC_DEF_SVR("MPC8347EAT",
|
8575 |
CPU_POWERPC_MPC834x, POWERPC_SVR_8347EAT, e300), |
8576 |
/* MPC8343EAP */
|
8577 |
POWERPC_DEF_SVR("MPC8347EAP",
|
8578 |
CPU_POWERPC_MPC834x, POWERPC_SVR_8347EAP, e300), |
8579 |
/* MPC8349 */
|
8580 |
POWERPC_DEF_SVR("MPC8349",
|
8581 |
CPU_POWERPC_MPC834x, POWERPC_SVR_8349, e300), |
8582 |
/* MPC8349A */
|
8583 |
POWERPC_DEF_SVR("MPC8349A",
|
8584 |
CPU_POWERPC_MPC834x, POWERPC_SVR_8349A, e300), |
8585 |
/* MPC8349E */
|
8586 |
POWERPC_DEF_SVR("MPC8349E",
|
8587 |
CPU_POWERPC_MPC834x, POWERPC_SVR_8349E, e300), |
8588 |
/* MPC8349EA */
|
8589 |
POWERPC_DEF_SVR("MPC8349EA",
|
8590 |
CPU_POWERPC_MPC834x, POWERPC_SVR_8349EA, e300), |
8591 |
#if defined (TODO)
|
8592 |
/* MPC8358E */
|
8593 |
POWERPC_DEF_SVR("MPC8358E",
|
8594 |
CPU_POWERPC_MPC835x, POWERPC_SVR_8358E, e300), |
8595 |
#endif
|
8596 |
#if defined (TODO)
|
8597 |
/* MPC8360E */
|
8598 |
POWERPC_DEF_SVR("MPC8360E",
|
8599 |
CPU_POWERPC_MPC836x, POWERPC_SVR_8360E, e300), |
8600 |
#endif
|
8601 |
/* MPC8377 */
|
8602 |
POWERPC_DEF_SVR("MPC8377",
|
8603 |
CPU_POWERPC_MPC837x, POWERPC_SVR_8377, e300), |
8604 |
/* MPC8377E */
|
8605 |
POWERPC_DEF_SVR("MPC8377E",
|
8606 |
CPU_POWERPC_MPC837x, POWERPC_SVR_8377E, e300), |
8607 |
/* MPC8378 */
|
8608 |
POWERPC_DEF_SVR("MPC8378",
|
8609 |
CPU_POWERPC_MPC837x, POWERPC_SVR_8378, e300), |
8610 |
/* MPC8378E */
|
8611 |
POWERPC_DEF_SVR("MPC8378E",
|
8612 |
CPU_POWERPC_MPC837x, POWERPC_SVR_8378E, e300), |
8613 |
/* MPC8379 */
|
8614 |
POWERPC_DEF_SVR("MPC8379",
|
8615 |
CPU_POWERPC_MPC837x, POWERPC_SVR_8379, e300), |
8616 |
/* MPC8379E */
|
8617 |
POWERPC_DEF_SVR("MPC8379E",
|
8618 |
CPU_POWERPC_MPC837x, POWERPC_SVR_8379E, e300), |
8619 |
/* e500 family */
|
8620 |
/* PowerPC e500 core */
|
8621 |
POWERPC_DEF("e500", CPU_POWERPC_e500v2_v22, e500v2),
|
8622 |
/* PowerPC e500v1 core */
|
8623 |
POWERPC_DEF("e500v1", CPU_POWERPC_e500v1, e500v1),
|
8624 |
/* PowerPC e500 v1.0 core */
|
8625 |
POWERPC_DEF("e500_v10", CPU_POWERPC_e500v1_v10, e500v1),
|
8626 |
/* PowerPC e500 v2.0 core */
|
8627 |
POWERPC_DEF("e500_v20", CPU_POWERPC_e500v1_v20, e500v1),
|
8628 |
/* PowerPC e500v2 core */
|
8629 |
POWERPC_DEF("e500v2", CPU_POWERPC_e500v2, e500v2),
|
8630 |
/* PowerPC e500v2 v1.0 core */
|
8631 |
POWERPC_DEF("e500v2_v10", CPU_POWERPC_e500v2_v10, e500v2),
|
8632 |
/* PowerPC e500v2 v2.0 core */
|
8633 |
POWERPC_DEF("e500v2_v20", CPU_POWERPC_e500v2_v20, e500v2),
|
8634 |
/* PowerPC e500v2 v2.1 core */
|
8635 |
POWERPC_DEF("e500v2_v21", CPU_POWERPC_e500v2_v21, e500v2),
|
8636 |
/* PowerPC e500v2 v2.2 core */
|
8637 |
POWERPC_DEF("e500v2_v22", CPU_POWERPC_e500v2_v22, e500v2),
|
8638 |
/* PowerPC e500v2 v3.0 core */
|
8639 |
POWERPC_DEF("e500v2_v30", CPU_POWERPC_e500v2_v30, e500v2),
|
8640 |
POWERPC_DEF("e500mc", CPU_POWERPC_e500mc, e500mc),
|
8641 |
#ifdef TARGET_PPC64
|
8642 |
POWERPC_DEF("e5500", CPU_POWERPC_e5500, e5500),
|
8643 |
#endif
|
8644 |
/* PowerPC e500 microcontrollers */
|
8645 |
/* MPC8533 */
|
8646 |
POWERPC_DEF_SVR("MPC8533",
|
8647 |
CPU_POWERPC_MPC8533, POWERPC_SVR_8533, e500v2), |
8648 |
/* MPC8533 v1.0 */
|
8649 |
POWERPC_DEF_SVR("MPC8533_v10",
|
8650 |
CPU_POWERPC_MPC8533_v10, POWERPC_SVR_8533_v10, e500v2), |
8651 |
/* MPC8533 v1.1 */
|
8652 |
POWERPC_DEF_SVR("MPC8533_v11",
|
8653 |
CPU_POWERPC_MPC8533_v11, POWERPC_SVR_8533_v11, e500v2), |
8654 |
/* MPC8533E */
|
8655 |
POWERPC_DEF_SVR("MPC8533E",
|
8656 |
CPU_POWERPC_MPC8533E, POWERPC_SVR_8533E, e500v2), |
8657 |
/* MPC8533E v1.0 */
|
8658 |
POWERPC_DEF_SVR("MPC8533E_v10",
|
8659 |
CPU_POWERPC_MPC8533E_v10, POWERPC_SVR_8533E_v10, e500v2), |
8660 |
POWERPC_DEF_SVR("MPC8533E_v11",
|
8661 |
CPU_POWERPC_MPC8533E_v11, POWERPC_SVR_8533E_v11, e500v2), |
8662 |
/* MPC8540 */
|
8663 |
POWERPC_DEF_SVR("MPC8540",
|
8664 |
CPU_POWERPC_MPC8540, POWERPC_SVR_8540, e500v1), |
8665 |
/* MPC8540 v1.0 */
|
8666 |
POWERPC_DEF_SVR("MPC8540_v10",
|
8667 |
CPU_POWERPC_MPC8540_v10, POWERPC_SVR_8540_v10, e500v1), |
8668 |
/* MPC8540 v2.0 */
|
8669 |
POWERPC_DEF_SVR("MPC8540_v20",
|
8670 |
CPU_POWERPC_MPC8540_v20, POWERPC_SVR_8540_v20, e500v1), |
8671 |
/* MPC8540 v2.1 */
|
8672 |
POWERPC_DEF_SVR("MPC8540_v21",
|
8673 |
CPU_POWERPC_MPC8540_v21, POWERPC_SVR_8540_v21, e500v1), |
8674 |
/* MPC8541 */
|
8675 |
POWERPC_DEF_SVR("MPC8541",
|
8676 |
CPU_POWERPC_MPC8541, POWERPC_SVR_8541, e500v1), |
8677 |
/* MPC8541 v1.0 */
|
8678 |
POWERPC_DEF_SVR("MPC8541_v10",
|
8679 |
CPU_POWERPC_MPC8541_v10, POWERPC_SVR_8541_v10, e500v1), |
8680 |
/* MPC8541 v1.1 */
|
8681 |
POWERPC_DEF_SVR("MPC8541_v11",
|
8682 |
CPU_POWERPC_MPC8541_v11, POWERPC_SVR_8541_v11, e500v1), |
8683 |
/* MPC8541E */
|
8684 |
POWERPC_DEF_SVR("MPC8541E",
|
8685 |
CPU_POWERPC_MPC8541E, POWERPC_SVR_8541E, e500v1), |
8686 |
/* MPC8541E v1.0 */
|
8687 |
POWERPC_DEF_SVR("MPC8541E_v10",
|
8688 |
CPU_POWERPC_MPC8541E_v10, POWERPC_SVR_8541E_v10, e500v1), |
8689 |
/* MPC8541E v1.1 */
|
8690 |
POWERPC_DEF_SVR("MPC8541E_v11",
|
8691 |
CPU_POWERPC_MPC8541E_v11, POWERPC_SVR_8541E_v11, e500v1), |
8692 |
/* MPC8543 */
|
8693 |
POWERPC_DEF_SVR("MPC8543",
|
8694 |
CPU_POWERPC_MPC8543, POWERPC_SVR_8543, e500v2), |
8695 |
/* MPC8543 v1.0 */
|
8696 |
POWERPC_DEF_SVR("MPC8543_v10",
|
8697 |
CPU_POWERPC_MPC8543_v10, POWERPC_SVR_8543_v10, e500v2), |
8698 |
/* MPC8543 v1.1 */
|
8699 |
POWERPC_DEF_SVR("MPC8543_v11",
|
8700 |
CPU_POWERPC_MPC8543_v11, POWERPC_SVR_8543_v11, e500v2), |
8701 |
/* MPC8543 v2.0 */
|
8702 |
POWERPC_DEF_SVR("MPC8543_v20",
|
8703 |
CPU_POWERPC_MPC8543_v20, POWERPC_SVR_8543_v20, e500v2), |
8704 |
/* MPC8543 v2.1 */
|
8705 |
POWERPC_DEF_SVR("MPC8543_v21",
|
8706 |
CPU_POWERPC_MPC8543_v21, POWERPC_SVR_8543_v21, e500v2), |
8707 |
/* MPC8543E */
|
8708 |
POWERPC_DEF_SVR("MPC8543E",
|
8709 |
CPU_POWERPC_MPC8543E, POWERPC_SVR_8543E, e500v2), |
8710 |
/* MPC8543E v1.0 */
|
8711 |
POWERPC_DEF_SVR("MPC8543E_v10",
|
8712 |
CPU_POWERPC_MPC8543E_v10, POWERPC_SVR_8543E_v10, e500v2), |
8713 |
/* MPC8543E v1.1 */
|
8714 |
POWERPC_DEF_SVR("MPC8543E_v11",
|
8715 |
CPU_POWERPC_MPC8543E_v11, POWERPC_SVR_8543E_v11, e500v2), |
8716 |
/* MPC8543E v2.0 */
|
8717 |
POWERPC_DEF_SVR("MPC8543E_v20",
|
8718 |
CPU_POWERPC_MPC8543E_v20, POWERPC_SVR_8543E_v20, e500v2), |
8719 |
/* MPC8543E v2.1 */
|
8720 |
POWERPC_DEF_SVR("MPC8543E_v21",
|
8721 |
CPU_POWERPC_MPC8543E_v21, POWERPC_SVR_8543E_v21, e500v2), |
8722 |
/* MPC8544 */
|
8723 |
POWERPC_DEF_SVR("MPC8544",
|
8724 |
CPU_POWERPC_MPC8544, POWERPC_SVR_8544, e500v2), |
8725 |
/* MPC8544 v1.0 */
|
8726 |
POWERPC_DEF_SVR("MPC8544_v10",
|
8727 |
CPU_POWERPC_MPC8544_v10, POWERPC_SVR_8544_v10, e500v2), |
8728 |
/* MPC8544 v1.1 */
|
8729 |
POWERPC_DEF_SVR("MPC8544_v11",
|
8730 |
CPU_POWERPC_MPC8544_v11, POWERPC_SVR_8544_v11, e500v2), |
8731 |
/* MPC8544E */
|
8732 |
POWERPC_DEF_SVR("MPC8544E",
|
8733 |
CPU_POWERPC_MPC8544E, POWERPC_SVR_8544E, e500v2), |
8734 |
/* MPC8544E v1.0 */
|
8735 |
POWERPC_DEF_SVR("MPC8544E_v10",
|
8736 |
CPU_POWERPC_MPC8544E_v10, POWERPC_SVR_8544E_v10, e500v2), |
8737 |
/* MPC8544E v1.1 */
|
8738 |
POWERPC_DEF_SVR("MPC8544E_v11",
|
8739 |
CPU_POWERPC_MPC8544E_v11, POWERPC_SVR_8544E_v11, e500v2), |
8740 |
/* MPC8545 */
|
8741 |
POWERPC_DEF_SVR("MPC8545",
|
8742 |
CPU_POWERPC_MPC8545, POWERPC_SVR_8545, e500v2), |
8743 |
/* MPC8545 v2.0 */
|
8744 |
POWERPC_DEF_SVR("MPC8545_v20",
|
8745 |
CPU_POWERPC_MPC8545_v20, POWERPC_SVR_8545_v20, e500v2), |
8746 |
/* MPC8545 v2.1 */
|
8747 |
POWERPC_DEF_SVR("MPC8545_v21",
|
8748 |
CPU_POWERPC_MPC8545_v21, POWERPC_SVR_8545_v21, e500v2), |
8749 |
/* MPC8545E */
|
8750 |
POWERPC_DEF_SVR("MPC8545E",
|
8751 |
CPU_POWERPC_MPC8545E, POWERPC_SVR_8545E, e500v2), |
8752 |
/* MPC8545E v2.0 */
|
8753 |
POWERPC_DEF_SVR("MPC8545E_v20",
|
8754 |
CPU_POWERPC_MPC8545E_v20, POWERPC_SVR_8545E_v20, e500v2), |
8755 |
/* MPC8545E v2.1 */
|
8756 |
POWERPC_DEF_SVR("MPC8545E_v21",
|
8757 |
CPU_POWERPC_MPC8545E_v21, POWERPC_SVR_8545E_v21, e500v2), |
8758 |
/* MPC8547E */
|
8759 |
POWERPC_DEF_SVR("MPC8547E",
|
8760 |
CPU_POWERPC_MPC8547E, POWERPC_SVR_8547E, e500v2), |
8761 |
/* MPC8547E v2.0 */
|
8762 |
POWERPC_DEF_SVR("MPC8547E_v20",
|
8763 |
CPU_POWERPC_MPC8547E_v20, POWERPC_SVR_8547E_v20, e500v2), |
8764 |
/* MPC8547E v2.1 */
|
8765 |
POWERPC_DEF_SVR("MPC8547E_v21",
|
8766 |
CPU_POWERPC_MPC8547E_v21, POWERPC_SVR_8547E_v21, e500v2), |
8767 |
/* MPC8548 */
|
8768 |
POWERPC_DEF_SVR("MPC8548",
|
8769 |
CPU_POWERPC_MPC8548, POWERPC_SVR_8548, e500v2), |
8770 |
/* MPC8548 v1.0 */
|
8771 |
POWERPC_DEF_SVR("MPC8548_v10",
|
8772 |
CPU_POWERPC_MPC8548_v10, POWERPC_SVR_8548_v10, e500v2), |
8773 |
/* MPC8548 v1.1 */
|
8774 |
POWERPC_DEF_SVR("MPC8548_v11",
|
8775 |
CPU_POWERPC_MPC8548_v11, POWERPC_SVR_8548_v11, e500v2), |
8776 |
/* MPC8548 v2.0 */
|
8777 |
POWERPC_DEF_SVR("MPC8548_v20",
|
8778 |
CPU_POWERPC_MPC8548_v20, POWERPC_SVR_8548_v20, e500v2), |
8779 |
/* MPC8548 v2.1 */
|
8780 |
POWERPC_DEF_SVR("MPC8548_v21",
|
8781 |
CPU_POWERPC_MPC8548_v21, POWERPC_SVR_8548_v21, e500v2), |
8782 |
/* MPC8548E */
|
8783 |
POWERPC_DEF_SVR("MPC8548E",
|
8784 |
CPU_POWERPC_MPC8548E, POWERPC_SVR_8548E, e500v2), |
8785 |
/* MPC8548E v1.0 */
|
8786 |
POWERPC_DEF_SVR("MPC8548E_v10",
|
8787 |
CPU_POWERPC_MPC8548E_v10, POWERPC_SVR_8548E_v10, e500v2), |
8788 |
/* MPC8548E v1.1 */
|
8789 |
POWERPC_DEF_SVR("MPC8548E_v11",
|
8790 |
CPU_POWERPC_MPC8548E_v11, POWERPC_SVR_8548E_v11, e500v2), |
8791 |
/* MPC8548E v2.0 */
|
8792 |
POWERPC_DEF_SVR("MPC8548E_v20",
|
8793 |
CPU_POWERPC_MPC8548E_v20, POWERPC_SVR_8548E_v20, e500v2), |
8794 |
/* MPC8548E v2.1 */
|
8795 |
POWERPC_DEF_SVR("MPC8548E_v21",
|
8796 |
CPU_POWERPC_MPC8548E_v21, POWERPC_SVR_8548E_v21, e500v2), |
8797 |
/* MPC8555 */
|
8798 |
POWERPC_DEF_SVR("MPC8555",
|
8799 |
CPU_POWERPC_MPC8555, POWERPC_SVR_8555, e500v2), |
8800 |
/* MPC8555 v1.0 */
|
8801 |
POWERPC_DEF_SVR("MPC8555_v10",
|
8802 |
CPU_POWERPC_MPC8555_v10, POWERPC_SVR_8555_v10, e500v2), |
8803 |
/* MPC8555 v1.1 */
|
8804 |
POWERPC_DEF_SVR("MPC8555_v11",
|
8805 |
CPU_POWERPC_MPC8555_v11, POWERPC_SVR_8555_v11, e500v2), |
8806 |
/* MPC8555E */
|
8807 |
POWERPC_DEF_SVR("MPC8555E",
|
8808 |
CPU_POWERPC_MPC8555E, POWERPC_SVR_8555E, e500v2), |
8809 |
/* MPC8555E v1.0 */
|
8810 |
POWERPC_DEF_SVR("MPC8555E_v10",
|
8811 |
CPU_POWERPC_MPC8555E_v10, POWERPC_SVR_8555E_v10, e500v2), |
8812 |
/* MPC8555E v1.1 */
|
8813 |
POWERPC_DEF_SVR("MPC8555E_v11",
|
8814 |
CPU_POWERPC_MPC8555E_v11, POWERPC_SVR_8555E_v11, e500v2), |
8815 |
/* MPC8560 */
|
8816 |
POWERPC_DEF_SVR("MPC8560",
|
8817 |
CPU_POWERPC_MPC8560, POWERPC_SVR_8560, e500v2), |
8818 |
/* MPC8560 v1.0 */
|
8819 |
POWERPC_DEF_SVR("MPC8560_v10",
|
8820 |
CPU_POWERPC_MPC8560_v10, POWERPC_SVR_8560_v10, e500v2), |
8821 |
/* MPC8560 v2.0 */
|
8822 |
POWERPC_DEF_SVR("MPC8560_v20",
|
8823 |
CPU_POWERPC_MPC8560_v20, POWERPC_SVR_8560_v20, e500v2), |
8824 |
/* MPC8560 v2.1 */
|
8825 |
POWERPC_DEF_SVR("MPC8560_v21",
|
8826 |
CPU_POWERPC_MPC8560_v21, POWERPC_SVR_8560_v21, e500v2), |
8827 |
/* MPC8567 */
|
8828 |
POWERPC_DEF_SVR("MPC8567",
|
8829 |
CPU_POWERPC_MPC8567, POWERPC_SVR_8567, e500v2), |
8830 |
/* MPC8567E */
|
8831 |
POWERPC_DEF_SVR("MPC8567E",
|
8832 |
CPU_POWERPC_MPC8567E, POWERPC_SVR_8567E, e500v2), |
8833 |
/* MPC8568 */
|
8834 |
POWERPC_DEF_SVR("MPC8568",
|
8835 |
CPU_POWERPC_MPC8568, POWERPC_SVR_8568, e500v2), |
8836 |
/* MPC8568E */
|
8837 |
POWERPC_DEF_SVR("MPC8568E",
|
8838 |
CPU_POWERPC_MPC8568E, POWERPC_SVR_8568E, e500v2), |
8839 |
/* MPC8572 */
|
8840 |
POWERPC_DEF_SVR("MPC8572",
|
8841 |
CPU_POWERPC_MPC8572, POWERPC_SVR_8572, e500v2), |
8842 |
/* MPC8572E */
|
8843 |
POWERPC_DEF_SVR("MPC8572E",
|
8844 |
CPU_POWERPC_MPC8572E, POWERPC_SVR_8572E, e500v2), |
8845 |
/* e600 family */
|
8846 |
/* PowerPC e600 core */
|
8847 |
POWERPC_DEF("e600", CPU_POWERPC_e600, 7400), |
8848 |
/* PowerPC e600 microcontrollers */
|
8849 |
#if defined (TODO)
|
8850 |
/* MPC8610 */
|
8851 |
POWERPC_DEF_SVR("MPC8610",
|
8852 |
CPU_POWERPC_MPC8610, POWERPC_SVR_8610, 7400),
|
8853 |
#endif
|
8854 |
/* MPC8641 */
|
8855 |
POWERPC_DEF_SVR("MPC8641",
|
8856 |
CPU_POWERPC_MPC8641, POWERPC_SVR_8641, 7400),
|
8857 |
/* MPC8641D */
|
8858 |
POWERPC_DEF_SVR("MPC8641D",
|
8859 |
CPU_POWERPC_MPC8641D, POWERPC_SVR_8641D, 7400),
|
8860 |
/* 32 bits "classic" PowerPC */
|
8861 |
/* PowerPC 6xx family */
|
8862 |
/* PowerPC 601 */
|
8863 |
POWERPC_DEF("601", CPU_POWERPC_601, 601v), |
8864 |
/* PowerPC 601v0 */
|
8865 |
POWERPC_DEF("601_v0", CPU_POWERPC_601_v0, 601), |
8866 |
/* PowerPC 601v1 */
|
8867 |
POWERPC_DEF("601_v1", CPU_POWERPC_601_v1, 601), |
8868 |
/* PowerPC 601v */
|
8869 |
POWERPC_DEF("601v", CPU_POWERPC_601v, 601v), |
8870 |
/* PowerPC 601v2 */
|
8871 |
POWERPC_DEF("601_v2", CPU_POWERPC_601_v2, 601v), |
8872 |
/* PowerPC 602 */
|
8873 |
POWERPC_DEF("602", CPU_POWERPC_602, 602), |
8874 |
/* PowerPC 603 */
|
8875 |
POWERPC_DEF("603", CPU_POWERPC_603, 603), |
8876 |
/* Code name for PowerPC 603 */
|
8877 |
POWERPC_DEF("Vanilla", CPU_POWERPC_603, 603), |
8878 |
/* PowerPC 603e (aka PID6) */
|
8879 |
POWERPC_DEF("603e", CPU_POWERPC_603E, 603E), |
8880 |
/* Code name for PowerPC 603e */
|
8881 |
POWERPC_DEF("Stretch", CPU_POWERPC_603E, 603E), |
8882 |
/* PowerPC 603e v1.1 */
|
8883 |
POWERPC_DEF("603e_v1.1", CPU_POWERPC_603E_v11, 603E), |
8884 |
/* PowerPC 603e v1.2 */
|
8885 |
POWERPC_DEF("603e_v1.2", CPU_POWERPC_603E_v12, 603E), |
8886 |
/* PowerPC 603e v1.3 */
|
8887 |
POWERPC_DEF("603e_v1.3", CPU_POWERPC_603E_v13, 603E), |
8888 |
/* PowerPC 603e v1.4 */
|
8889 |
POWERPC_DEF("603e_v1.4", CPU_POWERPC_603E_v14, 603E), |
8890 |
/* PowerPC 603e v2.2 */
|
8891 |
POWERPC_DEF("603e_v2.2", CPU_POWERPC_603E_v22, 603E), |
8892 |
/* PowerPC 603e v3 */
|
8893 |
POWERPC_DEF("603e_v3", CPU_POWERPC_603E_v3, 603E), |
8894 |
/* PowerPC 603e v4 */
|
8895 |
POWERPC_DEF("603e_v4", CPU_POWERPC_603E_v4, 603E), |
8896 |
/* PowerPC 603e v4.1 */
|
8897 |
POWERPC_DEF("603e_v4.1", CPU_POWERPC_603E_v41, 603E), |
8898 |
/* PowerPC 603e (aka PID7) */
|
8899 |
POWERPC_DEF("603e7", CPU_POWERPC_603E7, 603E), |
8900 |
/* PowerPC 603e7t */
|
8901 |
POWERPC_DEF("603e7t", CPU_POWERPC_603E7t, 603E), |
8902 |
/* PowerPC 603e7v */
|
8903 |
POWERPC_DEF("603e7v", CPU_POWERPC_603E7v, 603E), |
8904 |
/* Code name for PowerPC 603ev */
|
8905 |
POWERPC_DEF("Vaillant", CPU_POWERPC_603E7v, 603E), |
8906 |
/* PowerPC 603e7v1 */
|
8907 |
POWERPC_DEF("603e7v1", CPU_POWERPC_603E7v1, 603E), |
8908 |
/* PowerPC 603e7v2 */
|
8909 |
POWERPC_DEF("603e7v2", CPU_POWERPC_603E7v2, 603E), |
8910 |
/* PowerPC 603p (aka PID7v) */
|
8911 |
POWERPC_DEF("603p", CPU_POWERPC_603P, 603E), |
8912 |
/* PowerPC 603r (aka PID7t) */
|
8913 |
POWERPC_DEF("603r", CPU_POWERPC_603R, 603E), |
8914 |
/* Code name for PowerPC 603r */
|
8915 |
POWERPC_DEF("Goldeneye", CPU_POWERPC_603R, 603E), |
8916 |
/* PowerPC 604 */
|
8917 |
POWERPC_DEF("604", CPU_POWERPC_604, 604), |
8918 |
/* PowerPC 604e (aka PID9) */
|
8919 |
POWERPC_DEF("604e", CPU_POWERPC_604E, 604E), |
8920 |
/* Code name for PowerPC 604e */
|
8921 |
POWERPC_DEF("Sirocco", CPU_POWERPC_604E, 604E), |
8922 |
/* PowerPC 604e v1.0 */
|
8923 |
POWERPC_DEF("604e_v1.0", CPU_POWERPC_604E_v10, 604E), |
8924 |
/* PowerPC 604e v2.2 */
|
8925 |
POWERPC_DEF("604e_v2.2", CPU_POWERPC_604E_v22, 604E), |
8926 |
/* PowerPC 604e v2.4 */
|
8927 |
POWERPC_DEF("604e_v2.4", CPU_POWERPC_604E_v24, 604E), |
8928 |
/* PowerPC 604r (aka PIDA) */
|
8929 |
POWERPC_DEF("604r", CPU_POWERPC_604R, 604E), |
8930 |
/* Code name for PowerPC 604r */
|
8931 |
POWERPC_DEF("Mach5", CPU_POWERPC_604R, 604E), |
8932 |
#if defined(TODO)
|
8933 |
/* PowerPC 604ev */
|
8934 |
POWERPC_DEF("604ev", CPU_POWERPC_604EV, 604E), |
8935 |
#endif
|
8936 |
/* PowerPC 7xx family */
|
8937 |
/* Generic PowerPC 740 (G3) */
|
8938 |
POWERPC_DEF("740", CPU_POWERPC_7x0, 740), |
8939 |
/* Code name for PowerPC 740 */
|
8940 |
POWERPC_DEF("Arthur", CPU_POWERPC_7x0, 740), |
8941 |
/* Generic PowerPC 750 (G3) */
|
8942 |
POWERPC_DEF("750", CPU_POWERPC_7x0, 750), |
8943 |
/* Code name for PowerPC 750 */
|
8944 |
POWERPC_DEF("Typhoon", CPU_POWERPC_7x0, 750), |
8945 |
/* PowerPC 740/750 is also known as G3 */
|
8946 |
POWERPC_DEF("G3", CPU_POWERPC_7x0, 750), |
8947 |
/* PowerPC 740 v1.0 (G3) */
|
8948 |
POWERPC_DEF("740_v1.0", CPU_POWERPC_7x0_v10, 740), |
8949 |
/* PowerPC 750 v1.0 (G3) */
|
8950 |
POWERPC_DEF("750_v1.0", CPU_POWERPC_7x0_v10, 750), |
8951 |
/* PowerPC 740 v2.0 (G3) */
|
8952 |
POWERPC_DEF("740_v2.0", CPU_POWERPC_7x0_v20, 740), |
8953 |
/* PowerPC 750 v2.0 (G3) */
|
8954 |
POWERPC_DEF("750_v2.0", CPU_POWERPC_7x0_v20, 750), |
8955 |
/* PowerPC 740 v2.1 (G3) */
|
8956 |
POWERPC_DEF("740_v2.1", CPU_POWERPC_7x0_v21, 740), |
8957 |
/* PowerPC 750 v2.1 (G3) */
|
8958 |
POWERPC_DEF("750_v2.1", CPU_POWERPC_7x0_v21, 750), |
8959 |
/* PowerPC 740 v2.2 (G3) */
|
8960 |
POWERPC_DEF("740_v2.2", CPU_POWERPC_7x0_v22, 740), |
8961 |
/* PowerPC 750 v2.2 (G3) */
|
8962 |
POWERPC_DEF("750_v2.2", CPU_POWERPC_7x0_v22, 750), |
8963 |
/* PowerPC 740 v3.0 (G3) */
|
8964 |
POWERPC_DEF("740_v3.0", CPU_POWERPC_7x0_v30, 740), |
8965 |
/* PowerPC 750 v3.0 (G3) */
|
8966 |
POWERPC_DEF("750_v3.0", CPU_POWERPC_7x0_v30, 750), |
8967 |
/* PowerPC 740 v3.1 (G3) */
|
8968 |
POWERPC_DEF("740_v3.1", CPU_POWERPC_7x0_v31, 740), |
8969 |
/* PowerPC 750 v3.1 (G3) */
|
8970 |
POWERPC_DEF("750_v3.1", CPU_POWERPC_7x0_v31, 750), |
8971 |
/* PowerPC 740E (G3) */
|
8972 |
POWERPC_DEF("740e", CPU_POWERPC_740E, 740), |
8973 |
/* PowerPC 750E (G3) */
|
8974 |
POWERPC_DEF("750e", CPU_POWERPC_750E, 750), |
8975 |
/* PowerPC 740P (G3) */
|
8976 |
POWERPC_DEF("740p", CPU_POWERPC_7x0P, 740), |
8977 |
/* PowerPC 750P (G3) */
|
8978 |
POWERPC_DEF("750p", CPU_POWERPC_7x0P, 750), |
8979 |
/* Code name for PowerPC 740P/750P (G3) */
|
8980 |
POWERPC_DEF("Conan/Doyle", CPU_POWERPC_7x0P, 750), |
8981 |
/* PowerPC 750CL (G3 embedded) */
|
8982 |
POWERPC_DEF("750cl", CPU_POWERPC_750CL, 750cl), |
8983 |
/* PowerPC 750CL v1.0 */
|
8984 |
POWERPC_DEF("750cl_v1.0", CPU_POWERPC_750CL_v10, 750cl), |
8985 |
/* PowerPC 750CL v2.0 */
|
8986 |
POWERPC_DEF("750cl_v2.0", CPU_POWERPC_750CL_v20, 750cl), |
8987 |
/* PowerPC 750CX (G3 embedded) */
|
8988 |
POWERPC_DEF("750cx", CPU_POWERPC_750CX, 750cx), |
8989 |
/* PowerPC 750CX v1.0 (G3 embedded) */
|
8990 |
POWERPC_DEF("750cx_v1.0", CPU_POWERPC_750CX_v10, 750cx), |
8991 |
/* PowerPC 750CX v2.1 (G3 embedded) */
|
8992 |
POWERPC_DEF("750cx_v2.0", CPU_POWERPC_750CX_v20, 750cx), |
8993 |
/* PowerPC 750CX v2.1 (G3 embedded) */
|
8994 |
POWERPC_DEF("750cx_v2.1", CPU_POWERPC_750CX_v21, 750cx), |
8995 |
/* PowerPC 750CX v2.2 (G3 embedded) */
|
8996 |
POWERPC_DEF("750cx_v2.2", CPU_POWERPC_750CX_v22, 750cx), |
8997 |
/* PowerPC 750CXe (G3 embedded) */
|
8998 |
POWERPC_DEF("750cxe", CPU_POWERPC_750CXE, 750cx), |
8999 |
/* PowerPC 750CXe v2.1 (G3 embedded) */
|
9000 |
POWERPC_DEF("750cxe_v2.1", CPU_POWERPC_750CXE_v21, 750cx), |
9001 |
/* PowerPC 750CXe v2.2 (G3 embedded) */
|
9002 |
POWERPC_DEF("750cxe_v2.2", CPU_POWERPC_750CXE_v22, 750cx), |
9003 |
/* PowerPC 750CXe v2.3 (G3 embedded) */
|
9004 |
POWERPC_DEF("750cxe_v2.3", CPU_POWERPC_750CXE_v23, 750cx), |
9005 |
/* PowerPC 750CXe v2.4 (G3 embedded) */
|
9006 |
POWERPC_DEF("750cxe_v2.4", CPU_POWERPC_750CXE_v24, 750cx), |
9007 |
/* PowerPC 750CXe v2.4b (G3 embedded) */
|
9008 |
POWERPC_DEF("750cxe_v2.4b", CPU_POWERPC_750CXE_v24b, 750cx), |
9009 |
/* PowerPC 750CXe v3.0 (G3 embedded) */
|
9010 |
POWERPC_DEF("750cxe_v3.0", CPU_POWERPC_750CXE_v30, 750cx), |
9011 |
/* PowerPC 750CXe v3.1 (G3 embedded) */
|
9012 |
POWERPC_DEF("750cxe_v3.1", CPU_POWERPC_750CXE_v31, 750cx), |
9013 |
/* PowerPC 750CXe v3.1b (G3 embedded) */
|
9014 |
POWERPC_DEF("750cxe_v3.1b", CPU_POWERPC_750CXE_v31b, 750cx), |
9015 |
/* PowerPC 750CXr (G3 embedded) */
|
9016 |
POWERPC_DEF("750cxr", CPU_POWERPC_750CXR, 750cx), |
9017 |
/* PowerPC 750FL (G3 embedded) */
|
9018 |
POWERPC_DEF("750fl", CPU_POWERPC_750FL, 750fx), |
9019 |
/* PowerPC 750FX (G3 embedded) */
|
9020 |
POWERPC_DEF("750fx", CPU_POWERPC_750FX, 750fx), |
9021 |
/* PowerPC 750FX v1.0 (G3 embedded) */
|
9022 |
POWERPC_DEF("750fx_v1.0", CPU_POWERPC_750FX_v10, 750fx), |
9023 |
/* PowerPC 750FX v2.0 (G3 embedded) */
|
9024 |
POWERPC_DEF("750fx_v2.0", CPU_POWERPC_750FX_v20, 750fx), |
9025 |
/* PowerPC 750FX v2.1 (G3 embedded) */
|
9026 |
POWERPC_DEF("750fx_v2.1", CPU_POWERPC_750FX_v21, 750fx), |
9027 |
/* PowerPC 750FX v2.2 (G3 embedded) */
|
9028 |
POWERPC_DEF("750fx_v2.2", CPU_POWERPC_750FX_v22, 750fx), |
9029 |
/* PowerPC 750FX v2.3 (G3 embedded) */
|
9030 |
POWERPC_DEF("750fx_v2.3", CPU_POWERPC_750FX_v23, 750fx), |
9031 |
/* PowerPC 750GL (G3 embedded) */
|
9032 |
POWERPC_DEF("750gl", CPU_POWERPC_750GL, 750gx), |
9033 |
/* PowerPC 750GX (G3 embedded) */
|
9034 |
POWERPC_DEF("750gx", CPU_POWERPC_750GX, 750gx), |
9035 |
/* PowerPC 750GX v1.0 (G3 embedded) */
|
9036 |
POWERPC_DEF("750gx_v1.0", CPU_POWERPC_750GX_v10, 750gx), |
9037 |
/* PowerPC 750GX v1.1 (G3 embedded) */
|
9038 |
POWERPC_DEF("750gx_v1.1", CPU_POWERPC_750GX_v11, 750gx), |
9039 |
/* PowerPC 750GX v1.2 (G3 embedded) */
|
9040 |
POWERPC_DEF("750gx_v1.2", CPU_POWERPC_750GX_v12, 750gx), |
9041 |
/* PowerPC 750L (G3 embedded) */
|
9042 |
POWERPC_DEF("750l", CPU_POWERPC_750L, 750), |
9043 |
/* Code name for PowerPC 750L (G3 embedded) */
|
9044 |
POWERPC_DEF("LoneStar", CPU_POWERPC_750L, 750), |
9045 |
/* PowerPC 750L v2.0 (G3 embedded) */
|
9046 |
POWERPC_DEF("750l_v2.0", CPU_POWERPC_750L_v20, 750), |
9047 |
/* PowerPC 750L v2.1 (G3 embedded) */
|
9048 |
POWERPC_DEF("750l_v2.1", CPU_POWERPC_750L_v21, 750), |
9049 |
/* PowerPC 750L v2.2 (G3 embedded) */
|
9050 |
POWERPC_DEF("750l_v2.2", CPU_POWERPC_750L_v22, 750), |
9051 |
/* PowerPC 750L v3.0 (G3 embedded) */
|
9052 |
POWERPC_DEF("750l_v3.0", CPU_POWERPC_750L_v30, 750), |
9053 |
/* PowerPC 750L v3.2 (G3 embedded) */
|
9054 |
POWERPC_DEF("750l_v3.2", CPU_POWERPC_750L_v32, 750), |
9055 |
/* Generic PowerPC 745 */
|
9056 |
POWERPC_DEF("745", CPU_POWERPC_7x5, 745), |
9057 |
/* Generic PowerPC 755 */
|
9058 |
POWERPC_DEF("755", CPU_POWERPC_7x5, 755), |
9059 |
/* Code name for PowerPC 745/755 */
|
9060 |
POWERPC_DEF("Goldfinger", CPU_POWERPC_7x5, 755), |
9061 |
/* PowerPC 745 v1.0 */
|
9062 |
POWERPC_DEF("745_v1.0", CPU_POWERPC_7x5_v10, 745), |
9063 |
/* PowerPC 755 v1.0 */
|
9064 |
POWERPC_DEF("755_v1.0", CPU_POWERPC_7x5_v10, 755), |
9065 |
/* PowerPC 745 v1.1 */
|
9066 |
POWERPC_DEF("745_v1.1", CPU_POWERPC_7x5_v11, 745), |
9067 |
/* PowerPC 755 v1.1 */
|
9068 |
POWERPC_DEF("755_v1.1", CPU_POWERPC_7x5_v11, 755), |
9069 |
/* PowerPC 745 v2.0 */
|
9070 |
POWERPC_DEF("745_v2.0", CPU_POWERPC_7x5_v20, 745), |
9071 |
/* PowerPC 755 v2.0 */
|
9072 |
POWERPC_DEF("755_v2.0", CPU_POWERPC_7x5_v20, 755), |
9073 |
/* PowerPC 745 v2.1 */
|
9074 |
POWERPC_DEF("745_v2.1", CPU_POWERPC_7x5_v21, 745), |
9075 |
/* PowerPC 755 v2.1 */
|
9076 |
POWERPC_DEF("755_v2.1", CPU_POWERPC_7x5_v21, 755), |
9077 |
/* PowerPC 745 v2.2 */
|
9078 |
POWERPC_DEF("745_v2.2", CPU_POWERPC_7x5_v22, 745), |
9079 |
/* PowerPC 755 v2.2 */
|
9080 |
POWERPC_DEF("755_v2.2", CPU_POWERPC_7x5_v22, 755), |
9081 |
/* PowerPC 745 v2.3 */
|
9082 |
POWERPC_DEF("745_v2.3", CPU_POWERPC_7x5_v23, 745), |
9083 |
/* PowerPC 755 v2.3 */
|
9084 |
POWERPC_DEF("755_v2.3", CPU_POWERPC_7x5_v23, 755), |
9085 |
/* PowerPC 745 v2.4 */
|
9086 |
POWERPC_DEF("745_v2.4", CPU_POWERPC_7x5_v24, 745), |
9087 |
/* PowerPC 755 v2.4 */
|
9088 |
POWERPC_DEF("755_v2.4", CPU_POWERPC_7x5_v24, 755), |
9089 |
/* PowerPC 745 v2.5 */
|
9090 |
POWERPC_DEF("745_v2.5", CPU_POWERPC_7x5_v25, 745), |
9091 |
/* PowerPC 755 v2.5 */
|
9092 |
POWERPC_DEF("755_v2.5", CPU_POWERPC_7x5_v25, 755), |
9093 |
/* PowerPC 745 v2.6 */
|
9094 |
POWERPC_DEF("745_v2.6", CPU_POWERPC_7x5_v26, 745), |
9095 |
/* PowerPC 755 v2.6 */
|
9096 |
POWERPC_DEF("755_v2.6", CPU_POWERPC_7x5_v26, 755), |
9097 |
/* PowerPC 745 v2.7 */
|
9098 |
POWERPC_DEF("745_v2.7", CPU_POWERPC_7x5_v27, 745), |
9099 |
/* PowerPC 755 v2.7 */
|
9100 |
POWERPC_DEF("755_v2.7", CPU_POWERPC_7x5_v27, 755), |
9101 |
/* PowerPC 745 v2.8 */
|
9102 |
POWERPC_DEF("745_v2.8", CPU_POWERPC_7x5_v28, 745), |
9103 |
/* PowerPC 755 v2.8 */
|
9104 |
POWERPC_DEF("755_v2.8", CPU_POWERPC_7x5_v28, 755), |
9105 |
#if defined (TODO)
|
9106 |
/* PowerPC 745P (G3) */
|
9107 |
POWERPC_DEF("745p", CPU_POWERPC_7x5P, 745), |
9108 |
/* PowerPC 755P (G3) */
|
9109 |
POWERPC_DEF("755p", CPU_POWERPC_7x5P, 755), |
9110 |
#endif
|
9111 |
/* PowerPC 74xx family */
|
9112 |
/* PowerPC 7400 (G4) */
|
9113 |
POWERPC_DEF("7400", CPU_POWERPC_7400, 7400), |
9114 |
/* Code name for PowerPC 7400 */
|
9115 |
POWERPC_DEF("Max", CPU_POWERPC_7400, 7400), |
9116 |
/* PowerPC 74xx is also well known as G4 */
|
9117 |
POWERPC_DEF("G4", CPU_POWERPC_7400, 7400), |
9118 |
/* PowerPC 7400 v1.0 (G4) */
|
9119 |
POWERPC_DEF("7400_v1.0", CPU_POWERPC_7400_v10, 7400), |
9120 |
/* PowerPC 7400 v1.1 (G4) */
|
9121 |
POWERPC_DEF("7400_v1.1", CPU_POWERPC_7400_v11, 7400), |
9122 |
/* PowerPC 7400 v2.0 (G4) */
|
9123 |
POWERPC_DEF("7400_v2.0", CPU_POWERPC_7400_v20, 7400), |
9124 |
/* PowerPC 7400 v2.1 (G4) */
|
9125 |
POWERPC_DEF("7400_v2.1", CPU_POWERPC_7400_v21, 7400), |
9126 |
/* PowerPC 7400 v2.2 (G4) */
|
9127 |
POWERPC_DEF("7400_v2.2", CPU_POWERPC_7400_v22, 7400), |
9128 |
/* PowerPC 7400 v2.6 (G4) */
|
9129 |
POWERPC_DEF("7400_v2.6", CPU_POWERPC_7400_v26, 7400), |
9130 |
/* PowerPC 7400 v2.7 (G4) */
|
9131 |
POWERPC_DEF("7400_v2.7", CPU_POWERPC_7400_v27, 7400), |
9132 |
/* PowerPC 7400 v2.8 (G4) */
|
9133 |
POWERPC_DEF("7400_v2.8", CPU_POWERPC_7400_v28, 7400), |
9134 |
/* PowerPC 7400 v2.9 (G4) */
|
9135 |
POWERPC_DEF("7400_v2.9", CPU_POWERPC_7400_v29, 7400), |
9136 |
/* PowerPC 7410 (G4) */
|
9137 |
POWERPC_DEF("7410", CPU_POWERPC_7410, 7410), |
9138 |
/* Code name for PowerPC 7410 */
|
9139 |
POWERPC_DEF("Nitro", CPU_POWERPC_7410, 7410), |
9140 |
/* PowerPC 7410 v1.0 (G4) */
|
9141 |
POWERPC_DEF("7410_v1.0", CPU_POWERPC_7410_v10, 7410), |
9142 |
/* PowerPC 7410 v1.1 (G4) */
|
9143 |
POWERPC_DEF("7410_v1.1", CPU_POWERPC_7410_v11, 7410), |
9144 |
/* PowerPC 7410 v1.2 (G4) */
|
9145 |
POWERPC_DEF("7410_v1.2", CPU_POWERPC_7410_v12, 7410), |
9146 |
/* PowerPC 7410 v1.3 (G4) */
|
9147 |
POWERPC_DEF("7410_v1.3", CPU_POWERPC_7410_v13, 7410), |
9148 |
/* PowerPC 7410 v1.4 (G4) */
|
9149 |
POWERPC_DEF("7410_v1.4", CPU_POWERPC_7410_v14, 7410), |
9150 |
/* PowerPC 7448 (G4) */
|
9151 |
POWERPC_DEF("7448", CPU_POWERPC_7448, 7400), |
9152 |
/* PowerPC 7448 v1.0 (G4) */
|
9153 |
POWERPC_DEF("7448_v1.0", CPU_POWERPC_7448_v10, 7400), |
9154 |
/* PowerPC 7448 v1.1 (G4) */
|
9155 |
POWERPC_DEF("7448_v1.1", CPU_POWERPC_7448_v11, 7400), |
9156 |
/* PowerPC 7448 v2.0 (G4) */
|
9157 |
POWERPC_DEF("7448_v2.0", CPU_POWERPC_7448_v20, 7400), |
9158 |
/* PowerPC 7448 v2.1 (G4) */
|
9159 |
POWERPC_DEF("7448_v2.1", CPU_POWERPC_7448_v21, 7400), |
9160 |
/* PowerPC 7450 (G4) */
|
9161 |
POWERPC_DEF("7450", CPU_POWERPC_7450, 7450), |
9162 |
/* Code name for PowerPC 7450 */
|
9163 |
POWERPC_DEF("Vger", CPU_POWERPC_7450, 7450), |
9164 |
/* PowerPC 7450 v1.0 (G4) */
|
9165 |
POWERPC_DEF("7450_v1.0", CPU_POWERPC_7450_v10, 7450), |
9166 |
/* PowerPC 7450 v1.1 (G4) */
|
9167 |
POWERPC_DEF("7450_v1.1", CPU_POWERPC_7450_v11, 7450), |
9168 |
/* PowerPC 7450 v1.2 (G4) */
|
9169 |
POWERPC_DEF("7450_v1.2", CPU_POWERPC_7450_v12, 7450), |
9170 |
/* PowerPC 7450 v2.0 (G4) */
|
9171 |
POWERPC_DEF("7450_v2.0", CPU_POWERPC_7450_v20, 7450), |
9172 |
/* PowerPC 7450 v2.1 (G4) */
|
9173 |
POWERPC_DEF("7450_v2.1", CPU_POWERPC_7450_v21, 7450), |
9174 |
/* PowerPC 7441 (G4) */
|
9175 |
POWERPC_DEF("7441", CPU_POWERPC_74x1, 7440), |
9176 |
/* PowerPC 7451 (G4) */
|
9177 |
POWERPC_DEF("7451", CPU_POWERPC_74x1, 7450), |
9178 |
/* PowerPC 7441 v2.1 (G4) */
|
9179 |
POWERPC_DEF("7441_v2.1", CPU_POWERPC_7450_v21, 7440), |
9180 |
/* PowerPC 7441 v2.3 (G4) */
|
9181 |
POWERPC_DEF("7441_v2.3", CPU_POWERPC_74x1_v23, 7440), |
9182 |
/* PowerPC 7451 v2.3 (G4) */
|
9183 |
POWERPC_DEF("7451_v2.3", CPU_POWERPC_74x1_v23, 7450), |
9184 |
/* PowerPC 7441 v2.10 (G4) */
|
9185 |
POWERPC_DEF("7441_v2.10", CPU_POWERPC_74x1_v210, 7440), |
9186 |
/* PowerPC 7451 v2.10 (G4) */
|
9187 |
POWERPC_DEF("7451_v2.10", CPU_POWERPC_74x1_v210, 7450), |
9188 |
/* PowerPC 7445 (G4) */
|
9189 |
POWERPC_DEF("7445", CPU_POWERPC_74x5, 7445), |
9190 |
/* PowerPC 7455 (G4) */
|
9191 |
POWERPC_DEF("7455", CPU_POWERPC_74x5, 7455), |
9192 |
/* Code name for PowerPC 7445/7455 */
|
9193 |
POWERPC_DEF("Apollo6", CPU_POWERPC_74x5, 7455), |
9194 |
/* PowerPC 7445 v1.0 (G4) */
|
9195 |
POWERPC_DEF("7445_v1.0", CPU_POWERPC_74x5_v10, 7445), |
9196 |
/* PowerPC 7455 v1.0 (G4) */
|
9197 |
POWERPC_DEF("7455_v1.0", CPU_POWERPC_74x5_v10, 7455), |
9198 |
/* PowerPC 7445 v2.1 (G4) */
|
9199 |
POWERPC_DEF("7445_v2.1", CPU_POWERPC_74x5_v21, 7445), |
9200 |
/* PowerPC 7455 v2.1 (G4) */
|
9201 |
POWERPC_DEF("7455_v2.1", CPU_POWERPC_74x5_v21, 7455), |
9202 |
/* PowerPC 7445 v3.2 (G4) */
|
9203 |
POWERPC_DEF("7445_v3.2", CPU_POWERPC_74x5_v32, 7445), |
9204 |
/* PowerPC 7455 v3.2 (G4) */
|
9205 |
POWERPC_DEF("7455_v3.2", CPU_POWERPC_74x5_v32, 7455), |
9206 |
/* PowerPC 7445 v3.3 (G4) */
|
9207 |
POWERPC_DEF("7445_v3.3", CPU_POWERPC_74x5_v33, 7445), |
9208 |
/* PowerPC 7455 v3.3 (G4) */
|
9209 |
POWERPC_DEF("7455_v3.3", CPU_POWERPC_74x5_v33, 7455), |
9210 |
/* PowerPC 7445 v3.4 (G4) */
|
9211 |
POWERPC_DEF("7445_v3.4", CPU_POWERPC_74x5_v34, 7445), |
9212 |
/* PowerPC 7455 v3.4 (G4) */
|
9213 |
POWERPC_DEF("7455_v3.4", CPU_POWERPC_74x5_v34, 7455), |
9214 |
/* PowerPC 7447 (G4) */
|
9215 |
POWERPC_DEF("7447", CPU_POWERPC_74x7, 7445), |
9216 |
/* PowerPC 7457 (G4) */
|
9217 |
POWERPC_DEF("7457", CPU_POWERPC_74x7, 7455), |
9218 |
/* Code name for PowerPC 7447/7457 */
|
9219 |
POWERPC_DEF("Apollo7", CPU_POWERPC_74x7, 7455), |
9220 |
/* PowerPC 7447 v1.0 (G4) */
|
9221 |
POWERPC_DEF("7447_v1.0", CPU_POWERPC_74x7_v10, 7445), |
9222 |
/* PowerPC 7457 v1.0 (G4) */
|
9223 |
POWERPC_DEF("7457_v1.0", CPU_POWERPC_74x7_v10, 7455), |
9224 |
/* PowerPC 7447 v1.1 (G4) */
|
9225 |
POWERPC_DEF("7447_v1.1", CPU_POWERPC_74x7_v11, 7445), |
9226 |
/* PowerPC 7457 v1.1 (G4) */
|
9227 |
POWERPC_DEF("7457_v1.1", CPU_POWERPC_74x7_v11, 7455), |
9228 |
/* PowerPC 7457 v1.2 (G4) */
|
9229 |
POWERPC_DEF("7457_v1.2", CPU_POWERPC_74x7_v12, 7455), |
9230 |
/* PowerPC 7447A (G4) */
|
9231 |
POWERPC_DEF("7447A", CPU_POWERPC_74x7A, 7445), |
9232 |
/* PowerPC 7457A (G4) */
|
9233 |
POWERPC_DEF("7457A", CPU_POWERPC_74x7A, 7455), |
9234 |
/* PowerPC 7447A v1.0 (G4) */
|
9235 |
POWERPC_DEF("7447A_v1.0", CPU_POWERPC_74x7A_v10, 7445), |
9236 |
/* PowerPC 7457A v1.0 (G4) */
|
9237 |
POWERPC_DEF("7457A_v1.0", CPU_POWERPC_74x7A_v10, 7455), |
9238 |
/* Code name for PowerPC 7447A/7457A */
|
9239 |
POWERPC_DEF("Apollo7PM", CPU_POWERPC_74x7A_v10, 7455), |
9240 |
/* PowerPC 7447A v1.1 (G4) */
|
9241 |
POWERPC_DEF("7447A_v1.1", CPU_POWERPC_74x7A_v11, 7445), |
9242 |
/* PowerPC 7457A v1.1 (G4) */
|
9243 |
POWERPC_DEF("7457A_v1.1", CPU_POWERPC_74x7A_v11, 7455), |
9244 |
/* PowerPC 7447A v1.2 (G4) */
|
9245 |
POWERPC_DEF("7447A_v1.2", CPU_POWERPC_74x7A_v12, 7445), |
9246 |
/* PowerPC 7457A v1.2 (G4) */
|
9247 |
POWERPC_DEF("7457A_v1.2", CPU_POWERPC_74x7A_v12, 7455), |
9248 |
/* 64 bits PowerPC */
|
9249 |
#if defined (TARGET_PPC64)
|
9250 |
/* PowerPC 620 */
|
9251 |
POWERPC_DEF("620", CPU_POWERPC_620, 620), |
9252 |
/* Code name for PowerPC 620 */
|
9253 |
POWERPC_DEF("Trident", CPU_POWERPC_620, 620), |
9254 |
#if defined (TODO)
|
9255 |
/* PowerPC 630 (POWER3) */
|
9256 |
POWERPC_DEF("630", CPU_POWERPC_630, 630), |
9257 |
POWERPC_DEF("POWER3", CPU_POWERPC_630, 630), |
9258 |
/* Code names for POWER3 */
|
9259 |
POWERPC_DEF("Boxer", CPU_POWERPC_630, 630), |
9260 |
POWERPC_DEF("Dino", CPU_POWERPC_630, 630), |
9261 |
#endif
|
9262 |
#if defined (TODO)
|
9263 |
/* PowerPC 631 (Power 3+) */
|
9264 |
POWERPC_DEF("631", CPU_POWERPC_631, 631), |
9265 |
POWERPC_DEF("POWER3+", CPU_POWERPC_631, 631), |
9266 |
#endif
|
9267 |
#if defined (TODO)
|
9268 |
/* POWER4 */
|
9269 |
POWERPC_DEF("POWER4", CPU_POWERPC_POWER4, POWER4),
|
9270 |
#endif
|
9271 |
#if defined (TODO)
|
9272 |
/* POWER4p */
|
9273 |
POWERPC_DEF("POWER4+", CPU_POWERPC_POWER4P, POWER4P),
|
9274 |
#endif
|
9275 |
#if defined (TODO)
|
9276 |
/* POWER5 */
|
9277 |
POWERPC_DEF("POWER5", CPU_POWERPC_POWER5, POWER5),
|
9278 |
/* POWER5GR */
|
9279 |
POWERPC_DEF("POWER5gr", CPU_POWERPC_POWER5GR, POWER5),
|
9280 |
#endif
|
9281 |
#if defined (TODO)
|
9282 |
/* POWER5+ */
|
9283 |
POWERPC_DEF("POWER5+", CPU_POWERPC_POWER5P, POWER5P),
|
9284 |
/* POWER5GS */
|
9285 |
POWERPC_DEF("POWER5gs", CPU_POWERPC_POWER5GS, POWER5P),
|
9286 |
#endif
|
9287 |
#if defined (TODO)
|
9288 |
/* POWER6 */
|
9289 |
POWERPC_DEF("POWER6", CPU_POWERPC_POWER6, POWER6),
|
9290 |
/* POWER6 running in POWER5 mode */
|
9291 |
POWERPC_DEF("POWER6_5", CPU_POWERPC_POWER6_5, POWER5),
|
9292 |
/* POWER6A */
|
9293 |
POWERPC_DEF("POWER6A", CPU_POWERPC_POWER6A, POWER6),
|
9294 |
#endif
|
9295 |
/* POWER7 */
|
9296 |
POWERPC_DEF("POWER7", CPU_POWERPC_POWER7, POWER7),
|
9297 |
POWERPC_DEF("POWER7_v2.0", CPU_POWERPC_POWER7_v20, POWER7),
|
9298 |
POWERPC_DEF("POWER7_v2.1", CPU_POWERPC_POWER7_v21, POWER7),
|
9299 |
POWERPC_DEF("POWER7_v2.3", CPU_POWERPC_POWER7_v23, POWER7),
|
9300 |
/* PowerPC 970 */
|
9301 |
POWERPC_DEF("970", CPU_POWERPC_970, 970), |
9302 |
/* PowerPC 970FX (G5) */
|
9303 |
POWERPC_DEF("970fx", CPU_POWERPC_970FX, 970FX), |
9304 |
/* PowerPC 970FX v1.0 (G5) */
|
9305 |
POWERPC_DEF("970fx_v1.0", CPU_POWERPC_970FX_v10, 970FX), |
9306 |
/* PowerPC 970FX v2.0 (G5) */
|
9307 |
POWERPC_DEF("970fx_v2.0", CPU_POWERPC_970FX_v20, 970FX), |
9308 |
/* PowerPC 970FX v2.1 (G5) */
|
9309 |
POWERPC_DEF("970fx_v2.1", CPU_POWERPC_970FX_v21, 970FX), |
9310 |
/* PowerPC 970FX v3.0 (G5) */
|
9311 |
POWERPC_DEF("970fx_v3.0", CPU_POWERPC_970FX_v30, 970FX), |
9312 |
/* PowerPC 970FX v3.1 (G5) */
|
9313 |
POWERPC_DEF("970fx_v3.1", CPU_POWERPC_970FX_v31, 970FX), |
9314 |
/* PowerPC 970GX (G5) */
|
9315 |
POWERPC_DEF("970gx", CPU_POWERPC_970GX, 970GX), |
9316 |
/* PowerPC 970MP */
|
9317 |
POWERPC_DEF("970mp", CPU_POWERPC_970MP, 970MP), |
9318 |
/* PowerPC 970MP v1.0 */
|
9319 |
POWERPC_DEF("970mp_v1.0", CPU_POWERPC_970MP_v10, 970MP), |
9320 |
/* PowerPC 970MP v1.1 */
|
9321 |
POWERPC_DEF("970mp_v1.1", CPU_POWERPC_970MP_v11, 970MP), |
9322 |
#if defined (TODO)
|
9323 |
/* PowerPC Cell */
|
9324 |
POWERPC_DEF("Cell", CPU_POWERPC_CELL, 970), |
9325 |
#endif
|
9326 |
#if defined (TODO)
|
9327 |
/* PowerPC Cell v1.0 */
|
9328 |
POWERPC_DEF("Cell_v1.0", CPU_POWERPC_CELL_v10, 970), |
9329 |
#endif
|
9330 |
#if defined (TODO)
|
9331 |
/* PowerPC Cell v2.0 */
|
9332 |
POWERPC_DEF("Cell_v2.0", CPU_POWERPC_CELL_v20, 970), |
9333 |
#endif
|
9334 |
#if defined (TODO)
|
9335 |
/* PowerPC Cell v3.0 */
|
9336 |
POWERPC_DEF("Cell_v3.0", CPU_POWERPC_CELL_v30, 970), |
9337 |
#endif
|
9338 |
#if defined (TODO)
|
9339 |
/* PowerPC Cell v3.1 */
|
9340 |
POWERPC_DEF("Cell_v3.1", CPU_POWERPC_CELL_v31, 970), |
9341 |
#endif
|
9342 |
#if defined (TODO)
|
9343 |
/* PowerPC Cell v3.2 */
|
9344 |
POWERPC_DEF("Cell_v3.2", CPU_POWERPC_CELL_v32, 970), |
9345 |
#endif
|
9346 |
#if defined (TODO)
|
9347 |
/* RS64 (Apache/A35) */
|
9348 |
/* This one seems to support the whole POWER2 instruction set
|
9349 |
* and the PowerPC 64 one.
|
9350 |
*/
|
9351 |
/* What about A10 & A30 ? */
|
9352 |
POWERPC_DEF("RS64", CPU_POWERPC_RS64, RS64),
|
9353 |
POWERPC_DEF("Apache", CPU_POWERPC_RS64, RS64),
|
9354 |
POWERPC_DEF("A35", CPU_POWERPC_RS64, RS64),
|
9355 |
#endif
|
9356 |
#if defined (TODO)
|
9357 |
/* RS64-II (NorthStar/A50) */
|
9358 |
POWERPC_DEF("RS64-II", CPU_POWERPC_RS64II, RS64),
|
9359 |
POWERPC_DEF("NorthStar", CPU_POWERPC_RS64II, RS64),
|
9360 |
POWERPC_DEF("A50", CPU_POWERPC_RS64II, RS64),
|
9361 |
#endif
|
9362 |
#if defined (TODO)
|
9363 |
/* RS64-III (Pulsar) */
|
9364 |
POWERPC_DEF("RS64-III", CPU_POWERPC_RS64III, RS64),
|
9365 |
POWERPC_DEF("Pulsar", CPU_POWERPC_RS64III, RS64),
|
9366 |
#endif
|
9367 |
#if defined (TODO)
|
9368 |
/* RS64-IV (IceStar/IStar/SStar) */
|
9369 |
POWERPC_DEF("RS64-IV", CPU_POWERPC_RS64IV, RS64),
|
9370 |
POWERPC_DEF("IceStar", CPU_POWERPC_RS64IV, RS64),
|
9371 |
POWERPC_DEF("IStar", CPU_POWERPC_RS64IV, RS64),
|
9372 |
POWERPC_DEF("SStar", CPU_POWERPC_RS64IV, RS64),
|
9373 |
#endif
|
9374 |
#endif /* defined (TARGET_PPC64) */ |
9375 |
/* POWER */
|
9376 |
#if defined (TODO)
|
9377 |
/* Original POWER */
|
9378 |
POWERPC_DEF("POWER", CPU_POWERPC_POWER, POWER),
|
9379 |
POWERPC_DEF("RIOS", CPU_POWERPC_POWER, POWER),
|
9380 |
POWERPC_DEF("RSC", CPU_POWERPC_POWER, POWER),
|
9381 |
POWERPC_DEF("RSC3308", CPU_POWERPC_POWER, POWER),
|
9382 |
POWERPC_DEF("RSC4608", CPU_POWERPC_POWER, POWER),
|
9383 |
#endif
|
9384 |
#if defined (TODO)
|
9385 |
/* POWER2 */
|
9386 |
POWERPC_DEF("POWER2", CPU_POWERPC_POWER2, POWER),
|
9387 |
POWERPC_DEF("RSC2", CPU_POWERPC_POWER2, POWER),
|
9388 |
POWERPC_DEF("P2SC", CPU_POWERPC_POWER2, POWER),
|
9389 |
#endif
|
9390 |
/* PA semi cores */
|
9391 |
#if defined (TODO)
|
9392 |
/* PA PA6T */
|
9393 |
POWERPC_DEF("PA6T", CPU_POWERPC_PA6T, PA6T),
|
9394 |
#endif
|
9395 |
/* Generic PowerPCs */
|
9396 |
#if defined (TARGET_PPC64)
|
9397 |
POWERPC_DEF("ppc64", CPU_POWERPC_PPC64, PPC64),
|
9398 |
#endif
|
9399 |
POWERPC_DEF("ppc32", CPU_POWERPC_PPC32, PPC32),
|
9400 |
POWERPC_DEF("ppc", CPU_POWERPC_DEFAULT, DEFAULT),
|
9401 |
/* Fallback */
|
9402 |
POWERPC_DEF("default", CPU_POWERPC_DEFAULT, DEFAULT),
|
9403 |
}; |
9404 |
|
9405 |
/*****************************************************************************/
|
9406 |
/* Generic CPU instantiation routine */
|
9407 |
static void init_ppc_proc (CPUPPCState *env, const ppc_def_t *def) |
9408 |
{ |
9409 |
#if !defined(CONFIG_USER_ONLY)
|
9410 |
int i;
|
9411 |
|
9412 |
env->irq_inputs = NULL;
|
9413 |
/* Set all exception vectors to an invalid address */
|
9414 |
for (i = 0; i < POWERPC_EXCP_NB; i++) |
9415 |
env->excp_vectors[i] = (target_ulong)(-1ULL);
|
9416 |
env->hreset_excp_prefix = 0x00000000;
|
9417 |
env->ivor_mask = 0x00000000;
|
9418 |
env->ivpr_mask = 0x00000000;
|
9419 |
/* Default MMU definitions */
|
9420 |
env->nb_BATs = 0;
|
9421 |
env->nb_tlb = 0;
|
9422 |
env->nb_ways = 0;
|
9423 |
env->tlb_type = TLB_NONE; |
9424 |
#endif
|
9425 |
/* Register SPR common to all PowerPC implementations */
|
9426 |
gen_spr_generic(env); |
9427 |
spr_register(env, SPR_PVR, "PVR",
|
9428 |
/* Linux permits userspace to read PVR */
|
9429 |
#if defined(CONFIG_LINUX_USER)
|
9430 |
&spr_read_generic, |
9431 |
#else
|
9432 |
SPR_NOACCESS, |
9433 |
#endif
|
9434 |
SPR_NOACCESS, |
9435 |
&spr_read_generic, SPR_NOACCESS, |
9436 |
def->pvr); |
9437 |
/* Register SVR if it's defined to anything else than POWERPC_SVR_NONE */
|
9438 |
if (def->svr != POWERPC_SVR_NONE) {
|
9439 |
if (def->svr & POWERPC_SVR_E500) {
|
9440 |
spr_register(env, SPR_E500_SVR, "SVR",
|
9441 |
SPR_NOACCESS, SPR_NOACCESS, |
9442 |
&spr_read_generic, SPR_NOACCESS, |
9443 |
def->svr & ~POWERPC_SVR_E500); |
9444 |
} else {
|
9445 |
spr_register(env, SPR_SVR, "SVR",
|
9446 |
SPR_NOACCESS, SPR_NOACCESS, |
9447 |
&spr_read_generic, SPR_NOACCESS, |
9448 |
def->svr); |
9449 |
} |
9450 |
} |
9451 |
/* PowerPC implementation specific initialisations (SPRs, timers, ...) */
|
9452 |
(*def->init_proc)(env); |
9453 |
#if !defined(CONFIG_USER_ONLY)
|
9454 |
env->excp_prefix = env->hreset_excp_prefix; |
9455 |
#endif
|
9456 |
/* MSR bits & flags consistency checks */
|
9457 |
if (env->msr_mask & (1 << 25)) { |
9458 |
switch (env->flags & (POWERPC_FLAG_SPE | POWERPC_FLAG_VRE)) {
|
9459 |
case POWERPC_FLAG_SPE:
|
9460 |
case POWERPC_FLAG_VRE:
|
9461 |
break;
|
9462 |
default:
|
9463 |
fprintf(stderr, "PowerPC MSR definition inconsistency\n"
|
9464 |
"Should define POWERPC_FLAG_SPE or POWERPC_FLAG_VRE\n");
|
9465 |
exit(1);
|
9466 |
} |
9467 |
} else if (env->flags & (POWERPC_FLAG_SPE | POWERPC_FLAG_VRE)) { |
9468 |
fprintf(stderr, "PowerPC MSR definition inconsistency\n"
|
9469 |
"Should not define POWERPC_FLAG_SPE nor POWERPC_FLAG_VRE\n");
|
9470 |
exit(1);
|
9471 |
} |
9472 |
if (env->msr_mask & (1 << 17)) { |
9473 |
switch (env->flags & (POWERPC_FLAG_TGPR | POWERPC_FLAG_CE)) {
|
9474 |
case POWERPC_FLAG_TGPR:
|
9475 |
case POWERPC_FLAG_CE:
|
9476 |
break;
|
9477 |
default:
|
9478 |
fprintf(stderr, "PowerPC MSR definition inconsistency\n"
|
9479 |
"Should define POWERPC_FLAG_TGPR or POWERPC_FLAG_CE\n");
|
9480 |
exit(1);
|
9481 |
} |
9482 |
} else if (env->flags & (POWERPC_FLAG_TGPR | POWERPC_FLAG_CE)) { |
9483 |
fprintf(stderr, "PowerPC MSR definition inconsistency\n"
|
9484 |
"Should not define POWERPC_FLAG_TGPR nor POWERPC_FLAG_CE\n");
|
9485 |
exit(1);
|
9486 |
} |
9487 |
if (env->msr_mask & (1 << 10)) { |
9488 |
switch (env->flags & (POWERPC_FLAG_SE | POWERPC_FLAG_DWE |
|
9489 |
POWERPC_FLAG_UBLE)) { |
9490 |
case POWERPC_FLAG_SE:
|
9491 |
case POWERPC_FLAG_DWE:
|
9492 |
case POWERPC_FLAG_UBLE:
|
9493 |
break;
|
9494 |
default:
|
9495 |
fprintf(stderr, "PowerPC MSR definition inconsistency\n"
|
9496 |
"Should define POWERPC_FLAG_SE or POWERPC_FLAG_DWE or "
|
9497 |
"POWERPC_FLAG_UBLE\n");
|
9498 |
exit(1);
|
9499 |
} |
9500 |
} else if (env->flags & (POWERPC_FLAG_SE | POWERPC_FLAG_DWE | |
9501 |
POWERPC_FLAG_UBLE)) { |
9502 |
fprintf(stderr, "PowerPC MSR definition inconsistency\n"
|
9503 |
"Should not define POWERPC_FLAG_SE nor POWERPC_FLAG_DWE nor "
|
9504 |
"POWERPC_FLAG_UBLE\n");
|
9505 |
exit(1);
|
9506 |
} |
9507 |
if (env->msr_mask & (1 << 9)) { |
9508 |
switch (env->flags & (POWERPC_FLAG_BE | POWERPC_FLAG_DE)) {
|
9509 |
case POWERPC_FLAG_BE:
|
9510 |
case POWERPC_FLAG_DE:
|
9511 |
break;
|
9512 |
default:
|
9513 |
fprintf(stderr, "PowerPC MSR definition inconsistency\n"
|
9514 |
"Should define POWERPC_FLAG_BE or POWERPC_FLAG_DE\n");
|
9515 |
exit(1);
|
9516 |
} |
9517 |
} else if (env->flags & (POWERPC_FLAG_BE | POWERPC_FLAG_DE)) { |
9518 |
fprintf(stderr, "PowerPC MSR definition inconsistency\n"
|
9519 |
"Should not define POWERPC_FLAG_BE nor POWERPC_FLAG_DE\n");
|
9520 |
exit(1);
|
9521 |
} |
9522 |
if (env->msr_mask & (1 << 2)) { |
9523 |
switch (env->flags & (POWERPC_FLAG_PX | POWERPC_FLAG_PMM)) {
|
9524 |
case POWERPC_FLAG_PX:
|
9525 |
case POWERPC_FLAG_PMM:
|
9526 |
break;
|
9527 |
default:
|
9528 |
fprintf(stderr, "PowerPC MSR definition inconsistency\n"
|
9529 |
"Should define POWERPC_FLAG_PX or POWERPC_FLAG_PMM\n");
|
9530 |
exit(1);
|
9531 |
} |
9532 |
} else if (env->flags & (POWERPC_FLAG_PX | POWERPC_FLAG_PMM)) { |
9533 |
fprintf(stderr, "PowerPC MSR definition inconsistency\n"
|
9534 |
"Should not define POWERPC_FLAG_PX nor POWERPC_FLAG_PMM\n");
|
9535 |
exit(1);
|
9536 |
} |
9537 |
if ((env->flags & (POWERPC_FLAG_RTC_CLK | POWERPC_FLAG_BUS_CLK)) == 0) { |
9538 |
fprintf(stderr, "PowerPC flags inconsistency\n"
|
9539 |
"Should define the time-base and decrementer clock source\n");
|
9540 |
exit(1);
|
9541 |
} |
9542 |
/* Allocate TLBs buffer when needed */
|
9543 |
#if !defined(CONFIG_USER_ONLY)
|
9544 |
if (env->nb_tlb != 0) { |
9545 |
int nb_tlb = env->nb_tlb;
|
9546 |
if (env->id_tlbs != 0) |
9547 |
nb_tlb *= 2;
|
9548 |
switch (env->tlb_type) {
|
9549 |
case TLB_6XX:
|
9550 |
env->tlb.tlb6 = g_malloc0(nb_tlb * sizeof(ppc6xx_tlb_t));
|
9551 |
break;
|
9552 |
case TLB_EMB:
|
9553 |
env->tlb.tlbe = g_malloc0(nb_tlb * sizeof(ppcemb_tlb_t));
|
9554 |
break;
|
9555 |
case TLB_MAS:
|
9556 |
env->tlb.tlbm = g_malloc0(nb_tlb * sizeof(ppcmas_tlb_t));
|
9557 |
break;
|
9558 |
} |
9559 |
/* Pre-compute some useful values */
|
9560 |
env->tlb_per_way = env->nb_tlb / env->nb_ways; |
9561 |
} |
9562 |
if (env->irq_inputs == NULL) { |
9563 |
fprintf(stderr, "WARNING: no internal IRQ controller registered.\n"
|
9564 |
" Attempt QEMU to crash very soon !\n");
|
9565 |
} |
9566 |
#endif
|
9567 |
if (env->check_pow == NULL) { |
9568 |
fprintf(stderr, "WARNING: no power management check handler "
|
9569 |
"registered.\n"
|
9570 |
" Attempt QEMU to crash very soon !\n");
|
9571 |
} |
9572 |
} |
9573 |
|
9574 |
#if defined(PPC_DUMP_CPU)
|
9575 |
static void dump_ppc_sprs (CPUPPCState *env) |
9576 |
{ |
9577 |
ppc_spr_t *spr; |
9578 |
#if !defined(CONFIG_USER_ONLY)
|
9579 |
uint32_t sr, sw; |
9580 |
#endif
|
9581 |
uint32_t ur, uw; |
9582 |
int i, j, n;
|
9583 |
|
9584 |
printf("Special purpose registers:\n");
|
9585 |
for (i = 0; i < 32; i++) { |
9586 |
for (j = 0; j < 32; j++) { |
9587 |
n = (i << 5) | j;
|
9588 |
spr = &env->spr_cb[n]; |
9589 |
uw = spr->uea_write != NULL && spr->uea_write != SPR_NOACCESS;
|
9590 |
ur = spr->uea_read != NULL && spr->uea_read != SPR_NOACCESS;
|
9591 |
#if !defined(CONFIG_USER_ONLY)
|
9592 |
sw = spr->oea_write != NULL && spr->oea_write != SPR_NOACCESS;
|
9593 |
sr = spr->oea_read != NULL && spr->oea_read != SPR_NOACCESS;
|
9594 |
if (sw || sr || uw || ur) {
|
9595 |
printf("SPR: %4d (%03x) %-8s s%c%c u%c%c\n",
|
9596 |
(i << 5) | j, (i << 5) | j, spr->name, |
9597 |
sw ? 'w' : '-', sr ? 'r' : '-', |
9598 |
uw ? 'w' : '-', ur ? 'r' : '-'); |
9599 |
} |
9600 |
#else
|
9601 |
if (uw || ur) {
|
9602 |
printf("SPR: %4d (%03x) %-8s u%c%c\n",
|
9603 |
(i << 5) | j, (i << 5) | j, spr->name, |
9604 |
uw ? 'w' : '-', ur ? 'r' : '-'); |
9605 |
} |
9606 |
#endif
|
9607 |
} |
9608 |
} |
9609 |
fflush(stdout); |
9610 |
fflush(stderr); |
9611 |
} |
9612 |
#endif
|
9613 |
|
9614 |
/*****************************************************************************/
|
9615 |
#include <stdlib.h> |
9616 |
#include <string.h> |
9617 |
|
9618 |
/* Opcode types */
|
9619 |
enum {
|
9620 |
PPC_DIRECT = 0, /* Opcode routine */ |
9621 |
PPC_INDIRECT = 1, /* Indirect opcode table */ |
9622 |
}; |
9623 |
|
9624 |
static inline int is_indirect_opcode (void *handler) |
9625 |
{ |
9626 |
return ((uintptr_t)handler & 0x03) == PPC_INDIRECT; |
9627 |
} |
9628 |
|
9629 |
static inline opc_handler_t **ind_table(void *handler) |
9630 |
{ |
9631 |
return (opc_handler_t **)((uintptr_t)handler & ~3); |
9632 |
} |
9633 |
|
9634 |
/* Instruction table creation */
|
9635 |
/* Opcodes tables creation */
|
9636 |
static void fill_new_table (opc_handler_t **table, int len) |
9637 |
{ |
9638 |
int i;
|
9639 |
|
9640 |
for (i = 0; i < len; i++) |
9641 |
table[i] = &invalid_handler; |
9642 |
} |
9643 |
|
9644 |
static int create_new_table (opc_handler_t **table, unsigned char idx) |
9645 |
{ |
9646 |
opc_handler_t **tmp; |
9647 |
|
9648 |
tmp = malloc(0x20 * sizeof(opc_handler_t)); |
9649 |
fill_new_table(tmp, 0x20);
|
9650 |
table[idx] = (opc_handler_t *)((uintptr_t)tmp | PPC_INDIRECT); |
9651 |
|
9652 |
return 0; |
9653 |
} |
9654 |
|
9655 |
static int insert_in_table (opc_handler_t **table, unsigned char idx, |
9656 |
opc_handler_t *handler) |
9657 |
{ |
9658 |
if (table[idx] != &invalid_handler)
|
9659 |
return -1; |
9660 |
table[idx] = handler; |
9661 |
|
9662 |
return 0; |
9663 |
} |
9664 |
|
9665 |
static int register_direct_insn (opc_handler_t **ppc_opcodes, |
9666 |
unsigned char idx, opc_handler_t *handler) |
9667 |
{ |
9668 |
if (insert_in_table(ppc_opcodes, idx, handler) < 0) { |
9669 |
printf("*** ERROR: opcode %02x already assigned in main "
|
9670 |
"opcode table\n", idx);
|
9671 |
#if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
|
9672 |
printf(" Registered handler '%s' - new handler '%s'\n",
|
9673 |
ppc_opcodes[idx]->oname, handler->oname); |
9674 |
#endif
|
9675 |
return -1; |
9676 |
} |
9677 |
|
9678 |
return 0; |
9679 |
} |
9680 |
|
9681 |
static int register_ind_in_table (opc_handler_t **table, |
9682 |
unsigned char idx1, unsigned char idx2, |
9683 |
opc_handler_t *handler) |
9684 |
{ |
9685 |
if (table[idx1] == &invalid_handler) {
|
9686 |
if (create_new_table(table, idx1) < 0) { |
9687 |
printf("*** ERROR: unable to create indirect table "
|
9688 |
"idx=%02x\n", idx1);
|
9689 |
return -1; |
9690 |
} |
9691 |
} else {
|
9692 |
if (!is_indirect_opcode(table[idx1])) {
|
9693 |
printf("*** ERROR: idx %02x already assigned to a direct "
|
9694 |
"opcode\n", idx1);
|
9695 |
#if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
|
9696 |
printf(" Registered handler '%s' - new handler '%s'\n",
|
9697 |
ind_table(table[idx1])[idx2]->oname, handler->oname); |
9698 |
#endif
|
9699 |
return -1; |
9700 |
} |
9701 |
} |
9702 |
if (handler != NULL && |
9703 |
insert_in_table(ind_table(table[idx1]), idx2, handler) < 0) {
|
9704 |
printf("*** ERROR: opcode %02x already assigned in "
|
9705 |
"opcode table %02x\n", idx2, idx1);
|
9706 |
#if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
|
9707 |
printf(" Registered handler '%s' - new handler '%s'\n",
|
9708 |
ind_table(table[idx1])[idx2]->oname, handler->oname); |
9709 |
#endif
|
9710 |
return -1; |
9711 |
} |
9712 |
|
9713 |
return 0; |
9714 |
} |
9715 |
|
9716 |
static int register_ind_insn (opc_handler_t **ppc_opcodes, |
9717 |
unsigned char idx1, unsigned char idx2, |
9718 |
opc_handler_t *handler) |
9719 |
{ |
9720 |
int ret;
|
9721 |
|
9722 |
ret = register_ind_in_table(ppc_opcodes, idx1, idx2, handler); |
9723 |
|
9724 |
return ret;
|
9725 |
} |
9726 |
|
9727 |
static int register_dblind_insn (opc_handler_t **ppc_opcodes, |
9728 |
unsigned char idx1, unsigned char idx2, |
9729 |
unsigned char idx3, opc_handler_t *handler) |
9730 |
{ |
9731 |
if (register_ind_in_table(ppc_opcodes, idx1, idx2, NULL) < 0) { |
9732 |
printf("*** ERROR: unable to join indirect table idx "
|
9733 |
"[%02x-%02x]\n", idx1, idx2);
|
9734 |
return -1; |
9735 |
} |
9736 |
if (register_ind_in_table(ind_table(ppc_opcodes[idx1]), idx2, idx3,
|
9737 |
handler) < 0) {
|
9738 |
printf("*** ERROR: unable to insert opcode "
|
9739 |
"[%02x-%02x-%02x]\n", idx1, idx2, idx3);
|
9740 |
return -1; |
9741 |
} |
9742 |
|
9743 |
return 0; |
9744 |
} |
9745 |
|
9746 |
static int register_insn (opc_handler_t **ppc_opcodes, opcode_t *insn) |
9747 |
{ |
9748 |
if (insn->opc2 != 0xFF) { |
9749 |
if (insn->opc3 != 0xFF) { |
9750 |
if (register_dblind_insn(ppc_opcodes, insn->opc1, insn->opc2,
|
9751 |
insn->opc3, &insn->handler) < 0)
|
9752 |
return -1; |
9753 |
} else {
|
9754 |
if (register_ind_insn(ppc_opcodes, insn->opc1,
|
9755 |
insn->opc2, &insn->handler) < 0)
|
9756 |
return -1; |
9757 |
} |
9758 |
} else {
|
9759 |
if (register_direct_insn(ppc_opcodes, insn->opc1, &insn->handler) < 0) |
9760 |
return -1; |
9761 |
} |
9762 |
|
9763 |
return 0; |
9764 |
} |
9765 |
|
9766 |
static int test_opcode_table (opc_handler_t **table, int len) |
9767 |
{ |
9768 |
int i, count, tmp;
|
9769 |
|
9770 |
for (i = 0, count = 0; i < len; i++) { |
9771 |
/* Consistency fixup */
|
9772 |
if (table[i] == NULL) |
9773 |
table[i] = &invalid_handler; |
9774 |
if (table[i] != &invalid_handler) {
|
9775 |
if (is_indirect_opcode(table[i])) {
|
9776 |
tmp = test_opcode_table(ind_table(table[i]), 0x20);
|
9777 |
if (tmp == 0) { |
9778 |
free(table[i]); |
9779 |
table[i] = &invalid_handler; |
9780 |
} else {
|
9781 |
count++; |
9782 |
} |
9783 |
} else {
|
9784 |
count++; |
9785 |
} |
9786 |
} |
9787 |
} |
9788 |
|
9789 |
return count;
|
9790 |
} |
9791 |
|
9792 |
static void fix_opcode_tables (opc_handler_t **ppc_opcodes) |
9793 |
{ |
9794 |
if (test_opcode_table(ppc_opcodes, 0x40) == 0) |
9795 |
printf("*** WARNING: no opcode defined !\n");
|
9796 |
} |
9797 |
|
9798 |
/*****************************************************************************/
|
9799 |
static int create_ppc_opcodes (CPUPPCState *env, const ppc_def_t *def) |
9800 |
{ |
9801 |
opcode_t *opc; |
9802 |
|
9803 |
fill_new_table(env->opcodes, 0x40);
|
9804 |
for (opc = opcodes; opc < &opcodes[ARRAY_SIZE(opcodes)]; opc++) {
|
9805 |
if (((opc->handler.type & def->insns_flags) != 0) || |
9806 |
((opc->handler.type2 & def->insns_flags2) != 0)) {
|
9807 |
if (register_insn(env->opcodes, opc) < 0) { |
9808 |
printf("*** ERROR initializing PowerPC instruction "
|
9809 |
"0x%02x 0x%02x 0x%02x\n", opc->opc1, opc->opc2,
|
9810 |
opc->opc3); |
9811 |
return -1; |
9812 |
} |
9813 |
} |
9814 |
} |
9815 |
fix_opcode_tables(env->opcodes); |
9816 |
fflush(stdout); |
9817 |
fflush(stderr); |
9818 |
|
9819 |
return 0; |
9820 |
} |
9821 |
|
9822 |
#if defined(PPC_DUMP_CPU)
|
9823 |
static void dump_ppc_insns (CPUPPCState *env) |
9824 |
{ |
9825 |
opc_handler_t **table, *handler; |
9826 |
const char *p, *q; |
9827 |
uint8_t opc1, opc2, opc3; |
9828 |
|
9829 |
printf("Instructions set:\n");
|
9830 |
/* opc1 is 6 bits long */
|
9831 |
for (opc1 = 0x00; opc1 < 0x40; opc1++) { |
9832 |
table = env->opcodes; |
9833 |
handler = table[opc1]; |
9834 |
if (is_indirect_opcode(handler)) {
|
9835 |
/* opc2 is 5 bits long */
|
9836 |
for (opc2 = 0; opc2 < 0x20; opc2++) { |
9837 |
table = env->opcodes; |
9838 |
handler = env->opcodes[opc1]; |
9839 |
table = ind_table(handler); |
9840 |
handler = table[opc2]; |
9841 |
if (is_indirect_opcode(handler)) {
|
9842 |
table = ind_table(handler); |
9843 |
/* opc3 is 5 bits long */
|
9844 |
for (opc3 = 0; opc3 < 0x20; opc3++) { |
9845 |
handler = table[opc3]; |
9846 |
if (handler->handler != &gen_invalid) {
|
9847 |
/* Special hack to properly dump SPE insns */
|
9848 |
p = strchr(handler->oname, '_');
|
9849 |
if (p == NULL) { |
9850 |
printf("INSN: %02x %02x %02x (%02d %04d) : "
|
9851 |
"%s\n",
|
9852 |
opc1, opc2, opc3, opc1, |
9853 |
(opc3 << 5) | opc2,
|
9854 |
handler->oname); |
9855 |
} else {
|
9856 |
q = "speundef";
|
9857 |
if ((p - handler->oname) != strlen(q) ||
|
9858 |
memcmp(handler->oname, q, strlen(q)) != 0) {
|
9859 |
/* First instruction */
|
9860 |
printf("INSN: %02x %02x %02x (%02d %04d) : "
|
9861 |
"%.*s\n",
|
9862 |
opc1, opc2 << 1, opc3, opc1,
|
9863 |
(opc3 << 6) | (opc2 << 1), |
9864 |
(int)(p - handler->oname),
|
9865 |
handler->oname); |
9866 |
} |
9867 |
if (strcmp(p + 1, q) != 0) { |
9868 |
/* Second instruction */
|
9869 |
printf("INSN: %02x %02x %02x (%02d %04d) : "
|
9870 |
"%s\n",
|
9871 |
opc1, (opc2 << 1) | 1, opc3, opc1, |
9872 |
(opc3 << 6) | (opc2 << 1) | 1, |
9873 |
p + 1);
|
9874 |
} |
9875 |
} |
9876 |
} |
9877 |
} |
9878 |
} else {
|
9879 |
if (handler->handler != &gen_invalid) {
|
9880 |
printf("INSN: %02x %02x -- (%02d %04d) : %s\n",
|
9881 |
opc1, opc2, opc1, opc2, handler->oname); |
9882 |
} |
9883 |
} |
9884 |
} |
9885 |
} else {
|
9886 |
if (handler->handler != &gen_invalid) {
|
9887 |
printf("INSN: %02x -- -- (%02d ----) : %s\n",
|
9888 |
opc1, opc1, handler->oname); |
9889 |
} |
9890 |
} |
9891 |
} |
9892 |
} |
9893 |
#endif
|
9894 |
|
9895 |
static int gdb_get_float_reg(CPUPPCState *env, uint8_t *mem_buf, int n) |
9896 |
{ |
9897 |
if (n < 32) { |
9898 |
stfq_p(mem_buf, env->fpr[n]); |
9899 |
return 8; |
9900 |
} |
9901 |
if (n == 32) { |
9902 |
stl_p(mem_buf, env->fpscr); |
9903 |
return 4; |
9904 |
} |
9905 |
return 0; |
9906 |
} |
9907 |
|
9908 |
static int gdb_set_float_reg(CPUPPCState *env, uint8_t *mem_buf, int n) |
9909 |
{ |
9910 |
if (n < 32) { |
9911 |
env->fpr[n] = ldfq_p(mem_buf); |
9912 |
return 8; |
9913 |
} |
9914 |
if (n == 32) { |
9915 |
/* FPSCR not implemented */
|
9916 |
return 4; |
9917 |
} |
9918 |
return 0; |
9919 |
} |
9920 |
|
9921 |
static int gdb_get_avr_reg(CPUPPCState *env, uint8_t *mem_buf, int n) |
9922 |
{ |
9923 |
if (n < 32) { |
9924 |
#ifdef HOST_WORDS_BIGENDIAN
|
9925 |
stq_p(mem_buf, env->avr[n].u64[0]);
|
9926 |
stq_p(mem_buf+8, env->avr[n].u64[1]); |
9927 |
#else
|
9928 |
stq_p(mem_buf, env->avr[n].u64[1]);
|
9929 |
stq_p(mem_buf+8, env->avr[n].u64[0]); |
9930 |
#endif
|
9931 |
return 16; |
9932 |
} |
9933 |
if (n == 32) { |
9934 |
stl_p(mem_buf, env->vscr); |
9935 |
return 4; |
9936 |
} |
9937 |
if (n == 33) { |
9938 |
stl_p(mem_buf, (uint32_t)env->spr[SPR_VRSAVE]); |
9939 |
return 4; |
9940 |
} |
9941 |
return 0; |
9942 |
} |
9943 |
|
9944 |
static int gdb_set_avr_reg(CPUPPCState *env, uint8_t *mem_buf, int n) |
9945 |
{ |
9946 |
if (n < 32) { |
9947 |
#ifdef HOST_WORDS_BIGENDIAN
|
9948 |
env->avr[n].u64[0] = ldq_p(mem_buf);
|
9949 |
env->avr[n].u64[1] = ldq_p(mem_buf+8); |
9950 |
#else
|
9951 |
env->avr[n].u64[1] = ldq_p(mem_buf);
|
9952 |
env->avr[n].u64[0] = ldq_p(mem_buf+8); |
9953 |
#endif
|
9954 |
return 16; |
9955 |
} |
9956 |
if (n == 32) { |
9957 |
env->vscr = ldl_p(mem_buf); |
9958 |
return 4; |
9959 |
} |
9960 |
if (n == 33) { |
9961 |
env->spr[SPR_VRSAVE] = (target_ulong)ldl_p(mem_buf); |
9962 |
return 4; |
9963 |
} |
9964 |
return 0; |
9965 |
} |
9966 |
|
9967 |
static int gdb_get_spe_reg(CPUPPCState *env, uint8_t *mem_buf, int n) |
9968 |
{ |
9969 |
if (n < 32) { |
9970 |
#if defined(TARGET_PPC64)
|
9971 |
stl_p(mem_buf, env->gpr[n] >> 32);
|
9972 |
#else
|
9973 |
stl_p(mem_buf, env->gprh[n]); |
9974 |
#endif
|
9975 |
return 4; |
9976 |
} |
9977 |
if (n == 32) { |
9978 |
stq_p(mem_buf, env->spe_acc); |
9979 |
return 8; |
9980 |
} |
9981 |
if (n == 33) { |
9982 |
stl_p(mem_buf, env->spe_fscr); |
9983 |
return 4; |
9984 |
} |
9985 |
return 0; |
9986 |
} |
9987 |
|
9988 |
static int gdb_set_spe_reg(CPUPPCState *env, uint8_t *mem_buf, int n) |
9989 |
{ |
9990 |
if (n < 32) { |
9991 |
#if defined(TARGET_PPC64)
|
9992 |
target_ulong lo = (uint32_t)env->gpr[n]; |
9993 |
target_ulong hi = (target_ulong)ldl_p(mem_buf) << 32;
|
9994 |
env->gpr[n] = lo | hi; |
9995 |
#else
|
9996 |
env->gprh[n] = ldl_p(mem_buf); |
9997 |
#endif
|
9998 |
return 4; |
9999 |
} |
10000 |
if (n == 32) { |
10001 |
env->spe_acc = ldq_p(mem_buf); |
10002 |
return 8; |
10003 |
} |
10004 |
if (n == 33) { |
10005 |
env->spe_fscr = ldl_p(mem_buf); |
10006 |
return 4; |
10007 |
} |
10008 |
return 0; |
10009 |
} |
10010 |
|
10011 |
static int ppc_fixup_cpu(CPUPPCState *env) |
10012 |
{ |
10013 |
/* TCG doesn't (yet) emulate some groups of instructions that
|
10014 |
* are implemented on some otherwise supported CPUs (e.g. VSX
|
10015 |
* and decimal floating point instructions on POWER7). We
|
10016 |
* remove unsupported instruction groups from the cpu state's
|
10017 |
* instruction masks and hope the guest can cope. For at
|
10018 |
* least the pseries machine, the unavailability of these
|
10019 |
* instructions can be advertised to the guest via the device
|
10020 |
* tree. */
|
10021 |
if ((env->insns_flags & ~PPC_TCG_INSNS)
|
10022 |
|| (env->insns_flags2 & ~PPC_TCG_INSNS2)) { |
10023 |
fprintf(stderr, "Warning: Disabling some instructions which are not "
|
10024 |
"emulated by TCG (0x%" PRIx64 ", 0x%" PRIx64 ")\n", |
10025 |
env->insns_flags & ~PPC_TCG_INSNS, |
10026 |
env->insns_flags2 & ~PPC_TCG_INSNS2); |
10027 |
} |
10028 |
env->insns_flags &= PPC_TCG_INSNS; |
10029 |
env->insns_flags2 &= PPC_TCG_INSNS2; |
10030 |
return 0; |
10031 |
} |
10032 |
|
10033 |
int cpu_ppc_register_internal (CPUPPCState *env, const ppc_def_t *def) |
10034 |
{ |
10035 |
env->msr_mask = def->msr_mask; |
10036 |
env->mmu_model = def->mmu_model; |
10037 |
env->excp_model = def->excp_model; |
10038 |
env->bus_model = def->bus_model; |
10039 |
env->insns_flags = def->insns_flags; |
10040 |
env->insns_flags2 = def->insns_flags2; |
10041 |
env->flags = def->flags; |
10042 |
env->bfd_mach = def->bfd_mach; |
10043 |
env->check_pow = def->check_pow; |
10044 |
|
10045 |
#if defined(TARGET_PPC64)
|
10046 |
if (def->sps)
|
10047 |
env->sps = *def->sps; |
10048 |
else if (env->mmu_model & POWERPC_MMU_64) { |
10049 |
/* Use default sets of page sizes */
|
10050 |
static const struct ppc_segment_page_sizes defsps = { |
10051 |
.sps = { |
10052 |
{ .page_shift = 12, /* 4K */ |
10053 |
.slb_enc = 0,
|
10054 |
.enc = { { .page_shift = 12, .pte_enc = 0 } } |
10055 |
}, |
10056 |
{ .page_shift = 24, /* 16M */ |
10057 |
.slb_enc = 0x100,
|
10058 |
.enc = { { .page_shift = 24, .pte_enc = 0 } } |
10059 |
}, |
10060 |
}, |
10061 |
}; |
10062 |
env->sps = defsps; |
10063 |
} |
10064 |
#endif /* defined(TARGET_PPC64) */ |
10065 |
|
10066 |
if (kvm_enabled()) {
|
10067 |
if (kvmppc_fixup_cpu(env) != 0) { |
10068 |
fprintf(stderr, "Unable to virtualize selected CPU with KVM\n");
|
10069 |
exit(1);
|
10070 |
} |
10071 |
} else {
|
10072 |
if (ppc_fixup_cpu(env) != 0) { |
10073 |
fprintf(stderr, "Unable to emulate selected CPU with TCG\n");
|
10074 |
exit(1);
|
10075 |
} |
10076 |
} |
10077 |
|
10078 |
if (create_ppc_opcodes(env, def) < 0) |
10079 |
return -1; |
10080 |
init_ppc_proc(env, def); |
10081 |
|
10082 |
if (def->insns_flags & PPC_FLOAT) {
|
10083 |
gdb_register_coprocessor(env, gdb_get_float_reg, gdb_set_float_reg, |
10084 |
33, "power-fpu.xml", 0); |
10085 |
} |
10086 |
if (def->insns_flags & PPC_ALTIVEC) {
|
10087 |
gdb_register_coprocessor(env, gdb_get_avr_reg, gdb_set_avr_reg, |
10088 |
34, "power-altivec.xml", 0); |
10089 |
} |
10090 |
if (def->insns_flags & PPC_SPE) {
|
10091 |
gdb_register_coprocessor(env, gdb_get_spe_reg, gdb_set_spe_reg, |
10092 |
34, "power-spe.xml", 0); |
10093 |
} |
10094 |
|
10095 |
#if defined(PPC_DUMP_CPU)
|
10096 |
{ |
10097 |
const char *mmu_model, *excp_model, *bus_model; |
10098 |
switch (env->mmu_model) {
|
10099 |
case POWERPC_MMU_32B:
|
10100 |
mmu_model = "PowerPC 32";
|
10101 |
break;
|
10102 |
case POWERPC_MMU_SOFT_6xx:
|
10103 |
mmu_model = "PowerPC 6xx/7xx with software driven TLBs";
|
10104 |
break;
|
10105 |
case POWERPC_MMU_SOFT_74xx:
|
10106 |
mmu_model = "PowerPC 74xx with software driven TLBs";
|
10107 |
break;
|
10108 |
case POWERPC_MMU_SOFT_4xx:
|
10109 |
mmu_model = "PowerPC 4xx with software driven TLBs";
|
10110 |
break;
|
10111 |
case POWERPC_MMU_SOFT_4xx_Z:
|
10112 |
mmu_model = "PowerPC 4xx with software driven TLBs "
|
10113 |
"and zones protections";
|
10114 |
break;
|
10115 |
case POWERPC_MMU_REAL:
|
10116 |
mmu_model = "PowerPC real mode only";
|
10117 |
break;
|
10118 |
case POWERPC_MMU_MPC8xx:
|
10119 |
mmu_model = "PowerPC MPC8xx";
|
10120 |
break;
|
10121 |
case POWERPC_MMU_BOOKE:
|
10122 |
mmu_model = "PowerPC BookE";
|
10123 |
break;
|
10124 |
case POWERPC_MMU_BOOKE206:
|
10125 |
mmu_model = "PowerPC BookE 2.06";
|
10126 |
break;
|
10127 |
case POWERPC_MMU_601:
|
10128 |
mmu_model = "PowerPC 601";
|
10129 |
break;
|
10130 |
#if defined (TARGET_PPC64)
|
10131 |
case POWERPC_MMU_64B:
|
10132 |
mmu_model = "PowerPC 64";
|
10133 |
break;
|
10134 |
case POWERPC_MMU_620:
|
10135 |
mmu_model = "PowerPC 620";
|
10136 |
break;
|
10137 |
#endif
|
10138 |
default:
|
10139 |
mmu_model = "Unknown or invalid";
|
10140 |
break;
|
10141 |
} |
10142 |
switch (env->excp_model) {
|
10143 |
case POWERPC_EXCP_STD:
|
10144 |
excp_model = "PowerPC";
|
10145 |
break;
|
10146 |
case POWERPC_EXCP_40x:
|
10147 |
excp_model = "PowerPC 40x";
|
10148 |
break;
|
10149 |
case POWERPC_EXCP_601:
|
10150 |
excp_model = "PowerPC 601";
|
10151 |
break;
|
10152 |
case POWERPC_EXCP_602:
|
10153 |
excp_model = "PowerPC 602";
|
10154 |
break;
|
10155 |
case POWERPC_EXCP_603:
|
10156 |
excp_model = "PowerPC 603";
|
10157 |
break;
|
10158 |
case POWERPC_EXCP_603E:
|
10159 |
excp_model = "PowerPC 603e";
|
10160 |
break;
|
10161 |
case POWERPC_EXCP_604:
|
10162 |
excp_model = "PowerPC 604";
|
10163 |
break;
|
10164 |
case POWERPC_EXCP_7x0:
|
10165 |
excp_model = "PowerPC 740/750";
|
10166 |
break;
|
10167 |
case POWERPC_EXCP_7x5:
|
10168 |
excp_model = "PowerPC 745/755";
|
10169 |
break;
|
10170 |
case POWERPC_EXCP_74xx:
|
10171 |
excp_model = "PowerPC 74xx";
|
10172 |
break;
|
10173 |
case POWERPC_EXCP_BOOKE:
|
10174 |
excp_model = "PowerPC BookE";
|
10175 |
break;
|
10176 |
#if defined (TARGET_PPC64)
|
10177 |
case POWERPC_EXCP_970:
|
10178 |
excp_model = "PowerPC 970";
|
10179 |
break;
|
10180 |
#endif
|
10181 |
default:
|
10182 |
excp_model = "Unknown or invalid";
|
10183 |
break;
|
10184 |
} |
10185 |
switch (env->bus_model) {
|
10186 |
case PPC_FLAGS_INPUT_6xx:
|
10187 |
bus_model = "PowerPC 6xx";
|
10188 |
break;
|
10189 |
case PPC_FLAGS_INPUT_BookE:
|
10190 |
bus_model = "PowerPC BookE";
|
10191 |
break;
|
10192 |
case PPC_FLAGS_INPUT_405:
|
10193 |
bus_model = "PowerPC 405";
|
10194 |
break;
|
10195 |
case PPC_FLAGS_INPUT_401:
|
10196 |
bus_model = "PowerPC 401/403";
|
10197 |
break;
|
10198 |
case PPC_FLAGS_INPUT_RCPU:
|
10199 |
bus_model = "RCPU / MPC8xx";
|
10200 |
break;
|
10201 |
#if defined (TARGET_PPC64)
|
10202 |
case PPC_FLAGS_INPUT_970:
|
10203 |
bus_model = "PowerPC 970";
|
10204 |
break;
|
10205 |
#endif
|
10206 |
default:
|
10207 |
bus_model = "Unknown or invalid";
|
10208 |
break;
|
10209 |
} |
10210 |
printf("PowerPC %-12s : PVR %08x MSR %016" PRIx64 "\n" |
10211 |
" MMU model : %s\n",
|
10212 |
def->name, def->pvr, def->msr_mask, mmu_model); |
10213 |
#if !defined(CONFIG_USER_ONLY)
|
10214 |
if (env->tlb != NULL) { |
10215 |
printf(" %d %s TLB in %d ways\n",
|
10216 |
env->nb_tlb, env->id_tlbs ? "splitted" : "merged", |
10217 |
env->nb_ways); |
10218 |
} |
10219 |
#endif
|
10220 |
printf(" Exceptions model : %s\n"
|
10221 |
" Bus model : %s\n",
|
10222 |
excp_model, bus_model); |
10223 |
printf(" MSR features :\n");
|
10224 |
if (env->flags & POWERPC_FLAG_SPE)
|
10225 |
printf(" signal processing engine enable"
|
10226 |
"\n");
|
10227 |
else if (env->flags & POWERPC_FLAG_VRE) |
10228 |
printf(" vector processor enable\n");
|
10229 |
if (env->flags & POWERPC_FLAG_TGPR)
|
10230 |
printf(" temporary GPRs\n");
|
10231 |
else if (env->flags & POWERPC_FLAG_CE) |
10232 |
printf(" critical input enable\n");
|
10233 |
if (env->flags & POWERPC_FLAG_SE)
|
10234 |
printf(" single-step trace mode\n");
|
10235 |
else if (env->flags & POWERPC_FLAG_DWE) |
10236 |
printf(" debug wait enable\n");
|
10237 |
else if (env->flags & POWERPC_FLAG_UBLE) |
10238 |
printf(" user BTB lock enable\n");
|
10239 |
if (env->flags & POWERPC_FLAG_BE)
|
10240 |
printf(" branch-step trace mode\n");
|
10241 |
else if (env->flags & POWERPC_FLAG_DE) |
10242 |
printf(" debug interrupt enable\n");
|
10243 |
if (env->flags & POWERPC_FLAG_PX)
|
10244 |
printf(" inclusive protection\n");
|
10245 |
else if (env->flags & POWERPC_FLAG_PMM) |
10246 |
printf(" performance monitor mark\n");
|
10247 |
if (env->flags == POWERPC_FLAG_NONE)
|
10248 |
printf(" none\n");
|
10249 |
printf(" Time-base/decrementer clock source: %s\n",
|
10250 |
env->flags & POWERPC_FLAG_RTC_CLK ? "RTC clock" : "bus clock"); |
10251 |
} |
10252 |
dump_ppc_insns(env); |
10253 |
dump_ppc_sprs(env); |
10254 |
fflush(stdout); |
10255 |
#endif
|
10256 |
|
10257 |
return 0; |
10258 |
} |
10259 |
|
10260 |
static bool ppc_cpu_usable(const ppc_def_t *def) |
10261 |
{ |
10262 |
#if defined(TARGET_PPCEMB)
|
10263 |
/* When using the ppcemb target, we only support 440 style cores */
|
10264 |
if (def->mmu_model != POWERPC_MMU_BOOKE) {
|
10265 |
return false; |
10266 |
} |
10267 |
#endif
|
10268 |
|
10269 |
return true; |
10270 |
} |
10271 |
|
10272 |
const ppc_def_t *ppc_find_by_pvr(uint32_t pvr)
|
10273 |
{ |
10274 |
int i;
|
10275 |
|
10276 |
for (i = 0; i < ARRAY_SIZE(ppc_defs); i++) { |
10277 |
if (!ppc_cpu_usable(&ppc_defs[i])) {
|
10278 |
continue;
|
10279 |
} |
10280 |
|
10281 |
/* If we have an exact match, we're done */
|
10282 |
if (pvr == ppc_defs[i].pvr) {
|
10283 |
return &ppc_defs[i];
|
10284 |
} |
10285 |
} |
10286 |
|
10287 |
return NULL; |
10288 |
} |
10289 |
|
10290 |
#include <ctype.h> |
10291 |
|
10292 |
const ppc_def_t *cpu_ppc_find_by_name (const char *name) |
10293 |
{ |
10294 |
const ppc_def_t *ret;
|
10295 |
const char *p; |
10296 |
int i, max, len;
|
10297 |
|
10298 |
if (kvm_enabled() && (strcasecmp(name, "host") == 0)) { |
10299 |
return kvmppc_host_cpu_def();
|
10300 |
} |
10301 |
|
10302 |
/* Check if the given name is a PVR */
|
10303 |
len = strlen(name); |
10304 |
if (len == 10 && name[0] == '0' && name[1] == 'x') { |
10305 |
p = name + 2;
|
10306 |
goto check_pvr;
|
10307 |
} else if (len == 8) { |
10308 |
p = name; |
10309 |
check_pvr:
|
10310 |
for (i = 0; i < 8; i++) { |
10311 |
if (!qemu_isxdigit(*p++))
|
10312 |
break;
|
10313 |
} |
10314 |
if (i == 8) |
10315 |
return ppc_find_by_pvr(strtoul(name, NULL, 16)); |
10316 |
} |
10317 |
ret = NULL;
|
10318 |
max = ARRAY_SIZE(ppc_defs); |
10319 |
for (i = 0; i < max; i++) { |
10320 |
if (!ppc_cpu_usable(&ppc_defs[i])) {
|
10321 |
continue;
|
10322 |
} |
10323 |
|
10324 |
if (strcasecmp(name, ppc_defs[i].name) == 0) { |
10325 |
ret = &ppc_defs[i]; |
10326 |
break;
|
10327 |
} |
10328 |
} |
10329 |
|
10330 |
return ret;
|
10331 |
} |
10332 |
|
10333 |
void ppc_cpu_list (FILE *f, fprintf_function cpu_fprintf)
|
10334 |
{ |
10335 |
int i, max;
|
10336 |
|
10337 |
max = ARRAY_SIZE(ppc_defs); |
10338 |
for (i = 0; i < max; i++) { |
10339 |
if (!ppc_cpu_usable(&ppc_defs[i])) {
|
10340 |
continue;
|
10341 |
} |
10342 |
|
10343 |
(*cpu_fprintf)(f, "PowerPC %-16s PVR %08x\n",
|
10344 |
ppc_defs[i].name, ppc_defs[i].pvr); |
10345 |
} |
10346 |
} |
10347 |
|
10348 |
/* CPUClass::reset() */
|
10349 |
static void ppc_cpu_reset(CPUState *s) |
10350 |
{ |
10351 |
PowerPCCPU *cpu = POWERPC_CPU(s); |
10352 |
PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); |
10353 |
CPUPPCState *env = &cpu->env; |
10354 |
target_ulong msr; |
10355 |
|
10356 |
if (qemu_loglevel_mask(CPU_LOG_RESET)) {
|
10357 |
qemu_log("CPU Reset (CPU %d)\n", env->cpu_index);
|
10358 |
log_cpu_state(env, 0);
|
10359 |
} |
10360 |
|
10361 |
pcc->parent_reset(s); |
10362 |
|
10363 |
msr = (target_ulong)0;
|
10364 |
if (0) { |
10365 |
/* XXX: find a suitable condition to enable the hypervisor mode */
|
10366 |
msr |= (target_ulong)MSR_HVB; |
10367 |
} |
10368 |
msr |= (target_ulong)0 << MSR_AP; /* TO BE CHECKED */ |
10369 |
msr |= (target_ulong)0 << MSR_SA; /* TO BE CHECKED */ |
10370 |
msr |= (target_ulong)1 << MSR_EP;
|
10371 |
#if defined(DO_SINGLE_STEP) && 0 |
10372 |
/* Single step trace mode */
|
10373 |
msr |= (target_ulong)1 << MSR_SE;
|
10374 |
msr |= (target_ulong)1 << MSR_BE;
|
10375 |
#endif
|
10376 |
#if defined(CONFIG_USER_ONLY)
|
10377 |
msr |= (target_ulong)1 << MSR_FP; /* Allow floating point usage */ |
10378 |
msr |= (target_ulong)1 << MSR_VR; /* Allow altivec usage */ |
10379 |
msr |= (target_ulong)1 << MSR_SPE; /* Allow SPE usage */ |
10380 |
msr |= (target_ulong)1 << MSR_PR;
|
10381 |
#else
|
10382 |
env->excp_prefix = env->hreset_excp_prefix; |
10383 |
env->nip = env->hreset_vector | env->excp_prefix; |
10384 |
if (env->mmu_model != POWERPC_MMU_REAL) {
|
10385 |
ppc_tlb_invalidate_all(env); |
10386 |
} |
10387 |
#endif
|
10388 |
env->msr = msr & env->msr_mask; |
10389 |
#if defined(TARGET_PPC64)
|
10390 |
if (env->mmu_model & POWERPC_MMU_64) {
|
10391 |
env->msr |= (1ULL << MSR_SF);
|
10392 |
} |
10393 |
#endif
|
10394 |
hreg_compute_hflags(env); |
10395 |
env->reserve_addr = (target_ulong)-1ULL;
|
10396 |
/* Be sure no exception or interrupt is pending */
|
10397 |
env->pending_interrupts = 0;
|
10398 |
env->exception_index = POWERPC_EXCP_NONE; |
10399 |
env->error_code = 0;
|
10400 |
/* Flush all TLBs */
|
10401 |
tlb_flush(env, 1);
|
10402 |
} |
10403 |
|
10404 |
static void ppc_cpu_initfn(Object *obj) |
10405 |
{ |
10406 |
PowerPCCPU *cpu = POWERPC_CPU(obj); |
10407 |
CPUPPCState *env = &cpu->env; |
10408 |
|
10409 |
cpu_exec_init(env); |
10410 |
} |
10411 |
|
10412 |
static void ppc_cpu_class_init(ObjectClass *oc, void *data) |
10413 |
{ |
10414 |
PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); |
10415 |
CPUClass *cc = CPU_CLASS(oc); |
10416 |
|
10417 |
pcc->parent_reset = cc->reset; |
10418 |
cc->reset = ppc_cpu_reset; |
10419 |
} |
10420 |
|
10421 |
static const TypeInfo ppc_cpu_type_info = { |
10422 |
.name = TYPE_POWERPC_CPU, |
10423 |
.parent = TYPE_CPU, |
10424 |
.instance_size = sizeof(PowerPCCPU),
|
10425 |
.instance_init = ppc_cpu_initfn, |
10426 |
.abstract = false,
|
10427 |
.class_size = sizeof(PowerPCCPUClass),
|
10428 |
.class_init = ppc_cpu_class_init, |
10429 |
}; |
10430 |
|
10431 |
static void ppc_cpu_register_types(void) |
10432 |
{ |
10433 |
type_register_static(&ppc_cpu_type_info); |
10434 |
} |
10435 |
|
10436 |
type_init(ppc_cpu_register_types) |