root / hw / pflash_cfi02.c @ 81486b55
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1 | 29133e9a | bellard | /*
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2 | 29133e9a | bellard | * CFI parallel flash with AMD command set emulation
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3 | 5fafdf24 | ths | *
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4 | 29133e9a | bellard | * Copyright (c) 2005 Jocelyn Mayer
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5 | 29133e9a | bellard | *
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6 | 29133e9a | bellard | * This library is free software; you can redistribute it and/or
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7 | 29133e9a | bellard | * modify it under the terms of the GNU Lesser General Public
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8 | 29133e9a | bellard | * License as published by the Free Software Foundation; either
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9 | 29133e9a | bellard | * version 2 of the License, or (at your option) any later version.
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10 | 29133e9a | bellard | *
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11 | 29133e9a | bellard | * This library is distributed in the hope that it will be useful,
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12 | 29133e9a | bellard | * but WITHOUT ANY WARRANTY; without even the implied warranty of
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13 | 29133e9a | bellard | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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14 | 29133e9a | bellard | * Lesser General Public License for more details.
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15 | 29133e9a | bellard | *
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16 | 29133e9a | bellard | * You should have received a copy of the GNU Lesser General Public
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17 | 8167ee88 | Blue Swirl | * License along with this library; if not, see <http://www.gnu.org/licenses/>.
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18 | 29133e9a | bellard | */
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19 | 29133e9a | bellard | |
20 | 29133e9a | bellard | /*
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21 | 29133e9a | bellard | * For now, this code can emulate flashes of 1, 2 or 4 bytes width.
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22 | 29133e9a | bellard | * Supported commands/modes are:
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23 | 29133e9a | bellard | * - flash read
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24 | 29133e9a | bellard | * - flash write
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25 | 29133e9a | bellard | * - flash ID read
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26 | 29133e9a | bellard | * - sector erase
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27 | 29133e9a | bellard | * - chip erase
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28 | 29133e9a | bellard | * - unlock bypass command
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29 | 29133e9a | bellard | * - CFI queries
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30 | 29133e9a | bellard | *
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31 | 29133e9a | bellard | * It does not support flash interleaving.
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32 | 29133e9a | bellard | * It does not implement boot blocs with reduced size
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33 | 29133e9a | bellard | * It does not implement software data protection as found in many real chips
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34 | 29133e9a | bellard | * It does not implement erase suspend/resume commands
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35 | 29133e9a | bellard | * It does not implement multiple sectors erase
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36 | 29133e9a | bellard | */
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37 | 29133e9a | bellard | |
38 | 87ecb68b | pbrook | #include "hw.h" |
39 | 87ecb68b | pbrook | #include "flash.h" |
40 | 87ecb68b | pbrook | #include "qemu-timer.h" |
41 | 87ecb68b | pbrook | #include "block.h" |
42 | 29133e9a | bellard | |
43 | 29133e9a | bellard | //#define PFLASH_DEBUG
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44 | 29133e9a | bellard | #ifdef PFLASH_DEBUG
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45 | 001faf32 | Blue Swirl | #define DPRINTF(fmt, ...) \
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46 | 29133e9a | bellard | do { \
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47 | 001faf32 | Blue Swirl | printf("PFLASH: " fmt , ## __VA_ARGS__); \ |
48 | 29133e9a | bellard | } while (0) |
49 | 29133e9a | bellard | #else
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50 | 001faf32 | Blue Swirl | #define DPRINTF(fmt, ...) do { } while (0) |
51 | 29133e9a | bellard | #endif
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52 | 29133e9a | bellard | |
53 | 661bfc80 | Jan Kiszka | #define PFLASH_LAZY_ROMD_THRESHOLD 42 |
54 | 661bfc80 | Jan Kiszka | |
55 | c227f099 | Anthony Liguori | struct pflash_t {
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56 | 29133e9a | bellard | BlockDriverState *bs; |
57 | c227f099 | Anthony Liguori | target_phys_addr_t base; |
58 | 71db710f | blueswir1 | uint32_t sector_len; |
59 | 4fbd24ba | balrog | uint32_t chip_len; |
60 | 4fbd24ba | balrog | int mappings;
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61 | 29133e9a | bellard | int width;
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62 | 29133e9a | bellard | int wcycle; /* if 0, the flash is read normally */ |
63 | 29133e9a | bellard | int bypass;
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64 | 29133e9a | bellard | int ro;
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65 | 29133e9a | bellard | uint8_t cmd; |
66 | 29133e9a | bellard | uint8_t status; |
67 | 29133e9a | bellard | uint16_t ident[4];
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68 | 6725070d | balrog | uint16_t unlock_addr[2];
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69 | 29133e9a | bellard | uint8_t cfi_len; |
70 | 29133e9a | bellard | uint8_t cfi_table[0x52];
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71 | 29133e9a | bellard | QEMUTimer *timer; |
72 | c227f099 | Anthony Liguori | ram_addr_t off; |
73 | 29133e9a | bellard | int fl_mem;
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74 | 9c9bb6c8 | balrog | int rom_mode;
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75 | 661bfc80 | Jan Kiszka | int read_counter; /* used for lazy switch-back to rom mode */ |
76 | 29133e9a | bellard | void *storage;
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77 | 29133e9a | bellard | }; |
78 | 29133e9a | bellard | |
79 | c227f099 | Anthony Liguori | static void pflash_register_memory(pflash_t *pfl, int rom_mode) |
80 | 4fbd24ba | balrog | { |
81 | 4fbd24ba | balrog | unsigned long phys_offset = pfl->fl_mem; |
82 | 4fbd24ba | balrog | int i;
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83 | 4fbd24ba | balrog | |
84 | 4fbd24ba | balrog | if (rom_mode)
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85 | 4fbd24ba | balrog | phys_offset |= pfl->off | IO_MEM_ROMD; |
86 | 9c9bb6c8 | balrog | pfl->rom_mode = rom_mode; |
87 | 4fbd24ba | balrog | |
88 | 4fbd24ba | balrog | for (i = 0; i < pfl->mappings; i++) |
89 | 4fbd24ba | balrog | cpu_register_physical_memory(pfl->base + i * pfl->chip_len, |
90 | 4fbd24ba | balrog | pfl->chip_len, phys_offset); |
91 | 4fbd24ba | balrog | } |
92 | 4fbd24ba | balrog | |
93 | 29133e9a | bellard | static void pflash_timer (void *opaque) |
94 | 29133e9a | bellard | { |
95 | c227f099 | Anthony Liguori | pflash_t *pfl = opaque; |
96 | 29133e9a | bellard | |
97 | 29133e9a | bellard | DPRINTF("%s: command %02x done\n", __func__, pfl->cmd);
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98 | 29133e9a | bellard | /* Reset flash */
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99 | 29133e9a | bellard | pfl->status ^= 0x80;
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100 | 29133e9a | bellard | if (pfl->bypass) {
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101 | 29133e9a | bellard | pfl->wcycle = 2;
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102 | 29133e9a | bellard | } else {
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103 | 4fbd24ba | balrog | pflash_register_memory(pfl, 1);
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104 | 29133e9a | bellard | pfl->wcycle = 0;
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105 | 29133e9a | bellard | } |
106 | 29133e9a | bellard | pfl->cmd = 0;
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107 | 29133e9a | bellard | } |
108 | 29133e9a | bellard | |
109 | 5f9fc5ad | Blue Swirl | static uint32_t pflash_read (pflash_t *pfl, target_phys_addr_t offset,
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110 | 5f9fc5ad | Blue Swirl | int width, int be) |
111 | 29133e9a | bellard | { |
112 | f8be67ee | Blue Swirl | target_phys_addr_t boff; |
113 | 29133e9a | bellard | uint32_t ret; |
114 | 29133e9a | bellard | uint8_t *p; |
115 | 29133e9a | bellard | |
116 | f8be67ee | Blue Swirl | DPRINTF("%s: offset " TARGET_FMT_plx "\n", __func__, offset); |
117 | 29133e9a | bellard | ret = -1;
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118 | 661bfc80 | Jan Kiszka | /* Lazy reset to ROMD mode after a certain amount of read accesses */
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119 | 661bfc80 | Jan Kiszka | if (!pfl->rom_mode && pfl->wcycle == 0 && |
120 | 661bfc80 | Jan Kiszka | ++pfl->read_counter > PFLASH_LAZY_ROMD_THRESHOLD) { |
121 | 661bfc80 | Jan Kiszka | pflash_register_memory(pfl, 1);
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122 | 0f459d16 | pbrook | } |
123 | 4fbd24ba | balrog | offset &= pfl->chip_len - 1;
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124 | 29133e9a | bellard | boff = offset & 0xFF;
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125 | 29133e9a | bellard | if (pfl->width == 2) |
126 | 29133e9a | bellard | boff = boff >> 1;
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127 | 29133e9a | bellard | else if (pfl->width == 4) |
128 | 29133e9a | bellard | boff = boff >> 2;
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129 | 29133e9a | bellard | switch (pfl->cmd) {
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130 | 29133e9a | bellard | default:
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131 | 29133e9a | bellard | /* This should never happen : reset state & treat it as a read*/
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132 | 29133e9a | bellard | DPRINTF("%s: unknown command state: %x\n", __func__, pfl->cmd);
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133 | 29133e9a | bellard | pfl->wcycle = 0;
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134 | 29133e9a | bellard | pfl->cmd = 0;
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135 | 29133e9a | bellard | case 0x80: |
136 | 29133e9a | bellard | /* We accept reads during second unlock sequence... */
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137 | 29133e9a | bellard | case 0x00: |
138 | 29133e9a | bellard | flash_read:
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139 | 29133e9a | bellard | /* Flash area read */
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140 | 29133e9a | bellard | p = pfl->storage; |
141 | 29133e9a | bellard | switch (width) {
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142 | 29133e9a | bellard | case 1: |
143 | 29133e9a | bellard | ret = p[offset]; |
144 | 29133e9a | bellard | // DPRINTF("%s: data offset %08x %02x\n", __func__, offset, ret);
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145 | 29133e9a | bellard | break;
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146 | 29133e9a | bellard | case 2: |
147 | 5f9fc5ad | Blue Swirl | if (be) {
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148 | 5f9fc5ad | Blue Swirl | ret = p[offset] << 8;
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149 | 5f9fc5ad | Blue Swirl | ret |= p[offset + 1];
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150 | 5f9fc5ad | Blue Swirl | } else {
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151 | 5f9fc5ad | Blue Swirl | ret = p[offset]; |
152 | 5f9fc5ad | Blue Swirl | ret |= p[offset + 1] << 8; |
153 | 5f9fc5ad | Blue Swirl | } |
154 | 29133e9a | bellard | // DPRINTF("%s: data offset %08x %04x\n", __func__, offset, ret);
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155 | 29133e9a | bellard | break;
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156 | 29133e9a | bellard | case 4: |
157 | 5f9fc5ad | Blue Swirl | if (be) {
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158 | 5f9fc5ad | Blue Swirl | ret = p[offset] << 24;
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159 | 5f9fc5ad | Blue Swirl | ret |= p[offset + 1] << 16; |
160 | 5f9fc5ad | Blue Swirl | ret |= p[offset + 2] << 8; |
161 | 5f9fc5ad | Blue Swirl | ret |= p[offset + 3];
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162 | 5f9fc5ad | Blue Swirl | } else {
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163 | 5f9fc5ad | Blue Swirl | ret = p[offset]; |
164 | 5f9fc5ad | Blue Swirl | ret |= p[offset + 1] << 8; |
165 | 5f9fc5ad | Blue Swirl | ret |= p[offset + 2] << 16; |
166 | 5f9fc5ad | Blue Swirl | ret |= p[offset + 3] << 24; |
167 | 5f9fc5ad | Blue Swirl | } |
168 | 29133e9a | bellard | // DPRINTF("%s: data offset %08x %08x\n", __func__, offset, ret);
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169 | 29133e9a | bellard | break;
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170 | 29133e9a | bellard | } |
171 | 29133e9a | bellard | break;
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172 | 29133e9a | bellard | case 0x90: |
173 | 29133e9a | bellard | /* flash ID read */
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174 | 29133e9a | bellard | switch (boff) {
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175 | 29133e9a | bellard | case 0x00: |
176 | 29133e9a | bellard | case 0x01: |
177 | 29133e9a | bellard | ret = pfl->ident[boff & 0x01];
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178 | 29133e9a | bellard | break;
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179 | 29133e9a | bellard | case 0x02: |
180 | 29133e9a | bellard | ret = 0x00; /* Pretend all sectors are unprotected */ |
181 | 29133e9a | bellard | break;
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182 | 29133e9a | bellard | case 0x0E: |
183 | 29133e9a | bellard | case 0x0F: |
184 | 29133e9a | bellard | if (pfl->ident[2 + (boff & 0x01)] == (uint8_t)-1) |
185 | 29133e9a | bellard | goto flash_read;
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186 | 29133e9a | bellard | ret = pfl->ident[2 + (boff & 0x01)]; |
187 | 29133e9a | bellard | break;
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188 | 29133e9a | bellard | default:
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189 | 29133e9a | bellard | goto flash_read;
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190 | 29133e9a | bellard | } |
191 | f8be67ee | Blue Swirl | DPRINTF("%s: ID " TARGET_FMT_pld " %x\n", __func__, boff, ret); |
192 | 29133e9a | bellard | break;
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193 | 29133e9a | bellard | case 0xA0: |
194 | 29133e9a | bellard | case 0x10: |
195 | 29133e9a | bellard | case 0x30: |
196 | 29133e9a | bellard | /* Status register read */
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197 | 29133e9a | bellard | ret = pfl->status; |
198 | 29133e9a | bellard | DPRINTF("%s: status %x\n", __func__, ret);
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199 | 29133e9a | bellard | /* Toggle bit 6 */
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200 | 29133e9a | bellard | pfl->status ^= 0x40;
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201 | 29133e9a | bellard | break;
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202 | 29133e9a | bellard | case 0x98: |
203 | 29133e9a | bellard | /* CFI query mode */
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204 | 29133e9a | bellard | if (boff > pfl->cfi_len)
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205 | 29133e9a | bellard | ret = 0;
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206 | 29133e9a | bellard | else
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207 | 29133e9a | bellard | ret = pfl->cfi_table[boff]; |
208 | 29133e9a | bellard | break;
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209 | 29133e9a | bellard | } |
210 | 29133e9a | bellard | |
211 | 29133e9a | bellard | return ret;
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212 | 29133e9a | bellard | } |
213 | 29133e9a | bellard | |
214 | 29133e9a | bellard | /* update flash content on disk */
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215 | c227f099 | Anthony Liguori | static void pflash_update(pflash_t *pfl, int offset, |
216 | 29133e9a | bellard | int size)
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217 | 29133e9a | bellard | { |
218 | 29133e9a | bellard | int offset_end;
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219 | 29133e9a | bellard | if (pfl->bs) {
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220 | 29133e9a | bellard | offset_end = offset + size; |
221 | 29133e9a | bellard | /* round to sectors */
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222 | 29133e9a | bellard | offset = offset >> 9;
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223 | 29133e9a | bellard | offset_end = (offset_end + 511) >> 9; |
224 | 5fafdf24 | ths | bdrv_write(pfl->bs, offset, pfl->storage + (offset << 9),
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225 | 29133e9a | bellard | offset_end - offset); |
226 | 29133e9a | bellard | } |
227 | 29133e9a | bellard | } |
228 | 29133e9a | bellard | |
229 | f8be67ee | Blue Swirl | static void pflash_write (pflash_t *pfl, target_phys_addr_t offset, |
230 | 5f9fc5ad | Blue Swirl | uint32_t value, int width, int be) |
231 | 29133e9a | bellard | { |
232 | f8be67ee | Blue Swirl | target_phys_addr_t boff; |
233 | 29133e9a | bellard | uint8_t *p; |
234 | 29133e9a | bellard | uint8_t cmd; |
235 | 29133e9a | bellard | |
236 | 95d1f3ed | j_mayer | cmd = value; |
237 | 95d1f3ed | j_mayer | if (pfl->cmd != 0xA0 && cmd == 0xF0) { |
238 | 95d1f3ed | j_mayer | #if 0
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239 | 95d1f3ed | j_mayer | DPRINTF("%s: flash reset asked (%02x %02x)\n",
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240 | 95d1f3ed | j_mayer | __func__, pfl->cmd, cmd);
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241 | 95d1f3ed | j_mayer | #endif
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242 | 95d1f3ed | j_mayer | goto reset_flash;
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243 | 95d1f3ed | j_mayer | } |
244 | f8be67ee | Blue Swirl | DPRINTF("%s: offset " TARGET_FMT_plx " %08x %d %d\n", __func__, |
245 | 95d1f3ed | j_mayer | offset, value, width, pfl->wcycle); |
246 | 4fbd24ba | balrog | offset &= pfl->chip_len - 1;
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247 | 3b46e624 | ths | |
248 | f8be67ee | Blue Swirl | DPRINTF("%s: offset " TARGET_FMT_plx " %08x %d\n", __func__, |
249 | e96efcfc | j_mayer | offset, value, width); |
250 | 29133e9a | bellard | boff = offset & (pfl->sector_len - 1);
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251 | 29133e9a | bellard | if (pfl->width == 2) |
252 | 29133e9a | bellard | boff = boff >> 1;
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253 | 29133e9a | bellard | else if (pfl->width == 4) |
254 | 29133e9a | bellard | boff = boff >> 2;
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255 | 29133e9a | bellard | switch (pfl->wcycle) {
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256 | 29133e9a | bellard | case 0: |
257 | 9c9bb6c8 | balrog | /* Set the device in I/O access mode if required */
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258 | 9c9bb6c8 | balrog | if (pfl->rom_mode)
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259 | 9c9bb6c8 | balrog | pflash_register_memory(pfl, 0);
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260 | 661bfc80 | Jan Kiszka | pfl->read_counter = 0;
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261 | 29133e9a | bellard | /* We're in read mode */
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262 | 29133e9a | bellard | check_unlock0:
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263 | 29133e9a | bellard | if (boff == 0x55 && cmd == 0x98) { |
264 | 29133e9a | bellard | enter_CFI_mode:
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265 | 29133e9a | bellard | /* Enter CFI query mode */
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266 | 29133e9a | bellard | pfl->wcycle = 7;
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267 | 29133e9a | bellard | pfl->cmd = 0x98;
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268 | 29133e9a | bellard | return;
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269 | 29133e9a | bellard | } |
270 | 6725070d | balrog | if (boff != pfl->unlock_addr[0] || cmd != 0xAA) { |
271 | f8be67ee | Blue Swirl | DPRINTF("%s: unlock0 failed " TARGET_FMT_plx " %02x %04x\n", |
272 | 6725070d | balrog | __func__, boff, cmd, pfl->unlock_addr[0]);
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273 | 29133e9a | bellard | goto reset_flash;
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274 | 29133e9a | bellard | } |
275 | 29133e9a | bellard | DPRINTF("%s: unlock sequence started\n", __func__);
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276 | 29133e9a | bellard | break;
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277 | 29133e9a | bellard | case 1: |
278 | 29133e9a | bellard | /* We started an unlock sequence */
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279 | 29133e9a | bellard | check_unlock1:
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280 | 6725070d | balrog | if (boff != pfl->unlock_addr[1] || cmd != 0x55) { |
281 | f8be67ee | Blue Swirl | DPRINTF("%s: unlock1 failed " TARGET_FMT_plx " %02x\n", __func__, |
282 | e96efcfc | j_mayer | boff, cmd); |
283 | 29133e9a | bellard | goto reset_flash;
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284 | 29133e9a | bellard | } |
285 | 29133e9a | bellard | DPRINTF("%s: unlock sequence done\n", __func__);
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286 | 29133e9a | bellard | break;
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287 | 29133e9a | bellard | case 2: |
288 | 29133e9a | bellard | /* We finished an unlock sequence */
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289 | 6725070d | balrog | if (!pfl->bypass && boff != pfl->unlock_addr[0]) { |
290 | f8be67ee | Blue Swirl | DPRINTF("%s: command failed " TARGET_FMT_plx " %02x\n", __func__, |
291 | e96efcfc | j_mayer | boff, cmd); |
292 | 29133e9a | bellard | goto reset_flash;
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293 | 29133e9a | bellard | } |
294 | 29133e9a | bellard | switch (cmd) {
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295 | 29133e9a | bellard | case 0x20: |
296 | 29133e9a | bellard | pfl->bypass = 1;
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297 | 29133e9a | bellard | goto do_bypass;
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298 | 29133e9a | bellard | case 0x80: |
299 | 29133e9a | bellard | case 0x90: |
300 | 29133e9a | bellard | case 0xA0: |
301 | 29133e9a | bellard | pfl->cmd = cmd; |
302 | 29133e9a | bellard | DPRINTF("%s: starting command %02x\n", __func__, cmd);
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303 | 29133e9a | bellard | break;
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304 | 29133e9a | bellard | default:
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305 | 29133e9a | bellard | DPRINTF("%s: unknown command %02x\n", __func__, cmd);
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306 | 29133e9a | bellard | goto reset_flash;
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307 | 29133e9a | bellard | } |
308 | 29133e9a | bellard | break;
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309 | 29133e9a | bellard | case 3: |
310 | 29133e9a | bellard | switch (pfl->cmd) {
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311 | 29133e9a | bellard | case 0x80: |
312 | 29133e9a | bellard | /* We need another unlock sequence */
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313 | 29133e9a | bellard | goto check_unlock0;
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314 | 29133e9a | bellard | case 0xA0: |
315 | f8be67ee | Blue Swirl | DPRINTF("%s: write data offset " TARGET_FMT_plx " %08x %d\n", |
316 | 29133e9a | bellard | __func__, offset, value, width); |
317 | 29133e9a | bellard | p = pfl->storage; |
318 | 29133e9a | bellard | switch (width) {
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319 | 29133e9a | bellard | case 1: |
320 | 29133e9a | bellard | p[offset] &= value; |
321 | 29133e9a | bellard | pflash_update(pfl, offset, 1);
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322 | 29133e9a | bellard | break;
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323 | 29133e9a | bellard | case 2: |
324 | 5f9fc5ad | Blue Swirl | if (be) {
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325 | 5f9fc5ad | Blue Swirl | p[offset] &= value >> 8;
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326 | 5f9fc5ad | Blue Swirl | p[offset + 1] &= value;
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327 | 5f9fc5ad | Blue Swirl | } else {
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328 | 5f9fc5ad | Blue Swirl | p[offset] &= value; |
329 | 5f9fc5ad | Blue Swirl | p[offset + 1] &= value >> 8; |
330 | 5f9fc5ad | Blue Swirl | } |
331 | 29133e9a | bellard | pflash_update(pfl, offset, 2);
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332 | 29133e9a | bellard | break;
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333 | 29133e9a | bellard | case 4: |
334 | 5f9fc5ad | Blue Swirl | if (be) {
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335 | 5f9fc5ad | Blue Swirl | p[offset] &= value >> 24;
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336 | 5f9fc5ad | Blue Swirl | p[offset + 1] &= value >> 16; |
337 | 5f9fc5ad | Blue Swirl | p[offset + 2] &= value >> 8; |
338 | 5f9fc5ad | Blue Swirl | p[offset + 3] &= value;
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339 | 5f9fc5ad | Blue Swirl | } else {
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340 | 5f9fc5ad | Blue Swirl | p[offset] &= value; |
341 | 5f9fc5ad | Blue Swirl | p[offset + 1] &= value >> 8; |
342 | 5f9fc5ad | Blue Swirl | p[offset + 2] &= value >> 16; |
343 | 5f9fc5ad | Blue Swirl | p[offset + 3] &= value >> 24; |
344 | 5f9fc5ad | Blue Swirl | } |
345 | 29133e9a | bellard | pflash_update(pfl, offset, 4);
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346 | 29133e9a | bellard | break;
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347 | 29133e9a | bellard | } |
348 | 29133e9a | bellard | pfl->status = 0x00 | ~(value & 0x80); |
349 | 29133e9a | bellard | /* Let's pretend write is immediate */
|
350 | 29133e9a | bellard | if (pfl->bypass)
|
351 | 29133e9a | bellard | goto do_bypass;
|
352 | 29133e9a | bellard | goto reset_flash;
|
353 | 29133e9a | bellard | case 0x90: |
354 | 29133e9a | bellard | if (pfl->bypass && cmd == 0x00) { |
355 | 29133e9a | bellard | /* Unlock bypass reset */
|
356 | 29133e9a | bellard | goto reset_flash;
|
357 | 29133e9a | bellard | } |
358 | 29133e9a | bellard | /* We can enter CFI query mode from autoselect mode */
|
359 | 29133e9a | bellard | if (boff == 0x55 && cmd == 0x98) |
360 | 29133e9a | bellard | goto enter_CFI_mode;
|
361 | 29133e9a | bellard | /* No break here */
|
362 | 29133e9a | bellard | default:
|
363 | 29133e9a | bellard | DPRINTF("%s: invalid write for command %02x\n",
|
364 | 29133e9a | bellard | __func__, pfl->cmd); |
365 | 29133e9a | bellard | goto reset_flash;
|
366 | 29133e9a | bellard | } |
367 | 29133e9a | bellard | case 4: |
368 | 29133e9a | bellard | switch (pfl->cmd) {
|
369 | 29133e9a | bellard | case 0xA0: |
370 | 29133e9a | bellard | /* Ignore writes while flash data write is occuring */
|
371 | 29133e9a | bellard | /* As we suppose write is immediate, this should never happen */
|
372 | 29133e9a | bellard | return;
|
373 | 29133e9a | bellard | case 0x80: |
374 | 29133e9a | bellard | goto check_unlock1;
|
375 | 29133e9a | bellard | default:
|
376 | 29133e9a | bellard | /* Should never happen */
|
377 | 29133e9a | bellard | DPRINTF("%s: invalid command state %02x (wc 4)\n",
|
378 | 29133e9a | bellard | __func__, pfl->cmd); |
379 | 29133e9a | bellard | goto reset_flash;
|
380 | 29133e9a | bellard | } |
381 | 29133e9a | bellard | break;
|
382 | 29133e9a | bellard | case 5: |
383 | 29133e9a | bellard | switch (cmd) {
|
384 | 29133e9a | bellard | case 0x10: |
385 | 6725070d | balrog | if (boff != pfl->unlock_addr[0]) { |
386 | f8be67ee | Blue Swirl | DPRINTF("%s: chip erase: invalid address " TARGET_FMT_plx "\n", |
387 | 29133e9a | bellard | __func__, offset); |
388 | 29133e9a | bellard | goto reset_flash;
|
389 | 29133e9a | bellard | } |
390 | 29133e9a | bellard | /* Chip erase */
|
391 | 29133e9a | bellard | DPRINTF("%s: start chip erase\n", __func__);
|
392 | 4fbd24ba | balrog | memset(pfl->storage, 0xFF, pfl->chip_len);
|
393 | 29133e9a | bellard | pfl->status = 0x00;
|
394 | 4fbd24ba | balrog | pflash_update(pfl, 0, pfl->chip_len);
|
395 | 29133e9a | bellard | /* Let's wait 5 seconds before chip erase is done */
|
396 | 5fafdf24 | ths | qemu_mod_timer(pfl->timer, |
397 | 74475455 | Paolo Bonzini | qemu_get_clock_ns(vm_clock) + (get_ticks_per_sec() * 5));
|
398 | 29133e9a | bellard | break;
|
399 | 29133e9a | bellard | case 0x30: |
400 | 29133e9a | bellard | /* Sector erase */
|
401 | 29133e9a | bellard | p = pfl->storage; |
402 | 29133e9a | bellard | offset &= ~(pfl->sector_len - 1);
|
403 | f8be67ee | Blue Swirl | DPRINTF("%s: start sector erase at " TARGET_FMT_plx "\n", __func__, |
404 | e96efcfc | j_mayer | offset); |
405 | 29133e9a | bellard | memset(p + offset, 0xFF, pfl->sector_len);
|
406 | 29133e9a | bellard | pflash_update(pfl, offset, pfl->sector_len); |
407 | 29133e9a | bellard | pfl->status = 0x00;
|
408 | 29133e9a | bellard | /* Let's wait 1/2 second before sector erase is done */
|
409 | 5fafdf24 | ths | qemu_mod_timer(pfl->timer, |
410 | 74475455 | Paolo Bonzini | qemu_get_clock_ns(vm_clock) + (get_ticks_per_sec() / 2));
|
411 | 29133e9a | bellard | break;
|
412 | 29133e9a | bellard | default:
|
413 | 29133e9a | bellard | DPRINTF("%s: invalid command %02x (wc 5)\n", __func__, cmd);
|
414 | 29133e9a | bellard | goto reset_flash;
|
415 | 29133e9a | bellard | } |
416 | 29133e9a | bellard | pfl->cmd = cmd; |
417 | 29133e9a | bellard | break;
|
418 | 29133e9a | bellard | case 6: |
419 | 29133e9a | bellard | switch (pfl->cmd) {
|
420 | 29133e9a | bellard | case 0x10: |
421 | 29133e9a | bellard | /* Ignore writes during chip erase */
|
422 | 29133e9a | bellard | return;
|
423 | 29133e9a | bellard | case 0x30: |
424 | 29133e9a | bellard | /* Ignore writes during sector erase */
|
425 | 29133e9a | bellard | return;
|
426 | 29133e9a | bellard | default:
|
427 | 29133e9a | bellard | /* Should never happen */
|
428 | 29133e9a | bellard | DPRINTF("%s: invalid command state %02x (wc 6)\n",
|
429 | 29133e9a | bellard | __func__, pfl->cmd); |
430 | 29133e9a | bellard | goto reset_flash;
|
431 | 29133e9a | bellard | } |
432 | 29133e9a | bellard | break;
|
433 | 29133e9a | bellard | case 7: /* Special value for CFI queries */ |
434 | 29133e9a | bellard | DPRINTF("%s: invalid write in CFI query mode\n", __func__);
|
435 | 29133e9a | bellard | goto reset_flash;
|
436 | 29133e9a | bellard | default:
|
437 | 29133e9a | bellard | /* Should never happen */
|
438 | 29133e9a | bellard | DPRINTF("%s: invalid write state (wc 7)\n", __func__);
|
439 | 29133e9a | bellard | goto reset_flash;
|
440 | 29133e9a | bellard | } |
441 | 29133e9a | bellard | pfl->wcycle++; |
442 | 29133e9a | bellard | |
443 | 29133e9a | bellard | return;
|
444 | 29133e9a | bellard | |
445 | 29133e9a | bellard | /* Reset flash */
|
446 | 29133e9a | bellard | reset_flash:
|
447 | 29133e9a | bellard | pfl->bypass = 0;
|
448 | 29133e9a | bellard | pfl->wcycle = 0;
|
449 | 29133e9a | bellard | pfl->cmd = 0;
|
450 | 29133e9a | bellard | return;
|
451 | 29133e9a | bellard | |
452 | 29133e9a | bellard | do_bypass:
|
453 | 29133e9a | bellard | pfl->wcycle = 2;
|
454 | 29133e9a | bellard | pfl->cmd = 0;
|
455 | 29133e9a | bellard | return;
|
456 | 29133e9a | bellard | } |
457 | 29133e9a | bellard | |
458 | 29133e9a | bellard | |
459 | 5f9fc5ad | Blue Swirl | static uint32_t pflash_readb_be(void *opaque, target_phys_addr_t addr) |
460 | 5f9fc5ad | Blue Swirl | { |
461 | 5f9fc5ad | Blue Swirl | return pflash_read(opaque, addr, 1, 1); |
462 | 5f9fc5ad | Blue Swirl | } |
463 | 5f9fc5ad | Blue Swirl | |
464 | 5f9fc5ad | Blue Swirl | static uint32_t pflash_readb_le(void *opaque, target_phys_addr_t addr) |
465 | 5f9fc5ad | Blue Swirl | { |
466 | 5f9fc5ad | Blue Swirl | return pflash_read(opaque, addr, 1, 0); |
467 | 5f9fc5ad | Blue Swirl | } |
468 | 5f9fc5ad | Blue Swirl | |
469 | 5f9fc5ad | Blue Swirl | static uint32_t pflash_readw_be(void *opaque, target_phys_addr_t addr) |
470 | 5f9fc5ad | Blue Swirl | { |
471 | 5f9fc5ad | Blue Swirl | pflash_t *pfl = opaque; |
472 | 5f9fc5ad | Blue Swirl | |
473 | 5f9fc5ad | Blue Swirl | return pflash_read(pfl, addr, 2, 1); |
474 | 5f9fc5ad | Blue Swirl | } |
475 | 5f9fc5ad | Blue Swirl | |
476 | 5f9fc5ad | Blue Swirl | static uint32_t pflash_readw_le(void *opaque, target_phys_addr_t addr) |
477 | 5f9fc5ad | Blue Swirl | { |
478 | 5f9fc5ad | Blue Swirl | pflash_t *pfl = opaque; |
479 | 5f9fc5ad | Blue Swirl | |
480 | 5f9fc5ad | Blue Swirl | return pflash_read(pfl, addr, 2, 0); |
481 | 5f9fc5ad | Blue Swirl | } |
482 | 5f9fc5ad | Blue Swirl | |
483 | 5f9fc5ad | Blue Swirl | static uint32_t pflash_readl_be(void *opaque, target_phys_addr_t addr) |
484 | 29133e9a | bellard | { |
485 | 5f9fc5ad | Blue Swirl | pflash_t *pfl = opaque; |
486 | 5f9fc5ad | Blue Swirl | |
487 | 5f9fc5ad | Blue Swirl | return pflash_read(pfl, addr, 4, 1); |
488 | 29133e9a | bellard | } |
489 | 29133e9a | bellard | |
490 | 5f9fc5ad | Blue Swirl | static uint32_t pflash_readl_le(void *opaque, target_phys_addr_t addr) |
491 | 29133e9a | bellard | { |
492 | c227f099 | Anthony Liguori | pflash_t *pfl = opaque; |
493 | 29133e9a | bellard | |
494 | 5f9fc5ad | Blue Swirl | return pflash_read(pfl, addr, 4, 0); |
495 | 5f9fc5ad | Blue Swirl | } |
496 | 5f9fc5ad | Blue Swirl | |
497 | 5f9fc5ad | Blue Swirl | static void pflash_writeb_be(void *opaque, target_phys_addr_t addr, |
498 | 5f9fc5ad | Blue Swirl | uint32_t value) |
499 | 5f9fc5ad | Blue Swirl | { |
500 | 5f9fc5ad | Blue Swirl | pflash_write(opaque, addr, value, 1, 1); |
501 | 29133e9a | bellard | } |
502 | 29133e9a | bellard | |
503 | 5f9fc5ad | Blue Swirl | static void pflash_writeb_le(void *opaque, target_phys_addr_t addr, |
504 | 5f9fc5ad | Blue Swirl | uint32_t value) |
505 | 5f9fc5ad | Blue Swirl | { |
506 | 5f9fc5ad | Blue Swirl | pflash_write(opaque, addr, value, 1, 0); |
507 | 5f9fc5ad | Blue Swirl | } |
508 | 5f9fc5ad | Blue Swirl | |
509 | 5f9fc5ad | Blue Swirl | static void pflash_writew_be(void *opaque, target_phys_addr_t addr, |
510 | 5f9fc5ad | Blue Swirl | uint32_t value) |
511 | 29133e9a | bellard | { |
512 | c227f099 | Anthony Liguori | pflash_t *pfl = opaque; |
513 | 29133e9a | bellard | |
514 | 5f9fc5ad | Blue Swirl | pflash_write(pfl, addr, value, 2, 1); |
515 | 29133e9a | bellard | } |
516 | 29133e9a | bellard | |
517 | 5f9fc5ad | Blue Swirl | static void pflash_writew_le(void *opaque, target_phys_addr_t addr, |
518 | 5f9fc5ad | Blue Swirl | uint32_t value) |
519 | 29133e9a | bellard | { |
520 | 5f9fc5ad | Blue Swirl | pflash_t *pfl = opaque; |
521 | 5f9fc5ad | Blue Swirl | |
522 | 5f9fc5ad | Blue Swirl | pflash_write(pfl, addr, value, 2, 0); |
523 | 29133e9a | bellard | } |
524 | 29133e9a | bellard | |
525 | 5f9fc5ad | Blue Swirl | static void pflash_writel_be(void *opaque, target_phys_addr_t addr, |
526 | 5f9fc5ad | Blue Swirl | uint32_t value) |
527 | 29133e9a | bellard | { |
528 | c227f099 | Anthony Liguori | pflash_t *pfl = opaque; |
529 | 29133e9a | bellard | |
530 | 5f9fc5ad | Blue Swirl | pflash_write(pfl, addr, value, 4, 1); |
531 | 29133e9a | bellard | } |
532 | 29133e9a | bellard | |
533 | 5f9fc5ad | Blue Swirl | static void pflash_writel_le(void *opaque, target_phys_addr_t addr, |
534 | 5f9fc5ad | Blue Swirl | uint32_t value) |
535 | 29133e9a | bellard | { |
536 | c227f099 | Anthony Liguori | pflash_t *pfl = opaque; |
537 | 29133e9a | bellard | |
538 | 5f9fc5ad | Blue Swirl | pflash_write(pfl, addr, value, 4, 0); |
539 | 29133e9a | bellard | } |
540 | 29133e9a | bellard | |
541 | 5f9fc5ad | Blue Swirl | static CPUWriteMemoryFunc * const pflash_write_ops_be[] = { |
542 | 5f9fc5ad | Blue Swirl | &pflash_writeb_be, |
543 | 5f9fc5ad | Blue Swirl | &pflash_writew_be, |
544 | 5f9fc5ad | Blue Swirl | &pflash_writel_be, |
545 | 29133e9a | bellard | }; |
546 | 29133e9a | bellard | |
547 | 5f9fc5ad | Blue Swirl | static CPUReadMemoryFunc * const pflash_read_ops_be[] = { |
548 | 5f9fc5ad | Blue Swirl | &pflash_readb_be, |
549 | 5f9fc5ad | Blue Swirl | &pflash_readw_be, |
550 | 5f9fc5ad | Blue Swirl | &pflash_readl_be, |
551 | 5f9fc5ad | Blue Swirl | }; |
552 | 5f9fc5ad | Blue Swirl | |
553 | 5f9fc5ad | Blue Swirl | static CPUWriteMemoryFunc * const pflash_write_ops_le[] = { |
554 | 5f9fc5ad | Blue Swirl | &pflash_writeb_le, |
555 | 5f9fc5ad | Blue Swirl | &pflash_writew_le, |
556 | 5f9fc5ad | Blue Swirl | &pflash_writel_le, |
557 | 5f9fc5ad | Blue Swirl | }; |
558 | 5f9fc5ad | Blue Swirl | |
559 | 5f9fc5ad | Blue Swirl | static CPUReadMemoryFunc * const pflash_read_ops_le[] = { |
560 | 5f9fc5ad | Blue Swirl | &pflash_readb_le, |
561 | 5f9fc5ad | Blue Swirl | &pflash_readw_le, |
562 | 5f9fc5ad | Blue Swirl | &pflash_readl_le, |
563 | 29133e9a | bellard | }; |
564 | 29133e9a | bellard | |
565 | 29133e9a | bellard | /* Count trailing zeroes of a 32 bits quantity */
|
566 | 29133e9a | bellard | static int ctz32 (uint32_t n) |
567 | 29133e9a | bellard | { |
568 | 29133e9a | bellard | int ret;
|
569 | 29133e9a | bellard | |
570 | 29133e9a | bellard | ret = 0;
|
571 | 29133e9a | bellard | if (!(n & 0xFFFF)) { |
572 | 29133e9a | bellard | ret += 16;
|
573 | 29133e9a | bellard | n = n >> 16;
|
574 | 29133e9a | bellard | } |
575 | 29133e9a | bellard | if (!(n & 0xFF)) { |
576 | 29133e9a | bellard | ret += 8;
|
577 | 29133e9a | bellard | n = n >> 8;
|
578 | 29133e9a | bellard | } |
579 | 29133e9a | bellard | if (!(n & 0xF)) { |
580 | 29133e9a | bellard | ret += 4;
|
581 | 29133e9a | bellard | n = n >> 4;
|
582 | 29133e9a | bellard | } |
583 | 29133e9a | bellard | if (!(n & 0x3)) { |
584 | 29133e9a | bellard | ret += 2;
|
585 | 29133e9a | bellard | n = n >> 2;
|
586 | 29133e9a | bellard | } |
587 | 29133e9a | bellard | if (!(n & 0x1)) { |
588 | 29133e9a | bellard | ret++; |
589 | 22ed1d34 | Blue Swirl | #if 0 /* This is not necessary as n is never 0 */
|
590 | 29133e9a | bellard | n = n >> 1;
|
591 | 22ed1d34 | Blue Swirl | #endif
|
592 | 29133e9a | bellard | } |
593 | 29133e9a | bellard | #if 0 /* This is not necessary as n is never 0 */
|
594 | 29133e9a | bellard | if (!n)
|
595 | 29133e9a | bellard | ret++;
|
596 | 29133e9a | bellard | #endif
|
597 | 29133e9a | bellard | |
598 | 29133e9a | bellard | return ret;
|
599 | 29133e9a | bellard | } |
600 | 29133e9a | bellard | |
601 | c227f099 | Anthony Liguori | pflash_t *pflash_cfi02_register(target_phys_addr_t base, ram_addr_t off, |
602 | cf6d9118 | balrog | BlockDriverState *bs, uint32_t sector_len, |
603 | 4fbd24ba | balrog | int nb_blocs, int nb_mappings, int width, |
604 | 88eeee0a | balrog | uint16_t id0, uint16_t id1, |
605 | 6725070d | balrog | uint16_t id2, uint16_t id3, |
606 | 5f9fc5ad | Blue Swirl | uint16_t unlock_addr0, uint16_t unlock_addr1, |
607 | 5f9fc5ad | Blue Swirl | int be)
|
608 | 29133e9a | bellard | { |
609 | c227f099 | Anthony Liguori | pflash_t *pfl; |
610 | 4fbd24ba | balrog | int32_t chip_len; |
611 | d0e7605e | Vijay Kumar | int ret;
|
612 | 29133e9a | bellard | |
613 | 4fbd24ba | balrog | chip_len = sector_len * nb_blocs; |
614 | 29133e9a | bellard | /* XXX: to be fixed */
|
615 | 95d1f3ed | j_mayer | #if 0
|
616 | 29133e9a | bellard | if (total_len != (8 * 1024 * 1024) && total_len != (16 * 1024 * 1024) &&
|
617 | 29133e9a | bellard | total_len != (32 * 1024 * 1024) && total_len != (64 * 1024 * 1024))
|
618 | 29133e9a | bellard | return NULL;
|
619 | 95d1f3ed | j_mayer | #endif
|
620 | c227f099 | Anthony Liguori | pfl = qemu_mallocz(sizeof(pflash_t));
|
621 | 5c130f65 | pbrook | /* FIXME: Allocate ram ourselves. */
|
622 | 5c130f65 | pbrook | pfl->storage = qemu_get_ram_ptr(off); |
623 | 5f9fc5ad | Blue Swirl | if (be) {
|
624 | 5f9fc5ad | Blue Swirl | pfl->fl_mem = cpu_register_io_memory(pflash_read_ops_be, |
625 | 5f9fc5ad | Blue Swirl | pflash_write_ops_be, |
626 | 2507c12a | Alexander Graf | pfl, DEVICE_NATIVE_ENDIAN); |
627 | 5f9fc5ad | Blue Swirl | } else {
|
628 | 5f9fc5ad | Blue Swirl | pfl->fl_mem = cpu_register_io_memory(pflash_read_ops_le, |
629 | 5f9fc5ad | Blue Swirl | pflash_write_ops_le, |
630 | 2507c12a | Alexander Graf | pfl, DEVICE_NATIVE_ENDIAN); |
631 | 5f9fc5ad | Blue Swirl | } |
632 | 29133e9a | bellard | pfl->off = off; |
633 | 4fbd24ba | balrog | pfl->base = base; |
634 | 4fbd24ba | balrog | pfl->chip_len = chip_len; |
635 | 4fbd24ba | balrog | pfl->mappings = nb_mappings; |
636 | 4fbd24ba | balrog | pflash_register_memory(pfl, 1);
|
637 | 29133e9a | bellard | pfl->bs = bs; |
638 | 29133e9a | bellard | if (pfl->bs) {
|
639 | 29133e9a | bellard | /* read the initial flash content */
|
640 | d0e7605e | Vijay Kumar | ret = bdrv_read(pfl->bs, 0, pfl->storage, chip_len >> 9); |
641 | d0e7605e | Vijay Kumar | if (ret < 0) { |
642 | d0e7605e | Vijay Kumar | cpu_unregister_io_memory(pfl->fl_mem); |
643 | d0e7605e | Vijay Kumar | qemu_free(pfl); |
644 | d0e7605e | Vijay Kumar | return NULL; |
645 | d0e7605e | Vijay Kumar | } |
646 | 29133e9a | bellard | } |
647 | 29133e9a | bellard | #if 0 /* XXX: there should be a bit to set up read-only,
|
648 | 29133e9a | bellard | * the same way the hardware does (with WP pin).
|
649 | 29133e9a | bellard | */
|
650 | 29133e9a | bellard | pfl->ro = 1;
|
651 | 29133e9a | bellard | #else
|
652 | 29133e9a | bellard | pfl->ro = 0;
|
653 | 29133e9a | bellard | #endif
|
654 | 74475455 | Paolo Bonzini | pfl->timer = qemu_new_timer_ns(vm_clock, pflash_timer, pfl); |
655 | 29133e9a | bellard | pfl->sector_len = sector_len; |
656 | 29133e9a | bellard | pfl->width = width; |
657 | 29133e9a | bellard | pfl->wcycle = 0;
|
658 | 29133e9a | bellard | pfl->cmd = 0;
|
659 | 29133e9a | bellard | pfl->status = 0;
|
660 | 29133e9a | bellard | pfl->ident[0] = id0;
|
661 | 29133e9a | bellard | pfl->ident[1] = id1;
|
662 | 29133e9a | bellard | pfl->ident[2] = id2;
|
663 | 29133e9a | bellard | pfl->ident[3] = id3;
|
664 | 6725070d | balrog | pfl->unlock_addr[0] = unlock_addr0;
|
665 | 6725070d | balrog | pfl->unlock_addr[1] = unlock_addr1;
|
666 | 29133e9a | bellard | /* Hardcoded CFI table (mostly from SG29 Spansion flash) */
|
667 | 29133e9a | bellard | pfl->cfi_len = 0x52;
|
668 | 29133e9a | bellard | /* Standard "QRY" string */
|
669 | 29133e9a | bellard | pfl->cfi_table[0x10] = 'Q'; |
670 | 29133e9a | bellard | pfl->cfi_table[0x11] = 'R'; |
671 | 29133e9a | bellard | pfl->cfi_table[0x12] = 'Y'; |
672 | 29133e9a | bellard | /* Command set (AMD/Fujitsu) */
|
673 | 29133e9a | bellard | pfl->cfi_table[0x13] = 0x02; |
674 | 29133e9a | bellard | pfl->cfi_table[0x14] = 0x00; |
675 | 78556820 | edgar_igl | /* Primary extended table address */
|
676 | 78556820 | edgar_igl | pfl->cfi_table[0x15] = 0x31; |
677 | 29133e9a | bellard | pfl->cfi_table[0x16] = 0x00; |
678 | 29133e9a | bellard | /* Alternate command set (none) */
|
679 | 29133e9a | bellard | pfl->cfi_table[0x17] = 0x00; |
680 | 29133e9a | bellard | pfl->cfi_table[0x18] = 0x00; |
681 | 29133e9a | bellard | /* Alternate extended table (none) */
|
682 | 29133e9a | bellard | pfl->cfi_table[0x19] = 0x00; |
683 | 29133e9a | bellard | pfl->cfi_table[0x1A] = 0x00; |
684 | 29133e9a | bellard | /* Vcc min */
|
685 | 29133e9a | bellard | pfl->cfi_table[0x1B] = 0x27; |
686 | 29133e9a | bellard | /* Vcc max */
|
687 | 29133e9a | bellard | pfl->cfi_table[0x1C] = 0x36; |
688 | 29133e9a | bellard | /* Vpp min (no Vpp pin) */
|
689 | 29133e9a | bellard | pfl->cfi_table[0x1D] = 0x00; |
690 | 29133e9a | bellard | /* Vpp max (no Vpp pin) */
|
691 | 29133e9a | bellard | pfl->cfi_table[0x1E] = 0x00; |
692 | 29133e9a | bellard | /* Reserved */
|
693 | 29133e9a | bellard | pfl->cfi_table[0x1F] = 0x07; |
694 | 78556820 | edgar_igl | /* Timeout for min size buffer write (NA) */
|
695 | 78556820 | edgar_igl | pfl->cfi_table[0x20] = 0x00; |
696 | 29133e9a | bellard | /* Typical timeout for block erase (512 ms) */
|
697 | 29133e9a | bellard | pfl->cfi_table[0x21] = 0x09; |
698 | 29133e9a | bellard | /* Typical timeout for full chip erase (4096 ms) */
|
699 | 29133e9a | bellard | pfl->cfi_table[0x22] = 0x0C; |
700 | 29133e9a | bellard | /* Reserved */
|
701 | 29133e9a | bellard | pfl->cfi_table[0x23] = 0x01; |
702 | 78556820 | edgar_igl | /* Max timeout for buffer write (NA) */
|
703 | 78556820 | edgar_igl | pfl->cfi_table[0x24] = 0x00; |
704 | 29133e9a | bellard | /* Max timeout for block erase */
|
705 | 29133e9a | bellard | pfl->cfi_table[0x25] = 0x0A; |
706 | 29133e9a | bellard | /* Max timeout for chip erase */
|
707 | 29133e9a | bellard | pfl->cfi_table[0x26] = 0x0D; |
708 | 29133e9a | bellard | /* Device size */
|
709 | 78556820 | edgar_igl | pfl->cfi_table[0x27] = ctz32(chip_len);
|
710 | 29133e9a | bellard | /* Flash device interface (8 & 16 bits) */
|
711 | 29133e9a | bellard | pfl->cfi_table[0x28] = 0x02; |
712 | 29133e9a | bellard | pfl->cfi_table[0x29] = 0x00; |
713 | 29133e9a | bellard | /* Max number of bytes in multi-bytes write */
|
714 | 95d1f3ed | j_mayer | /* XXX: disable buffered write as it's not supported */
|
715 | 95d1f3ed | j_mayer | // pfl->cfi_table[0x2A] = 0x05;
|
716 | 95d1f3ed | j_mayer | pfl->cfi_table[0x2A] = 0x00; |
717 | 29133e9a | bellard | pfl->cfi_table[0x2B] = 0x00; |
718 | 29133e9a | bellard | /* Number of erase block regions (uniform) */
|
719 | 29133e9a | bellard | pfl->cfi_table[0x2C] = 0x01; |
720 | 29133e9a | bellard | /* Erase block region 1 */
|
721 | 29133e9a | bellard | pfl->cfi_table[0x2D] = nb_blocs - 1; |
722 | 29133e9a | bellard | pfl->cfi_table[0x2E] = (nb_blocs - 1) >> 8; |
723 | 29133e9a | bellard | pfl->cfi_table[0x2F] = sector_len >> 8; |
724 | 29133e9a | bellard | pfl->cfi_table[0x30] = sector_len >> 16; |
725 | 29133e9a | bellard | |
726 | 78556820 | edgar_igl | /* Extended */
|
727 | 78556820 | edgar_igl | pfl->cfi_table[0x31] = 'P'; |
728 | 78556820 | edgar_igl | pfl->cfi_table[0x32] = 'R'; |
729 | 78556820 | edgar_igl | pfl->cfi_table[0x33] = 'I'; |
730 | 78556820 | edgar_igl | |
731 | 78556820 | edgar_igl | pfl->cfi_table[0x34] = '1'; |
732 | 78556820 | edgar_igl | pfl->cfi_table[0x35] = '0'; |
733 | 78556820 | edgar_igl | |
734 | 78556820 | edgar_igl | pfl->cfi_table[0x36] = 0x00; |
735 | 78556820 | edgar_igl | pfl->cfi_table[0x37] = 0x00; |
736 | 78556820 | edgar_igl | pfl->cfi_table[0x38] = 0x00; |
737 | 78556820 | edgar_igl | pfl->cfi_table[0x39] = 0x00; |
738 | 78556820 | edgar_igl | |
739 | 78556820 | edgar_igl | pfl->cfi_table[0x3a] = 0x00; |
740 | 78556820 | edgar_igl | |
741 | 78556820 | edgar_igl | pfl->cfi_table[0x3b] = 0x00; |
742 | 78556820 | edgar_igl | pfl->cfi_table[0x3c] = 0x00; |
743 | 78556820 | edgar_igl | |
744 | 29133e9a | bellard | return pfl;
|
745 | 29133e9a | bellard | } |