Revision 81635574 target-arm/kvm.c
| b/target-arm/kvm.c | ||
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| 43 | 43 |
int kvm_arch_init_vcpu(CPUState *cs) |
| 44 | 44 |
{
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struct kvm_vcpu_init init; |
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int ret; |
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uint64_t v; |
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struct kvm_one_reg r; |
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init.target = KVM_ARM_TARGET_CORTEX_A15; |
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memset(init.features, 0, sizeof(init.features)); |
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return kvm_vcpu_ioctl(cs, KVM_ARM_VCPU_INIT, &init); |
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ret = kvm_vcpu_ioctl(cs, KVM_ARM_VCPU_INIT, &init); |
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if (ret) {
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return ret; |
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} |
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/* Query the kernel to make sure it supports 32 VFP |
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* registers: QEMU's "cortex-a15" CPU is always a |
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* VFP-D32 core. The simplest way to do this is just |
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* to attempt to read register d31. |
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*/ |
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r.id = KVM_REG_ARM | KVM_REG_SIZE_U64 | KVM_REG_ARM_VFP | 31; |
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r.addr = (uintptr_t)(&v); |
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ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &r); |
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if (ret == ENOENT) {
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return EINVAL; |
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} |
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return ret; |
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} |
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typedef struct Reg {
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| ... | ... | |
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offsetof(CPUARMState, QEMUFIELD) \ |
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} |
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#define VFPSYSREG(R) \ |
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{ \
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KVM_REG_ARM | KVM_REG_SIZE_U32 | KVM_REG_ARM_VFP | \ |
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KVM_REG_ARM_VFP_##R, \ |
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offsetof(CPUARMState, vfp.xregs[ARM_VFP_##R]) \ |
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} |
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static const Reg regs[] = {
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/* R0_usr .. R14_usr */ |
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COREREG(usr_regs.uregs[0], regs[0]), |
| ... | ... | |
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CP15REG(1, 0, 0, 0, cp15.c1_sys), /* SCTLR */ |
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CP15REG(2, 0, 0, 2, cp15.c2_control), /* TTBCR */ |
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CP15REG(3, 0, 0, 0, cp15.c3), /* DACR */ |
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/* VFP system registers */ |
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VFPSYSREG(FPSID), |
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VFPSYSREG(MVFR1), |
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VFPSYSREG(MVFR0), |
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VFPSYSREG(FPEXC), |
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VFPSYSREG(FPINST), |
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VFPSYSREG(FPINST2), |
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}; |
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int kvm_arch_put_registers(CPUState *cs, int level) |
| ... | ... | |
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struct kvm_one_reg r; |
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int mode, bn; |
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int ret, i; |
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uint32_t cpsr; |
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uint32_t cpsr, fpscr;
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uint64_t ttbr; |
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/* Make sure the banked regs are properly set */ |
| ... | ... | |
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(2 << KVM_REG_ARM_CRM_SHIFT) | (1 << KVM_REG_ARM_OPC1_SHIFT); |
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r.addr = (uintptr_t)(&ttbr); |
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ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &r); |
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if (ret) {
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return ret; |
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} |
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|
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/* VFP registers */ |
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r.id = KVM_REG_ARM | KVM_REG_SIZE_U64 | KVM_REG_ARM_VFP; |
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for (i = 0; i < 32; i++) {
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r.addr = (uintptr_t)(&env->vfp.regs[i]); |
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ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &r); |
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if (ret) {
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return ret; |
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} |
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r.id++; |
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} |
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r.id = KVM_REG_ARM | KVM_REG_SIZE_U32 | KVM_REG_ARM_VFP | |
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KVM_REG_ARM_VFP_FPSCR; |
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fpscr = vfp_get_fpscr(env); |
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r.addr = (uintptr_t)&fpscr; |
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ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &r); |
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return ret; |
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} |
| ... | ... | |
| 190 | 242 |
struct kvm_one_reg r; |
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int mode, bn; |
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int ret, i; |
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uint32_t cpsr; |
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uint32_t cpsr, fpscr;
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uint64_t ttbr; |
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for (i = 0; i < ARRAY_SIZE(regs); i++) {
|
| ... | ... | |
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env->cp15.c2_mask = ~(0xffffffffu >> env->cp15.c2_control); |
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env->cp15.c2_base_mask = ~(0x3fffu >> env->cp15.c2_control); |
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/* VFP registers */ |
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r.id = KVM_REG_ARM | KVM_REG_SIZE_U64 | KVM_REG_ARM_VFP; |
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for (i = 0; i < 32; i++) {
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r.addr = (uintptr_t)(&env->vfp.regs[i]); |
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ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &r); |
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if (ret) {
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return ret; |
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} |
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r.id++; |
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} |
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r.id = KVM_REG_ARM | KVM_REG_SIZE_U32 | KVM_REG_ARM_VFP | |
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KVM_REG_ARM_VFP_FPSCR; |
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r.addr = (uintptr_t)&fpscr; |
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ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &r); |
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if (ret) {
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return ret; |
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} |
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vfp_set_fpscr(env, fpscr); |
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return 0; |
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} |
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