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1 | 4c9649a9 | j_mayer | /*
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2 | 4c9649a9 | j_mayer | * Alpha emulation cpu translation for qemu.
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3 | 5fafdf24 | ths | *
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4 | 4c9649a9 | j_mayer | * Copyright (c) 2007 Jocelyn Mayer
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5 | 4c9649a9 | j_mayer | *
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6 | 4c9649a9 | j_mayer | * This library is free software; you can redistribute it and/or
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7 | 4c9649a9 | j_mayer | * modify it under the terms of the GNU Lesser General Public
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8 | 4c9649a9 | j_mayer | * License as published by the Free Software Foundation; either
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9 | 4c9649a9 | j_mayer | * version 2 of the License, or (at your option) any later version.
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10 | 4c9649a9 | j_mayer | *
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11 | 4c9649a9 | j_mayer | * This library is distributed in the hope that it will be useful,
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12 | 4c9649a9 | j_mayer | * but WITHOUT ANY WARRANTY; without even the implied warranty of
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13 | 4c9649a9 | j_mayer | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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14 | 4c9649a9 | j_mayer | * Lesser General Public License for more details.
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15 | 4c9649a9 | j_mayer | *
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16 | 4c9649a9 | j_mayer | * You should have received a copy of the GNU Lesser General Public
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17 | 8167ee88 | Blue Swirl | * License along with this library; if not, see <http://www.gnu.org/licenses/>.
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18 | 4c9649a9 | j_mayer | */
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19 | 4c9649a9 | j_mayer | |
20 | 4c9649a9 | j_mayer | #include <stdint.h> |
21 | 4c9649a9 | j_mayer | #include <stdlib.h> |
22 | 4c9649a9 | j_mayer | #include <stdio.h> |
23 | 4c9649a9 | j_mayer | |
24 | 4c9649a9 | j_mayer | #include "cpu.h" |
25 | 4c9649a9 | j_mayer | #include "exec-all.h" |
26 | 4c9649a9 | j_mayer | #include "disas.h" |
27 | ae8ecd42 | aurel32 | #include "host-utils.h" |
28 | 57fec1fe | bellard | #include "tcg-op.h" |
29 | ca10f867 | aurel32 | #include "qemu-common.h" |
30 | 4c9649a9 | j_mayer | |
31 | a7812ae4 | pbrook | #include "helper.h" |
32 | a7812ae4 | pbrook | #define GEN_HELPER 1 |
33 | a7812ae4 | pbrook | #include "helper.h" |
34 | a7812ae4 | pbrook | |
35 | 55489a17 | aurel32 | /* #define DO_SINGLE_STEP */
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36 | 4c9649a9 | j_mayer | #define ALPHA_DEBUG_DISAS
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37 | 55489a17 | aurel32 | /* #define DO_TB_FLUSH */
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38 | 4c9649a9 | j_mayer | |
39 | d12d51d5 | aliguori | |
40 | d12d51d5 | aliguori | #ifdef ALPHA_DEBUG_DISAS
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41 | 93fcfe39 | aliguori | # define LOG_DISAS(...) qemu_log(__VA_ARGS__)
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42 | d12d51d5 | aliguori | #else
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43 | d12d51d5 | aliguori | # define LOG_DISAS(...) do { } while (0) |
44 | d12d51d5 | aliguori | #endif
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45 | d12d51d5 | aliguori | |
46 | 4c9649a9 | j_mayer | typedef struct DisasContext DisasContext; |
47 | 4c9649a9 | j_mayer | struct DisasContext {
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48 | 4c9649a9 | j_mayer | uint64_t pc; |
49 | 4c9649a9 | j_mayer | int mem_idx;
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50 | 4c9649a9 | j_mayer | #if !defined (CONFIG_USER_ONLY)
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51 | 4c9649a9 | j_mayer | int pal_mode;
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52 | 4c9649a9 | j_mayer | #endif
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53 | 8579095b | aurel32 | CPUAlphaState *env; |
54 | 4c9649a9 | j_mayer | uint32_t amask; |
55 | 4c9649a9 | j_mayer | }; |
56 | 4c9649a9 | j_mayer | |
57 | 3761035f | aurel32 | /* global register indexes */
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58 | a7812ae4 | pbrook | static TCGv_ptr cpu_env;
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59 | 496cb5b9 | aurel32 | static TCGv cpu_ir[31]; |
60 | f18cd223 | aurel32 | static TCGv cpu_fir[31]; |
61 | 496cb5b9 | aurel32 | static TCGv cpu_pc;
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62 | f4ed8679 | aurel32 | static TCGv cpu_lock;
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63 | 496cb5b9 | aurel32 | |
64 | 3761035f | aurel32 | /* register names */
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65 | f18cd223 | aurel32 | static char cpu_reg_names[10*4+21*5 + 10*5+21*6]; |
66 | 2e70f6ef | pbrook | |
67 | 2e70f6ef | pbrook | #include "gen-icount.h" |
68 | 2e70f6ef | pbrook | |
69 | a5f1b965 | blueswir1 | static void alpha_translate_init(void) |
70 | 2e70f6ef | pbrook | { |
71 | 496cb5b9 | aurel32 | int i;
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72 | 496cb5b9 | aurel32 | char *p;
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73 | 2e70f6ef | pbrook | static int done_init = 0; |
74 | 496cb5b9 | aurel32 | |
75 | 2e70f6ef | pbrook | if (done_init)
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76 | 2e70f6ef | pbrook | return;
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77 | 496cb5b9 | aurel32 | |
78 | a7812ae4 | pbrook | cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
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79 | 496cb5b9 | aurel32 | |
80 | 496cb5b9 | aurel32 | p = cpu_reg_names; |
81 | 496cb5b9 | aurel32 | for (i = 0; i < 31; i++) { |
82 | 496cb5b9 | aurel32 | sprintf(p, "ir%d", i);
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83 | a7812ae4 | pbrook | cpu_ir[i] = tcg_global_mem_new_i64(TCG_AREG0, |
84 | a7812ae4 | pbrook | offsetof(CPUState, ir[i]), p); |
85 | 6ba8dcd7 | aurel32 | p += (i < 10) ? 4 : 5; |
86 | f18cd223 | aurel32 | |
87 | f18cd223 | aurel32 | sprintf(p, "fir%d", i);
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88 | a7812ae4 | pbrook | cpu_fir[i] = tcg_global_mem_new_i64(TCG_AREG0, |
89 | a7812ae4 | pbrook | offsetof(CPUState, fir[i]), p); |
90 | f18cd223 | aurel32 | p += (i < 10) ? 5 : 6; |
91 | 496cb5b9 | aurel32 | } |
92 | 496cb5b9 | aurel32 | |
93 | a7812ae4 | pbrook | cpu_pc = tcg_global_mem_new_i64(TCG_AREG0, |
94 | a7812ae4 | pbrook | offsetof(CPUState, pc), "pc");
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95 | 496cb5b9 | aurel32 | |
96 | a7812ae4 | pbrook | cpu_lock = tcg_global_mem_new_i64(TCG_AREG0, |
97 | a7812ae4 | pbrook | offsetof(CPUState, lock), "lock");
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98 | f4ed8679 | aurel32 | |
99 | 496cb5b9 | aurel32 | /* register helpers */
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100 | a7812ae4 | pbrook | #define GEN_HELPER 2 |
101 | 496cb5b9 | aurel32 | #include "helper.h" |
102 | 496cb5b9 | aurel32 | |
103 | 2e70f6ef | pbrook | done_init = 1;
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104 | 2e70f6ef | pbrook | } |
105 | 2e70f6ef | pbrook | |
106 | f071b4d3 | j_mayer | static always_inline void gen_excp (DisasContext *ctx, |
107 | f071b4d3 | j_mayer | int exception, int error_code) |
108 | 4c9649a9 | j_mayer | { |
109 | a7812ae4 | pbrook | TCGv_i32 tmp1, tmp2; |
110 | 6ad02592 | aurel32 | |
111 | 496cb5b9 | aurel32 | tcg_gen_movi_i64(cpu_pc, ctx->pc); |
112 | 6ad02592 | aurel32 | tmp1 = tcg_const_i32(exception); |
113 | 6ad02592 | aurel32 | tmp2 = tcg_const_i32(error_code); |
114 | a7812ae4 | pbrook | gen_helper_excp(tmp1, tmp2); |
115 | a7812ae4 | pbrook | tcg_temp_free_i32(tmp2); |
116 | a7812ae4 | pbrook | tcg_temp_free_i32(tmp1); |
117 | 4c9649a9 | j_mayer | } |
118 | 4c9649a9 | j_mayer | |
119 | f071b4d3 | j_mayer | static always_inline void gen_invalid (DisasContext *ctx) |
120 | 4c9649a9 | j_mayer | { |
121 | 4c9649a9 | j_mayer | gen_excp(ctx, EXCP_OPCDEC, 0);
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122 | 4c9649a9 | j_mayer | } |
123 | 4c9649a9 | j_mayer | |
124 | f18cd223 | aurel32 | static always_inline void gen_qemu_ldf (TCGv t0, TCGv t1, int flags) |
125 | f18cd223 | aurel32 | { |
126 | a7812ae4 | pbrook | TCGv tmp = tcg_temp_new(); |
127 | a7812ae4 | pbrook | TCGv_i32 tmp32 = tcg_temp_new_i32(); |
128 | f18cd223 | aurel32 | tcg_gen_qemu_ld32u(tmp, t1, flags); |
129 | a7812ae4 | pbrook | tcg_gen_trunc_i64_i32(tmp32, tmp); |
130 | a7812ae4 | pbrook | gen_helper_memory_to_f(t0, tmp32); |
131 | a7812ae4 | pbrook | tcg_temp_free_i32(tmp32); |
132 | f18cd223 | aurel32 | tcg_temp_free(tmp); |
133 | f18cd223 | aurel32 | } |
134 | f18cd223 | aurel32 | |
135 | f18cd223 | aurel32 | static always_inline void gen_qemu_ldg (TCGv t0, TCGv t1, int flags) |
136 | f18cd223 | aurel32 | { |
137 | a7812ae4 | pbrook | TCGv tmp = tcg_temp_new(); |
138 | f18cd223 | aurel32 | tcg_gen_qemu_ld64(tmp, t1, flags); |
139 | a7812ae4 | pbrook | gen_helper_memory_to_g(t0, tmp); |
140 | f18cd223 | aurel32 | tcg_temp_free(tmp); |
141 | f18cd223 | aurel32 | } |
142 | f18cd223 | aurel32 | |
143 | f18cd223 | aurel32 | static always_inline void gen_qemu_lds (TCGv t0, TCGv t1, int flags) |
144 | f18cd223 | aurel32 | { |
145 | a7812ae4 | pbrook | TCGv tmp = tcg_temp_new(); |
146 | a7812ae4 | pbrook | TCGv_i32 tmp32 = tcg_temp_new_i32(); |
147 | f18cd223 | aurel32 | tcg_gen_qemu_ld32u(tmp, t1, flags); |
148 | a7812ae4 | pbrook | tcg_gen_trunc_i64_i32(tmp32, tmp); |
149 | a7812ae4 | pbrook | gen_helper_memory_to_s(t0, tmp32); |
150 | a7812ae4 | pbrook | tcg_temp_free_i32(tmp32); |
151 | f18cd223 | aurel32 | tcg_temp_free(tmp); |
152 | f18cd223 | aurel32 | } |
153 | f18cd223 | aurel32 | |
154 | f4ed8679 | aurel32 | static always_inline void gen_qemu_ldl_l (TCGv t0, TCGv t1, int flags) |
155 | f4ed8679 | aurel32 | { |
156 | f4ed8679 | aurel32 | tcg_gen_mov_i64(cpu_lock, t1); |
157 | f4ed8679 | aurel32 | tcg_gen_qemu_ld32s(t0, t1, flags); |
158 | f4ed8679 | aurel32 | } |
159 | f4ed8679 | aurel32 | |
160 | f4ed8679 | aurel32 | static always_inline void gen_qemu_ldq_l (TCGv t0, TCGv t1, int flags) |
161 | f4ed8679 | aurel32 | { |
162 | f4ed8679 | aurel32 | tcg_gen_mov_i64(cpu_lock, t1); |
163 | f4ed8679 | aurel32 | tcg_gen_qemu_ld64(t0, t1, flags); |
164 | f4ed8679 | aurel32 | } |
165 | f4ed8679 | aurel32 | |
166 | 023d8ca2 | aurel32 | static always_inline void gen_load_mem (DisasContext *ctx, |
167 | 023d8ca2 | aurel32 | void (*tcg_gen_qemu_load)(TCGv t0, TCGv t1, int flags), |
168 | 023d8ca2 | aurel32 | int ra, int rb, int32_t disp16, |
169 | f18cd223 | aurel32 | int fp, int clear) |
170 | 023d8ca2 | aurel32 | { |
171 | 023d8ca2 | aurel32 | TCGv addr; |
172 | 023d8ca2 | aurel32 | |
173 | 023d8ca2 | aurel32 | if (unlikely(ra == 31)) |
174 | 023d8ca2 | aurel32 | return;
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175 | 023d8ca2 | aurel32 | |
176 | a7812ae4 | pbrook | addr = tcg_temp_new(); |
177 | 023d8ca2 | aurel32 | if (rb != 31) { |
178 | 023d8ca2 | aurel32 | tcg_gen_addi_i64(addr, cpu_ir[rb], disp16); |
179 | 023d8ca2 | aurel32 | if (clear)
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180 | 023d8ca2 | aurel32 | tcg_gen_andi_i64(addr, addr, ~0x7);
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181 | 023d8ca2 | aurel32 | } else {
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182 | 023d8ca2 | aurel32 | if (clear)
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183 | 023d8ca2 | aurel32 | disp16 &= ~0x7;
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184 | 023d8ca2 | aurel32 | tcg_gen_movi_i64(addr, disp16); |
185 | 023d8ca2 | aurel32 | } |
186 | f18cd223 | aurel32 | if (fp)
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187 | f18cd223 | aurel32 | tcg_gen_qemu_load(cpu_fir[ra], addr, ctx->mem_idx); |
188 | f18cd223 | aurel32 | else
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189 | f18cd223 | aurel32 | tcg_gen_qemu_load(cpu_ir[ra], addr, ctx->mem_idx); |
190 | 023d8ca2 | aurel32 | tcg_temp_free(addr); |
191 | 023d8ca2 | aurel32 | } |
192 | 023d8ca2 | aurel32 | |
193 | f18cd223 | aurel32 | static always_inline void gen_qemu_stf (TCGv t0, TCGv t1, int flags) |
194 | f18cd223 | aurel32 | { |
195 | a7812ae4 | pbrook | TCGv_i32 tmp32 = tcg_temp_new_i32(); |
196 | a7812ae4 | pbrook | TCGv tmp = tcg_temp_new(); |
197 | a7812ae4 | pbrook | gen_helper_f_to_memory(tmp32, t0); |
198 | a7812ae4 | pbrook | tcg_gen_extu_i32_i64(tmp, tmp32); |
199 | f18cd223 | aurel32 | tcg_gen_qemu_st32(tmp, t1, flags); |
200 | f18cd223 | aurel32 | tcg_temp_free(tmp); |
201 | a7812ae4 | pbrook | tcg_temp_free_i32(tmp32); |
202 | f18cd223 | aurel32 | } |
203 | f18cd223 | aurel32 | |
204 | f18cd223 | aurel32 | static always_inline void gen_qemu_stg (TCGv t0, TCGv t1, int flags) |
205 | f18cd223 | aurel32 | { |
206 | a7812ae4 | pbrook | TCGv tmp = tcg_temp_new(); |
207 | a7812ae4 | pbrook | gen_helper_g_to_memory(tmp, t0); |
208 | f18cd223 | aurel32 | tcg_gen_qemu_st64(tmp, t1, flags); |
209 | f18cd223 | aurel32 | tcg_temp_free(tmp); |
210 | f18cd223 | aurel32 | } |
211 | f18cd223 | aurel32 | |
212 | f18cd223 | aurel32 | static always_inline void gen_qemu_sts (TCGv t0, TCGv t1, int flags) |
213 | f18cd223 | aurel32 | { |
214 | a7812ae4 | pbrook | TCGv_i32 tmp32 = tcg_temp_new_i32(); |
215 | a7812ae4 | pbrook | TCGv tmp = tcg_temp_new(); |
216 | a7812ae4 | pbrook | gen_helper_s_to_memory(tmp32, t0); |
217 | a7812ae4 | pbrook | tcg_gen_extu_i32_i64(tmp, tmp32); |
218 | f18cd223 | aurel32 | tcg_gen_qemu_st32(tmp, t1, flags); |
219 | f18cd223 | aurel32 | tcg_temp_free(tmp); |
220 | a7812ae4 | pbrook | tcg_temp_free_i32(tmp32); |
221 | f18cd223 | aurel32 | } |
222 | f18cd223 | aurel32 | |
223 | f4ed8679 | aurel32 | static always_inline void gen_qemu_stl_c (TCGv t0, TCGv t1, int flags) |
224 | f4ed8679 | aurel32 | { |
225 | f4ed8679 | aurel32 | int l1, l2;
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226 | f4ed8679 | aurel32 | |
227 | f4ed8679 | aurel32 | l1 = gen_new_label(); |
228 | f4ed8679 | aurel32 | l2 = gen_new_label(); |
229 | f4ed8679 | aurel32 | tcg_gen_brcond_i64(TCG_COND_NE, cpu_lock, t1, l1); |
230 | f4ed8679 | aurel32 | tcg_gen_qemu_st32(t0, t1, flags); |
231 | 6223246a | aurel32 | tcg_gen_movi_i64(t0, 1);
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232 | f4ed8679 | aurel32 | tcg_gen_br(l2); |
233 | f4ed8679 | aurel32 | gen_set_label(l1); |
234 | 6223246a | aurel32 | tcg_gen_movi_i64(t0, 0);
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235 | f4ed8679 | aurel32 | gen_set_label(l2); |
236 | f4ed8679 | aurel32 | tcg_gen_movi_i64(cpu_lock, -1);
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237 | f4ed8679 | aurel32 | } |
238 | f4ed8679 | aurel32 | |
239 | f4ed8679 | aurel32 | static always_inline void gen_qemu_stq_c (TCGv t0, TCGv t1, int flags) |
240 | f4ed8679 | aurel32 | { |
241 | f4ed8679 | aurel32 | int l1, l2;
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242 | f4ed8679 | aurel32 | |
243 | f4ed8679 | aurel32 | l1 = gen_new_label(); |
244 | f4ed8679 | aurel32 | l2 = gen_new_label(); |
245 | f4ed8679 | aurel32 | tcg_gen_brcond_i64(TCG_COND_NE, cpu_lock, t1, l1); |
246 | f4ed8679 | aurel32 | tcg_gen_qemu_st64(t0, t1, flags); |
247 | 6223246a | aurel32 | tcg_gen_movi_i64(t0, 1);
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248 | f4ed8679 | aurel32 | tcg_gen_br(l2); |
249 | f4ed8679 | aurel32 | gen_set_label(l1); |
250 | 6223246a | aurel32 | tcg_gen_movi_i64(t0, 0);
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251 | f4ed8679 | aurel32 | gen_set_label(l2); |
252 | f4ed8679 | aurel32 | tcg_gen_movi_i64(cpu_lock, -1);
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253 | f4ed8679 | aurel32 | } |
254 | f4ed8679 | aurel32 | |
255 | 023d8ca2 | aurel32 | static always_inline void gen_store_mem (DisasContext *ctx, |
256 | 023d8ca2 | aurel32 | void (*tcg_gen_qemu_store)(TCGv t0, TCGv t1, int flags), |
257 | 023d8ca2 | aurel32 | int ra, int rb, int32_t disp16, |
258 | 57a92c8e | aurel32 | int fp, int clear, int local) |
259 | 023d8ca2 | aurel32 | { |
260 | 9cd38c23 | aurel32 | TCGv addr; |
261 | 57a92c8e | aurel32 | if (local)
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262 | a7812ae4 | pbrook | addr = tcg_temp_local_new(); |
263 | 57a92c8e | aurel32 | else
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264 | a7812ae4 | pbrook | addr = tcg_temp_new(); |
265 | 023d8ca2 | aurel32 | if (rb != 31) { |
266 | 023d8ca2 | aurel32 | tcg_gen_addi_i64(addr, cpu_ir[rb], disp16); |
267 | 023d8ca2 | aurel32 | if (clear)
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268 | 023d8ca2 | aurel32 | tcg_gen_andi_i64(addr, addr, ~0x7);
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269 | 023d8ca2 | aurel32 | } else {
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270 | 023d8ca2 | aurel32 | if (clear)
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271 | 023d8ca2 | aurel32 | disp16 &= ~0x7;
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272 | 023d8ca2 | aurel32 | tcg_gen_movi_i64(addr, disp16); |
273 | 023d8ca2 | aurel32 | } |
274 | f18cd223 | aurel32 | if (ra != 31) { |
275 | f18cd223 | aurel32 | if (fp)
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276 | f18cd223 | aurel32 | tcg_gen_qemu_store(cpu_fir[ra], addr, ctx->mem_idx); |
277 | f18cd223 | aurel32 | else
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278 | f18cd223 | aurel32 | tcg_gen_qemu_store(cpu_ir[ra], addr, ctx->mem_idx); |
279 | f18cd223 | aurel32 | } else {
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280 | 57a92c8e | aurel32 | TCGv zero; |
281 | 57a92c8e | aurel32 | if (local)
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282 | 57a92c8e | aurel32 | zero = tcg_const_local_i64(0);
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283 | 57a92c8e | aurel32 | else
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284 | 57a92c8e | aurel32 | zero = tcg_const_i64(0);
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285 | 023d8ca2 | aurel32 | tcg_gen_qemu_store(zero, addr, ctx->mem_idx); |
286 | 023d8ca2 | aurel32 | tcg_temp_free(zero); |
287 | 023d8ca2 | aurel32 | } |
288 | 023d8ca2 | aurel32 | tcg_temp_free(addr); |
289 | 023d8ca2 | aurel32 | } |
290 | 023d8ca2 | aurel32 | |
291 | f071b4d3 | j_mayer | static always_inline void gen_bcond (DisasContext *ctx, |
292 | 9c29504e | aurel32 | TCGCond cond, |
293 | a1516744 | aurel32 | int ra, int32_t disp, int mask) |
294 | 4c9649a9 | j_mayer | { |
295 | 9c29504e | aurel32 | int l1, l2;
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296 | 9c29504e | aurel32 | |
297 | 9c29504e | aurel32 | l1 = gen_new_label(); |
298 | 9c29504e | aurel32 | l2 = gen_new_label(); |
299 | 9c29504e | aurel32 | if (likely(ra != 31)) { |
300 | 9c29504e | aurel32 | if (mask) {
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301 | a7812ae4 | pbrook | TCGv tmp = tcg_temp_new(); |
302 | 9c29504e | aurel32 | tcg_gen_andi_i64(tmp, cpu_ir[ra], 1);
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303 | 9c29504e | aurel32 | tcg_gen_brcondi_i64(cond, tmp, 0, l1);
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304 | 9c29504e | aurel32 | tcg_temp_free(tmp); |
305 | 9c29504e | aurel32 | } else
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306 | 9c29504e | aurel32 | tcg_gen_brcondi_i64(cond, cpu_ir[ra], 0, l1);
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307 | 9c29504e | aurel32 | } else {
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308 | 9c29504e | aurel32 | /* Very uncommon case - Do not bother to optimize. */
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309 | 9c29504e | aurel32 | TCGv tmp = tcg_const_i64(0);
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310 | 9c29504e | aurel32 | tcg_gen_brcondi_i64(cond, tmp, 0, l1);
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311 | 9c29504e | aurel32 | tcg_temp_free(tmp); |
312 | 9c29504e | aurel32 | } |
313 | 9c29504e | aurel32 | tcg_gen_movi_i64(cpu_pc, ctx->pc); |
314 | 9c29504e | aurel32 | tcg_gen_br(l2); |
315 | 9c29504e | aurel32 | gen_set_label(l1); |
316 | a1516744 | aurel32 | tcg_gen_movi_i64(cpu_pc, ctx->pc + (int64_t)(disp << 2));
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317 | 9c29504e | aurel32 | gen_set_label(l2); |
318 | 4c9649a9 | j_mayer | } |
319 | 4c9649a9 | j_mayer | |
320 | a7812ae4 | pbrook | static always_inline void gen_fbcond (DisasContext *ctx, int opc, |
321 | f071b4d3 | j_mayer | int ra, int32_t disp16)
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322 | 4c9649a9 | j_mayer | { |
323 | f18cd223 | aurel32 | int l1, l2;
|
324 | f18cd223 | aurel32 | TCGv tmp; |
325 | a7812ae4 | pbrook | TCGv src; |
326 | f18cd223 | aurel32 | |
327 | f18cd223 | aurel32 | l1 = gen_new_label(); |
328 | f18cd223 | aurel32 | l2 = gen_new_label(); |
329 | f18cd223 | aurel32 | if (ra != 31) { |
330 | a7812ae4 | pbrook | tmp = tcg_temp_new(); |
331 | a7812ae4 | pbrook | src = cpu_fir[ra]; |
332 | f18cd223 | aurel32 | } else {
|
333 | f18cd223 | aurel32 | tmp = tcg_const_i64(0);
|
334 | a7812ae4 | pbrook | src = tmp; |
335 | a7812ae4 | pbrook | } |
336 | a7812ae4 | pbrook | switch (opc) {
|
337 | a7812ae4 | pbrook | case 0x31: /* FBEQ */ |
338 | a7812ae4 | pbrook | gen_helper_cmpfeq(tmp, src); |
339 | a7812ae4 | pbrook | break;
|
340 | a7812ae4 | pbrook | case 0x32: /* FBLT */ |
341 | a7812ae4 | pbrook | gen_helper_cmpflt(tmp, src); |
342 | a7812ae4 | pbrook | break;
|
343 | a7812ae4 | pbrook | case 0x33: /* FBLE */ |
344 | a7812ae4 | pbrook | gen_helper_cmpfle(tmp, src); |
345 | a7812ae4 | pbrook | break;
|
346 | a7812ae4 | pbrook | case 0x35: /* FBNE */ |
347 | a7812ae4 | pbrook | gen_helper_cmpfne(tmp, src); |
348 | a7812ae4 | pbrook | break;
|
349 | a7812ae4 | pbrook | case 0x36: /* FBGE */ |
350 | a7812ae4 | pbrook | gen_helper_cmpfge(tmp, src); |
351 | a7812ae4 | pbrook | break;
|
352 | a7812ae4 | pbrook | case 0x37: /* FBGT */ |
353 | a7812ae4 | pbrook | gen_helper_cmpfgt(tmp, src); |
354 | a7812ae4 | pbrook | break;
|
355 | a7812ae4 | pbrook | default:
|
356 | a7812ae4 | pbrook | abort(); |
357 | f18cd223 | aurel32 | } |
358 | f18cd223 | aurel32 | tcg_gen_brcondi_i64(TCG_COND_NE, tmp, 0, l1);
|
359 | f18cd223 | aurel32 | tcg_gen_movi_i64(cpu_pc, ctx->pc); |
360 | f18cd223 | aurel32 | tcg_gen_br(l2); |
361 | f18cd223 | aurel32 | gen_set_label(l1); |
362 | f18cd223 | aurel32 | tcg_gen_movi_i64(cpu_pc, ctx->pc + (int64_t)(disp16 << 2));
|
363 | f18cd223 | aurel32 | gen_set_label(l2); |
364 | 4c9649a9 | j_mayer | } |
365 | 4c9649a9 | j_mayer | |
366 | fe2b269a | aurel32 | static always_inline void gen_cmov (TCGCond inv_cond, |
367 | f071b4d3 | j_mayer | int ra, int rb, int rc, |
368 | adf3c8b6 | aurel32 | int islit, uint8_t lit, int mask) |
369 | 4c9649a9 | j_mayer | { |
370 | 9c29504e | aurel32 | int l1;
|
371 | 9c29504e | aurel32 | |
372 | 9c29504e | aurel32 | if (unlikely(rc == 31)) |
373 | 9c29504e | aurel32 | return;
|
374 | 9c29504e | aurel32 | |
375 | 9c29504e | aurel32 | l1 = gen_new_label(); |
376 | 9c29504e | aurel32 | |
377 | 9c29504e | aurel32 | if (ra != 31) { |
378 | 9c29504e | aurel32 | if (mask) {
|
379 | a7812ae4 | pbrook | TCGv tmp = tcg_temp_new(); |
380 | 9c29504e | aurel32 | tcg_gen_andi_i64(tmp, cpu_ir[ra], 1);
|
381 | 9c29504e | aurel32 | tcg_gen_brcondi_i64(inv_cond, tmp, 0, l1);
|
382 | 9c29504e | aurel32 | tcg_temp_free(tmp); |
383 | 9c29504e | aurel32 | } else
|
384 | 9c29504e | aurel32 | tcg_gen_brcondi_i64(inv_cond, cpu_ir[ra], 0, l1);
|
385 | 9c29504e | aurel32 | } else {
|
386 | 9c29504e | aurel32 | /* Very uncommon case - Do not bother to optimize. */
|
387 | 9c29504e | aurel32 | TCGv tmp = tcg_const_i64(0);
|
388 | 9c29504e | aurel32 | tcg_gen_brcondi_i64(inv_cond, tmp, 0, l1);
|
389 | 9c29504e | aurel32 | tcg_temp_free(tmp); |
390 | 9c29504e | aurel32 | } |
391 | 9c29504e | aurel32 | |
392 | 4c9649a9 | j_mayer | if (islit)
|
393 | 9c29504e | aurel32 | tcg_gen_movi_i64(cpu_ir[rc], lit); |
394 | 4c9649a9 | j_mayer | else
|
395 | dfaa8583 | aurel32 | tcg_gen_mov_i64(cpu_ir[rc], cpu_ir[rb]); |
396 | 9c29504e | aurel32 | gen_set_label(l1); |
397 | 4c9649a9 | j_mayer | } |
398 | 4c9649a9 | j_mayer | |
399 | a7812ae4 | pbrook | #define FARITH2(name) \
|
400 | a7812ae4 | pbrook | static always_inline void glue(gen_f, name)(int rb, int rc) \ |
401 | a7812ae4 | pbrook | { \ |
402 | a7812ae4 | pbrook | if (unlikely(rc == 31)) \ |
403 | a7812ae4 | pbrook | return; \
|
404 | a7812ae4 | pbrook | \ |
405 | a7812ae4 | pbrook | if (rb != 31) \ |
406 | a7812ae4 | pbrook | gen_helper_ ## name (cpu_fir[rc], cpu_fir[rb]); \ |
407 | a7812ae4 | pbrook | else { \
|
408 | a7812ae4 | pbrook | TCGv tmp = tcg_const_i64(0); \
|
409 | a7812ae4 | pbrook | gen_helper_ ## name (cpu_fir[rc], tmp); \ |
410 | a7812ae4 | pbrook | tcg_temp_free(tmp); \ |
411 | a7812ae4 | pbrook | } \ |
412 | 4c9649a9 | j_mayer | } |
413 | a7812ae4 | pbrook | FARITH2(sqrts) |
414 | a7812ae4 | pbrook | FARITH2(sqrtf) |
415 | a7812ae4 | pbrook | FARITH2(sqrtg) |
416 | a7812ae4 | pbrook | FARITH2(sqrtt) |
417 | a7812ae4 | pbrook | FARITH2(cvtgf) |
418 | a7812ae4 | pbrook | FARITH2(cvtgq) |
419 | a7812ae4 | pbrook | FARITH2(cvtqf) |
420 | a7812ae4 | pbrook | FARITH2(cvtqg) |
421 | a7812ae4 | pbrook | FARITH2(cvtst) |
422 | a7812ae4 | pbrook | FARITH2(cvtts) |
423 | a7812ae4 | pbrook | FARITH2(cvttq) |
424 | a7812ae4 | pbrook | FARITH2(cvtqs) |
425 | a7812ae4 | pbrook | FARITH2(cvtqt) |
426 | a7812ae4 | pbrook | FARITH2(cvtlq) |
427 | a7812ae4 | pbrook | FARITH2(cvtql) |
428 | a7812ae4 | pbrook | FARITH2(cvtqlv) |
429 | a7812ae4 | pbrook | FARITH2(cvtqlsv) |
430 | a7812ae4 | pbrook | |
431 | a7812ae4 | pbrook | #define FARITH3(name) \
|
432 | a7812ae4 | pbrook | static always_inline void glue(gen_f, name) (int ra, int rb, int rc) \ |
433 | a7812ae4 | pbrook | { \ |
434 | a7812ae4 | pbrook | if (unlikely(rc == 31)) \ |
435 | a7812ae4 | pbrook | return; \
|
436 | a7812ae4 | pbrook | \ |
437 | a7812ae4 | pbrook | if (ra != 31) { \ |
438 | a7812ae4 | pbrook | if (rb != 31) \ |
439 | a7812ae4 | pbrook | gen_helper_ ## name (cpu_fir[rc], cpu_fir[ra], cpu_fir[rb]); \ |
440 | a7812ae4 | pbrook | else { \
|
441 | a7812ae4 | pbrook | TCGv tmp = tcg_const_i64(0); \
|
442 | a7812ae4 | pbrook | gen_helper_ ## name (cpu_fir[rc], cpu_fir[ra], tmp); \ |
443 | a7812ae4 | pbrook | tcg_temp_free(tmp); \ |
444 | a7812ae4 | pbrook | } \ |
445 | a7812ae4 | pbrook | } else { \
|
446 | a7812ae4 | pbrook | TCGv tmp = tcg_const_i64(0); \
|
447 | a7812ae4 | pbrook | if (rb != 31) \ |
448 | a7812ae4 | pbrook | gen_helper_ ## name (cpu_fir[rc], tmp, cpu_fir[rb]); \ |
449 | a7812ae4 | pbrook | else \
|
450 | a7812ae4 | pbrook | gen_helper_ ## name (cpu_fir[rc], tmp, tmp); \ |
451 | a7812ae4 | pbrook | tcg_temp_free(tmp); \ |
452 | a7812ae4 | pbrook | } \ |
453 | 4c9649a9 | j_mayer | } |
454 | 4c9649a9 | j_mayer | |
455 | a7812ae4 | pbrook | FARITH3(addf) |
456 | a7812ae4 | pbrook | FARITH3(subf) |
457 | a7812ae4 | pbrook | FARITH3(mulf) |
458 | a7812ae4 | pbrook | FARITH3(divf) |
459 | a7812ae4 | pbrook | FARITH3(addg) |
460 | a7812ae4 | pbrook | FARITH3(subg) |
461 | a7812ae4 | pbrook | FARITH3(mulg) |
462 | a7812ae4 | pbrook | FARITH3(divg) |
463 | a7812ae4 | pbrook | FARITH3(cmpgeq) |
464 | a7812ae4 | pbrook | FARITH3(cmpglt) |
465 | a7812ae4 | pbrook | FARITH3(cmpgle) |
466 | a7812ae4 | pbrook | FARITH3(adds) |
467 | a7812ae4 | pbrook | FARITH3(subs) |
468 | a7812ae4 | pbrook | FARITH3(muls) |
469 | a7812ae4 | pbrook | FARITH3(divs) |
470 | a7812ae4 | pbrook | FARITH3(addt) |
471 | a7812ae4 | pbrook | FARITH3(subt) |
472 | a7812ae4 | pbrook | FARITH3(mult) |
473 | a7812ae4 | pbrook | FARITH3(divt) |
474 | a7812ae4 | pbrook | FARITH3(cmptun) |
475 | a7812ae4 | pbrook | FARITH3(cmpteq) |
476 | a7812ae4 | pbrook | FARITH3(cmptlt) |
477 | a7812ae4 | pbrook | FARITH3(cmptle) |
478 | a7812ae4 | pbrook | FARITH3(cpys) |
479 | a7812ae4 | pbrook | FARITH3(cpysn) |
480 | a7812ae4 | pbrook | FARITH3(cpyse) |
481 | a7812ae4 | pbrook | |
482 | a7812ae4 | pbrook | #define FCMOV(name) \
|
483 | a7812ae4 | pbrook | static always_inline void glue(gen_f, name) (int ra, int rb, int rc) \ |
484 | a7812ae4 | pbrook | { \ |
485 | a7812ae4 | pbrook | int l1; \
|
486 | a7812ae4 | pbrook | TCGv tmp; \ |
487 | a7812ae4 | pbrook | \ |
488 | a7812ae4 | pbrook | if (unlikely(rc == 31)) \ |
489 | a7812ae4 | pbrook | return; \
|
490 | a7812ae4 | pbrook | \ |
491 | a7812ae4 | pbrook | l1 = gen_new_label(); \ |
492 | a7812ae4 | pbrook | tmp = tcg_temp_new(); \ |
493 | a7812ae4 | pbrook | if (ra != 31) { \ |
494 | a7812ae4 | pbrook | tmp = tcg_temp_new(); \ |
495 | a7812ae4 | pbrook | gen_helper_ ## name (tmp, cpu_fir[ra]); \ |
496 | a7812ae4 | pbrook | } else { \
|
497 | a7812ae4 | pbrook | tmp = tcg_const_i64(0); \
|
498 | a7812ae4 | pbrook | gen_helper_ ## name (tmp, tmp); \ |
499 | a7812ae4 | pbrook | } \ |
500 | a7812ae4 | pbrook | tcg_gen_brcondi_i64(TCG_COND_EQ, tmp, 0, l1); \
|
501 | a7812ae4 | pbrook | if (rb != 31) \ |
502 | a7812ae4 | pbrook | tcg_gen_mov_i64(cpu_fir[rc], cpu_fir[ra]); \ |
503 | a7812ae4 | pbrook | else \
|
504 | a7812ae4 | pbrook | tcg_gen_movi_i64(cpu_fir[rc], 0); \
|
505 | a7812ae4 | pbrook | gen_set_label(l1); \ |
506 | 4c9649a9 | j_mayer | } |
507 | a7812ae4 | pbrook | FCMOV(cmpfeq) |
508 | a7812ae4 | pbrook | FCMOV(cmpfne) |
509 | a7812ae4 | pbrook | FCMOV(cmpflt) |
510 | a7812ae4 | pbrook | FCMOV(cmpfge) |
511 | a7812ae4 | pbrook | FCMOV(cmpfle) |
512 | a7812ae4 | pbrook | FCMOV(cmpfgt) |
513 | 4c9649a9 | j_mayer | |
514 | b3249f63 | aurel32 | /* EXTWH, EXTWH, EXTLH, EXTQH */
|
515 | b3249f63 | aurel32 | static always_inline void gen_ext_h(void (*tcg_gen_ext_i64)(TCGv t0, TCGv t1), |
516 | b3249f63 | aurel32 | int ra, int rb, int rc, |
517 | adf3c8b6 | aurel32 | int islit, uint8_t lit)
|
518 | b3249f63 | aurel32 | { |
519 | b3249f63 | aurel32 | if (unlikely(rc == 31)) |
520 | b3249f63 | aurel32 | return;
|
521 | b3249f63 | aurel32 | |
522 | b3249f63 | aurel32 | if (ra != 31) { |
523 | dfaa8583 | aurel32 | if (islit) {
|
524 | dfaa8583 | aurel32 | if (lit != 0) |
525 | dfaa8583 | aurel32 | tcg_gen_shli_i64(cpu_ir[rc], cpu_ir[ra], 64 - ((lit & 7) * 8)); |
526 | dfaa8583 | aurel32 | else
|
527 | dfaa8583 | aurel32 | tcg_gen_mov_i64(cpu_ir[rc], cpu_ir[ra]); |
528 | fe2b269a | aurel32 | } else {
|
529 | b3249f63 | aurel32 | TCGv tmp1, tmp2; |
530 | a7812ae4 | pbrook | tmp1 = tcg_temp_new(); |
531 | b3249f63 | aurel32 | tcg_gen_andi_i64(tmp1, cpu_ir[rb], 7);
|
532 | b3249f63 | aurel32 | tcg_gen_shli_i64(tmp1, tmp1, 3);
|
533 | b3249f63 | aurel32 | tmp2 = tcg_const_i64(64);
|
534 | b3249f63 | aurel32 | tcg_gen_sub_i64(tmp1, tmp2, tmp1); |
535 | b3249f63 | aurel32 | tcg_temp_free(tmp2); |
536 | dfaa8583 | aurel32 | tcg_gen_shl_i64(cpu_ir[rc], cpu_ir[ra], tmp1); |
537 | b3249f63 | aurel32 | tcg_temp_free(tmp1); |
538 | dfaa8583 | aurel32 | } |
539 | dfaa8583 | aurel32 | if (tcg_gen_ext_i64)
|
540 | dfaa8583 | aurel32 | tcg_gen_ext_i64(cpu_ir[rc], cpu_ir[rc]); |
541 | b3249f63 | aurel32 | } else
|
542 | b3249f63 | aurel32 | tcg_gen_movi_i64(cpu_ir[rc], 0);
|
543 | b3249f63 | aurel32 | } |
544 | b3249f63 | aurel32 | |
545 | b3249f63 | aurel32 | /* EXTBL, EXTWL, EXTWL, EXTLL, EXTQL */
|
546 | b3249f63 | aurel32 | static always_inline void gen_ext_l(void (*tcg_gen_ext_i64)(TCGv t0, TCGv t1), |
547 | b3249f63 | aurel32 | int ra, int rb, int rc, |
548 | adf3c8b6 | aurel32 | int islit, uint8_t lit)
|
549 | b3249f63 | aurel32 | { |
550 | b3249f63 | aurel32 | if (unlikely(rc == 31)) |
551 | b3249f63 | aurel32 | return;
|
552 | b3249f63 | aurel32 | |
553 | b3249f63 | aurel32 | if (ra != 31) { |
554 | dfaa8583 | aurel32 | if (islit) {
|
555 | dfaa8583 | aurel32 | tcg_gen_shri_i64(cpu_ir[rc], cpu_ir[ra], (lit & 7) * 8); |
556 | dfaa8583 | aurel32 | } else {
|
557 | a7812ae4 | pbrook | TCGv tmp = tcg_temp_new(); |
558 | b3249f63 | aurel32 | tcg_gen_andi_i64(tmp, cpu_ir[rb], 7);
|
559 | b3249f63 | aurel32 | tcg_gen_shli_i64(tmp, tmp, 3);
|
560 | dfaa8583 | aurel32 | tcg_gen_shr_i64(cpu_ir[rc], cpu_ir[ra], tmp); |
561 | b3249f63 | aurel32 | tcg_temp_free(tmp); |
562 | fe2b269a | aurel32 | } |
563 | dfaa8583 | aurel32 | if (tcg_gen_ext_i64)
|
564 | dfaa8583 | aurel32 | tcg_gen_ext_i64(cpu_ir[rc], cpu_ir[rc]); |
565 | b3249f63 | aurel32 | } else
|
566 | b3249f63 | aurel32 | tcg_gen_movi_i64(cpu_ir[rc], 0);
|
567 | b3249f63 | aurel32 | } |
568 | b3249f63 | aurel32 | |
569 | 04acd307 | aurel32 | /* Code to call arith3 helpers */
|
570 | a7812ae4 | pbrook | #define ARITH3(name) \
|
571 | a7812ae4 | pbrook | static always_inline void glue(gen_, name) (int ra, int rb, int rc, \ |
572 | a7812ae4 | pbrook | int islit, uint8_t lit) \
|
573 | a7812ae4 | pbrook | { \ |
574 | a7812ae4 | pbrook | if (unlikely(rc == 31)) \ |
575 | a7812ae4 | pbrook | return; \
|
576 | a7812ae4 | pbrook | \ |
577 | a7812ae4 | pbrook | if (ra != 31) { \ |
578 | a7812ae4 | pbrook | if (islit) { \
|
579 | a7812ae4 | pbrook | TCGv tmp = tcg_const_i64(lit); \ |
580 | a7812ae4 | pbrook | gen_helper_ ## name(cpu_ir[rc], cpu_ir[ra], tmp); \ |
581 | a7812ae4 | pbrook | tcg_temp_free(tmp); \ |
582 | a7812ae4 | pbrook | } else \
|
583 | a7812ae4 | pbrook | gen_helper_ ## name (cpu_ir[rc], cpu_ir[ra], cpu_ir[rb]); \ |
584 | a7812ae4 | pbrook | } else { \
|
585 | a7812ae4 | pbrook | TCGv tmp1 = tcg_const_i64(0); \
|
586 | a7812ae4 | pbrook | if (islit) { \
|
587 | a7812ae4 | pbrook | TCGv tmp2 = tcg_const_i64(lit); \ |
588 | a7812ae4 | pbrook | gen_helper_ ## name (cpu_ir[rc], tmp1, tmp2); \ |
589 | a7812ae4 | pbrook | tcg_temp_free(tmp2); \ |
590 | a7812ae4 | pbrook | } else \
|
591 | a7812ae4 | pbrook | gen_helper_ ## name (cpu_ir[rc], tmp1, cpu_ir[rb]); \ |
592 | a7812ae4 | pbrook | tcg_temp_free(tmp1); \ |
593 | a7812ae4 | pbrook | } \ |
594 | b3249f63 | aurel32 | } |
595 | a7812ae4 | pbrook | ARITH3(cmpbge) |
596 | a7812ae4 | pbrook | ARITH3(addlv) |
597 | a7812ae4 | pbrook | ARITH3(sublv) |
598 | a7812ae4 | pbrook | ARITH3(addqv) |
599 | a7812ae4 | pbrook | ARITH3(subqv) |
600 | a7812ae4 | pbrook | ARITH3(mskbl) |
601 | a7812ae4 | pbrook | ARITH3(insbl) |
602 | a7812ae4 | pbrook | ARITH3(mskwl) |
603 | a7812ae4 | pbrook | ARITH3(inswl) |
604 | a7812ae4 | pbrook | ARITH3(mskll) |
605 | a7812ae4 | pbrook | ARITH3(insll) |
606 | a7812ae4 | pbrook | ARITH3(zap) |
607 | a7812ae4 | pbrook | ARITH3(zapnot) |
608 | a7812ae4 | pbrook | ARITH3(mskql) |
609 | a7812ae4 | pbrook | ARITH3(insql) |
610 | a7812ae4 | pbrook | ARITH3(mskwh) |
611 | a7812ae4 | pbrook | ARITH3(inswh) |
612 | a7812ae4 | pbrook | ARITH3(msklh) |
613 | a7812ae4 | pbrook | ARITH3(inslh) |
614 | a7812ae4 | pbrook | ARITH3(mskqh) |
615 | a7812ae4 | pbrook | ARITH3(insqh) |
616 | a7812ae4 | pbrook | ARITH3(umulh) |
617 | a7812ae4 | pbrook | ARITH3(mullv) |
618 | a7812ae4 | pbrook | ARITH3(mulqv) |
619 | b3249f63 | aurel32 | |
620 | 01ff9cc8 | aurel32 | static always_inline void gen_cmp(TCGCond cond, |
621 | 01ff9cc8 | aurel32 | int ra, int rb, int rc, |
622 | a1cf28f4 | aurel32 | int islit, uint8_t lit)
|
623 | 01ff9cc8 | aurel32 | { |
624 | 01ff9cc8 | aurel32 | int l1, l2;
|
625 | 01ff9cc8 | aurel32 | TCGv tmp; |
626 | 01ff9cc8 | aurel32 | |
627 | 01ff9cc8 | aurel32 | if (unlikely(rc == 31)) |
628 | 01ff9cc8 | aurel32 | return;
|
629 | 01ff9cc8 | aurel32 | |
630 | 01ff9cc8 | aurel32 | l1 = gen_new_label(); |
631 | 01ff9cc8 | aurel32 | l2 = gen_new_label(); |
632 | 01ff9cc8 | aurel32 | |
633 | 01ff9cc8 | aurel32 | if (ra != 31) { |
634 | a7812ae4 | pbrook | tmp = tcg_temp_new(); |
635 | 01ff9cc8 | aurel32 | tcg_gen_mov_i64(tmp, cpu_ir[ra]); |
636 | 01ff9cc8 | aurel32 | } else
|
637 | 01ff9cc8 | aurel32 | tmp = tcg_const_i64(0);
|
638 | 01ff9cc8 | aurel32 | if (islit)
|
639 | 01ff9cc8 | aurel32 | tcg_gen_brcondi_i64(cond, tmp, lit, l1); |
640 | 01ff9cc8 | aurel32 | else
|
641 | dfaa8583 | aurel32 | tcg_gen_brcond_i64(cond, tmp, cpu_ir[rb], l1); |
642 | 01ff9cc8 | aurel32 | |
643 | 01ff9cc8 | aurel32 | tcg_gen_movi_i64(cpu_ir[rc], 0);
|
644 | 01ff9cc8 | aurel32 | tcg_gen_br(l2); |
645 | 01ff9cc8 | aurel32 | gen_set_label(l1); |
646 | 01ff9cc8 | aurel32 | tcg_gen_movi_i64(cpu_ir[rc], 1);
|
647 | 01ff9cc8 | aurel32 | gen_set_label(l2); |
648 | 01ff9cc8 | aurel32 | } |
649 | 01ff9cc8 | aurel32 | |
650 | f071b4d3 | j_mayer | static always_inline int translate_one (DisasContext *ctx, uint32_t insn) |
651 | 4c9649a9 | j_mayer | { |
652 | 4c9649a9 | j_mayer | uint32_t palcode; |
653 | 4c9649a9 | j_mayer | int32_t disp21, disp16, disp12; |
654 | 4c9649a9 | j_mayer | uint16_t fn11, fn16; |
655 | 4c9649a9 | j_mayer | uint8_t opc, ra, rb, rc, sbz, fpfn, fn7, fn2, islit; |
656 | adf3c8b6 | aurel32 | uint8_t lit; |
657 | 4c9649a9 | j_mayer | int ret;
|
658 | 4c9649a9 | j_mayer | |
659 | 4c9649a9 | j_mayer | /* Decode all instruction fields */
|
660 | 4c9649a9 | j_mayer | opc = insn >> 26;
|
661 | 4c9649a9 | j_mayer | ra = (insn >> 21) & 0x1F; |
662 | 4c9649a9 | j_mayer | rb = (insn >> 16) & 0x1F; |
663 | 4c9649a9 | j_mayer | rc = insn & 0x1F;
|
664 | 4c9649a9 | j_mayer | sbz = (insn >> 13) & 0x07; |
665 | 4c9649a9 | j_mayer | islit = (insn >> 12) & 1; |
666 | dfaa8583 | aurel32 | if (rb == 31 && !islit) { |
667 | dfaa8583 | aurel32 | islit = 1;
|
668 | dfaa8583 | aurel32 | lit = 0;
|
669 | dfaa8583 | aurel32 | } else
|
670 | dfaa8583 | aurel32 | lit = (insn >> 13) & 0xFF; |
671 | 4c9649a9 | j_mayer | palcode = insn & 0x03FFFFFF;
|
672 | 4c9649a9 | j_mayer | disp21 = ((int32_t)((insn & 0x001FFFFF) << 11)) >> 11; |
673 | 4c9649a9 | j_mayer | disp16 = (int16_t)(insn & 0x0000FFFF);
|
674 | 4c9649a9 | j_mayer | disp12 = (int32_t)((insn & 0x00000FFF) << 20) >> 20; |
675 | 4c9649a9 | j_mayer | fn16 = insn & 0x0000FFFF;
|
676 | 4c9649a9 | j_mayer | fn11 = (insn >> 5) & 0x000007FF; |
677 | 4c9649a9 | j_mayer | fpfn = fn11 & 0x3F;
|
678 | 4c9649a9 | j_mayer | fn7 = (insn >> 5) & 0x0000007F; |
679 | 4c9649a9 | j_mayer | fn2 = (insn >> 5) & 0x00000003; |
680 | 4c9649a9 | j_mayer | ret = 0;
|
681 | d12d51d5 | aliguori | LOG_DISAS("opc %02x ra %d rb %d rc %d disp16 %04x\n",
|
682 | d12d51d5 | aliguori | opc, ra, rb, rc, disp16); |
683 | 4c9649a9 | j_mayer | switch (opc) {
|
684 | 4c9649a9 | j_mayer | case 0x00: |
685 | 4c9649a9 | j_mayer | /* CALL_PAL */
|
686 | 4c9649a9 | j_mayer | if (palcode >= 0x80 && palcode < 0xC0) { |
687 | 4c9649a9 | j_mayer | /* Unprivileged PAL call */
|
688 | 31a877f2 | aurel32 | gen_excp(ctx, EXCP_CALL_PAL + ((palcode & 0x3F) << 6), 0); |
689 | 4c9649a9 | j_mayer | #if !defined (CONFIG_USER_ONLY)
|
690 | 4c9649a9 | j_mayer | } else if (palcode < 0x40) { |
691 | 4c9649a9 | j_mayer | /* Privileged PAL code */
|
692 | 4c9649a9 | j_mayer | if (ctx->mem_idx & 1) |
693 | 4c9649a9 | j_mayer | goto invalid_opc;
|
694 | 4c9649a9 | j_mayer | else
|
695 | e79ab941 | aurel32 | gen_excp(ctx, EXCP_CALL_PALP + ((palcode & 0x3F) << 6), 0); |
696 | 4c9649a9 | j_mayer | #endif
|
697 | 4c9649a9 | j_mayer | } else {
|
698 | 4c9649a9 | j_mayer | /* Invalid PAL call */
|
699 | 4c9649a9 | j_mayer | goto invalid_opc;
|
700 | 4c9649a9 | j_mayer | } |
701 | 4c9649a9 | j_mayer | ret = 3;
|
702 | 4c9649a9 | j_mayer | break;
|
703 | 4c9649a9 | j_mayer | case 0x01: |
704 | 4c9649a9 | j_mayer | /* OPC01 */
|
705 | 4c9649a9 | j_mayer | goto invalid_opc;
|
706 | 4c9649a9 | j_mayer | case 0x02: |
707 | 4c9649a9 | j_mayer | /* OPC02 */
|
708 | 4c9649a9 | j_mayer | goto invalid_opc;
|
709 | 4c9649a9 | j_mayer | case 0x03: |
710 | 4c9649a9 | j_mayer | /* OPC03 */
|
711 | 4c9649a9 | j_mayer | goto invalid_opc;
|
712 | 4c9649a9 | j_mayer | case 0x04: |
713 | 4c9649a9 | j_mayer | /* OPC04 */
|
714 | 4c9649a9 | j_mayer | goto invalid_opc;
|
715 | 4c9649a9 | j_mayer | case 0x05: |
716 | 4c9649a9 | j_mayer | /* OPC05 */
|
717 | 4c9649a9 | j_mayer | goto invalid_opc;
|
718 | 4c9649a9 | j_mayer | case 0x06: |
719 | 4c9649a9 | j_mayer | /* OPC06 */
|
720 | 4c9649a9 | j_mayer | goto invalid_opc;
|
721 | 4c9649a9 | j_mayer | case 0x07: |
722 | 4c9649a9 | j_mayer | /* OPC07 */
|
723 | 4c9649a9 | j_mayer | goto invalid_opc;
|
724 | 4c9649a9 | j_mayer | case 0x08: |
725 | 4c9649a9 | j_mayer | /* LDA */
|
726 | 1ef4ef4e | aurel32 | if (likely(ra != 31)) { |
727 | 496cb5b9 | aurel32 | if (rb != 31) |
728 | 3761035f | aurel32 | tcg_gen_addi_i64(cpu_ir[ra], cpu_ir[rb], disp16); |
729 | 3761035f | aurel32 | else
|
730 | 3761035f | aurel32 | tcg_gen_movi_i64(cpu_ir[ra], disp16); |
731 | 496cb5b9 | aurel32 | } |
732 | 4c9649a9 | j_mayer | break;
|
733 | 4c9649a9 | j_mayer | case 0x09: |
734 | 4c9649a9 | j_mayer | /* LDAH */
|
735 | 1ef4ef4e | aurel32 | if (likely(ra != 31)) { |
736 | 496cb5b9 | aurel32 | if (rb != 31) |
737 | 3761035f | aurel32 | tcg_gen_addi_i64(cpu_ir[ra], cpu_ir[rb], disp16 << 16);
|
738 | 3761035f | aurel32 | else
|
739 | 3761035f | aurel32 | tcg_gen_movi_i64(cpu_ir[ra], disp16 << 16);
|
740 | 496cb5b9 | aurel32 | } |
741 | 4c9649a9 | j_mayer | break;
|
742 | 4c9649a9 | j_mayer | case 0x0A: |
743 | 4c9649a9 | j_mayer | /* LDBU */
|
744 | 4c9649a9 | j_mayer | if (!(ctx->amask & AMASK_BWX))
|
745 | 4c9649a9 | j_mayer | goto invalid_opc;
|
746 | f18cd223 | aurel32 | gen_load_mem(ctx, &tcg_gen_qemu_ld8u, ra, rb, disp16, 0, 0); |
747 | 4c9649a9 | j_mayer | break;
|
748 | 4c9649a9 | j_mayer | case 0x0B: |
749 | 4c9649a9 | j_mayer | /* LDQ_U */
|
750 | f18cd223 | aurel32 | gen_load_mem(ctx, &tcg_gen_qemu_ld64, ra, rb, disp16, 0, 1); |
751 | 4c9649a9 | j_mayer | break;
|
752 | 4c9649a9 | j_mayer | case 0x0C: |
753 | 4c9649a9 | j_mayer | /* LDWU */
|
754 | 4c9649a9 | j_mayer | if (!(ctx->amask & AMASK_BWX))
|
755 | 4c9649a9 | j_mayer | goto invalid_opc;
|
756 | 577d5e7f | aurel32 | gen_load_mem(ctx, &tcg_gen_qemu_ld16u, ra, rb, disp16, 0, 0); |
757 | 4c9649a9 | j_mayer | break;
|
758 | 4c9649a9 | j_mayer | case 0x0D: |
759 | 4c9649a9 | j_mayer | /* STW */
|
760 | 57a92c8e | aurel32 | gen_store_mem(ctx, &tcg_gen_qemu_st16, ra, rb, disp16, 0, 0, 0); |
761 | 4c9649a9 | j_mayer | break;
|
762 | 4c9649a9 | j_mayer | case 0x0E: |
763 | 4c9649a9 | j_mayer | /* STB */
|
764 | 57a92c8e | aurel32 | gen_store_mem(ctx, &tcg_gen_qemu_st8, ra, rb, disp16, 0, 0, 0); |
765 | 4c9649a9 | j_mayer | break;
|
766 | 4c9649a9 | j_mayer | case 0x0F: |
767 | 4c9649a9 | j_mayer | /* STQ_U */
|
768 | 57a92c8e | aurel32 | gen_store_mem(ctx, &tcg_gen_qemu_st64, ra, rb, disp16, 0, 1, 0); |
769 | 4c9649a9 | j_mayer | break;
|
770 | 4c9649a9 | j_mayer | case 0x10: |
771 | 4c9649a9 | j_mayer | switch (fn7) {
|
772 | 4c9649a9 | j_mayer | case 0x00: |
773 | 4c9649a9 | j_mayer | /* ADDL */
|
774 | 30c7183b | aurel32 | if (likely(rc != 31)) { |
775 | 30c7183b | aurel32 | if (ra != 31) { |
776 | 30c7183b | aurel32 | if (islit) {
|
777 | 30c7183b | aurel32 | tcg_gen_addi_i64(cpu_ir[rc], cpu_ir[ra], lit); |
778 | 30c7183b | aurel32 | tcg_gen_ext32s_i64(cpu_ir[rc], cpu_ir[rc]); |
779 | dfaa8583 | aurel32 | } else {
|
780 | 30c7183b | aurel32 | tcg_gen_add_i64(cpu_ir[rc], cpu_ir[ra], cpu_ir[rb]); |
781 | 30c7183b | aurel32 | tcg_gen_ext32s_i64(cpu_ir[rc], cpu_ir[rc]); |
782 | dfaa8583 | aurel32 | } |
783 | 30c7183b | aurel32 | } else {
|
784 | 30c7183b | aurel32 | if (islit)
|
785 | dfaa8583 | aurel32 | tcg_gen_movi_i64(cpu_ir[rc], lit); |
786 | 30c7183b | aurel32 | else
|
787 | dfaa8583 | aurel32 | tcg_gen_ext32s_i64(cpu_ir[rc], cpu_ir[rb]); |
788 | 30c7183b | aurel32 | } |
789 | 30c7183b | aurel32 | } |
790 | 4c9649a9 | j_mayer | break;
|
791 | 4c9649a9 | j_mayer | case 0x02: |
792 | 4c9649a9 | j_mayer | /* S4ADDL */
|
793 | 30c7183b | aurel32 | if (likely(rc != 31)) { |
794 | 30c7183b | aurel32 | if (ra != 31) { |
795 | a7812ae4 | pbrook | TCGv tmp = tcg_temp_new(); |
796 | dfaa8583 | aurel32 | tcg_gen_shli_i64(tmp, cpu_ir[ra], 2);
|
797 | dfaa8583 | aurel32 | if (islit)
|
798 | dfaa8583 | aurel32 | tcg_gen_addi_i64(tmp, tmp, lit); |
799 | dfaa8583 | aurel32 | else
|
800 | dfaa8583 | aurel32 | tcg_gen_add_i64(tmp, tmp, cpu_ir[rb]); |
801 | dfaa8583 | aurel32 | tcg_gen_ext32s_i64(cpu_ir[rc], tmp); |
802 | dfaa8583 | aurel32 | tcg_temp_free(tmp); |
803 | 30c7183b | aurel32 | } else {
|
804 | 30c7183b | aurel32 | if (islit)
|
805 | 30c7183b | aurel32 | tcg_gen_movi_i64(cpu_ir[rc], lit); |
806 | 30c7183b | aurel32 | else
|
807 | dfaa8583 | aurel32 | tcg_gen_ext32s_i64(cpu_ir[rc], cpu_ir[rb]); |
808 | 30c7183b | aurel32 | } |
809 | 30c7183b | aurel32 | } |
810 | 4c9649a9 | j_mayer | break;
|
811 | 4c9649a9 | j_mayer | case 0x09: |
812 | 4c9649a9 | j_mayer | /* SUBL */
|
813 | 30c7183b | aurel32 | if (likely(rc != 31)) { |
814 | 30c7183b | aurel32 | if (ra != 31) { |
815 | dfaa8583 | aurel32 | if (islit)
|
816 | 30c7183b | aurel32 | tcg_gen_subi_i64(cpu_ir[rc], cpu_ir[ra], lit); |
817 | dfaa8583 | aurel32 | else
|
818 | 30c7183b | aurel32 | tcg_gen_sub_i64(cpu_ir[rc], cpu_ir[ra], cpu_ir[rb]); |
819 | dfaa8583 | aurel32 | tcg_gen_ext32s_i64(cpu_ir[rc], cpu_ir[rc]); |
820 | 30c7183b | aurel32 | } else {
|
821 | 30c7183b | aurel32 | if (islit)
|
822 | 30c7183b | aurel32 | tcg_gen_movi_i64(cpu_ir[rc], -lit); |
823 | dfaa8583 | aurel32 | else {
|
824 | 30c7183b | aurel32 | tcg_gen_neg_i64(cpu_ir[rc], cpu_ir[rb]); |
825 | 30c7183b | aurel32 | tcg_gen_ext32s_i64(cpu_ir[rc], cpu_ir[rc]); |
826 | 30c7183b | aurel32 | } |
827 | 30c7183b | aurel32 | } |
828 | 4c9649a9 | j_mayer | break;
|
829 | 4c9649a9 | j_mayer | case 0x0B: |
830 | 4c9649a9 | j_mayer | /* S4SUBL */
|
831 | 30c7183b | aurel32 | if (likely(rc != 31)) { |
832 | 30c7183b | aurel32 | if (ra != 31) { |
833 | a7812ae4 | pbrook | TCGv tmp = tcg_temp_new(); |
834 | dfaa8583 | aurel32 | tcg_gen_shli_i64(tmp, cpu_ir[ra], 2);
|
835 | dfaa8583 | aurel32 | if (islit)
|
836 | dfaa8583 | aurel32 | tcg_gen_subi_i64(tmp, tmp, lit); |
837 | dfaa8583 | aurel32 | else
|
838 | dfaa8583 | aurel32 | tcg_gen_sub_i64(tmp, tmp, cpu_ir[rb]); |
839 | dfaa8583 | aurel32 | tcg_gen_ext32s_i64(cpu_ir[rc], tmp); |
840 | dfaa8583 | aurel32 | tcg_temp_free(tmp); |
841 | 30c7183b | aurel32 | } else {
|
842 | 30c7183b | aurel32 | if (islit)
|
843 | 30c7183b | aurel32 | tcg_gen_movi_i64(cpu_ir[rc], -lit); |
844 | dfaa8583 | aurel32 | else {
|
845 | 30c7183b | aurel32 | tcg_gen_neg_i64(cpu_ir[rc], cpu_ir[rb]); |
846 | 30c7183b | aurel32 | tcg_gen_ext32s_i64(cpu_ir[rc], cpu_ir[rc]); |
847 | dfaa8583 | aurel32 | } |
848 | 30c7183b | aurel32 | } |
849 | 30c7183b | aurel32 | } |
850 | 4c9649a9 | j_mayer | break;
|
851 | 4c9649a9 | j_mayer | case 0x0F: |
852 | 4c9649a9 | j_mayer | /* CMPBGE */
|
853 | a7812ae4 | pbrook | gen_cmpbge(ra, rb, rc, islit, lit); |
854 | 4c9649a9 | j_mayer | break;
|
855 | 4c9649a9 | j_mayer | case 0x12: |
856 | 4c9649a9 | j_mayer | /* S8ADDL */
|
857 | 30c7183b | aurel32 | if (likely(rc != 31)) { |
858 | 30c7183b | aurel32 | if (ra != 31) { |
859 | a7812ae4 | pbrook | TCGv tmp = tcg_temp_new(); |
860 | dfaa8583 | aurel32 | tcg_gen_shli_i64(tmp, cpu_ir[ra], 3);
|
861 | dfaa8583 | aurel32 | if (islit)
|
862 | dfaa8583 | aurel32 | tcg_gen_addi_i64(tmp, tmp, lit); |
863 | dfaa8583 | aurel32 | else
|
864 | dfaa8583 | aurel32 | tcg_gen_add_i64(tmp, tmp, cpu_ir[rb]); |
865 | dfaa8583 | aurel32 | tcg_gen_ext32s_i64(cpu_ir[rc], tmp); |
866 | dfaa8583 | aurel32 | tcg_temp_free(tmp); |
867 | 30c7183b | aurel32 | } else {
|
868 | 30c7183b | aurel32 | if (islit)
|
869 | 30c7183b | aurel32 | tcg_gen_movi_i64(cpu_ir[rc], lit); |
870 | 30c7183b | aurel32 | else
|
871 | dfaa8583 | aurel32 | tcg_gen_ext32s_i64(cpu_ir[rc], cpu_ir[rb]); |
872 | 30c7183b | aurel32 | } |
873 | 30c7183b | aurel32 | } |
874 | 4c9649a9 | j_mayer | break;
|
875 | 4c9649a9 | j_mayer | case 0x1B: |
876 | 4c9649a9 | j_mayer | /* S8SUBL */
|
877 | 30c7183b | aurel32 | if (likely(rc != 31)) { |
878 | 30c7183b | aurel32 | if (ra != 31) { |
879 | a7812ae4 | pbrook | TCGv tmp = tcg_temp_new(); |
880 | dfaa8583 | aurel32 | tcg_gen_shli_i64(tmp, cpu_ir[ra], 3);
|
881 | dfaa8583 | aurel32 | if (islit)
|
882 | dfaa8583 | aurel32 | tcg_gen_subi_i64(tmp, tmp, lit); |
883 | dfaa8583 | aurel32 | else
|
884 | dfaa8583 | aurel32 | tcg_gen_sub_i64(tmp, tmp, cpu_ir[rb]); |
885 | dfaa8583 | aurel32 | tcg_gen_ext32s_i64(cpu_ir[rc], tmp); |
886 | dfaa8583 | aurel32 | tcg_temp_free(tmp); |
887 | 30c7183b | aurel32 | } else {
|
888 | 30c7183b | aurel32 | if (islit)
|
889 | 30c7183b | aurel32 | tcg_gen_movi_i64(cpu_ir[rc], -lit); |
890 | dfaa8583 | aurel32 | else
|
891 | 30c7183b | aurel32 | tcg_gen_neg_i64(cpu_ir[rc], cpu_ir[rb]); |
892 | 30c7183b | aurel32 | tcg_gen_ext32s_i64(cpu_ir[rc], cpu_ir[rc]); |
893 | dfaa8583 | aurel32 | } |
894 | 30c7183b | aurel32 | } |
895 | 30c7183b | aurel32 | } |
896 | 4c9649a9 | j_mayer | break;
|
897 | 4c9649a9 | j_mayer | case 0x1D: |
898 | 4c9649a9 | j_mayer | /* CMPULT */
|
899 | 01ff9cc8 | aurel32 | gen_cmp(TCG_COND_LTU, ra, rb, rc, islit, lit); |
900 | 4c9649a9 | j_mayer | break;
|
901 | 4c9649a9 | j_mayer | case 0x20: |
902 | 4c9649a9 | j_mayer | /* ADDQ */
|
903 | 30c7183b | aurel32 | if (likely(rc != 31)) { |
904 | 30c7183b | aurel32 | if (ra != 31) { |
905 | 30c7183b | aurel32 | if (islit)
|
906 | 30c7183b | aurel32 | tcg_gen_addi_i64(cpu_ir[rc], cpu_ir[ra], lit); |
907 | 30c7183b | aurel32 | else
|
908 | dfaa8583 | aurel32 | tcg_gen_add_i64(cpu_ir[rc], cpu_ir[ra], cpu_ir[rb]); |
909 | 30c7183b | aurel32 | } else {
|
910 | 30c7183b | aurel32 | if (islit)
|
911 | 30c7183b | aurel32 | tcg_gen_movi_i64(cpu_ir[rc], lit); |
912 | 30c7183b | aurel32 | else
|
913 | dfaa8583 | aurel32 | tcg_gen_mov_i64(cpu_ir[rc], cpu_ir[rb]); |
914 | 30c7183b | aurel32 | } |
915 | 30c7183b | aurel32 | } |
916 | 4c9649a9 | j_mayer | break;
|
917 | 4c9649a9 | j_mayer | case 0x22: |
918 | 4c9649a9 | j_mayer | /* S4ADDQ */
|
919 | 30c7183b | aurel32 | if (likely(rc != 31)) { |
920 | 30c7183b | aurel32 | if (ra != 31) { |
921 | a7812ae4 | pbrook | TCGv tmp = tcg_temp_new(); |
922 | dfaa8583 | aurel32 | tcg_gen_shli_i64(tmp, cpu_ir[ra], 2);
|
923 | dfaa8583 | aurel32 | if (islit)
|
924 | dfaa8583 | aurel32 | tcg_gen_addi_i64(cpu_ir[rc], tmp, lit); |
925 | dfaa8583 | aurel32 | else
|
926 | dfaa8583 | aurel32 | tcg_gen_add_i64(cpu_ir[rc], tmp, cpu_ir[rb]); |
927 | dfaa8583 | aurel32 | tcg_temp_free(tmp); |
928 | 30c7183b | aurel32 | } else {
|
929 | 30c7183b | aurel32 | if (islit)
|
930 | 30c7183b | aurel32 | tcg_gen_movi_i64(cpu_ir[rc], lit); |
931 | 30c7183b | aurel32 | else
|
932 | dfaa8583 | aurel32 | tcg_gen_mov_i64(cpu_ir[rc], cpu_ir[rb]); |
933 | 30c7183b | aurel32 | } |
934 | 30c7183b | aurel32 | } |
935 | 4c9649a9 | j_mayer | break;
|
936 | 4c9649a9 | j_mayer | case 0x29: |
937 | 4c9649a9 | j_mayer | /* SUBQ */
|
938 | 30c7183b | aurel32 | if (likely(rc != 31)) { |
939 | 30c7183b | aurel32 | if (ra != 31) { |
940 | 30c7183b | aurel32 | if (islit)
|
941 | 30c7183b | aurel32 | tcg_gen_subi_i64(cpu_ir[rc], cpu_ir[ra], lit); |
942 | 30c7183b | aurel32 | else
|
943 | dfaa8583 | aurel32 | tcg_gen_sub_i64(cpu_ir[rc], cpu_ir[ra], cpu_ir[rb]); |
944 | 30c7183b | aurel32 | } else {
|
945 | 30c7183b | aurel32 | if (islit)
|
946 | 30c7183b | aurel32 | tcg_gen_movi_i64(cpu_ir[rc], -lit); |
947 | 30c7183b | aurel32 | else
|
948 | dfaa8583 | aurel32 | tcg_gen_neg_i64(cpu_ir[rc], cpu_ir[rb]); |
949 | 30c7183b | aurel32 | } |
950 | 30c7183b | aurel32 | } |
951 | 4c9649a9 | j_mayer | break;
|
952 | 4c9649a9 | j_mayer | case 0x2B: |
953 | 4c9649a9 | j_mayer | /* S4SUBQ */
|
954 | 30c7183b | aurel32 | if (likely(rc != 31)) { |
955 | 30c7183b | aurel32 | if (ra != 31) { |
956 | a7812ae4 | pbrook | TCGv tmp = tcg_temp_new(); |
957 | dfaa8583 | aurel32 | tcg_gen_shli_i64(tmp, cpu_ir[ra], 2);
|
958 | dfaa8583 | aurel32 | if (islit)
|
959 | dfaa8583 | aurel32 | tcg_gen_subi_i64(cpu_ir[rc], tmp, lit); |
960 | dfaa8583 | aurel32 | else
|
961 | dfaa8583 | aurel32 | tcg_gen_sub_i64(cpu_ir[rc], tmp, cpu_ir[rb]); |
962 | dfaa8583 | aurel32 | tcg_temp_free(tmp); |
963 | 30c7183b | aurel32 | } else {
|
964 | 30c7183b | aurel32 | if (islit)
|
965 | 30c7183b | aurel32 | tcg_gen_movi_i64(cpu_ir[rc], -lit); |
966 | 30c7183b | aurel32 | else
|
967 | dfaa8583 | aurel32 | tcg_gen_neg_i64(cpu_ir[rc], cpu_ir[rb]); |
968 | 30c7183b | aurel32 | } |
969 | 30c7183b | aurel32 | } |
970 | 4c9649a9 | j_mayer | break;
|
971 | 4c9649a9 | j_mayer | case 0x2D: |
972 | 4c9649a9 | j_mayer | /* CMPEQ */
|
973 | 01ff9cc8 | aurel32 | gen_cmp(TCG_COND_EQ, ra, rb, rc, islit, lit); |
974 | 4c9649a9 | j_mayer | break;
|
975 | 4c9649a9 | j_mayer | case 0x32: |
976 | 4c9649a9 | j_mayer | /* S8ADDQ */
|
977 | 30c7183b | aurel32 | if (likely(rc != 31)) { |
978 | 30c7183b | aurel32 | if (ra != 31) { |
979 | a7812ae4 | pbrook | TCGv tmp = tcg_temp_new(); |
980 | dfaa8583 | aurel32 | tcg_gen_shli_i64(tmp, cpu_ir[ra], 3);
|
981 | dfaa8583 | aurel32 | if (islit)
|
982 | dfaa8583 | aurel32 | tcg_gen_addi_i64(cpu_ir[rc], tmp, lit); |
983 | dfaa8583 | aurel32 | else
|
984 | dfaa8583 | aurel32 | tcg_gen_add_i64(cpu_ir[rc], tmp, cpu_ir[rb]); |
985 | dfaa8583 | aurel32 | tcg_temp_free(tmp); |
986 | 30c7183b | aurel32 | } else {
|
987 | 30c7183b | aurel32 | if (islit)
|
988 | 30c7183b | aurel32 | tcg_gen_movi_i64(cpu_ir[rc], lit); |
989 | 30c7183b | aurel32 | else
|
990 | dfaa8583 | aurel32 | tcg_gen_mov_i64(cpu_ir[rc], cpu_ir[rb]); |
991 | 30c7183b | aurel32 | } |
992 | 30c7183b | aurel32 | } |
993 | 4c9649a9 | j_mayer | break;
|
994 | 4c9649a9 | j_mayer | case 0x3B: |
995 | 4c9649a9 | j_mayer | /* S8SUBQ */
|
996 | 30c7183b | aurel32 | if (likely(rc != 31)) { |
997 | 30c7183b | aurel32 | if (ra != 31) { |
998 | a7812ae4 | pbrook | TCGv tmp = tcg_temp_new(); |
999 | dfaa8583 | aurel32 | tcg_gen_shli_i64(tmp, cpu_ir[ra], 3);
|
1000 | dfaa8583 | aurel32 | if (islit)
|
1001 | dfaa8583 | aurel32 | tcg_gen_subi_i64(cpu_ir[rc], tmp, lit); |
1002 | dfaa8583 | aurel32 | else
|
1003 | dfaa8583 | aurel32 | tcg_gen_sub_i64(cpu_ir[rc], tmp, cpu_ir[rb]); |
1004 | dfaa8583 | aurel32 | tcg_temp_free(tmp); |
1005 | 30c7183b | aurel32 | } else {
|
1006 | 30c7183b | aurel32 | if (islit)
|
1007 | 30c7183b | aurel32 | tcg_gen_movi_i64(cpu_ir[rc], -lit); |
1008 | 30c7183b | aurel32 | else
|
1009 | dfaa8583 | aurel32 | tcg_gen_neg_i64(cpu_ir[rc], cpu_ir[rb]); |
1010 | 30c7183b | aurel32 | } |
1011 | 30c7183b | aurel32 | } |
1012 | 4c9649a9 | j_mayer | break;
|
1013 | 4c9649a9 | j_mayer | case 0x3D: |
1014 | 4c9649a9 | j_mayer | /* CMPULE */
|
1015 | 01ff9cc8 | aurel32 | gen_cmp(TCG_COND_LEU, ra, rb, rc, islit, lit); |
1016 | 4c9649a9 | j_mayer | break;
|
1017 | 4c9649a9 | j_mayer | case 0x40: |
1018 | 4c9649a9 | j_mayer | /* ADDL/V */
|
1019 | a7812ae4 | pbrook | gen_addlv(ra, rb, rc, islit, lit); |
1020 | 4c9649a9 | j_mayer | break;
|
1021 | 4c9649a9 | j_mayer | case 0x49: |
1022 | 4c9649a9 | j_mayer | /* SUBL/V */
|
1023 | a7812ae4 | pbrook | gen_sublv(ra, rb, rc, islit, lit); |
1024 | 4c9649a9 | j_mayer | break;
|
1025 | 4c9649a9 | j_mayer | case 0x4D: |
1026 | 4c9649a9 | j_mayer | /* CMPLT */
|
1027 | 01ff9cc8 | aurel32 | gen_cmp(TCG_COND_LT, ra, rb, rc, islit, lit); |
1028 | 4c9649a9 | j_mayer | break;
|
1029 | 4c9649a9 | j_mayer | case 0x60: |
1030 | 4c9649a9 | j_mayer | /* ADDQ/V */
|
1031 | a7812ae4 | pbrook | gen_addqv(ra, rb, rc, islit, lit); |
1032 | 4c9649a9 | j_mayer | break;
|
1033 | 4c9649a9 | j_mayer | case 0x69: |
1034 | 4c9649a9 | j_mayer | /* SUBQ/V */
|
1035 | a7812ae4 | pbrook | gen_subqv(ra, rb, rc, islit, lit); |
1036 | 4c9649a9 | j_mayer | break;
|
1037 | 4c9649a9 | j_mayer | case 0x6D: |
1038 | 4c9649a9 | j_mayer | /* CMPLE */
|
1039 | 01ff9cc8 | aurel32 | gen_cmp(TCG_COND_LE, ra, rb, rc, islit, lit); |
1040 | 4c9649a9 | j_mayer | break;
|
1041 | 4c9649a9 | j_mayer | default:
|
1042 | 4c9649a9 | j_mayer | goto invalid_opc;
|
1043 | 4c9649a9 | j_mayer | } |
1044 | 4c9649a9 | j_mayer | break;
|
1045 | 4c9649a9 | j_mayer | case 0x11: |
1046 | 4c9649a9 | j_mayer | switch (fn7) {
|
1047 | 4c9649a9 | j_mayer | case 0x00: |
1048 | 4c9649a9 | j_mayer | /* AND */
|
1049 | 30c7183b | aurel32 | if (likely(rc != 31)) { |
1050 | dfaa8583 | aurel32 | if (ra == 31) |
1051 | 30c7183b | aurel32 | tcg_gen_movi_i64(cpu_ir[rc], 0);
|
1052 | 30c7183b | aurel32 | else if (islit) |
1053 | 30c7183b | aurel32 | tcg_gen_andi_i64(cpu_ir[rc], cpu_ir[ra], lit); |
1054 | 30c7183b | aurel32 | else
|
1055 | 30c7183b | aurel32 | tcg_gen_and_i64(cpu_ir[rc], cpu_ir[ra], cpu_ir[rb]); |
1056 | 30c7183b | aurel32 | } |
1057 | 4c9649a9 | j_mayer | break;
|
1058 | 4c9649a9 | j_mayer | case 0x08: |
1059 | 4c9649a9 | j_mayer | /* BIC */
|
1060 | 30c7183b | aurel32 | if (likely(rc != 31)) { |
1061 | 30c7183b | aurel32 | if (ra != 31) { |
1062 | 30c7183b | aurel32 | if (islit)
|
1063 | 30c7183b | aurel32 | tcg_gen_andi_i64(cpu_ir[rc], cpu_ir[ra], ~lit); |
1064 | 1b581c44 | aurel32 | else
|
1065 | 1b581c44 | aurel32 | tcg_gen_andc_i64(cpu_ir[rc], cpu_ir[ra], cpu_ir[rb]); |
1066 | 30c7183b | aurel32 | } else
|
1067 | 30c7183b | aurel32 | tcg_gen_movi_i64(cpu_ir[rc], 0);
|
1068 | 30c7183b | aurel32 | } |
1069 | 4c9649a9 | j_mayer | break;
|
1070 | 4c9649a9 | j_mayer | case 0x14: |
1071 | 4c9649a9 | j_mayer | /* CMOVLBS */
|
1072 | fe2b269a | aurel32 | gen_cmov(TCG_COND_EQ, ra, rb, rc, islit, lit, 1);
|
1073 | 4c9649a9 | j_mayer | break;
|
1074 | 4c9649a9 | j_mayer | case 0x16: |
1075 | 4c9649a9 | j_mayer | /* CMOVLBC */
|
1076 | fe2b269a | aurel32 | gen_cmov(TCG_COND_NE, ra, rb, rc, islit, lit, 1);
|
1077 | 4c9649a9 | j_mayer | break;
|
1078 | 4c9649a9 | j_mayer | case 0x20: |
1079 | 4c9649a9 | j_mayer | /* BIS */
|
1080 | 30c7183b | aurel32 | if (likely(rc != 31)) { |
1081 | 30c7183b | aurel32 | if (ra != 31) { |
1082 | 30c7183b | aurel32 | if (islit)
|
1083 | 30c7183b | aurel32 | tcg_gen_ori_i64(cpu_ir[rc], cpu_ir[ra], lit); |
1084 | 8bb6e981 | aurel32 | else
|
1085 | 30c7183b | aurel32 | tcg_gen_or_i64(cpu_ir[rc], cpu_ir[ra], cpu_ir[rb]); |
1086 | 4c9649a9 | j_mayer | } else {
|
1087 | 30c7183b | aurel32 | if (islit)
|
1088 | 30c7183b | aurel32 | tcg_gen_movi_i64(cpu_ir[rc], lit); |
1089 | 30c7183b | aurel32 | else
|
1090 | dfaa8583 | aurel32 | tcg_gen_mov_i64(cpu_ir[rc], cpu_ir[rb]); |
1091 | 4c9649a9 | j_mayer | } |
1092 | 4c9649a9 | j_mayer | } |
1093 | 4c9649a9 | j_mayer | break;
|
1094 | 4c9649a9 | j_mayer | case 0x24: |
1095 | 4c9649a9 | j_mayer | /* CMOVEQ */
|
1096 | fe2b269a | aurel32 | gen_cmov(TCG_COND_NE, ra, rb, rc, islit, lit, 0);
|
1097 | 4c9649a9 | j_mayer | break;
|
1098 | 4c9649a9 | j_mayer | case 0x26: |
1099 | 4c9649a9 | j_mayer | /* CMOVNE */
|
1100 | fe2b269a | aurel32 | gen_cmov(TCG_COND_EQ, ra, rb, rc, islit, lit, 0);
|
1101 | 4c9649a9 | j_mayer | break;
|
1102 | 4c9649a9 | j_mayer | case 0x28: |
1103 | 4c9649a9 | j_mayer | /* ORNOT */
|
1104 | 30c7183b | aurel32 | if (likely(rc != 31)) { |
1105 | dfaa8583 | aurel32 | if (ra != 31) { |
1106 | 30c7183b | aurel32 | if (islit)
|
1107 | 30c7183b | aurel32 | tcg_gen_ori_i64(cpu_ir[rc], cpu_ir[ra], ~lit); |
1108 | 1b581c44 | aurel32 | else
|
1109 | 1b581c44 | aurel32 | tcg_gen_orc_i64(cpu_ir[rc], cpu_ir[ra], cpu_ir[rb]); |
1110 | 30c7183b | aurel32 | } else {
|
1111 | 30c7183b | aurel32 | if (islit)
|
1112 | 30c7183b | aurel32 | tcg_gen_movi_i64(cpu_ir[rc], ~lit); |
1113 | 30c7183b | aurel32 | else
|
1114 | 30c7183b | aurel32 | tcg_gen_not_i64(cpu_ir[rc], cpu_ir[rb]); |
1115 | 30c7183b | aurel32 | } |
1116 | 30c7183b | aurel32 | } |
1117 | 4c9649a9 | j_mayer | break;
|
1118 | 4c9649a9 | j_mayer | case 0x40: |
1119 | 4c9649a9 | j_mayer | /* XOR */
|
1120 | 30c7183b | aurel32 | if (likely(rc != 31)) { |
1121 | 30c7183b | aurel32 | if (ra != 31) { |
1122 | 30c7183b | aurel32 | if (islit)
|
1123 | 30c7183b | aurel32 | tcg_gen_xori_i64(cpu_ir[rc], cpu_ir[ra], lit); |
1124 | 30c7183b | aurel32 | else
|
1125 | dfaa8583 | aurel32 | tcg_gen_xor_i64(cpu_ir[rc], cpu_ir[ra], cpu_ir[rb]); |
1126 | 30c7183b | aurel32 | } else {
|
1127 | 30c7183b | aurel32 | if (islit)
|
1128 | 30c7183b | aurel32 | tcg_gen_movi_i64(cpu_ir[rc], lit); |
1129 | 30c7183b | aurel32 | else
|
1130 | dfaa8583 | aurel32 | tcg_gen_mov_i64(cpu_ir[rc], cpu_ir[rb]); |
1131 | 30c7183b | aurel32 | } |
1132 | 30c7183b | aurel32 | } |
1133 | 4c9649a9 | j_mayer | break;
|
1134 | 4c9649a9 | j_mayer | case 0x44: |
1135 | 4c9649a9 | j_mayer | /* CMOVLT */
|
1136 | fe2b269a | aurel32 | gen_cmov(TCG_COND_GE, ra, rb, rc, islit, lit, 0);
|
1137 | 4c9649a9 | j_mayer | break;
|
1138 | 4c9649a9 | j_mayer | case 0x46: |
1139 | 4c9649a9 | j_mayer | /* CMOVGE */
|
1140 | fe2b269a | aurel32 | gen_cmov(TCG_COND_LT, ra, rb, rc, islit, lit, 0);
|
1141 | 4c9649a9 | j_mayer | break;
|
1142 | 4c9649a9 | j_mayer | case 0x48: |
1143 | 4c9649a9 | j_mayer | /* EQV */
|
1144 | 30c7183b | aurel32 | if (likely(rc != 31)) { |
1145 | 30c7183b | aurel32 | if (ra != 31) { |
1146 | 30c7183b | aurel32 | if (islit)
|
1147 | 30c7183b | aurel32 | tcg_gen_xori_i64(cpu_ir[rc], cpu_ir[ra], ~lit); |
1148 | 1b581c44 | aurel32 | else
|
1149 | 1b581c44 | aurel32 | tcg_gen_eqv_i64(cpu_ir[rc], cpu_ir[ra], cpu_ir[rb]); |
1150 | 30c7183b | aurel32 | } else {
|
1151 | 30c7183b | aurel32 | if (islit)
|
1152 | 30c7183b | aurel32 | tcg_gen_movi_i64(cpu_ir[rc], ~lit); |
1153 | 30c7183b | aurel32 | else
|
1154 | dfaa8583 | aurel32 | tcg_gen_not_i64(cpu_ir[rc], cpu_ir[rb]); |
1155 | 30c7183b | aurel32 | } |
1156 | 30c7183b | aurel32 | } |
1157 | 4c9649a9 | j_mayer | break;
|
1158 | 4c9649a9 | j_mayer | case 0x61: |
1159 | 4c9649a9 | j_mayer | /* AMASK */
|
1160 | ae8ecd42 | aurel32 | if (likely(rc != 31)) { |
1161 | ae8ecd42 | aurel32 | if (islit)
|
1162 | 1a1f7dbc | aurel32 | tcg_gen_movi_i64(cpu_ir[rc], lit); |
1163 | ae8ecd42 | aurel32 | else
|
1164 | 1a1f7dbc | aurel32 | tcg_gen_mov_i64(cpu_ir[rc], cpu_ir[rb]); |
1165 | 1a1f7dbc | aurel32 | switch (ctx->env->implver) {
|
1166 | 1a1f7dbc | aurel32 | case IMPLVER_2106x:
|
1167 | 1a1f7dbc | aurel32 | /* EV4, EV45, LCA, LCA45 & EV5 */
|
1168 | 1a1f7dbc | aurel32 | break;
|
1169 | 1a1f7dbc | aurel32 | case IMPLVER_21164:
|
1170 | 1a1f7dbc | aurel32 | case IMPLVER_21264:
|
1171 | 1a1f7dbc | aurel32 | case IMPLVER_21364:
|
1172 | 1a1f7dbc | aurel32 | tcg_gen_andi_i64(cpu_ir[rc], cpu_ir[rc], |
1173 | 1a1f7dbc | aurel32 | ~(uint64_t)ctx->amask); |
1174 | 1a1f7dbc | aurel32 | break;
|
1175 | 1a1f7dbc | aurel32 | } |
1176 | ae8ecd42 | aurel32 | } |
1177 | 4c9649a9 | j_mayer | break;
|
1178 | 4c9649a9 | j_mayer | case 0x64: |
1179 | 4c9649a9 | j_mayer | /* CMOVLE */
|
1180 | fe2b269a | aurel32 | gen_cmov(TCG_COND_GT, ra, rb, rc, islit, lit, 0);
|
1181 | 4c9649a9 | j_mayer | break;
|
1182 | 4c9649a9 | j_mayer | case 0x66: |
1183 | 4c9649a9 | j_mayer | /* CMOVGT */
|
1184 | fe2b269a | aurel32 | gen_cmov(TCG_COND_LE, ra, rb, rc, islit, lit, 0);
|
1185 | 4c9649a9 | j_mayer | break;
|
1186 | 4c9649a9 | j_mayer | case 0x6C: |
1187 | 4c9649a9 | j_mayer | /* IMPLVER */
|
1188 | 3761035f | aurel32 | if (rc != 31) |
1189 | 8579095b | aurel32 | tcg_gen_movi_i64(cpu_ir[rc], ctx->env->implver); |
1190 | 4c9649a9 | j_mayer | break;
|
1191 | 4c9649a9 | j_mayer | default:
|
1192 | 4c9649a9 | j_mayer | goto invalid_opc;
|
1193 | 4c9649a9 | j_mayer | } |
1194 | 4c9649a9 | j_mayer | break;
|
1195 | 4c9649a9 | j_mayer | case 0x12: |
1196 | 4c9649a9 | j_mayer | switch (fn7) {
|
1197 | 4c9649a9 | j_mayer | case 0x02: |
1198 | 4c9649a9 | j_mayer | /* MSKBL */
|
1199 | a7812ae4 | pbrook | gen_mskbl(ra, rb, rc, islit, lit); |
1200 | 4c9649a9 | j_mayer | break;
|
1201 | 4c9649a9 | j_mayer | case 0x06: |
1202 | 4c9649a9 | j_mayer | /* EXTBL */
|
1203 | b3249f63 | aurel32 | gen_ext_l(&tcg_gen_ext8u_i64, ra, rb, rc, islit, lit); |
1204 | 4c9649a9 | j_mayer | break;
|
1205 | 4c9649a9 | j_mayer | case 0x0B: |
1206 | 4c9649a9 | j_mayer | /* INSBL */
|
1207 | a7812ae4 | pbrook | gen_insbl(ra, rb, rc, islit, lit); |
1208 | 4c9649a9 | j_mayer | break;
|
1209 | 4c9649a9 | j_mayer | case 0x12: |
1210 | 4c9649a9 | j_mayer | /* MSKWL */
|
1211 | a7812ae4 | pbrook | gen_mskwl(ra, rb, rc, islit, lit); |
1212 | 4c9649a9 | j_mayer | break;
|
1213 | 4c9649a9 | j_mayer | case 0x16: |
1214 | 4c9649a9 | j_mayer | /* EXTWL */
|
1215 | b3249f63 | aurel32 | gen_ext_l(&tcg_gen_ext16u_i64, ra, rb, rc, islit, lit); |
1216 | 4c9649a9 | j_mayer | break;
|
1217 | 4c9649a9 | j_mayer | case 0x1B: |
1218 | 4c9649a9 | j_mayer | /* INSWL */
|
1219 | a7812ae4 | pbrook | gen_inswl(ra, rb, rc, islit, lit); |
1220 | 4c9649a9 | j_mayer | break;
|
1221 | 4c9649a9 | j_mayer | case 0x22: |
1222 | 4c9649a9 | j_mayer | /* MSKLL */
|
1223 | a7812ae4 | pbrook | gen_mskll(ra, rb, rc, islit, lit); |
1224 | 4c9649a9 | j_mayer | break;
|
1225 | 4c9649a9 | j_mayer | case 0x26: |
1226 | 4c9649a9 | j_mayer | /* EXTLL */
|
1227 | b3249f63 | aurel32 | gen_ext_l(&tcg_gen_ext32u_i64, ra, rb, rc, islit, lit); |
1228 | 4c9649a9 | j_mayer | break;
|
1229 | 4c9649a9 | j_mayer | case 0x2B: |
1230 | 4c9649a9 | j_mayer | /* INSLL */
|
1231 | a7812ae4 | pbrook | gen_insll(ra, rb, rc, islit, lit); |
1232 | 4c9649a9 | j_mayer | break;
|
1233 | 4c9649a9 | j_mayer | case 0x30: |
1234 | 4c9649a9 | j_mayer | /* ZAP */
|
1235 | a7812ae4 | pbrook | gen_zap(ra, rb, rc, islit, lit); |
1236 | 4c9649a9 | j_mayer | break;
|
1237 | 4c9649a9 | j_mayer | case 0x31: |
1238 | 4c9649a9 | j_mayer | /* ZAPNOT */
|
1239 | a7812ae4 | pbrook | gen_zapnot(ra, rb, rc, islit, lit); |
1240 | 4c9649a9 | j_mayer | break;
|
1241 | 4c9649a9 | j_mayer | case 0x32: |
1242 | 4c9649a9 | j_mayer | /* MSKQL */
|
1243 | a7812ae4 | pbrook | gen_mskql(ra, rb, rc, islit, lit); |
1244 | 4c9649a9 | j_mayer | break;
|
1245 | 4c9649a9 | j_mayer | case 0x34: |
1246 | 4c9649a9 | j_mayer | /* SRL */
|
1247 | 30c7183b | aurel32 | if (likely(rc != 31)) { |
1248 | 30c7183b | aurel32 | if (ra != 31) { |
1249 | 30c7183b | aurel32 | if (islit)
|
1250 | 30c7183b | aurel32 | tcg_gen_shri_i64(cpu_ir[rc], cpu_ir[ra], lit & 0x3f);
|
1251 | dfaa8583 | aurel32 | else {
|
1252 | a7812ae4 | pbrook | TCGv shift = tcg_temp_new(); |
1253 | 30c7183b | aurel32 | tcg_gen_andi_i64(shift, cpu_ir[rb], 0x3f);
|
1254 | 30c7183b | aurel32 | tcg_gen_shr_i64(cpu_ir[rc], cpu_ir[ra], shift); |
1255 | 30c7183b | aurel32 | tcg_temp_free(shift); |
1256 | dfaa8583 | aurel32 | } |
1257 | 30c7183b | aurel32 | } else
|
1258 | 30c7183b | aurel32 | tcg_gen_movi_i64(cpu_ir[rc], 0);
|
1259 | 30c7183b | aurel32 | } |
1260 | 4c9649a9 | j_mayer | break;
|
1261 | 4c9649a9 | j_mayer | case 0x36: |
1262 | 4c9649a9 | j_mayer | /* EXTQL */
|
1263 | b3249f63 | aurel32 | gen_ext_l(NULL, ra, rb, rc, islit, lit);
|
1264 | 4c9649a9 | j_mayer | break;
|
1265 | 4c9649a9 | j_mayer | case 0x39: |
1266 | 4c9649a9 | j_mayer | /* SLL */
|
1267 | 30c7183b | aurel32 | if (likely(rc != 31)) { |
1268 | 30c7183b | aurel32 | if (ra != 31) { |
1269 | 30c7183b | aurel32 | if (islit)
|
1270 | 30c7183b | aurel32 | tcg_gen_shli_i64(cpu_ir[rc], cpu_ir[ra], lit & 0x3f);
|
1271 | dfaa8583 | aurel32 | else {
|
1272 | a7812ae4 | pbrook | TCGv shift = tcg_temp_new(); |
1273 | 30c7183b | aurel32 | tcg_gen_andi_i64(shift, cpu_ir[rb], 0x3f);
|
1274 | 30c7183b | aurel32 | tcg_gen_shl_i64(cpu_ir[rc], cpu_ir[ra], shift); |
1275 | 30c7183b | aurel32 | tcg_temp_free(shift); |
1276 | dfaa8583 | aurel32 | } |
1277 | 30c7183b | aurel32 | } else
|
1278 | 30c7183b | aurel32 | tcg_gen_movi_i64(cpu_ir[rc], 0);
|
1279 | 30c7183b | aurel32 | } |
1280 | 4c9649a9 | j_mayer | break;
|
1281 | 4c9649a9 | j_mayer | case 0x3B: |
1282 | 4c9649a9 | j_mayer | /* INSQL */
|
1283 | a7812ae4 | pbrook | gen_insql(ra, rb, rc, islit, lit); |
1284 | 4c9649a9 | j_mayer | break;
|
1285 | 4c9649a9 | j_mayer | case 0x3C: |
1286 | 4c9649a9 | j_mayer | /* SRA */
|
1287 | 30c7183b | aurel32 | if (likely(rc != 31)) { |
1288 | 30c7183b | aurel32 | if (ra != 31) { |
1289 | 30c7183b | aurel32 | if (islit)
|
1290 | 30c7183b | aurel32 | tcg_gen_sari_i64(cpu_ir[rc], cpu_ir[ra], lit & 0x3f);
|
1291 | dfaa8583 | aurel32 | else {
|
1292 | a7812ae4 | pbrook | TCGv shift = tcg_temp_new(); |
1293 | 30c7183b | aurel32 | tcg_gen_andi_i64(shift, cpu_ir[rb], 0x3f);
|
1294 | 30c7183b | aurel32 | tcg_gen_sar_i64(cpu_ir[rc], cpu_ir[ra], shift); |
1295 | 30c7183b | aurel32 | tcg_temp_free(shift); |
1296 | dfaa8583 | aurel32 | } |
1297 | 30c7183b | aurel32 | } else
|
1298 | 30c7183b | aurel32 | tcg_gen_movi_i64(cpu_ir[rc], 0);
|
1299 | 30c7183b | aurel32 | } |
1300 | 4c9649a9 | j_mayer | break;
|
1301 | 4c9649a9 | j_mayer | case 0x52: |
1302 | 4c9649a9 | j_mayer | /* MSKWH */
|
1303 | a7812ae4 | pbrook | gen_mskwh(ra, rb, rc, islit, lit); |
1304 | 4c9649a9 | j_mayer | break;
|
1305 | 4c9649a9 | j_mayer | case 0x57: |
1306 | 4c9649a9 | j_mayer | /* INSWH */
|
1307 | a7812ae4 | pbrook | gen_inswh(ra, rb, rc, islit, lit); |
1308 | 4c9649a9 | j_mayer | break;
|
1309 | 4c9649a9 | j_mayer | case 0x5A: |
1310 | 4c9649a9 | j_mayer | /* EXTWH */
|
1311 | b3249f63 | aurel32 | gen_ext_h(&tcg_gen_ext16u_i64, ra, rb, rc, islit, lit); |
1312 | 4c9649a9 | j_mayer | break;
|
1313 | 4c9649a9 | j_mayer | case 0x62: |
1314 | 4c9649a9 | j_mayer | /* MSKLH */
|
1315 | a7812ae4 | pbrook | gen_msklh(ra, rb, rc, islit, lit); |
1316 | 4c9649a9 | j_mayer | break;
|
1317 | 4c9649a9 | j_mayer | case 0x67: |
1318 | 4c9649a9 | j_mayer | /* INSLH */
|
1319 | a7812ae4 | pbrook | gen_inslh(ra, rb, rc, islit, lit); |
1320 | 4c9649a9 | j_mayer | break;
|
1321 | 4c9649a9 | j_mayer | case 0x6A: |
1322 | 4c9649a9 | j_mayer | /* EXTLH */
|
1323 | b3249f63 | aurel32 | gen_ext_h(&tcg_gen_ext16u_i64, ra, rb, rc, islit, lit); |
1324 | 4c9649a9 | j_mayer | break;
|
1325 | 4c9649a9 | j_mayer | case 0x72: |
1326 | 4c9649a9 | j_mayer | /* MSKQH */
|
1327 | a7812ae4 | pbrook | gen_mskqh(ra, rb, rc, islit, lit); |
1328 | 4c9649a9 | j_mayer | break;
|
1329 | 4c9649a9 | j_mayer | case 0x77: |
1330 | 4c9649a9 | j_mayer | /* INSQH */
|
1331 | a7812ae4 | pbrook | gen_insqh(ra, rb, rc, islit, lit); |
1332 | 4c9649a9 | j_mayer | break;
|
1333 | 4c9649a9 | j_mayer | case 0x7A: |
1334 | 4c9649a9 | j_mayer | /* EXTQH */
|
1335 | b3249f63 | aurel32 | gen_ext_h(NULL, ra, rb, rc, islit, lit);
|
1336 | 4c9649a9 | j_mayer | break;
|
1337 | 4c9649a9 | j_mayer | default:
|
1338 | 4c9649a9 | j_mayer | goto invalid_opc;
|
1339 | 4c9649a9 | j_mayer | } |
1340 | 4c9649a9 | j_mayer | break;
|
1341 | 4c9649a9 | j_mayer | case 0x13: |
1342 | 4c9649a9 | j_mayer | switch (fn7) {
|
1343 | 4c9649a9 | j_mayer | case 0x00: |
1344 | 4c9649a9 | j_mayer | /* MULL */
|
1345 | 30c7183b | aurel32 | if (likely(rc != 31)) { |
1346 | dfaa8583 | aurel32 | if (ra == 31) |
1347 | 30c7183b | aurel32 | tcg_gen_movi_i64(cpu_ir[rc], 0);
|
1348 | 30c7183b | aurel32 | else {
|
1349 | 30c7183b | aurel32 | if (islit)
|
1350 | 30c7183b | aurel32 | tcg_gen_muli_i64(cpu_ir[rc], cpu_ir[ra], lit); |
1351 | 30c7183b | aurel32 | else
|
1352 | 30c7183b | aurel32 | tcg_gen_mul_i64(cpu_ir[rc], cpu_ir[ra], cpu_ir[rb]); |
1353 | 30c7183b | aurel32 | tcg_gen_ext32s_i64(cpu_ir[rc], cpu_ir[rc]); |
1354 | 30c7183b | aurel32 | } |
1355 | 30c7183b | aurel32 | } |
1356 | 4c9649a9 | j_mayer | break;
|
1357 | 4c9649a9 | j_mayer | case 0x20: |
1358 | 4c9649a9 | j_mayer | /* MULQ */
|
1359 | 30c7183b | aurel32 | if (likely(rc != 31)) { |
1360 | dfaa8583 | aurel32 | if (ra == 31) |
1361 | 30c7183b | aurel32 | tcg_gen_movi_i64(cpu_ir[rc], 0);
|
1362 | 30c7183b | aurel32 | else if (islit) |
1363 | 30c7183b | aurel32 | tcg_gen_muli_i64(cpu_ir[rc], cpu_ir[ra], lit); |
1364 | 30c7183b | aurel32 | else
|
1365 | 30c7183b | aurel32 | tcg_gen_mul_i64(cpu_ir[rc], cpu_ir[ra], cpu_ir[rb]); |
1366 | 30c7183b | aurel32 | } |
1367 | 4c9649a9 | j_mayer | break;
|
1368 | 4c9649a9 | j_mayer | case 0x30: |
1369 | 4c9649a9 | j_mayer | /* UMULH */
|
1370 | a7812ae4 | pbrook | gen_umulh(ra, rb, rc, islit, lit); |
1371 | 4c9649a9 | j_mayer | break;
|
1372 | 4c9649a9 | j_mayer | case 0x40: |
1373 | 4c9649a9 | j_mayer | /* MULL/V */
|
1374 | a7812ae4 | pbrook | gen_mullv(ra, rb, rc, islit, lit); |
1375 | 4c9649a9 | j_mayer | break;
|
1376 | 4c9649a9 | j_mayer | case 0x60: |
1377 | 4c9649a9 | j_mayer | /* MULQ/V */
|
1378 | a7812ae4 | pbrook | gen_mulqv(ra, rb, rc, islit, lit); |
1379 | 4c9649a9 | j_mayer | break;
|
1380 | 4c9649a9 | j_mayer | default:
|
1381 | 4c9649a9 | j_mayer | goto invalid_opc;
|
1382 | 4c9649a9 | j_mayer | } |
1383 | 4c9649a9 | j_mayer | break;
|
1384 | 4c9649a9 | j_mayer | case 0x14: |
1385 | 4c9649a9 | j_mayer | switch (fpfn) { /* f11 & 0x3F */ |
1386 | 4c9649a9 | j_mayer | case 0x04: |
1387 | 4c9649a9 | j_mayer | /* ITOFS */
|
1388 | 4c9649a9 | j_mayer | if (!(ctx->amask & AMASK_FIX))
|
1389 | 4c9649a9 | j_mayer | goto invalid_opc;
|
1390 | f18cd223 | aurel32 | if (likely(rc != 31)) { |
1391 | f18cd223 | aurel32 | if (ra != 31) { |
1392 | a7812ae4 | pbrook | TCGv_i32 tmp = tcg_temp_new_i32(); |
1393 | f18cd223 | aurel32 | tcg_gen_trunc_i64_i32(tmp, cpu_ir[ra]); |
1394 | a7812ae4 | pbrook | gen_helper_memory_to_s(cpu_fir[rc], tmp); |
1395 | a7812ae4 | pbrook | tcg_temp_free_i32(tmp); |
1396 | f18cd223 | aurel32 | } else
|
1397 | f18cd223 | aurel32 | tcg_gen_movi_i64(cpu_fir[rc], 0);
|
1398 | f18cd223 | aurel32 | } |
1399 | 4c9649a9 | j_mayer | break;
|
1400 | 4c9649a9 | j_mayer | case 0x0A: |
1401 | 4c9649a9 | j_mayer | /* SQRTF */
|
1402 | 4c9649a9 | j_mayer | if (!(ctx->amask & AMASK_FIX))
|
1403 | 4c9649a9 | j_mayer | goto invalid_opc;
|
1404 | a7812ae4 | pbrook | gen_fsqrtf(rb, rc); |
1405 | 4c9649a9 | j_mayer | break;
|
1406 | 4c9649a9 | j_mayer | case 0x0B: |
1407 | 4c9649a9 | j_mayer | /* SQRTS */
|
1408 | 4c9649a9 | j_mayer | if (!(ctx->amask & AMASK_FIX))
|
1409 | 4c9649a9 | j_mayer | goto invalid_opc;
|
1410 | a7812ae4 | pbrook | gen_fsqrts(rb, rc); |
1411 | 4c9649a9 | j_mayer | break;
|
1412 | 4c9649a9 | j_mayer | case 0x14: |
1413 | 4c9649a9 | j_mayer | /* ITOFF */
|
1414 | 4c9649a9 | j_mayer | if (!(ctx->amask & AMASK_FIX))
|
1415 | 4c9649a9 | j_mayer | goto invalid_opc;
|
1416 | f18cd223 | aurel32 | if (likely(rc != 31)) { |
1417 | f18cd223 | aurel32 | if (ra != 31) { |
1418 | a7812ae4 | pbrook | TCGv_i32 tmp = tcg_temp_new_i32(); |
1419 | f18cd223 | aurel32 | tcg_gen_trunc_i64_i32(tmp, cpu_ir[ra]); |
1420 | a7812ae4 | pbrook | gen_helper_memory_to_f(cpu_fir[rc], tmp); |
1421 | a7812ae4 | pbrook | tcg_temp_free_i32(tmp); |
1422 | f18cd223 | aurel32 | } else
|
1423 | f18cd223 | aurel32 | tcg_gen_movi_i64(cpu_fir[rc], 0);
|
1424 | f18cd223 | aurel32 | } |
1425 | 4c9649a9 | j_mayer | break;
|
1426 | 4c9649a9 | j_mayer | case 0x24: |
1427 | 4c9649a9 | j_mayer | /* ITOFT */
|
1428 | 4c9649a9 | j_mayer | if (!(ctx->amask & AMASK_FIX))
|
1429 | 4c9649a9 | j_mayer | goto invalid_opc;
|
1430 | f18cd223 | aurel32 | if (likely(rc != 31)) { |
1431 | f18cd223 | aurel32 | if (ra != 31) |
1432 | f18cd223 | aurel32 | tcg_gen_mov_i64(cpu_fir[rc], cpu_ir[ra]); |
1433 | f18cd223 | aurel32 | else
|
1434 | f18cd223 | aurel32 | tcg_gen_movi_i64(cpu_fir[rc], 0);
|
1435 | f18cd223 | aurel32 | } |
1436 | 4c9649a9 | j_mayer | break;
|
1437 | 4c9649a9 | j_mayer | case 0x2A: |
1438 | 4c9649a9 | j_mayer | /* SQRTG */
|
1439 | 4c9649a9 | j_mayer | if (!(ctx->amask & AMASK_FIX))
|
1440 | 4c9649a9 | j_mayer | goto invalid_opc;
|
1441 | a7812ae4 | pbrook | gen_fsqrtg(rb, rc); |
1442 | 4c9649a9 | j_mayer | break;
|
1443 | 4c9649a9 | j_mayer | case 0x02B: |
1444 | 4c9649a9 | j_mayer | /* SQRTT */
|
1445 | 4c9649a9 | j_mayer | if (!(ctx->amask & AMASK_FIX))
|
1446 | 4c9649a9 | j_mayer | goto invalid_opc;
|
1447 | a7812ae4 | pbrook | gen_fsqrtt(rb, rc); |
1448 | 4c9649a9 | j_mayer | break;
|
1449 | 4c9649a9 | j_mayer | default:
|
1450 | 4c9649a9 | j_mayer | goto invalid_opc;
|
1451 | 4c9649a9 | j_mayer | } |
1452 | 4c9649a9 | j_mayer | break;
|
1453 | 4c9649a9 | j_mayer | case 0x15: |
1454 | 4c9649a9 | j_mayer | /* VAX floating point */
|
1455 | 4c9649a9 | j_mayer | /* XXX: rounding mode and trap are ignored (!) */
|
1456 | 4c9649a9 | j_mayer | switch (fpfn) { /* f11 & 0x3F */ |
1457 | 4c9649a9 | j_mayer | case 0x00: |
1458 | 4c9649a9 | j_mayer | /* ADDF */
|
1459 | a7812ae4 | pbrook | gen_faddf(ra, rb, rc); |
1460 | 4c9649a9 | j_mayer | break;
|
1461 | 4c9649a9 | j_mayer | case 0x01: |
1462 | 4c9649a9 | j_mayer | /* SUBF */
|
1463 | a7812ae4 | pbrook | gen_fsubf(ra, rb, rc); |
1464 | 4c9649a9 | j_mayer | break;
|
1465 | 4c9649a9 | j_mayer | case 0x02: |
1466 | 4c9649a9 | j_mayer | /* MULF */
|
1467 | a7812ae4 | pbrook | gen_fmulf(ra, rb, rc); |
1468 | 4c9649a9 | j_mayer | break;
|
1469 | 4c9649a9 | j_mayer | case 0x03: |
1470 | 4c9649a9 | j_mayer | /* DIVF */
|
1471 | a7812ae4 | pbrook | gen_fdivf(ra, rb, rc); |
1472 | 4c9649a9 | j_mayer | break;
|
1473 | 4c9649a9 | j_mayer | case 0x1E: |
1474 | 4c9649a9 | j_mayer | /* CVTDG */
|
1475 | 4c9649a9 | j_mayer | #if 0 // TODO
|
1476 | a7812ae4 | pbrook | gen_fcvtdg(rb, rc);
|
1477 | 4c9649a9 | j_mayer | #else
|
1478 | 4c9649a9 | j_mayer | goto invalid_opc;
|
1479 | 4c9649a9 | j_mayer | #endif
|
1480 | 4c9649a9 | j_mayer | break;
|
1481 | 4c9649a9 | j_mayer | case 0x20: |
1482 | 4c9649a9 | j_mayer | /* ADDG */
|
1483 | a7812ae4 | pbrook | gen_faddg(ra, rb, rc); |
1484 | 4c9649a9 | j_mayer | break;
|
1485 | 4c9649a9 | j_mayer | case 0x21: |
1486 | 4c9649a9 | j_mayer | /* SUBG */
|
1487 | a7812ae4 | pbrook | gen_fsubg(ra, rb, rc); |
1488 | 4c9649a9 | j_mayer | break;
|
1489 | 4c9649a9 | j_mayer | case 0x22: |
1490 | 4c9649a9 | j_mayer | /* MULG */
|
1491 | a7812ae4 | pbrook | gen_fmulg(ra, rb, rc); |
1492 | 4c9649a9 | j_mayer | break;
|
1493 | 4c9649a9 | j_mayer | case 0x23: |
1494 | 4c9649a9 | j_mayer | /* DIVG */
|
1495 | a7812ae4 | pbrook | gen_fdivg(ra, rb, rc); |
1496 | 4c9649a9 | j_mayer | break;
|
1497 | 4c9649a9 | j_mayer | case 0x25: |
1498 | 4c9649a9 | j_mayer | /* CMPGEQ */
|
1499 | a7812ae4 | pbrook | gen_fcmpgeq(ra, rb, rc); |
1500 | 4c9649a9 | j_mayer | break;
|
1501 | 4c9649a9 | j_mayer | case 0x26: |
1502 | 4c9649a9 | j_mayer | /* CMPGLT */
|
1503 | a7812ae4 | pbrook | gen_fcmpglt(ra, rb, rc); |
1504 | 4c9649a9 | j_mayer | break;
|
1505 | 4c9649a9 | j_mayer | case 0x27: |
1506 | 4c9649a9 | j_mayer | /* CMPGLE */
|
1507 | a7812ae4 | pbrook | gen_fcmpgle(ra, rb, rc); |
1508 | 4c9649a9 | j_mayer | break;
|
1509 | 4c9649a9 | j_mayer | case 0x2C: |
1510 | 4c9649a9 | j_mayer | /* CVTGF */
|
1511 | a7812ae4 | pbrook | gen_fcvtgf(rb, rc); |
1512 | 4c9649a9 | j_mayer | break;
|
1513 | 4c9649a9 | j_mayer | case 0x2D: |
1514 | 4c9649a9 | j_mayer | /* CVTGD */
|
1515 | 4c9649a9 | j_mayer | #if 0 // TODO
|
1516 | a7812ae4 | pbrook | gen_fcvtgd(rb, rc);
|
1517 | 4c9649a9 | j_mayer | #else
|
1518 | 4c9649a9 | j_mayer | goto invalid_opc;
|
1519 | 4c9649a9 | j_mayer | #endif
|
1520 | 4c9649a9 | j_mayer | break;
|
1521 | 4c9649a9 | j_mayer | case 0x2F: |
1522 | 4c9649a9 | j_mayer | /* CVTGQ */
|
1523 | a7812ae4 | pbrook | gen_fcvtgq(rb, rc); |
1524 | 4c9649a9 | j_mayer | break;
|
1525 | 4c9649a9 | j_mayer | case 0x3C: |
1526 | 4c9649a9 | j_mayer | /* CVTQF */
|
1527 | a7812ae4 | pbrook | gen_fcvtqf(rb, rc); |
1528 | 4c9649a9 | j_mayer | break;
|
1529 | 4c9649a9 | j_mayer | case 0x3E: |
1530 | 4c9649a9 | j_mayer | /* CVTQG */
|
1531 | a7812ae4 | pbrook | gen_fcvtqg(rb, rc); |
1532 | 4c9649a9 | j_mayer | break;
|
1533 | 4c9649a9 | j_mayer | default:
|
1534 | 4c9649a9 | j_mayer | goto invalid_opc;
|
1535 | 4c9649a9 | j_mayer | } |
1536 | 4c9649a9 | j_mayer | break;
|
1537 | 4c9649a9 | j_mayer | case 0x16: |
1538 | 4c9649a9 | j_mayer | /* IEEE floating-point */
|
1539 | 4c9649a9 | j_mayer | /* XXX: rounding mode and traps are ignored (!) */
|
1540 | 4c9649a9 | j_mayer | switch (fpfn) { /* f11 & 0x3F */ |
1541 | 4c9649a9 | j_mayer | case 0x00: |
1542 | 4c9649a9 | j_mayer | /* ADDS */
|
1543 | a7812ae4 | pbrook | gen_fadds(ra, rb, rc); |
1544 | 4c9649a9 | j_mayer | break;
|
1545 | 4c9649a9 | j_mayer | case 0x01: |
1546 | 4c9649a9 | j_mayer | /* SUBS */
|
1547 | a7812ae4 | pbrook | gen_fsubs(ra, rb, rc); |
1548 | 4c9649a9 | j_mayer | break;
|
1549 | 4c9649a9 | j_mayer | case 0x02: |
1550 | 4c9649a9 | j_mayer | /* MULS */
|
1551 | a7812ae4 | pbrook | gen_fmuls(ra, rb, rc); |
1552 | 4c9649a9 | j_mayer | break;
|
1553 | 4c9649a9 | j_mayer | case 0x03: |
1554 | 4c9649a9 | j_mayer | /* DIVS */
|
1555 | a7812ae4 | pbrook | gen_fdivs(ra, rb, rc); |
1556 | 4c9649a9 | j_mayer | break;
|
1557 | 4c9649a9 | j_mayer | case 0x20: |
1558 | 4c9649a9 | j_mayer | /* ADDT */
|
1559 | a7812ae4 | pbrook | gen_faddt(ra, rb, rc); |
1560 | 4c9649a9 | j_mayer | break;
|
1561 | 4c9649a9 | j_mayer | case 0x21: |
1562 | 4c9649a9 | j_mayer | /* SUBT */
|
1563 | a7812ae4 | pbrook | gen_fsubt(ra, rb, rc); |
1564 | 4c9649a9 | j_mayer | break;
|
1565 | 4c9649a9 | j_mayer | case 0x22: |
1566 | 4c9649a9 | j_mayer | /* MULT */
|
1567 | a7812ae4 | pbrook | gen_fmult(ra, rb, rc); |
1568 | 4c9649a9 | j_mayer | break;
|
1569 | 4c9649a9 | j_mayer | case 0x23: |
1570 | 4c9649a9 | j_mayer | /* DIVT */
|
1571 | a7812ae4 | pbrook | gen_fdivt(ra, rb, rc); |
1572 | 4c9649a9 | j_mayer | break;
|
1573 | 4c9649a9 | j_mayer | case 0x24: |
1574 | 4c9649a9 | j_mayer | /* CMPTUN */
|
1575 | a7812ae4 | pbrook | gen_fcmptun(ra, rb, rc); |
1576 | 4c9649a9 | j_mayer | break;
|
1577 | 4c9649a9 | j_mayer | case 0x25: |
1578 | 4c9649a9 | j_mayer | /* CMPTEQ */
|
1579 | a7812ae4 | pbrook | gen_fcmpteq(ra, rb, rc); |
1580 | 4c9649a9 | j_mayer | break;
|
1581 | 4c9649a9 | j_mayer | case 0x26: |
1582 | 4c9649a9 | j_mayer | /* CMPTLT */
|
1583 | a7812ae4 | pbrook | gen_fcmptlt(ra, rb, rc); |
1584 | 4c9649a9 | j_mayer | break;
|
1585 | 4c9649a9 | j_mayer | case 0x27: |
1586 | 4c9649a9 | j_mayer | /* CMPTLE */
|
1587 | a7812ae4 | pbrook | gen_fcmptle(ra, rb, rc); |
1588 | 4c9649a9 | j_mayer | break;
|
1589 | 4c9649a9 | j_mayer | case 0x2C: |
1590 | 4c9649a9 | j_mayer | /* XXX: incorrect */
|
1591 | a74b4d2c | aurel32 | if (fn11 == 0x2AC || fn11 == 0x6AC) { |
1592 | 4c9649a9 | j_mayer | /* CVTST */
|
1593 | a7812ae4 | pbrook | gen_fcvtst(rb, rc); |
1594 | 4c9649a9 | j_mayer | } else {
|
1595 | 4c9649a9 | j_mayer | /* CVTTS */
|
1596 | a7812ae4 | pbrook | gen_fcvtts(rb, rc); |
1597 | 4c9649a9 | j_mayer | } |
1598 | 4c9649a9 | j_mayer | break;
|
1599 | 4c9649a9 | j_mayer | case 0x2F: |
1600 | 4c9649a9 | j_mayer | /* CVTTQ */
|
1601 | a7812ae4 | pbrook | gen_fcvttq(rb, rc); |
1602 | 4c9649a9 | j_mayer | break;
|
1603 | 4c9649a9 | j_mayer | case 0x3C: |
1604 | 4c9649a9 | j_mayer | /* CVTQS */
|
1605 | a7812ae4 | pbrook | gen_fcvtqs(rb, rc); |
1606 | 4c9649a9 | j_mayer | break;
|
1607 | 4c9649a9 | j_mayer | case 0x3E: |
1608 | 4c9649a9 | j_mayer | /* CVTQT */
|
1609 | a7812ae4 | pbrook | gen_fcvtqt(rb, rc); |
1610 | 4c9649a9 | j_mayer | break;
|
1611 | 4c9649a9 | j_mayer | default:
|
1612 | 4c9649a9 | j_mayer | goto invalid_opc;
|
1613 | 4c9649a9 | j_mayer | } |
1614 | 4c9649a9 | j_mayer | break;
|
1615 | 4c9649a9 | j_mayer | case 0x17: |
1616 | 4c9649a9 | j_mayer | switch (fn11) {
|
1617 | 4c9649a9 | j_mayer | case 0x010: |
1618 | 4c9649a9 | j_mayer | /* CVTLQ */
|
1619 | a7812ae4 | pbrook | gen_fcvtlq(rb, rc); |
1620 | 4c9649a9 | j_mayer | break;
|
1621 | 4c9649a9 | j_mayer | case 0x020: |
1622 | f18cd223 | aurel32 | if (likely(rc != 31)) { |
1623 | f18cd223 | aurel32 | if (ra == rb)
|
1624 | 4c9649a9 | j_mayer | /* FMOV */
|
1625 | f18cd223 | aurel32 | tcg_gen_mov_i64(cpu_fir[rc], cpu_fir[ra]); |
1626 | f18cd223 | aurel32 | else
|
1627 | f18cd223 | aurel32 | /* CPYS */
|
1628 | a7812ae4 | pbrook | gen_fcpys(ra, rb, rc); |
1629 | 4c9649a9 | j_mayer | } |
1630 | 4c9649a9 | j_mayer | break;
|
1631 | 4c9649a9 | j_mayer | case 0x021: |
1632 | 4c9649a9 | j_mayer | /* CPYSN */
|
1633 | a7812ae4 | pbrook | gen_fcpysn(ra, rb, rc); |
1634 | 4c9649a9 | j_mayer | break;
|
1635 | 4c9649a9 | j_mayer | case 0x022: |
1636 | 4c9649a9 | j_mayer | /* CPYSE */
|
1637 | a7812ae4 | pbrook | gen_fcpyse(ra, rb, rc); |
1638 | 4c9649a9 | j_mayer | break;
|
1639 | 4c9649a9 | j_mayer | case 0x024: |
1640 | 4c9649a9 | j_mayer | /* MT_FPCR */
|
1641 | f18cd223 | aurel32 | if (likely(ra != 31)) |
1642 | a7812ae4 | pbrook | gen_helper_store_fpcr(cpu_fir[ra]); |
1643 | f18cd223 | aurel32 | else {
|
1644 | f18cd223 | aurel32 | TCGv tmp = tcg_const_i64(0);
|
1645 | a7812ae4 | pbrook | gen_helper_store_fpcr(tmp); |
1646 | f18cd223 | aurel32 | tcg_temp_free(tmp); |
1647 | f18cd223 | aurel32 | } |
1648 | 4c9649a9 | j_mayer | break;
|
1649 | 4c9649a9 | j_mayer | case 0x025: |
1650 | 4c9649a9 | j_mayer | /* MF_FPCR */
|
1651 | f18cd223 | aurel32 | if (likely(ra != 31)) |
1652 | a7812ae4 | pbrook | gen_helper_load_fpcr(cpu_fir[ra]); |
1653 | 4c9649a9 | j_mayer | break;
|
1654 | 4c9649a9 | j_mayer | case 0x02A: |
1655 | 4c9649a9 | j_mayer | /* FCMOVEQ */
|
1656 | a7812ae4 | pbrook | gen_fcmpfeq(ra, rb, rc); |
1657 | 4c9649a9 | j_mayer | break;
|
1658 | 4c9649a9 | j_mayer | case 0x02B: |
1659 | 4c9649a9 | j_mayer | /* FCMOVNE */
|
1660 | a7812ae4 | pbrook | gen_fcmpfne(ra, rb, rc); |
1661 | 4c9649a9 | j_mayer | break;
|
1662 | 4c9649a9 | j_mayer | case 0x02C: |
1663 | 4c9649a9 | j_mayer | /* FCMOVLT */
|
1664 | a7812ae4 | pbrook | gen_fcmpflt(ra, rb, rc); |
1665 | 4c9649a9 | j_mayer | break;
|
1666 | 4c9649a9 | j_mayer | case 0x02D: |
1667 | 4c9649a9 | j_mayer | /* FCMOVGE */
|
1668 | a7812ae4 | pbrook | gen_fcmpfge(ra, rb, rc); |
1669 | 4c9649a9 | j_mayer | break;
|
1670 | 4c9649a9 | j_mayer | case 0x02E: |
1671 | 4c9649a9 | j_mayer | /* FCMOVLE */
|
1672 | a7812ae4 | pbrook | gen_fcmpfle(ra, rb, rc); |
1673 | 4c9649a9 | j_mayer | break;
|
1674 | 4c9649a9 | j_mayer | case 0x02F: |
1675 | 4c9649a9 | j_mayer | /* FCMOVGT */
|
1676 | a7812ae4 | pbrook | gen_fcmpfgt(ra, rb, rc); |
1677 | 4c9649a9 | j_mayer | break;
|
1678 | 4c9649a9 | j_mayer | case 0x030: |
1679 | 4c9649a9 | j_mayer | /* CVTQL */
|
1680 | a7812ae4 | pbrook | gen_fcvtql(rb, rc); |
1681 | 4c9649a9 | j_mayer | break;
|
1682 | 4c9649a9 | j_mayer | case 0x130: |
1683 | 4c9649a9 | j_mayer | /* CVTQL/V */
|
1684 | a7812ae4 | pbrook | gen_fcvtqlv(rb, rc); |
1685 | 4c9649a9 | j_mayer | break;
|
1686 | 4c9649a9 | j_mayer | case 0x530: |
1687 | 4c9649a9 | j_mayer | /* CVTQL/SV */
|
1688 | a7812ae4 | pbrook | gen_fcvtqlsv(rb, rc); |
1689 | 4c9649a9 | j_mayer | break;
|
1690 | 4c9649a9 | j_mayer | default:
|
1691 | 4c9649a9 | j_mayer | goto invalid_opc;
|
1692 | 4c9649a9 | j_mayer | } |
1693 | 4c9649a9 | j_mayer | break;
|
1694 | 4c9649a9 | j_mayer | case 0x18: |
1695 | 4c9649a9 | j_mayer | switch ((uint16_t)disp16) {
|
1696 | 4c9649a9 | j_mayer | case 0x0000: |
1697 | 4c9649a9 | j_mayer | /* TRAPB */
|
1698 | 4c9649a9 | j_mayer | /* No-op. Just exit from the current tb */
|
1699 | 4c9649a9 | j_mayer | ret = 2;
|
1700 | 4c9649a9 | j_mayer | break;
|
1701 | 4c9649a9 | j_mayer | case 0x0400: |
1702 | 4c9649a9 | j_mayer | /* EXCB */
|
1703 | 4c9649a9 | j_mayer | /* No-op. Just exit from the current tb */
|
1704 | 4c9649a9 | j_mayer | ret = 2;
|
1705 | 4c9649a9 | j_mayer | break;
|
1706 | 4c9649a9 | j_mayer | case 0x4000: |
1707 | 4c9649a9 | j_mayer | /* MB */
|
1708 | 4c9649a9 | j_mayer | /* No-op */
|
1709 | 4c9649a9 | j_mayer | break;
|
1710 | 4c9649a9 | j_mayer | case 0x4400: |
1711 | 4c9649a9 | j_mayer | /* WMB */
|
1712 | 4c9649a9 | j_mayer | /* No-op */
|
1713 | 4c9649a9 | j_mayer | break;
|
1714 | 4c9649a9 | j_mayer | case 0x8000: |
1715 | 4c9649a9 | j_mayer | /* FETCH */
|
1716 | 4c9649a9 | j_mayer | /* No-op */
|
1717 | 4c9649a9 | j_mayer | break;
|
1718 | 4c9649a9 | j_mayer | case 0xA000: |
1719 | 4c9649a9 | j_mayer | /* FETCH_M */
|
1720 | 4c9649a9 | j_mayer | /* No-op */
|
1721 | 4c9649a9 | j_mayer | break;
|
1722 | 4c9649a9 | j_mayer | case 0xC000: |
1723 | 4c9649a9 | j_mayer | /* RPCC */
|
1724 | 3761035f | aurel32 | if (ra != 31) |
1725 | a7812ae4 | pbrook | gen_helper_load_pcc(cpu_ir[ra]); |
1726 | 4c9649a9 | j_mayer | break;
|
1727 | 4c9649a9 | j_mayer | case 0xE000: |
1728 | 4c9649a9 | j_mayer | /* RC */
|
1729 | 3761035f | aurel32 | if (ra != 31) |
1730 | a7812ae4 | pbrook | gen_helper_rc(cpu_ir[ra]); |
1731 | 4c9649a9 | j_mayer | break;
|
1732 | 4c9649a9 | j_mayer | case 0xE800: |
1733 | 4c9649a9 | j_mayer | /* ECB */
|
1734 | 4c9649a9 | j_mayer | break;
|
1735 | 4c9649a9 | j_mayer | case 0xF000: |
1736 | 4c9649a9 | j_mayer | /* RS */
|
1737 | 3761035f | aurel32 | if (ra != 31) |
1738 | a7812ae4 | pbrook | gen_helper_rs(cpu_ir[ra]); |
1739 | 4c9649a9 | j_mayer | break;
|
1740 | 4c9649a9 | j_mayer | case 0xF800: |
1741 | 4c9649a9 | j_mayer | /* WH64 */
|
1742 | 4c9649a9 | j_mayer | /* No-op */
|
1743 | 4c9649a9 | j_mayer | break;
|
1744 | 4c9649a9 | j_mayer | default:
|
1745 | 4c9649a9 | j_mayer | goto invalid_opc;
|
1746 | 4c9649a9 | j_mayer | } |
1747 | 4c9649a9 | j_mayer | break;
|
1748 | 4c9649a9 | j_mayer | case 0x19: |
1749 | 4c9649a9 | j_mayer | /* HW_MFPR (PALcode) */
|
1750 | 4c9649a9 | j_mayer | #if defined (CONFIG_USER_ONLY)
|
1751 | 4c9649a9 | j_mayer | goto invalid_opc;
|
1752 | 4c9649a9 | j_mayer | #else
|
1753 | 4c9649a9 | j_mayer | if (!ctx->pal_mode)
|
1754 | 4c9649a9 | j_mayer | goto invalid_opc;
|
1755 | 8bb6e981 | aurel32 | if (ra != 31) { |
1756 | 8bb6e981 | aurel32 | TCGv tmp = tcg_const_i32(insn & 0xFF);
|
1757 | a7812ae4 | pbrook | gen_helper_mfpr(cpu_ir[ra], tmp, cpu_ir[ra]); |
1758 | 8bb6e981 | aurel32 | tcg_temp_free(tmp); |
1759 | 8bb6e981 | aurel32 | } |
1760 | 4c9649a9 | j_mayer | break;
|
1761 | 4c9649a9 | j_mayer | #endif
|
1762 | 4c9649a9 | j_mayer | case 0x1A: |
1763 | 3761035f | aurel32 | if (rb != 31) |
1764 | 3761035f | aurel32 | tcg_gen_andi_i64(cpu_pc, cpu_ir[rb], ~3);
|
1765 | 3761035f | aurel32 | else
|
1766 | 3761035f | aurel32 | tcg_gen_movi_i64(cpu_pc, 0);
|
1767 | 1304ca87 | aurel32 | if (ra != 31) |
1768 | 1304ca87 | aurel32 | tcg_gen_movi_i64(cpu_ir[ra], ctx->pc); |
1769 | 4c9649a9 | j_mayer | /* Those four jumps only differ by the branch prediction hint */
|
1770 | 4c9649a9 | j_mayer | switch (fn2) {
|
1771 | 4c9649a9 | j_mayer | case 0x0: |
1772 | 4c9649a9 | j_mayer | /* JMP */
|
1773 | 4c9649a9 | j_mayer | break;
|
1774 | 4c9649a9 | j_mayer | case 0x1: |
1775 | 4c9649a9 | j_mayer | /* JSR */
|
1776 | 4c9649a9 | j_mayer | break;
|
1777 | 4c9649a9 | j_mayer | case 0x2: |
1778 | 4c9649a9 | j_mayer | /* RET */
|
1779 | 4c9649a9 | j_mayer | break;
|
1780 | 4c9649a9 | j_mayer | case 0x3: |
1781 | 4c9649a9 | j_mayer | /* JSR_COROUTINE */
|
1782 | 4c9649a9 | j_mayer | break;
|
1783 | 4c9649a9 | j_mayer | } |
1784 | 4c9649a9 | j_mayer | ret = 1;
|
1785 | 4c9649a9 | j_mayer | break;
|
1786 | 4c9649a9 | j_mayer | case 0x1B: |
1787 | 4c9649a9 | j_mayer | /* HW_LD (PALcode) */
|
1788 | 4c9649a9 | j_mayer | #if defined (CONFIG_USER_ONLY)
|
1789 | 4c9649a9 | j_mayer | goto invalid_opc;
|
1790 | 4c9649a9 | j_mayer | #else
|
1791 | 4c9649a9 | j_mayer | if (!ctx->pal_mode)
|
1792 | 4c9649a9 | j_mayer | goto invalid_opc;
|
1793 | 8bb6e981 | aurel32 | if (ra != 31) { |
1794 | a7812ae4 | pbrook | TCGv addr = tcg_temp_new(); |
1795 | 8bb6e981 | aurel32 | if (rb != 31) |
1796 | 8bb6e981 | aurel32 | tcg_gen_addi_i64(addr, cpu_ir[rb], disp12); |
1797 | 8bb6e981 | aurel32 | else
|
1798 | 8bb6e981 | aurel32 | tcg_gen_movi_i64(addr, disp12); |
1799 | 8bb6e981 | aurel32 | switch ((insn >> 12) & 0xF) { |
1800 | 8bb6e981 | aurel32 | case 0x0: |
1801 | b5d51029 | aurel32 | /* Longword physical access (hw_ldl/p) */
|
1802 | a7812ae4 | pbrook | gen_helper_ldl_raw(cpu_ir[ra], addr); |
1803 | 8bb6e981 | aurel32 | break;
|
1804 | 8bb6e981 | aurel32 | case 0x1: |
1805 | b5d51029 | aurel32 | /* Quadword physical access (hw_ldq/p) */
|
1806 | a7812ae4 | pbrook | gen_helper_ldq_raw(cpu_ir[ra], addr); |
1807 | 8bb6e981 | aurel32 | break;
|
1808 | 8bb6e981 | aurel32 | case 0x2: |
1809 | b5d51029 | aurel32 | /* Longword physical access with lock (hw_ldl_l/p) */
|
1810 | a7812ae4 | pbrook | gen_helper_ldl_l_raw(cpu_ir[ra], addr); |
1811 | 8bb6e981 | aurel32 | break;
|
1812 | 8bb6e981 | aurel32 | case 0x3: |
1813 | b5d51029 | aurel32 | /* Quadword physical access with lock (hw_ldq_l/p) */
|
1814 | a7812ae4 | pbrook | gen_helper_ldq_l_raw(cpu_ir[ra], addr); |
1815 | 8bb6e981 | aurel32 | break;
|
1816 | 8bb6e981 | aurel32 | case 0x4: |
1817 | b5d51029 | aurel32 | /* Longword virtual PTE fetch (hw_ldl/v) */
|
1818 | b5d51029 | aurel32 | tcg_gen_qemu_ld32s(cpu_ir[ra], addr, 0);
|
1819 | 8bb6e981 | aurel32 | break;
|
1820 | 8bb6e981 | aurel32 | case 0x5: |
1821 | b5d51029 | aurel32 | /* Quadword virtual PTE fetch (hw_ldq/v) */
|
1822 | b5d51029 | aurel32 | tcg_gen_qemu_ld64(cpu_ir[ra], addr, 0);
|
1823 | 8bb6e981 | aurel32 | break;
|
1824 | 8bb6e981 | aurel32 | case 0x6: |
1825 | 8bb6e981 | aurel32 | /* Incpu_ir[ra]id */
|
1826 | b5d51029 | aurel32 | goto invalid_opc;
|
1827 | 8bb6e981 | aurel32 | case 0x7: |
1828 | 8bb6e981 | aurel32 | /* Incpu_ir[ra]id */
|
1829 | b5d51029 | aurel32 | goto invalid_opc;
|
1830 | 8bb6e981 | aurel32 | case 0x8: |
1831 | b5d51029 | aurel32 | /* Longword virtual access (hw_ldl) */
|
1832 | a7812ae4 | pbrook | gen_helper_st_virt_to_phys(addr, addr); |
1833 | a7812ae4 | pbrook | gen_helper_ldl_raw(cpu_ir[ra], addr); |
1834 | 8bb6e981 | aurel32 | break;
|
1835 | 8bb6e981 | aurel32 | case 0x9: |
1836 | b5d51029 | aurel32 | /* Quadword virtual access (hw_ldq) */
|
1837 | a7812ae4 | pbrook | gen_helper_st_virt_to_phys(addr, addr); |
1838 | a7812ae4 | pbrook | gen_helper_ldq_raw(cpu_ir[ra], addr); |
1839 | 8bb6e981 | aurel32 | break;
|
1840 | 8bb6e981 | aurel32 | case 0xA: |
1841 | b5d51029 | aurel32 | /* Longword virtual access with protection check (hw_ldl/w) */
|
1842 | b5d51029 | aurel32 | tcg_gen_qemu_ld32s(cpu_ir[ra], addr, 0);
|
1843 | 8bb6e981 | aurel32 | break;
|
1844 | 8bb6e981 | aurel32 | case 0xB: |
1845 | b5d51029 | aurel32 | /* Quadword virtual access with protection check (hw_ldq/w) */
|
1846 | b5d51029 | aurel32 | tcg_gen_qemu_ld64(cpu_ir[ra], addr, 0);
|
1847 | 8bb6e981 | aurel32 | break;
|
1848 | 8bb6e981 | aurel32 | case 0xC: |
1849 | b5d51029 | aurel32 | /* Longword virtual access with alt access mode (hw_ldl/a)*/
|
1850 | a7812ae4 | pbrook | gen_helper_set_alt_mode(); |
1851 | a7812ae4 | pbrook | gen_helper_st_virt_to_phys(addr, addr); |
1852 | a7812ae4 | pbrook | gen_helper_ldl_raw(cpu_ir[ra], addr); |
1853 | a7812ae4 | pbrook | gen_helper_restore_mode(); |
1854 | 8bb6e981 | aurel32 | break;
|
1855 | 8bb6e981 | aurel32 | case 0xD: |
1856 | b5d51029 | aurel32 | /* Quadword virtual access with alt access mode (hw_ldq/a) */
|
1857 | a7812ae4 | pbrook | gen_helper_set_alt_mode(); |
1858 | a7812ae4 | pbrook | gen_helper_st_virt_to_phys(addr, addr); |
1859 | a7812ae4 | pbrook | gen_helper_ldq_raw(cpu_ir[ra], addr); |
1860 | a7812ae4 | pbrook | gen_helper_restore_mode(); |
1861 | 8bb6e981 | aurel32 | break;
|
1862 | 8bb6e981 | aurel32 | case 0xE: |
1863 | 8bb6e981 | aurel32 | /* Longword virtual access with alternate access mode and
|
1864 | b5d51029 | aurel32 | * protection checks (hw_ldl/wa)
|
1865 | 8bb6e981 | aurel32 | */
|
1866 | a7812ae4 | pbrook | gen_helper_set_alt_mode(); |
1867 | a7812ae4 | pbrook | gen_helper_ldl_data(cpu_ir[ra], addr); |
1868 | a7812ae4 | pbrook | gen_helper_restore_mode(); |
1869 | 8bb6e981 | aurel32 | break;
|
1870 | 8bb6e981 | aurel32 | case 0xF: |
1871 | 8bb6e981 | aurel32 | /* Quadword virtual access with alternate access mode and
|
1872 | b5d51029 | aurel32 | * protection checks (hw_ldq/wa)
|
1873 | 8bb6e981 | aurel32 | */
|
1874 | a7812ae4 | pbrook | gen_helper_set_alt_mode(); |
1875 | a7812ae4 | pbrook | gen_helper_ldq_data(cpu_ir[ra], addr); |
1876 | a7812ae4 | pbrook | gen_helper_restore_mode(); |
1877 | 8bb6e981 | aurel32 | break;
|
1878 | 8bb6e981 | aurel32 | } |
1879 | 8bb6e981 | aurel32 | tcg_temp_free(addr); |
1880 | 4c9649a9 | j_mayer | } |
1881 | 4c9649a9 | j_mayer | break;
|
1882 | 4c9649a9 | j_mayer | #endif
|
1883 | 4c9649a9 | j_mayer | case 0x1C: |
1884 | 4c9649a9 | j_mayer | switch (fn7) {
|
1885 | 4c9649a9 | j_mayer | case 0x00: |
1886 | 4c9649a9 | j_mayer | /* SEXTB */
|
1887 | 4c9649a9 | j_mayer | if (!(ctx->amask & AMASK_BWX))
|
1888 | 4c9649a9 | j_mayer | goto invalid_opc;
|
1889 | ae8ecd42 | aurel32 | if (likely(rc != 31)) { |
1890 | ae8ecd42 | aurel32 | if (islit)
|
1891 | ae8ecd42 | aurel32 | tcg_gen_movi_i64(cpu_ir[rc], (int64_t)((int8_t)lit)); |
1892 | ae8ecd42 | aurel32 | else
|
1893 | dfaa8583 | aurel32 | tcg_gen_ext8s_i64(cpu_ir[rc], cpu_ir[rb]); |
1894 | ae8ecd42 | aurel32 | } |
1895 | 4c9649a9 | j_mayer | break;
|
1896 | 4c9649a9 | j_mayer | case 0x01: |
1897 | 4c9649a9 | j_mayer | /* SEXTW */
|
1898 | 4c9649a9 | j_mayer | if (!(ctx->amask & AMASK_BWX))
|
1899 | 4c9649a9 | j_mayer | goto invalid_opc;
|
1900 | ae8ecd42 | aurel32 | if (likely(rc != 31)) { |
1901 | ae8ecd42 | aurel32 | if (islit)
|
1902 | ae8ecd42 | aurel32 | tcg_gen_movi_i64(cpu_ir[rc], (int64_t)((int16_t)lit)); |
1903 | ae8ecd42 | aurel32 | else
|
1904 | dfaa8583 | aurel32 | tcg_gen_ext16s_i64(cpu_ir[rc], cpu_ir[rb]); |
1905 | ae8ecd42 | aurel32 | } |
1906 | 4c9649a9 | j_mayer | break;
|
1907 | 4c9649a9 | j_mayer | case 0x30: |
1908 | 4c9649a9 | j_mayer | /* CTPOP */
|
1909 | 4c9649a9 | j_mayer | if (!(ctx->amask & AMASK_CIX))
|
1910 | 4c9649a9 | j_mayer | goto invalid_opc;
|
1911 | ae8ecd42 | aurel32 | if (likely(rc != 31)) { |
1912 | ae8ecd42 | aurel32 | if (islit)
|
1913 | ae8ecd42 | aurel32 | tcg_gen_movi_i64(cpu_ir[rc], ctpop64(lit)); |
1914 | ae8ecd42 | aurel32 | else
|
1915 | a7812ae4 | pbrook | gen_helper_ctpop(cpu_ir[rc], cpu_ir[rb]); |
1916 | ae8ecd42 | aurel32 | } |
1917 | 4c9649a9 | j_mayer | break;
|
1918 | 4c9649a9 | j_mayer | case 0x31: |
1919 | 4c9649a9 | j_mayer | /* PERR */
|
1920 | 4c9649a9 | j_mayer | if (!(ctx->amask & AMASK_MVI))
|
1921 | 4c9649a9 | j_mayer | goto invalid_opc;
|
1922 | 4c9649a9 | j_mayer | /* XXX: TODO */
|
1923 | 4c9649a9 | j_mayer | goto invalid_opc;
|
1924 | 4c9649a9 | j_mayer | break;
|
1925 | 4c9649a9 | j_mayer | case 0x32: |
1926 | 4c9649a9 | j_mayer | /* CTLZ */
|
1927 | 4c9649a9 | j_mayer | if (!(ctx->amask & AMASK_CIX))
|
1928 | 4c9649a9 | j_mayer | goto invalid_opc;
|
1929 | ae8ecd42 | aurel32 | if (likely(rc != 31)) { |
1930 | ae8ecd42 | aurel32 | if (islit)
|
1931 | ae8ecd42 | aurel32 | tcg_gen_movi_i64(cpu_ir[rc], clz64(lit)); |
1932 | ae8ecd42 | aurel32 | else
|
1933 | a7812ae4 | pbrook | gen_helper_ctlz(cpu_ir[rc], cpu_ir[rb]); |
1934 | ae8ecd42 | aurel32 | } |
1935 | 4c9649a9 | j_mayer | break;
|
1936 | 4c9649a9 | j_mayer | case 0x33: |
1937 | 4c9649a9 | j_mayer | /* CTTZ */
|
1938 | 4c9649a9 | j_mayer | if (!(ctx->amask & AMASK_CIX))
|
1939 | 4c9649a9 | j_mayer | goto invalid_opc;
|
1940 | ae8ecd42 | aurel32 | if (likely(rc != 31)) { |
1941 | ae8ecd42 | aurel32 | if (islit)
|
1942 | ae8ecd42 | aurel32 | tcg_gen_movi_i64(cpu_ir[rc], ctz64(lit)); |
1943 | ae8ecd42 | aurel32 | else
|
1944 | a7812ae4 | pbrook | gen_helper_cttz(cpu_ir[rc], cpu_ir[rb]); |
1945 | ae8ecd42 | aurel32 | } |
1946 | 4c9649a9 | j_mayer | break;
|
1947 | 4c9649a9 | j_mayer | case 0x34: |
1948 | 4c9649a9 | j_mayer | /* UNPKBW */
|
1949 | 4c9649a9 | j_mayer | if (!(ctx->amask & AMASK_MVI))
|
1950 | 4c9649a9 | j_mayer | goto invalid_opc;
|
1951 | 4c9649a9 | j_mayer | /* XXX: TODO */
|
1952 | 4c9649a9 | j_mayer | goto invalid_opc;
|
1953 | 4c9649a9 | j_mayer | break;
|
1954 | 4c9649a9 | j_mayer | case 0x35: |
1955 | 4c9649a9 | j_mayer | /* UNPKWL */
|
1956 | 4c9649a9 | j_mayer | if (!(ctx->amask & AMASK_MVI))
|
1957 | 4c9649a9 | j_mayer | goto invalid_opc;
|
1958 | 4c9649a9 | j_mayer | /* XXX: TODO */
|
1959 | 4c9649a9 | j_mayer | goto invalid_opc;
|
1960 | 4c9649a9 | j_mayer | break;
|
1961 | 4c9649a9 | j_mayer | case 0x36: |
1962 | 4c9649a9 | j_mayer | /* PKWB */
|
1963 | 4c9649a9 | j_mayer | if (!(ctx->amask & AMASK_MVI))
|
1964 | 4c9649a9 | j_mayer | goto invalid_opc;
|
1965 | 4c9649a9 | j_mayer | /* XXX: TODO */
|
1966 | 4c9649a9 | j_mayer | goto invalid_opc;
|
1967 | 4c9649a9 | j_mayer | break;
|
1968 | 4c9649a9 | j_mayer | case 0x37: |
1969 | 4c9649a9 | j_mayer | /* PKLB */
|
1970 | 4c9649a9 | j_mayer | if (!(ctx->amask & AMASK_MVI))
|
1971 | 4c9649a9 | j_mayer | goto invalid_opc;
|
1972 | 4c9649a9 | j_mayer | /* XXX: TODO */
|
1973 | 4c9649a9 | j_mayer | goto invalid_opc;
|
1974 | 4c9649a9 | j_mayer | break;
|
1975 | 4c9649a9 | j_mayer | case 0x38: |
1976 | 4c9649a9 | j_mayer | /* MINSB8 */
|
1977 | 4c9649a9 | j_mayer | if (!(ctx->amask & AMASK_MVI))
|
1978 | 4c9649a9 | j_mayer | goto invalid_opc;
|
1979 | 4c9649a9 | j_mayer | /* XXX: TODO */
|
1980 | 4c9649a9 | j_mayer | goto invalid_opc;
|
1981 | 4c9649a9 | j_mayer | break;
|
1982 | 4c9649a9 | j_mayer | case 0x39: |
1983 | 4c9649a9 | j_mayer | /* MINSW4 */
|
1984 | 4c9649a9 | j_mayer | if (!(ctx->amask & AMASK_MVI))
|
1985 | 4c9649a9 | j_mayer | goto invalid_opc;
|
1986 | 4c9649a9 | j_mayer | /* XXX: TODO */
|
1987 | 4c9649a9 | j_mayer | goto invalid_opc;
|
1988 | 4c9649a9 | j_mayer | break;
|
1989 | 4c9649a9 | j_mayer | case 0x3A: |
1990 | 4c9649a9 | j_mayer | /* MINUB8 */
|
1991 | 4c9649a9 | j_mayer | if (!(ctx->amask & AMASK_MVI))
|
1992 | 4c9649a9 | j_mayer | goto invalid_opc;
|
1993 | 4c9649a9 | j_mayer | /* XXX: TODO */
|
1994 | 4c9649a9 | j_mayer | goto invalid_opc;
|
1995 | 4c9649a9 | j_mayer | break;
|
1996 | 4c9649a9 | j_mayer | case 0x3B: |
1997 | 4c9649a9 | j_mayer | /* MINUW4 */
|
1998 | 4c9649a9 | j_mayer | if (!(ctx->amask & AMASK_MVI))
|
1999 | 4c9649a9 | j_mayer | goto invalid_opc;
|
2000 | 4c9649a9 | j_mayer | /* XXX: TODO */
|
2001 | 4c9649a9 | j_mayer | goto invalid_opc;
|
2002 | 4c9649a9 | j_mayer | break;
|
2003 | 4c9649a9 | j_mayer | case 0x3C: |
2004 | 4c9649a9 | j_mayer | /* MAXUB8 */
|
2005 | 4c9649a9 | j_mayer | if (!(ctx->amask & AMASK_MVI))
|
2006 | 4c9649a9 | j_mayer | goto invalid_opc;
|
2007 | 4c9649a9 | j_mayer | /* XXX: TODO */
|
2008 | 4c9649a9 | j_mayer | goto invalid_opc;
|
2009 | 4c9649a9 | j_mayer | break;
|
2010 | 4c9649a9 | j_mayer | case 0x3D: |
2011 | 4c9649a9 | j_mayer | /* MAXUW4 */
|
2012 | 4c9649a9 | j_mayer | if (!(ctx->amask & AMASK_MVI))
|
2013 | 4c9649a9 | j_mayer | goto invalid_opc;
|
2014 | 4c9649a9 | j_mayer | /* XXX: TODO */
|
2015 | 4c9649a9 | j_mayer | goto invalid_opc;
|
2016 | 4c9649a9 | j_mayer | break;
|
2017 | 4c9649a9 | j_mayer | case 0x3E: |
2018 | 4c9649a9 | j_mayer | /* MAXSB8 */
|
2019 | 4c9649a9 | j_mayer | if (!(ctx->amask & AMASK_MVI))
|
2020 | 4c9649a9 | j_mayer | goto invalid_opc;
|
2021 | 4c9649a9 | j_mayer | /* XXX: TODO */
|
2022 | 4c9649a9 | j_mayer | goto invalid_opc;
|
2023 | 4c9649a9 | j_mayer | break;
|
2024 | 4c9649a9 | j_mayer | case 0x3F: |
2025 | 4c9649a9 | j_mayer | /* MAXSW4 */
|
2026 | 4c9649a9 | j_mayer | if (!(ctx->amask & AMASK_MVI))
|
2027 | 4c9649a9 | j_mayer | goto invalid_opc;
|
2028 | 4c9649a9 | j_mayer | /* XXX: TODO */
|
2029 | 4c9649a9 | j_mayer | goto invalid_opc;
|
2030 | 4c9649a9 | j_mayer | break;
|
2031 | 4c9649a9 | j_mayer | case 0x70: |
2032 | 4c9649a9 | j_mayer | /* FTOIT */
|
2033 | 4c9649a9 | j_mayer | if (!(ctx->amask & AMASK_FIX))
|
2034 | 4c9649a9 | j_mayer | goto invalid_opc;
|
2035 | f18cd223 | aurel32 | if (likely(rc != 31)) { |
2036 | f18cd223 | aurel32 | if (ra != 31) |
2037 | f18cd223 | aurel32 | tcg_gen_mov_i64(cpu_ir[rc], cpu_fir[ra]); |
2038 | f18cd223 | aurel32 | else
|
2039 | f18cd223 | aurel32 | tcg_gen_movi_i64(cpu_ir[rc], 0);
|
2040 | f18cd223 | aurel32 | } |
2041 | 4c9649a9 | j_mayer | break;
|
2042 | 4c9649a9 | j_mayer | case 0x78: |
2043 | 4c9649a9 | j_mayer | /* FTOIS */
|
2044 | 4c9649a9 | j_mayer | if (!(ctx->amask & AMASK_FIX))
|
2045 | 4c9649a9 | j_mayer | goto invalid_opc;
|
2046 | f18cd223 | aurel32 | if (rc != 31) { |
2047 | a7812ae4 | pbrook | TCGv_i32 tmp1 = tcg_temp_new_i32(); |
2048 | f18cd223 | aurel32 | if (ra != 31) |
2049 | a7812ae4 | pbrook | gen_helper_s_to_memory(tmp1, cpu_fir[ra]); |
2050 | f18cd223 | aurel32 | else {
|
2051 | f18cd223 | aurel32 | TCGv tmp2 = tcg_const_i64(0);
|
2052 | a7812ae4 | pbrook | gen_helper_s_to_memory(tmp1, tmp2); |
2053 | f18cd223 | aurel32 | tcg_temp_free(tmp2); |
2054 | f18cd223 | aurel32 | } |
2055 | f18cd223 | aurel32 | tcg_gen_ext_i32_i64(cpu_ir[rc], tmp1); |
2056 | a7812ae4 | pbrook | tcg_temp_free_i32(tmp1); |
2057 | f18cd223 | aurel32 | } |
2058 | 4c9649a9 | j_mayer | break;
|
2059 | 4c9649a9 | j_mayer | default:
|
2060 | 4c9649a9 | j_mayer | goto invalid_opc;
|
2061 | 4c9649a9 | j_mayer | } |
2062 | 4c9649a9 | j_mayer | break;
|
2063 | 4c9649a9 | j_mayer | case 0x1D: |
2064 | 4c9649a9 | j_mayer | /* HW_MTPR (PALcode) */
|
2065 | 4c9649a9 | j_mayer | #if defined (CONFIG_USER_ONLY)
|
2066 | 4c9649a9 | j_mayer | goto invalid_opc;
|
2067 | 4c9649a9 | j_mayer | #else
|
2068 | 4c9649a9 | j_mayer | if (!ctx->pal_mode)
|
2069 | 4c9649a9 | j_mayer | goto invalid_opc;
|
2070 | 8bb6e981 | aurel32 | else {
|
2071 | 8bb6e981 | aurel32 | TCGv tmp1 = tcg_const_i32(insn & 0xFF);
|
2072 | 8bb6e981 | aurel32 | if (ra != 31) |
2073 | a7812ae4 | pbrook | gen_helper_mtpr(tmp1, cpu_ir[ra]); |
2074 | 8bb6e981 | aurel32 | else {
|
2075 | 8bb6e981 | aurel32 | TCGv tmp2 = tcg_const_i64(0);
|
2076 | a7812ae4 | pbrook | gen_helper_mtpr(tmp1, tmp2); |
2077 | 8bb6e981 | aurel32 | tcg_temp_free(tmp2); |
2078 | 8bb6e981 | aurel32 | } |
2079 | 8bb6e981 | aurel32 | tcg_temp_free(tmp1); |
2080 | 8bb6e981 | aurel32 | ret = 2;
|
2081 | 8bb6e981 | aurel32 | } |
2082 | 4c9649a9 | j_mayer | break;
|
2083 | 4c9649a9 | j_mayer | #endif
|
2084 | 4c9649a9 | j_mayer | case 0x1E: |
2085 | 4c9649a9 | j_mayer | /* HW_REI (PALcode) */
|
2086 | 4c9649a9 | j_mayer | #if defined (CONFIG_USER_ONLY)
|
2087 | 4c9649a9 | j_mayer | goto invalid_opc;
|
2088 | 4c9649a9 | j_mayer | #else
|
2089 | 4c9649a9 | j_mayer | if (!ctx->pal_mode)
|
2090 | 4c9649a9 | j_mayer | goto invalid_opc;
|
2091 | 4c9649a9 | j_mayer | if (rb == 31) { |
2092 | 4c9649a9 | j_mayer | /* "Old" alpha */
|
2093 | a7812ae4 | pbrook | gen_helper_hw_rei(); |
2094 | 4c9649a9 | j_mayer | } else {
|
2095 | 8bb6e981 | aurel32 | TCGv tmp; |
2096 | 8bb6e981 | aurel32 | |
2097 | 8bb6e981 | aurel32 | if (ra != 31) { |
2098 | a7812ae4 | pbrook | tmp = tcg_temp_new(); |
2099 | 8bb6e981 | aurel32 | tcg_gen_addi_i64(tmp, cpu_ir[rb], (((int64_t)insn << 51) >> 51)); |
2100 | 8bb6e981 | aurel32 | } else
|
2101 | 8bb6e981 | aurel32 | tmp = tcg_const_i64(((int64_t)insn << 51) >> 51); |
2102 | a7812ae4 | pbrook | gen_helper_hw_ret(tmp); |
2103 | 8bb6e981 | aurel32 | tcg_temp_free(tmp); |
2104 | 4c9649a9 | j_mayer | } |
2105 | 4c9649a9 | j_mayer | ret = 2;
|
2106 | 4c9649a9 | j_mayer | break;
|
2107 | 4c9649a9 | j_mayer | #endif
|
2108 | 4c9649a9 | j_mayer | case 0x1F: |
2109 | 4c9649a9 | j_mayer | /* HW_ST (PALcode) */
|
2110 | 4c9649a9 | j_mayer | #if defined (CONFIG_USER_ONLY)
|
2111 | 4c9649a9 | j_mayer | goto invalid_opc;
|
2112 | 4c9649a9 | j_mayer | #else
|
2113 | 4c9649a9 | j_mayer | if (!ctx->pal_mode)
|
2114 | 4c9649a9 | j_mayer | goto invalid_opc;
|
2115 | 8bb6e981 | aurel32 | else {
|
2116 | 8bb6e981 | aurel32 | TCGv addr, val; |
2117 | a7812ae4 | pbrook | addr = tcg_temp_new(); |
2118 | 8bb6e981 | aurel32 | if (rb != 31) |
2119 | 8bb6e981 | aurel32 | tcg_gen_addi_i64(addr, cpu_ir[rb], disp12); |
2120 | 8bb6e981 | aurel32 | else
|
2121 | 8bb6e981 | aurel32 | tcg_gen_movi_i64(addr, disp12); |
2122 | 8bb6e981 | aurel32 | if (ra != 31) |
2123 | 8bb6e981 | aurel32 | val = cpu_ir[ra]; |
2124 | 8bb6e981 | aurel32 | else {
|
2125 | a7812ae4 | pbrook | val = tcg_temp_new(); |
2126 | 8bb6e981 | aurel32 | tcg_gen_movi_i64(val, 0);
|
2127 | 8bb6e981 | aurel32 | } |
2128 | 8bb6e981 | aurel32 | switch ((insn >> 12) & 0xF) { |
2129 | 8bb6e981 | aurel32 | case 0x0: |
2130 | 8bb6e981 | aurel32 | /* Longword physical access */
|
2131 | a7812ae4 | pbrook | gen_helper_stl_raw(val, addr); |
2132 | 8bb6e981 | aurel32 | break;
|
2133 | 8bb6e981 | aurel32 | case 0x1: |
2134 | 8bb6e981 | aurel32 | /* Quadword physical access */
|
2135 | a7812ae4 | pbrook | gen_helper_stq_raw(val, addr); |
2136 | 8bb6e981 | aurel32 | break;
|
2137 | 8bb6e981 | aurel32 | case 0x2: |
2138 | 8bb6e981 | aurel32 | /* Longword physical access with lock */
|
2139 | a7812ae4 | pbrook | gen_helper_stl_c_raw(val, val, addr); |
2140 | 8bb6e981 | aurel32 | break;
|
2141 | 8bb6e981 | aurel32 | case 0x3: |
2142 | 8bb6e981 | aurel32 | /* Quadword physical access with lock */
|
2143 | a7812ae4 | pbrook | gen_helper_stq_c_raw(val, val, addr); |
2144 | 8bb6e981 | aurel32 | break;
|
2145 | 8bb6e981 | aurel32 | case 0x4: |
2146 | 8bb6e981 | aurel32 | /* Longword virtual access */
|
2147 | a7812ae4 | pbrook | gen_helper_st_virt_to_phys(addr, addr); |
2148 | a7812ae4 | pbrook | gen_helper_stl_raw(val, addr); |
2149 | 8bb6e981 | aurel32 | break;
|
2150 | 8bb6e981 | aurel32 | case 0x5: |
2151 | 8bb6e981 | aurel32 | /* Quadword virtual access */
|
2152 | a7812ae4 | pbrook | gen_helper_st_virt_to_phys(addr, addr); |
2153 | a7812ae4 | pbrook | gen_helper_stq_raw(val, addr); |
2154 | 8bb6e981 | aurel32 | break;
|
2155 | 8bb6e981 | aurel32 | case 0x6: |
2156 | 8bb6e981 | aurel32 | /* Invalid */
|
2157 | 8bb6e981 | aurel32 | goto invalid_opc;
|
2158 | 8bb6e981 | aurel32 | case 0x7: |
2159 | 8bb6e981 | aurel32 | /* Invalid */
|
2160 | 8bb6e981 | aurel32 | goto invalid_opc;
|
2161 | 8bb6e981 | aurel32 | case 0x8: |
2162 | 8bb6e981 | aurel32 | /* Invalid */
|
2163 | 8bb6e981 | aurel32 | goto invalid_opc;
|
2164 | 8bb6e981 | aurel32 | case 0x9: |
2165 | 8bb6e981 | aurel32 | /* Invalid */
|
2166 | 8bb6e981 | aurel32 | goto invalid_opc;
|
2167 | 8bb6e981 | aurel32 | case 0xA: |
2168 | 8bb6e981 | aurel32 | /* Invalid */
|
2169 | 8bb6e981 | aurel32 | goto invalid_opc;
|
2170 | 8bb6e981 | aurel32 | case 0xB: |
2171 | 8bb6e981 | aurel32 | /* Invalid */
|
2172 | 8bb6e981 | aurel32 | goto invalid_opc;
|
2173 | 8bb6e981 | aurel32 | case 0xC: |
2174 | 8bb6e981 | aurel32 | /* Longword virtual access with alternate access mode */
|
2175 | a7812ae4 | pbrook | gen_helper_set_alt_mode(); |
2176 | a7812ae4 | pbrook | gen_helper_st_virt_to_phys(addr, addr); |
2177 | a7812ae4 | pbrook | gen_helper_stl_raw(val, addr); |
2178 | a7812ae4 | pbrook | gen_helper_restore_mode(); |
2179 | 8bb6e981 | aurel32 | break;
|
2180 | 8bb6e981 | aurel32 | case 0xD: |
2181 | 8bb6e981 | aurel32 | /* Quadword virtual access with alternate access mode */
|
2182 | a7812ae4 | pbrook | gen_helper_set_alt_mode(); |
2183 | a7812ae4 | pbrook | gen_helper_st_virt_to_phys(addr, addr); |
2184 | a7812ae4 | pbrook | gen_helper_stl_raw(val, addr); |
2185 | a7812ae4 | pbrook | gen_helper_restore_mode(); |
2186 | 8bb6e981 | aurel32 | break;
|
2187 | 8bb6e981 | aurel32 | case 0xE: |
2188 | 8bb6e981 | aurel32 | /* Invalid */
|
2189 | 8bb6e981 | aurel32 | goto invalid_opc;
|
2190 | 8bb6e981 | aurel32 | case 0xF: |
2191 | 8bb6e981 | aurel32 | /* Invalid */
|
2192 | 8bb6e981 | aurel32 | goto invalid_opc;
|
2193 | 8bb6e981 | aurel32 | } |
2194 | 45d46ce8 | aurel32 | if (ra == 31) |
2195 | 8bb6e981 | aurel32 | tcg_temp_free(val); |
2196 | 8bb6e981 | aurel32 | tcg_temp_free(addr); |
2197 | 4c9649a9 | j_mayer | } |
2198 | 4c9649a9 | j_mayer | break;
|
2199 | 4c9649a9 | j_mayer | #endif
|
2200 | 4c9649a9 | j_mayer | case 0x20: |
2201 | 4c9649a9 | j_mayer | /* LDF */
|
2202 | f18cd223 | aurel32 | gen_load_mem(ctx, &gen_qemu_ldf, ra, rb, disp16, 1, 0); |
2203 | 4c9649a9 | j_mayer | break;
|
2204 | 4c9649a9 | j_mayer | case 0x21: |
2205 | 4c9649a9 | j_mayer | /* LDG */
|
2206 | f18cd223 | aurel32 | gen_load_mem(ctx, &gen_qemu_ldg, ra, rb, disp16, 1, 0); |
2207 | 4c9649a9 | j_mayer | break;
|
2208 | 4c9649a9 | j_mayer | case 0x22: |
2209 | 4c9649a9 | j_mayer | /* LDS */
|
2210 | f18cd223 | aurel32 | gen_load_mem(ctx, &gen_qemu_lds, ra, rb, disp16, 1, 0); |
2211 | 4c9649a9 | j_mayer | break;
|
2212 | 4c9649a9 | j_mayer | case 0x23: |
2213 | 4c9649a9 | j_mayer | /* LDT */
|
2214 | f18cd223 | aurel32 | gen_load_mem(ctx, &tcg_gen_qemu_ld64, ra, rb, disp16, 1, 0); |
2215 | 4c9649a9 | j_mayer | break;
|
2216 | 4c9649a9 | j_mayer | case 0x24: |
2217 | 4c9649a9 | j_mayer | /* STF */
|
2218 | 57a92c8e | aurel32 | gen_store_mem(ctx, &gen_qemu_stf, ra, rb, disp16, 1, 0, 0); |
2219 | 4c9649a9 | j_mayer | break;
|
2220 | 4c9649a9 | j_mayer | case 0x25: |
2221 | 4c9649a9 | j_mayer | /* STG */
|
2222 | 57a92c8e | aurel32 | gen_store_mem(ctx, &gen_qemu_stg, ra, rb, disp16, 1, 0, 0); |
2223 | 4c9649a9 | j_mayer | break;
|
2224 | 4c9649a9 | j_mayer | case 0x26: |
2225 | 4c9649a9 | j_mayer | /* STS */
|
2226 | 57a92c8e | aurel32 | gen_store_mem(ctx, &gen_qemu_sts, ra, rb, disp16, 1, 0, 0); |
2227 | 4c9649a9 | j_mayer | break;
|
2228 | 4c9649a9 | j_mayer | case 0x27: |
2229 | 4c9649a9 | j_mayer | /* STT */
|
2230 | 57a92c8e | aurel32 | gen_store_mem(ctx, &tcg_gen_qemu_st64, ra, rb, disp16, 1, 0, 0); |
2231 | 4c9649a9 | j_mayer | break;
|
2232 | 4c9649a9 | j_mayer | case 0x28: |
2233 | 4c9649a9 | j_mayer | /* LDL */
|
2234 | f18cd223 | aurel32 | gen_load_mem(ctx, &tcg_gen_qemu_ld32s, ra, rb, disp16, 0, 0); |
2235 | 4c9649a9 | j_mayer | break;
|
2236 | 4c9649a9 | j_mayer | case 0x29: |
2237 | 4c9649a9 | j_mayer | /* LDQ */
|
2238 | f18cd223 | aurel32 | gen_load_mem(ctx, &tcg_gen_qemu_ld64, ra, rb, disp16, 0, 0); |
2239 | 4c9649a9 | j_mayer | break;
|
2240 | 4c9649a9 | j_mayer | case 0x2A: |
2241 | 4c9649a9 | j_mayer | /* LDL_L */
|
2242 | f4ed8679 | aurel32 | gen_load_mem(ctx, &gen_qemu_ldl_l, ra, rb, disp16, 0, 0); |
2243 | 4c9649a9 | j_mayer | break;
|
2244 | 4c9649a9 | j_mayer | case 0x2B: |
2245 | 4c9649a9 | j_mayer | /* LDQ_L */
|
2246 | f4ed8679 | aurel32 | gen_load_mem(ctx, &gen_qemu_ldq_l, ra, rb, disp16, 0, 0); |
2247 | 4c9649a9 | j_mayer | break;
|
2248 | 4c9649a9 | j_mayer | case 0x2C: |
2249 | 4c9649a9 | j_mayer | /* STL */
|
2250 | 57a92c8e | aurel32 | gen_store_mem(ctx, &tcg_gen_qemu_st32, ra, rb, disp16, 0, 0, 0); |
2251 | 4c9649a9 | j_mayer | break;
|
2252 | 4c9649a9 | j_mayer | case 0x2D: |
2253 | 4c9649a9 | j_mayer | /* STQ */
|
2254 | 57a92c8e | aurel32 | gen_store_mem(ctx, &tcg_gen_qemu_st64, ra, rb, disp16, 0, 0, 0); |
2255 | 4c9649a9 | j_mayer | break;
|
2256 | 4c9649a9 | j_mayer | case 0x2E: |
2257 | 4c9649a9 | j_mayer | /* STL_C */
|
2258 | 57a92c8e | aurel32 | gen_store_mem(ctx, &gen_qemu_stl_c, ra, rb, disp16, 0, 0, 1); |
2259 | 4c9649a9 | j_mayer | break;
|
2260 | 4c9649a9 | j_mayer | case 0x2F: |
2261 | 4c9649a9 | j_mayer | /* STQ_C */
|
2262 | 57a92c8e | aurel32 | gen_store_mem(ctx, &gen_qemu_stq_c, ra, rb, disp16, 0, 0, 1); |
2263 | 4c9649a9 | j_mayer | break;
|
2264 | 4c9649a9 | j_mayer | case 0x30: |
2265 | 4c9649a9 | j_mayer | /* BR */
|
2266 | 3761035f | aurel32 | if (ra != 31) |
2267 | 3761035f | aurel32 | tcg_gen_movi_i64(cpu_ir[ra], ctx->pc); |
2268 | 3761035f | aurel32 | tcg_gen_movi_i64(cpu_pc, ctx->pc + (int64_t)(disp21 << 2));
|
2269 | 4c9649a9 | j_mayer | ret = 1;
|
2270 | 4c9649a9 | j_mayer | break;
|
2271 | a7812ae4 | pbrook | case 0x31: /* FBEQ */ |
2272 | a7812ae4 | pbrook | case 0x32: /* FBLT */ |
2273 | a7812ae4 | pbrook | case 0x33: /* FBLE */ |
2274 | a7812ae4 | pbrook | gen_fbcond(ctx, opc, ra, disp16); |
2275 | 4c9649a9 | j_mayer | ret = 1;
|
2276 | 4c9649a9 | j_mayer | break;
|
2277 | 4c9649a9 | j_mayer | case 0x34: |
2278 | 4c9649a9 | j_mayer | /* BSR */
|
2279 | 3761035f | aurel32 | if (ra != 31) |
2280 | 3761035f | aurel32 | tcg_gen_movi_i64(cpu_ir[ra], ctx->pc); |
2281 | 3761035f | aurel32 | tcg_gen_movi_i64(cpu_pc, ctx->pc + (int64_t)(disp21 << 2));
|
2282 | 4c9649a9 | j_mayer | ret = 1;
|
2283 | 4c9649a9 | j_mayer | break;
|
2284 | a7812ae4 | pbrook | case 0x35: /* FBNE */ |
2285 | a7812ae4 | pbrook | case 0x36: /* FBGE */ |
2286 | a7812ae4 | pbrook | case 0x37: /* FBGT */ |
2287 | a7812ae4 | pbrook | gen_fbcond(ctx, opc, ra, disp16); |
2288 | 4c9649a9 | j_mayer | ret = 1;
|
2289 | 4c9649a9 | j_mayer | break;
|
2290 | 4c9649a9 | j_mayer | case 0x38: |
2291 | 4c9649a9 | j_mayer | /* BLBC */
|
2292 | a1516744 | aurel32 | gen_bcond(ctx, TCG_COND_EQ, ra, disp21, 1);
|
2293 | 4c9649a9 | j_mayer | ret = 1;
|
2294 | 4c9649a9 | j_mayer | break;
|
2295 | 4c9649a9 | j_mayer | case 0x39: |
2296 | 4c9649a9 | j_mayer | /* BEQ */
|
2297 | a1516744 | aurel32 | gen_bcond(ctx, TCG_COND_EQ, ra, disp21, 0);
|
2298 | 4c9649a9 | j_mayer | ret = 1;
|
2299 | 4c9649a9 | j_mayer | break;
|
2300 | 4c9649a9 | j_mayer | case 0x3A: |
2301 | 4c9649a9 | j_mayer | /* BLT */
|
2302 | a1516744 | aurel32 | gen_bcond(ctx, TCG_COND_LT, ra, disp21, 0);
|
2303 | 4c9649a9 | j_mayer | ret = 1;
|
2304 | 4c9649a9 | j_mayer | break;
|
2305 | 4c9649a9 | j_mayer | case 0x3B: |
2306 | 4c9649a9 | j_mayer | /* BLE */
|
2307 | a1516744 | aurel32 | gen_bcond(ctx, TCG_COND_LE, ra, disp21, 0);
|
2308 | 4c9649a9 | j_mayer | ret = 1;
|
2309 | 4c9649a9 | j_mayer | break;
|
2310 | 4c9649a9 | j_mayer | case 0x3C: |
2311 | 4c9649a9 | j_mayer | /* BLBS */
|
2312 | a1516744 | aurel32 | gen_bcond(ctx, TCG_COND_NE, ra, disp21, 1);
|
2313 | 4c9649a9 | j_mayer | ret = 1;
|
2314 | 4c9649a9 | j_mayer | break;
|
2315 | 4c9649a9 | j_mayer | case 0x3D: |
2316 | 4c9649a9 | j_mayer | /* BNE */
|
2317 | a1516744 | aurel32 | gen_bcond(ctx, TCG_COND_NE, ra, disp21, 0);
|
2318 | 4c9649a9 | j_mayer | ret = 1;
|
2319 | 4c9649a9 | j_mayer | break;
|
2320 | 4c9649a9 | j_mayer | case 0x3E: |
2321 | 4c9649a9 | j_mayer | /* BGE */
|
2322 | a1516744 | aurel32 | gen_bcond(ctx, TCG_COND_GE, ra, disp21, 0);
|
2323 | 4c9649a9 | j_mayer | ret = 1;
|
2324 | 4c9649a9 | j_mayer | break;
|
2325 | 4c9649a9 | j_mayer | case 0x3F: |
2326 | 4c9649a9 | j_mayer | /* BGT */
|
2327 | a1516744 | aurel32 | gen_bcond(ctx, TCG_COND_GT, ra, disp21, 0);
|
2328 | 4c9649a9 | j_mayer | ret = 1;
|
2329 | 4c9649a9 | j_mayer | break;
|
2330 | 4c9649a9 | j_mayer | invalid_opc:
|
2331 | 4c9649a9 | j_mayer | gen_invalid(ctx); |
2332 | 4c9649a9 | j_mayer | ret = 3;
|
2333 | 4c9649a9 | j_mayer | break;
|
2334 | 4c9649a9 | j_mayer | } |
2335 | 4c9649a9 | j_mayer | |
2336 | 4c9649a9 | j_mayer | return ret;
|
2337 | 4c9649a9 | j_mayer | } |
2338 | 4c9649a9 | j_mayer | |
2339 | 2cfc5f17 | ths | static always_inline void gen_intermediate_code_internal (CPUState *env, |
2340 | 2cfc5f17 | ths | TranslationBlock *tb, |
2341 | 2cfc5f17 | ths | int search_pc)
|
2342 | 4c9649a9 | j_mayer | { |
2343 | 4c9649a9 | j_mayer | #if defined ALPHA_DEBUG_DISAS
|
2344 | 4c9649a9 | j_mayer | static int insn_count; |
2345 | 4c9649a9 | j_mayer | #endif
|
2346 | 4c9649a9 | j_mayer | DisasContext ctx, *ctxp = &ctx; |
2347 | 4c9649a9 | j_mayer | target_ulong pc_start; |
2348 | 4c9649a9 | j_mayer | uint32_t insn; |
2349 | 4c9649a9 | j_mayer | uint16_t *gen_opc_end; |
2350 | a1d1bb31 | aliguori | CPUBreakpoint *bp; |
2351 | 4c9649a9 | j_mayer | int j, lj = -1; |
2352 | 4c9649a9 | j_mayer | int ret;
|
2353 | 2e70f6ef | pbrook | int num_insns;
|
2354 | 2e70f6ef | pbrook | int max_insns;
|
2355 | 4c9649a9 | j_mayer | |
2356 | 4c9649a9 | j_mayer | pc_start = tb->pc; |
2357 | 4c9649a9 | j_mayer | gen_opc_end = gen_opc_buf + OPC_MAX_SIZE; |
2358 | 4c9649a9 | j_mayer | ctx.pc = pc_start; |
2359 | 4c9649a9 | j_mayer | ctx.amask = env->amask; |
2360 | 8579095b | aurel32 | ctx.env = env; |
2361 | 4c9649a9 | j_mayer | #if defined (CONFIG_USER_ONLY)
|
2362 | 4c9649a9 | j_mayer | ctx.mem_idx = 0;
|
2363 | 4c9649a9 | j_mayer | #else
|
2364 | 4c9649a9 | j_mayer | ctx.mem_idx = ((env->ps >> 3) & 3); |
2365 | 4c9649a9 | j_mayer | ctx.pal_mode = env->ipr[IPR_EXC_ADDR] & 1;
|
2366 | 4c9649a9 | j_mayer | #endif
|
2367 | 2e70f6ef | pbrook | num_insns = 0;
|
2368 | 2e70f6ef | pbrook | max_insns = tb->cflags & CF_COUNT_MASK; |
2369 | 2e70f6ef | pbrook | if (max_insns == 0) |
2370 | 2e70f6ef | pbrook | max_insns = CF_COUNT_MASK; |
2371 | 2e70f6ef | pbrook | |
2372 | 2e70f6ef | pbrook | gen_icount_start(); |
2373 | 4c9649a9 | j_mayer | for (ret = 0; ret == 0;) { |
2374 | c0ce998e | aliguori | if (unlikely(!TAILQ_EMPTY(&env->breakpoints))) {
|
2375 | c0ce998e | aliguori | TAILQ_FOREACH(bp, &env->breakpoints, entry) { |
2376 | a1d1bb31 | aliguori | if (bp->pc == ctx.pc) {
|
2377 | 4c9649a9 | j_mayer | gen_excp(&ctx, EXCP_DEBUG, 0);
|
2378 | 4c9649a9 | j_mayer | break;
|
2379 | 4c9649a9 | j_mayer | } |
2380 | 4c9649a9 | j_mayer | } |
2381 | 4c9649a9 | j_mayer | } |
2382 | 4c9649a9 | j_mayer | if (search_pc) {
|
2383 | 4c9649a9 | j_mayer | j = gen_opc_ptr - gen_opc_buf; |
2384 | 4c9649a9 | j_mayer | if (lj < j) {
|
2385 | 4c9649a9 | j_mayer | lj++; |
2386 | 4c9649a9 | j_mayer | while (lj < j)
|
2387 | 4c9649a9 | j_mayer | gen_opc_instr_start[lj++] = 0;
|
2388 | 4c9649a9 | j_mayer | } |
2389 | ed1dda53 | aurel32 | gen_opc_pc[lj] = ctx.pc; |
2390 | ed1dda53 | aurel32 | gen_opc_instr_start[lj] = 1;
|
2391 | ed1dda53 | aurel32 | gen_opc_icount[lj] = num_insns; |
2392 | 4c9649a9 | j_mayer | } |
2393 | 2e70f6ef | pbrook | if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO)) |
2394 | 2e70f6ef | pbrook | gen_io_start(); |
2395 | 4c9649a9 | j_mayer | #if defined ALPHA_DEBUG_DISAS
|
2396 | 4c9649a9 | j_mayer | insn_count++; |
2397 | d12d51d5 | aliguori | LOG_DISAS("pc " TARGET_FMT_lx " mem_idx %d\n", |
2398 | d12d51d5 | aliguori | ctx.pc, ctx.mem_idx); |
2399 | 4c9649a9 | j_mayer | #endif
|
2400 | 4c9649a9 | j_mayer | insn = ldl_code(ctx.pc); |
2401 | 4c9649a9 | j_mayer | #if defined ALPHA_DEBUG_DISAS
|
2402 | 4c9649a9 | j_mayer | insn_count++; |
2403 | d12d51d5 | aliguori | LOG_DISAS("opcode %08x %d\n", insn, insn_count);
|
2404 | 4c9649a9 | j_mayer | #endif
|
2405 | 2e70f6ef | pbrook | num_insns++; |
2406 | 4c9649a9 | j_mayer | ctx.pc += 4;
|
2407 | 4c9649a9 | j_mayer | ret = translate_one(ctxp, insn); |
2408 | 4c9649a9 | j_mayer | if (ret != 0) |
2409 | 4c9649a9 | j_mayer | break;
|
2410 | 4c9649a9 | j_mayer | /* if we reach a page boundary or are single stepping, stop
|
2411 | 4c9649a9 | j_mayer | * generation
|
2412 | 4c9649a9 | j_mayer | */
|
2413 | 19bf517b | aurel32 | if (env->singlestep_enabled) {
|
2414 | 19bf517b | aurel32 | gen_excp(&ctx, EXCP_DEBUG, 0);
|
2415 | 19bf517b | aurel32 | break;
|
2416 | 1b530a6d | aurel32 | } |
2417 | 19bf517b | aurel32 | |
2418 | 8fcc55f9 | aurel32 | if ((ctx.pc & (TARGET_PAGE_SIZE - 1)) == 0) |
2419 | 8fcc55f9 | aurel32 | break;
|
2420 | 8fcc55f9 | aurel32 | |
2421 | 8fcc55f9 | aurel32 | if (gen_opc_ptr >= gen_opc_end)
|
2422 | 8fcc55f9 | aurel32 | break;
|
2423 | 8fcc55f9 | aurel32 | |
2424 | 8fcc55f9 | aurel32 | if (num_insns >= max_insns)
|
2425 | 8fcc55f9 | aurel32 | break;
|
2426 | 8fcc55f9 | aurel32 | |
2427 | 1b530a6d | aurel32 | if (singlestep) {
|
2428 | 1b530a6d | aurel32 | break;
|
2429 | 1b530a6d | aurel32 | } |
2430 | 4c9649a9 | j_mayer | } |
2431 | 4c9649a9 | j_mayer | if (ret != 1 && ret != 3) { |
2432 | 496cb5b9 | aurel32 | tcg_gen_movi_i64(cpu_pc, ctx.pc); |
2433 | 4c9649a9 | j_mayer | } |
2434 | 4c9649a9 | j_mayer | #if defined (DO_TB_FLUSH)
|
2435 | a7812ae4 | pbrook | gen_helper_tb_flush(); |
2436 | 4c9649a9 | j_mayer | #endif
|
2437 | 2e70f6ef | pbrook | if (tb->cflags & CF_LAST_IO)
|
2438 | 2e70f6ef | pbrook | gen_io_end(); |
2439 | 4c9649a9 | j_mayer | /* Generate the return instruction */
|
2440 | 57fec1fe | bellard | tcg_gen_exit_tb(0);
|
2441 | 2e70f6ef | pbrook | gen_icount_end(tb, num_insns); |
2442 | 4c9649a9 | j_mayer | *gen_opc_ptr = INDEX_op_end; |
2443 | 4c9649a9 | j_mayer | if (search_pc) {
|
2444 | 4c9649a9 | j_mayer | j = gen_opc_ptr - gen_opc_buf; |
2445 | 4c9649a9 | j_mayer | lj++; |
2446 | 4c9649a9 | j_mayer | while (lj <= j)
|
2447 | 4c9649a9 | j_mayer | gen_opc_instr_start[lj++] = 0;
|
2448 | 4c9649a9 | j_mayer | } else {
|
2449 | 4c9649a9 | j_mayer | tb->size = ctx.pc - pc_start; |
2450 | 2e70f6ef | pbrook | tb->icount = num_insns; |
2451 | 4c9649a9 | j_mayer | } |
2452 | 4c9649a9 | j_mayer | #if defined ALPHA_DEBUG_DISAS
|
2453 | 93fcfe39 | aliguori | log_cpu_state_mask(CPU_LOG_TB_CPU, env, 0);
|
2454 | 8fec2b8c | aliguori | if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
|
2455 | 93fcfe39 | aliguori | qemu_log("IN: %s\n", lookup_symbol(pc_start));
|
2456 | 93fcfe39 | aliguori | log_target_disas(pc_start, ctx.pc - pc_start, 1);
|
2457 | 93fcfe39 | aliguori | qemu_log("\n");
|
2458 | 4c9649a9 | j_mayer | } |
2459 | 4c9649a9 | j_mayer | #endif
|
2460 | 4c9649a9 | j_mayer | } |
2461 | 4c9649a9 | j_mayer | |
2462 | 2cfc5f17 | ths | void gen_intermediate_code (CPUState *env, struct TranslationBlock *tb) |
2463 | 4c9649a9 | j_mayer | { |
2464 | 2cfc5f17 | ths | gen_intermediate_code_internal(env, tb, 0);
|
2465 | 4c9649a9 | j_mayer | } |
2466 | 4c9649a9 | j_mayer | |
2467 | 2cfc5f17 | ths | void gen_intermediate_code_pc (CPUState *env, struct TranslationBlock *tb) |
2468 | 4c9649a9 | j_mayer | { |
2469 | 2cfc5f17 | ths | gen_intermediate_code_internal(env, tb, 1);
|
2470 | 4c9649a9 | j_mayer | } |
2471 | 4c9649a9 | j_mayer | |
2472 | aaed909a | bellard | CPUAlphaState * cpu_alpha_init (const char *cpu_model) |
2473 | 4c9649a9 | j_mayer | { |
2474 | 4c9649a9 | j_mayer | CPUAlphaState *env; |
2475 | 4c9649a9 | j_mayer | uint64_t hwpcb; |
2476 | 4c9649a9 | j_mayer | |
2477 | 4c9649a9 | j_mayer | env = qemu_mallocz(sizeof(CPUAlphaState));
|
2478 | 4c9649a9 | j_mayer | cpu_exec_init(env); |
2479 | 2e70f6ef | pbrook | alpha_translate_init(); |
2480 | 4c9649a9 | j_mayer | tlb_flush(env, 1);
|
2481 | 4c9649a9 | j_mayer | /* XXX: should not be hardcoded */
|
2482 | 4c9649a9 | j_mayer | env->implver = IMPLVER_2106x; |
2483 | 4c9649a9 | j_mayer | env->ps = 0x1F00;
|
2484 | 4c9649a9 | j_mayer | #if defined (CONFIG_USER_ONLY)
|
2485 | 4c9649a9 | j_mayer | env->ps |= 1 << 3; |
2486 | 4c9649a9 | j_mayer | #endif
|
2487 | 4c9649a9 | j_mayer | pal_init(env); |
2488 | 4c9649a9 | j_mayer | /* Initialize IPR */
|
2489 | 4c9649a9 | j_mayer | hwpcb = env->ipr[IPR_PCBB]; |
2490 | 4c9649a9 | j_mayer | env->ipr[IPR_ASN] = 0;
|
2491 | 4c9649a9 | j_mayer | env->ipr[IPR_ASTEN] = 0;
|
2492 | 4c9649a9 | j_mayer | env->ipr[IPR_ASTSR] = 0;
|
2493 | 4c9649a9 | j_mayer | env->ipr[IPR_DATFX] = 0;
|
2494 | 4c9649a9 | j_mayer | /* XXX: fix this */
|
2495 | 4c9649a9 | j_mayer | // env->ipr[IPR_ESP] = ldq_raw(hwpcb + 8);
|
2496 | 4c9649a9 | j_mayer | // env->ipr[IPR_KSP] = ldq_raw(hwpcb + 0);
|
2497 | 4c9649a9 | j_mayer | // env->ipr[IPR_SSP] = ldq_raw(hwpcb + 16);
|
2498 | 4c9649a9 | j_mayer | // env->ipr[IPR_USP] = ldq_raw(hwpcb + 24);
|
2499 | 4c9649a9 | j_mayer | env->ipr[IPR_FEN] = 0;
|
2500 | 4c9649a9 | j_mayer | env->ipr[IPR_IPL] = 31;
|
2501 | 4c9649a9 | j_mayer | env->ipr[IPR_MCES] = 0;
|
2502 | 4c9649a9 | j_mayer | env->ipr[IPR_PERFMON] = 0; /* Implementation specific */ |
2503 | 4c9649a9 | j_mayer | // env->ipr[IPR_PTBR] = ldq_raw(hwpcb + 32);
|
2504 | 4c9649a9 | j_mayer | env->ipr[IPR_SISR] = 0;
|
2505 | 4c9649a9 | j_mayer | env->ipr[IPR_VIRBND] = -1ULL;
|
2506 | 4c9649a9 | j_mayer | |
2507 | 0bf46a40 | aliguori | qemu_init_vcpu(env); |
2508 | 4c9649a9 | j_mayer | return env;
|
2509 | 4c9649a9 | j_mayer | } |
2510 | aaed909a | bellard | |
2511 | d2856f1a | aurel32 | void gen_pc_load(CPUState *env, TranslationBlock *tb,
|
2512 | d2856f1a | aurel32 | unsigned long searched_pc, int pc_pos, void *puc) |
2513 | d2856f1a | aurel32 | { |
2514 | d2856f1a | aurel32 | env->pc = gen_opc_pc[pc_pos]; |
2515 | d2856f1a | aurel32 | } |