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1 | 34e65944 | Isaku Yamahata | /*
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2 | 34e65944 | Isaku Yamahata | * pcie_aer.c
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3 | 34e65944 | Isaku Yamahata | *
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4 | 34e65944 | Isaku Yamahata | * Copyright (c) 2010 Isaku Yamahata <yamahata at valinux co jp>
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5 | 34e65944 | Isaku Yamahata | * VA Linux Systems Japan K.K.
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6 | 34e65944 | Isaku Yamahata | *
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7 | 34e65944 | Isaku Yamahata | * This program is free software; you can redistribute it and/or modify
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8 | 34e65944 | Isaku Yamahata | * it under the terms of the GNU General Public License as published by
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9 | 34e65944 | Isaku Yamahata | * the Free Software Foundation; either version 2 of the License, or
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10 | 34e65944 | Isaku Yamahata | * (at your option) any later version.
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11 | 34e65944 | Isaku Yamahata | *
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12 | 34e65944 | Isaku Yamahata | * This program is distributed in the hope that it will be useful,
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13 | 34e65944 | Isaku Yamahata | * but WITHOUT ANY WARRANTY; without even the implied warranty of
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14 | 34e65944 | Isaku Yamahata | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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15 | 34e65944 | Isaku Yamahata | * GNU General Public License for more details.
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16 | 34e65944 | Isaku Yamahata | *
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17 | 34e65944 | Isaku Yamahata | * You should have received a copy of the GNU General Public License along
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18 | 34e65944 | Isaku Yamahata | * with this program; if not, see <http://www.gnu.org/licenses/>.
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19 | 34e65944 | Isaku Yamahata | */
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20 | 34e65944 | Isaku Yamahata | |
21 | 34e65944 | Isaku Yamahata | #include "sysemu.h" |
22 | 34e65944 | Isaku Yamahata | #include "pci_bridge.h" |
23 | 34e65944 | Isaku Yamahata | #include "pcie.h" |
24 | 34e65944 | Isaku Yamahata | #include "msix.h" |
25 | 34e65944 | Isaku Yamahata | #include "msi.h" |
26 | 34e65944 | Isaku Yamahata | #include "pci_internals.h" |
27 | 34e65944 | Isaku Yamahata | #include "pcie_regs.h" |
28 | 34e65944 | Isaku Yamahata | |
29 | 34e65944 | Isaku Yamahata | //#define DEBUG_PCIE
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30 | 34e65944 | Isaku Yamahata | #ifdef DEBUG_PCIE
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31 | 34e65944 | Isaku Yamahata | # define PCIE_DPRINTF(fmt, ...) \
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32 | 34e65944 | Isaku Yamahata | fprintf(stderr, "%s:%d " fmt, __func__, __LINE__, ## __VA_ARGS__) |
33 | 34e65944 | Isaku Yamahata | #else
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34 | 34e65944 | Isaku Yamahata | # define PCIE_DPRINTF(fmt, ...) do {} while (0) |
35 | 34e65944 | Isaku Yamahata | #endif
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36 | 34e65944 | Isaku Yamahata | #define PCIE_DEV_PRINTF(dev, fmt, ...) \
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37 | 34e65944 | Isaku Yamahata | PCIE_DPRINTF("%s:%x "fmt, (dev)->name, (dev)->devfn, ## __VA_ARGS__) |
38 | 34e65944 | Isaku Yamahata | |
39 | 34e65944 | Isaku Yamahata | /* From 6.2.7 Error Listing and Rules. Table 6-2, 6-3 and 6-4 */
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40 | 34e65944 | Isaku Yamahata | static uint32_t pcie_aer_uncor_default_severity(uint32_t status)
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41 | 34e65944 | Isaku Yamahata | { |
42 | 34e65944 | Isaku Yamahata | switch (status) {
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43 | 34e65944 | Isaku Yamahata | case PCI_ERR_UNC_INTN:
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44 | 34e65944 | Isaku Yamahata | case PCI_ERR_UNC_DLP:
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45 | 34e65944 | Isaku Yamahata | case PCI_ERR_UNC_SDN:
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46 | 34e65944 | Isaku Yamahata | case PCI_ERR_UNC_RX_OVER:
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47 | 34e65944 | Isaku Yamahata | case PCI_ERR_UNC_FCP:
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48 | 34e65944 | Isaku Yamahata | case PCI_ERR_UNC_MALF_TLP:
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49 | 34e65944 | Isaku Yamahata | return PCI_ERR_ROOT_CMD_FATAL_EN;
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50 | 34e65944 | Isaku Yamahata | case PCI_ERR_UNC_POISON_TLP:
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51 | 34e65944 | Isaku Yamahata | case PCI_ERR_UNC_ECRC:
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52 | 34e65944 | Isaku Yamahata | case PCI_ERR_UNC_UNSUP:
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53 | 34e65944 | Isaku Yamahata | case PCI_ERR_UNC_COMP_TIME:
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54 | 34e65944 | Isaku Yamahata | case PCI_ERR_UNC_COMP_ABORT:
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55 | 34e65944 | Isaku Yamahata | case PCI_ERR_UNC_UNX_COMP:
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56 | 34e65944 | Isaku Yamahata | case PCI_ERR_UNC_ACSV:
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57 | 34e65944 | Isaku Yamahata | case PCI_ERR_UNC_MCBTLP:
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58 | 34e65944 | Isaku Yamahata | case PCI_ERR_UNC_ATOP_EBLOCKED:
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59 | 34e65944 | Isaku Yamahata | case PCI_ERR_UNC_TLP_PRF_BLOCKED:
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60 | 34e65944 | Isaku Yamahata | return PCI_ERR_ROOT_CMD_NONFATAL_EN;
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61 | 34e65944 | Isaku Yamahata | default:
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62 | 34e65944 | Isaku Yamahata | abort(); |
63 | 34e65944 | Isaku Yamahata | break;
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64 | 34e65944 | Isaku Yamahata | } |
65 | 34e65944 | Isaku Yamahata | return PCI_ERR_ROOT_CMD_FATAL_EN;
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66 | 34e65944 | Isaku Yamahata | } |
67 | 34e65944 | Isaku Yamahata | |
68 | 34e65944 | Isaku Yamahata | static int aer_log_add_err(PCIEAERLog *aer_log, const PCIEAERErr *err) |
69 | 34e65944 | Isaku Yamahata | { |
70 | 34e65944 | Isaku Yamahata | if (aer_log->log_num == aer_log->log_max) {
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71 | 34e65944 | Isaku Yamahata | return -1; |
72 | 34e65944 | Isaku Yamahata | } |
73 | 34e65944 | Isaku Yamahata | memcpy(&aer_log->log[aer_log->log_num], err, sizeof *err);
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74 | 34e65944 | Isaku Yamahata | aer_log->log_num++; |
75 | 34e65944 | Isaku Yamahata | return 0; |
76 | 34e65944 | Isaku Yamahata | } |
77 | 34e65944 | Isaku Yamahata | |
78 | 34e65944 | Isaku Yamahata | static void aer_log_del_err(PCIEAERLog *aer_log, PCIEAERErr *err) |
79 | 34e65944 | Isaku Yamahata | { |
80 | 34e65944 | Isaku Yamahata | assert(aer_log->log_num); |
81 | 34e65944 | Isaku Yamahata | *err = aer_log->log[0];
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82 | 34e65944 | Isaku Yamahata | aer_log->log_num--; |
83 | 34e65944 | Isaku Yamahata | memmove(&aer_log->log[0], &aer_log->log[1], |
84 | 34e65944 | Isaku Yamahata | aer_log->log_num * sizeof *err);
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85 | 34e65944 | Isaku Yamahata | } |
86 | 34e65944 | Isaku Yamahata | |
87 | 34e65944 | Isaku Yamahata | static void aer_log_clear_all_err(PCIEAERLog *aer_log) |
88 | 34e65944 | Isaku Yamahata | { |
89 | 34e65944 | Isaku Yamahata | aer_log->log_num = 0;
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90 | 34e65944 | Isaku Yamahata | } |
91 | 34e65944 | Isaku Yamahata | |
92 | 34e65944 | Isaku Yamahata | int pcie_aer_init(PCIDevice *dev, uint16_t offset)
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93 | 34e65944 | Isaku Yamahata | { |
94 | 34e65944 | Isaku Yamahata | PCIExpressDevice *exp; |
95 | 34e65944 | Isaku Yamahata | |
96 | 34e65944 | Isaku Yamahata | pcie_add_capability(dev, PCI_EXT_CAP_ID_ERR, PCI_ERR_VER, |
97 | 34e65944 | Isaku Yamahata | offset, PCI_ERR_SIZEOF); |
98 | 34e65944 | Isaku Yamahata | exp = &dev->exp; |
99 | 34e65944 | Isaku Yamahata | exp->aer_cap = offset; |
100 | 34e65944 | Isaku Yamahata | |
101 | 34e65944 | Isaku Yamahata | /* log_max is property */
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102 | 34e65944 | Isaku Yamahata | if (dev->exp.aer_log.log_max == PCIE_AER_LOG_MAX_UNSET) {
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103 | 34e65944 | Isaku Yamahata | dev->exp.aer_log.log_max = PCIE_AER_LOG_MAX_DEFAULT; |
104 | 34e65944 | Isaku Yamahata | } |
105 | 34e65944 | Isaku Yamahata | /* clip down the value to avoid unreasobale memory usage */
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106 | 34e65944 | Isaku Yamahata | if (dev->exp.aer_log.log_max > PCIE_AER_LOG_MAX_LIMIT) {
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107 | 34e65944 | Isaku Yamahata | return -EINVAL;
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108 | 34e65944 | Isaku Yamahata | } |
109 | 34e65944 | Isaku Yamahata | dev->exp.aer_log.log = qemu_mallocz(sizeof dev->exp.aer_log.log[0] * |
110 | 34e65944 | Isaku Yamahata | dev->exp.aer_log.log_max); |
111 | 34e65944 | Isaku Yamahata | |
112 | 34e65944 | Isaku Yamahata | pci_set_long(dev->w1cmask + offset + PCI_ERR_UNCOR_STATUS, |
113 | 34e65944 | Isaku Yamahata | PCI_ERR_UNC_SUPPORTED); |
114 | 34e65944 | Isaku Yamahata | |
115 | 34e65944 | Isaku Yamahata | pci_set_long(dev->config + offset + PCI_ERR_UNCOR_SEVER, |
116 | 34e65944 | Isaku Yamahata | PCI_ERR_UNC_SEVERITY_DEFAULT); |
117 | 34e65944 | Isaku Yamahata | pci_set_long(dev->wmask + offset + PCI_ERR_UNCOR_SEVER, |
118 | 34e65944 | Isaku Yamahata | PCI_ERR_UNC_SUPPORTED); |
119 | 34e65944 | Isaku Yamahata | |
120 | 34e65944 | Isaku Yamahata | pci_long_test_and_set_mask(dev->w1cmask + offset + PCI_ERR_COR_STATUS, |
121 | 34e65944 | Isaku Yamahata | PCI_ERR_COR_STATUS); |
122 | 34e65944 | Isaku Yamahata | |
123 | 34e65944 | Isaku Yamahata | pci_set_long(dev->config + offset + PCI_ERR_COR_MASK, |
124 | 34e65944 | Isaku Yamahata | PCI_ERR_COR_MASK_DEFAULT); |
125 | 34e65944 | Isaku Yamahata | pci_set_long(dev->wmask + offset + PCI_ERR_COR_MASK, |
126 | 34e65944 | Isaku Yamahata | PCI_ERR_COR_SUPPORTED); |
127 | 34e65944 | Isaku Yamahata | |
128 | 34e65944 | Isaku Yamahata | /* capabilities and control. multiple header logging is supported */
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129 | 34e65944 | Isaku Yamahata | if (dev->exp.aer_log.log_max > 0) { |
130 | 34e65944 | Isaku Yamahata | pci_set_long(dev->config + offset + PCI_ERR_CAP, |
131 | 34e65944 | Isaku Yamahata | PCI_ERR_CAP_ECRC_GENC | PCI_ERR_CAP_ECRC_CHKC | |
132 | 34e65944 | Isaku Yamahata | PCI_ERR_CAP_MHRC); |
133 | 34e65944 | Isaku Yamahata | pci_set_long(dev->wmask + offset + PCI_ERR_CAP, |
134 | 34e65944 | Isaku Yamahata | PCI_ERR_CAP_ECRC_GENE | PCI_ERR_CAP_ECRC_CHKE | |
135 | 34e65944 | Isaku Yamahata | PCI_ERR_CAP_MHRE); |
136 | 34e65944 | Isaku Yamahata | } else {
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137 | 34e65944 | Isaku Yamahata | pci_set_long(dev->config + offset + PCI_ERR_CAP, |
138 | 34e65944 | Isaku Yamahata | PCI_ERR_CAP_ECRC_GENC | PCI_ERR_CAP_ECRC_CHKC); |
139 | 34e65944 | Isaku Yamahata | pci_set_long(dev->wmask + offset + PCI_ERR_CAP, |
140 | 34e65944 | Isaku Yamahata | PCI_ERR_CAP_ECRC_GENE | PCI_ERR_CAP_ECRC_CHKE); |
141 | 34e65944 | Isaku Yamahata | } |
142 | 34e65944 | Isaku Yamahata | |
143 | 34e65944 | Isaku Yamahata | switch (pcie_cap_get_type(dev)) {
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144 | 34e65944 | Isaku Yamahata | case PCI_EXP_TYPE_ROOT_PORT:
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145 | 34e65944 | Isaku Yamahata | /* this case will be set by pcie_aer_root_init() */
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146 | 34e65944 | Isaku Yamahata | /* fallthrough */
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147 | 34e65944 | Isaku Yamahata | case PCI_EXP_TYPE_DOWNSTREAM:
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148 | 34e65944 | Isaku Yamahata | case PCI_EXP_TYPE_UPSTREAM:
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149 | 34e65944 | Isaku Yamahata | pci_word_test_and_set_mask(dev->wmask + PCI_BRIDGE_CONTROL, |
150 | 34e65944 | Isaku Yamahata | PCI_BRIDGE_CTL_SERR); |
151 | 34e65944 | Isaku Yamahata | pci_long_test_and_set_mask(dev->w1cmask + PCI_STATUS, |
152 | 34e65944 | Isaku Yamahata | PCI_SEC_STATUS_RCV_SYSTEM_ERROR); |
153 | 34e65944 | Isaku Yamahata | break;
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154 | 34e65944 | Isaku Yamahata | default:
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155 | 34e65944 | Isaku Yamahata | /* nothing */
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156 | 34e65944 | Isaku Yamahata | break;
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157 | 34e65944 | Isaku Yamahata | } |
158 | 34e65944 | Isaku Yamahata | return 0; |
159 | 34e65944 | Isaku Yamahata | } |
160 | 34e65944 | Isaku Yamahata | |
161 | 34e65944 | Isaku Yamahata | void pcie_aer_exit(PCIDevice *dev)
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162 | 34e65944 | Isaku Yamahata | { |
163 | 34e65944 | Isaku Yamahata | qemu_free(dev->exp.aer_log.log); |
164 | 34e65944 | Isaku Yamahata | } |
165 | 34e65944 | Isaku Yamahata | |
166 | 34e65944 | Isaku Yamahata | static void pcie_aer_update_uncor_status(PCIDevice *dev) |
167 | 34e65944 | Isaku Yamahata | { |
168 | 34e65944 | Isaku Yamahata | uint8_t *aer_cap = dev->config + dev->exp.aer_cap; |
169 | 34e65944 | Isaku Yamahata | PCIEAERLog *aer_log = &dev->exp.aer_log; |
170 | 34e65944 | Isaku Yamahata | |
171 | 34e65944 | Isaku Yamahata | uint16_t i; |
172 | 34e65944 | Isaku Yamahata | for (i = 0; i < aer_log->log_num; i++) { |
173 | 34e65944 | Isaku Yamahata | pci_long_test_and_set_mask(aer_cap + PCI_ERR_UNCOR_STATUS, |
174 | 34e65944 | Isaku Yamahata | dev->exp.aer_log.log[i].status); |
175 | 34e65944 | Isaku Yamahata | } |
176 | 34e65944 | Isaku Yamahata | } |
177 | 34e65944 | Isaku Yamahata | |
178 | 34e65944 | Isaku Yamahata | /*
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179 | 34e65944 | Isaku Yamahata | * return value:
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180 | 247c97f3 | Michael S. Tsirkin | * true: error message needs to be sent up
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181 | 34e65944 | Isaku Yamahata | * false: error message is masked
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182 | 34e65944 | Isaku Yamahata | *
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183 | 34e65944 | Isaku Yamahata | * 6.2.6 Error Message Control
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184 | 34e65944 | Isaku Yamahata | * Figure 6-3
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185 | 34e65944 | Isaku Yamahata | * all pci express devices part
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186 | 34e65944 | Isaku Yamahata | */
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187 | 34e65944 | Isaku Yamahata | static bool |
188 | 34e65944 | Isaku Yamahata | pcie_aer_msg_alldev(PCIDevice *dev, const PCIEAERMsg *msg)
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189 | 34e65944 | Isaku Yamahata | { |
190 | 34e65944 | Isaku Yamahata | if (!(pcie_aer_msg_is_uncor(msg) &&
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191 | 34e65944 | Isaku Yamahata | (pci_get_word(dev->config + PCI_COMMAND) & PCI_COMMAND_SERR))) { |
192 | 34e65944 | Isaku Yamahata | return false; |
193 | 34e65944 | Isaku Yamahata | } |
194 | 34e65944 | Isaku Yamahata | |
195 | 34e65944 | Isaku Yamahata | /* Signaled System Error
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196 | 34e65944 | Isaku Yamahata | *
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197 | 34e65944 | Isaku Yamahata | * 7.5.1.1 Command register
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198 | 34e65944 | Isaku Yamahata | * Bit 8 SERR# Enable
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199 | 34e65944 | Isaku Yamahata | *
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200 | 34e65944 | Isaku Yamahata | * When Set, this bit enables reporting of Non-fatal and Fatal
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201 | 34e65944 | Isaku Yamahata | * errors detected by the Function to the Root Complex. Note that
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202 | 34e65944 | Isaku Yamahata | * errors are reported if enabled either through this bit or through
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203 | 34e65944 | Isaku Yamahata | * the PCI Express specific bits in the Device Control register (see
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204 | 34e65944 | Isaku Yamahata | * Section 7.8.4).
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205 | 34e65944 | Isaku Yamahata | */
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206 | 34e65944 | Isaku Yamahata | pci_word_test_and_set_mask(dev->config + PCI_STATUS, |
207 | 34e65944 | Isaku Yamahata | PCI_STATUS_SIG_SYSTEM_ERROR); |
208 | 34e65944 | Isaku Yamahata | |
209 | 34e65944 | Isaku Yamahata | if (!(msg->severity &
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210 | 34e65944 | Isaku Yamahata | pci_get_word(dev->config + dev->exp.exp_cap + PCI_EXP_DEVCTL))) { |
211 | 34e65944 | Isaku Yamahata | return false; |
212 | 34e65944 | Isaku Yamahata | } |
213 | 34e65944 | Isaku Yamahata | |
214 | 34e65944 | Isaku Yamahata | /* send up error message */
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215 | 247c97f3 | Michael S. Tsirkin | return true; |
216 | 247c97f3 | Michael S. Tsirkin | } |
217 | 247c97f3 | Michael S. Tsirkin | |
218 | 34e65944 | Isaku Yamahata | /*
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219 | 34e65944 | Isaku Yamahata | * return value:
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220 | 34e65944 | Isaku Yamahata | * true: error message is sent up
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221 | 34e65944 | Isaku Yamahata | * false: error message is masked
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222 | 34e65944 | Isaku Yamahata | *
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223 | 34e65944 | Isaku Yamahata | * 6.2.6 Error Message Control
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224 | 34e65944 | Isaku Yamahata | * Figure 6-3
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225 | 34e65944 | Isaku Yamahata | * virtual pci bridge part
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226 | 34e65944 | Isaku Yamahata | */
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227 | 34e65944 | Isaku Yamahata | static bool pcie_aer_msg_vbridge(PCIDevice *dev, const PCIEAERMsg *msg) |
228 | 34e65944 | Isaku Yamahata | { |
229 | 34e65944 | Isaku Yamahata | uint16_t bridge_control = pci_get_word(dev->config + PCI_BRIDGE_CONTROL); |
230 | 34e65944 | Isaku Yamahata | |
231 | 34e65944 | Isaku Yamahata | if (pcie_aer_msg_is_uncor(msg)) {
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232 | 34e65944 | Isaku Yamahata | /* Received System Error */
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233 | 34e65944 | Isaku Yamahata | pci_word_test_and_set_mask(dev->config + PCI_SEC_STATUS, |
234 | 34e65944 | Isaku Yamahata | PCI_SEC_STATUS_RCV_SYSTEM_ERROR); |
235 | 34e65944 | Isaku Yamahata | } |
236 | 34e65944 | Isaku Yamahata | |
237 | 34e65944 | Isaku Yamahata | if (!(bridge_control & PCI_BRIDGE_CTL_SERR)) {
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238 | 34e65944 | Isaku Yamahata | return false; |
239 | 34e65944 | Isaku Yamahata | } |
240 | 34e65944 | Isaku Yamahata | return true; |
241 | 34e65944 | Isaku Yamahata | } |
242 | 34e65944 | Isaku Yamahata | |
243 | 34e65944 | Isaku Yamahata | void pcie_aer_root_set_vector(PCIDevice *dev, unsigned int vector) |
244 | 34e65944 | Isaku Yamahata | { |
245 | 34e65944 | Isaku Yamahata | uint8_t *aer_cap = dev->config + dev->exp.aer_cap; |
246 | 34e65944 | Isaku Yamahata | assert(vector < PCI_ERR_ROOT_IRQ_MAX); |
247 | 34e65944 | Isaku Yamahata | pci_long_test_and_clear_mask(aer_cap + PCI_ERR_ROOT_STATUS, |
248 | 34e65944 | Isaku Yamahata | PCI_ERR_ROOT_IRQ); |
249 | 34e65944 | Isaku Yamahata | pci_long_test_and_set_mask(aer_cap + PCI_ERR_ROOT_STATUS, |
250 | 34e65944 | Isaku Yamahata | vector << PCI_ERR_ROOT_IRQ_SHIFT); |
251 | 34e65944 | Isaku Yamahata | } |
252 | 34e65944 | Isaku Yamahata | |
253 | 34e65944 | Isaku Yamahata | static unsigned int pcie_aer_root_get_vector(PCIDevice *dev) |
254 | 34e65944 | Isaku Yamahata | { |
255 | 34e65944 | Isaku Yamahata | uint8_t *aer_cap = dev->config + dev->exp.aer_cap; |
256 | 34e65944 | Isaku Yamahata | uint32_t root_status = pci_get_long(aer_cap + PCI_ERR_ROOT_STATUS); |
257 | 34e65944 | Isaku Yamahata | return (root_status & PCI_ERR_ROOT_IRQ) >> PCI_ERR_ROOT_IRQ_SHIFT;
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258 | 34e65944 | Isaku Yamahata | } |
259 | 34e65944 | Isaku Yamahata | |
260 | 34e65944 | Isaku Yamahata | /*
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261 | 34e65944 | Isaku Yamahata | * return value:
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262 | 34e65944 | Isaku Yamahata | * true: error message is sent up
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263 | 34e65944 | Isaku Yamahata | * false: error message is masked
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264 | 34e65944 | Isaku Yamahata | *
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265 | 34e65944 | Isaku Yamahata | * 6.2.6 Error Message Control
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266 | 34e65944 | Isaku Yamahata | * Figure 6-3
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267 | 34e65944 | Isaku Yamahata | * root port part
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268 | 34e65944 | Isaku Yamahata | */
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269 | 34e65944 | Isaku Yamahata | static bool pcie_aer_msg_root_port(PCIDevice *dev, const PCIEAERMsg *msg) |
270 | 34e65944 | Isaku Yamahata | { |
271 | 34e65944 | Isaku Yamahata | bool msg_sent;
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272 | 34e65944 | Isaku Yamahata | uint16_t cmd; |
273 | 34e65944 | Isaku Yamahata | uint8_t *aer_cap; |
274 | 34e65944 | Isaku Yamahata | uint32_t root_cmd; |
275 | 34e65944 | Isaku Yamahata | uint32_t root_status; |
276 | 34e65944 | Isaku Yamahata | bool msi_trigger;
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277 | 34e65944 | Isaku Yamahata | |
278 | 34e65944 | Isaku Yamahata | msg_sent = false;
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279 | 34e65944 | Isaku Yamahata | cmd = pci_get_word(dev->config + PCI_COMMAND); |
280 | 34e65944 | Isaku Yamahata | aer_cap = dev->config + dev->exp.aer_cap; |
281 | 34e65944 | Isaku Yamahata | root_cmd = pci_get_long(aer_cap + PCI_ERR_ROOT_COMMAND); |
282 | 34e65944 | Isaku Yamahata | root_status = pci_get_long(aer_cap + PCI_ERR_ROOT_STATUS); |
283 | 34e65944 | Isaku Yamahata | msi_trigger = false;
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284 | 34e65944 | Isaku Yamahata | |
285 | 34e65944 | Isaku Yamahata | if (cmd & PCI_COMMAND_SERR) {
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286 | 34e65944 | Isaku Yamahata | /* System Error.
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287 | 34e65944 | Isaku Yamahata | *
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288 | 34e65944 | Isaku Yamahata | * The way to report System Error is platform specific and
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289 | 34e65944 | Isaku Yamahata | * it isn't implemented in qemu right now.
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290 | 34e65944 | Isaku Yamahata | * So just discard the error for now.
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291 | 34e65944 | Isaku Yamahata | * OS which cares of aer would receive errors via
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292 | 34e65944 | Isaku Yamahata | * native aer mechanims, so this wouldn't matter.
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293 | 34e65944 | Isaku Yamahata | */
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294 | 34e65944 | Isaku Yamahata | } |
295 | 34e65944 | Isaku Yamahata | |
296 | 34e65944 | Isaku Yamahata | /* Errro Message Received: Root Error Status register */
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297 | 34e65944 | Isaku Yamahata | switch (msg->severity) {
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298 | 34e65944 | Isaku Yamahata | case PCI_ERR_ROOT_CMD_COR_EN:
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299 | 34e65944 | Isaku Yamahata | if (root_status & PCI_ERR_ROOT_COR_RCV) {
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300 | 34e65944 | Isaku Yamahata | root_status |= PCI_ERR_ROOT_MULTI_COR_RCV; |
301 | 34e65944 | Isaku Yamahata | } else {
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302 | 34e65944 | Isaku Yamahata | if (root_cmd & PCI_ERR_ROOT_CMD_COR_EN) {
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303 | 34e65944 | Isaku Yamahata | msi_trigger = true;
|
304 | 34e65944 | Isaku Yamahata | } |
305 | 34e65944 | Isaku Yamahata | pci_set_word(aer_cap + PCI_ERR_ROOT_COR_SRC, msg->source_id); |
306 | 34e65944 | Isaku Yamahata | } |
307 | 34e65944 | Isaku Yamahata | root_status |= PCI_ERR_ROOT_COR_RCV; |
308 | 34e65944 | Isaku Yamahata | break;
|
309 | 34e65944 | Isaku Yamahata | case PCI_ERR_ROOT_CMD_NONFATAL_EN:
|
310 | 34e65944 | Isaku Yamahata | if (!(root_status & PCI_ERR_ROOT_NONFATAL_RCV) &&
|
311 | 34e65944 | Isaku Yamahata | root_cmd & PCI_ERR_ROOT_CMD_NONFATAL_EN) { |
312 | 34e65944 | Isaku Yamahata | msi_trigger = true;
|
313 | 34e65944 | Isaku Yamahata | } |
314 | 34e65944 | Isaku Yamahata | root_status |= PCI_ERR_ROOT_NONFATAL_RCV; |
315 | 34e65944 | Isaku Yamahata | break;
|
316 | 34e65944 | Isaku Yamahata | case PCI_ERR_ROOT_CMD_FATAL_EN:
|
317 | 34e65944 | Isaku Yamahata | if (!(root_status & PCI_ERR_ROOT_FATAL_RCV) &&
|
318 | 34e65944 | Isaku Yamahata | root_cmd & PCI_ERR_ROOT_CMD_FATAL_EN) { |
319 | 34e65944 | Isaku Yamahata | msi_trigger = true;
|
320 | 34e65944 | Isaku Yamahata | } |
321 | 34e65944 | Isaku Yamahata | if (!(root_status & PCI_ERR_ROOT_UNCOR_RCV)) {
|
322 | 34e65944 | Isaku Yamahata | root_status |= PCI_ERR_ROOT_FIRST_FATAL; |
323 | 34e65944 | Isaku Yamahata | } |
324 | 34e65944 | Isaku Yamahata | root_status |= PCI_ERR_ROOT_FATAL_RCV; |
325 | 34e65944 | Isaku Yamahata | break;
|
326 | 34e65944 | Isaku Yamahata | default:
|
327 | 34e65944 | Isaku Yamahata | abort(); |
328 | 34e65944 | Isaku Yamahata | break;
|
329 | 34e65944 | Isaku Yamahata | } |
330 | 34e65944 | Isaku Yamahata | if (pcie_aer_msg_is_uncor(msg)) {
|
331 | 34e65944 | Isaku Yamahata | if (root_status & PCI_ERR_ROOT_UNCOR_RCV) {
|
332 | 34e65944 | Isaku Yamahata | root_status |= PCI_ERR_ROOT_MULTI_UNCOR_RCV; |
333 | 34e65944 | Isaku Yamahata | } else {
|
334 | 34e65944 | Isaku Yamahata | pci_set_word(aer_cap + PCI_ERR_ROOT_SRC, msg->source_id); |
335 | 34e65944 | Isaku Yamahata | } |
336 | 34e65944 | Isaku Yamahata | root_status |= PCI_ERR_ROOT_UNCOR_RCV; |
337 | 34e65944 | Isaku Yamahata | } |
338 | 34e65944 | Isaku Yamahata | pci_set_long(aer_cap + PCI_ERR_ROOT_STATUS, root_status); |
339 | 34e65944 | Isaku Yamahata | |
340 | 34e65944 | Isaku Yamahata | if (root_cmd & msg->severity) {
|
341 | 34e65944 | Isaku Yamahata | /* 6.2.4.1.2 Interrupt Generation */
|
342 | 34e65944 | Isaku Yamahata | if (pci_msi_enabled(dev)) {
|
343 | 34e65944 | Isaku Yamahata | if (msi_trigger) {
|
344 | 34e65944 | Isaku Yamahata | pci_msi_notify(dev, pcie_aer_root_get_vector(dev)); |
345 | 34e65944 | Isaku Yamahata | } |
346 | 34e65944 | Isaku Yamahata | } else {
|
347 | 34e65944 | Isaku Yamahata | qemu_set_irq(dev->irq[dev->exp.aer_intx], 1);
|
348 | 34e65944 | Isaku Yamahata | } |
349 | 34e65944 | Isaku Yamahata | msg_sent = true;
|
350 | 34e65944 | Isaku Yamahata | } |
351 | 34e65944 | Isaku Yamahata | return msg_sent;
|
352 | 34e65944 | Isaku Yamahata | } |
353 | 34e65944 | Isaku Yamahata | |
354 | 34e65944 | Isaku Yamahata | /*
|
355 | 34e65944 | Isaku Yamahata | * 6.2.6 Error Message Control Figure 6-3
|
356 | 247c97f3 | Michael S. Tsirkin | *
|
357 | d33d9156 | Michael S. Tsirkin | * Walk up the bus tree from the device, propagate the error message.
|
358 | 34e65944 | Isaku Yamahata | */
|
359 | d33d9156 | Michael S. Tsirkin | static void pcie_aer_msg(PCIDevice *dev, const PCIEAERMsg *msg) |
360 | 34e65944 | Isaku Yamahata | { |
361 | 34e65944 | Isaku Yamahata | uint8_t type; |
362 | 34e65944 | Isaku Yamahata | |
363 | d33d9156 | Michael S. Tsirkin | while (dev) {
|
364 | d33d9156 | Michael S. Tsirkin | if (!pci_is_express(dev)) {
|
365 | d33d9156 | Michael S. Tsirkin | /* just ignore it */
|
366 | d33d9156 | Michael S. Tsirkin | /* TODO: Shouldn't we set PCI_STATUS_SIG_SYSTEM_ERROR?
|
367 | d33d9156 | Michael S. Tsirkin | * Consider e.g. a PCI bridge above a PCI Express device. */
|
368 | 34e65944 | Isaku Yamahata | return;
|
369 | 34e65944 | Isaku Yamahata | } |
370 | 247c97f3 | Michael S. Tsirkin | |
371 | d33d9156 | Michael S. Tsirkin | type = pcie_cap_get_type(dev); |
372 | d33d9156 | Michael S. Tsirkin | if ((type == PCI_EXP_TYPE_ROOT_PORT ||
|
373 | d33d9156 | Michael S. Tsirkin | type == PCI_EXP_TYPE_UPSTREAM || |
374 | d33d9156 | Michael S. Tsirkin | type == PCI_EXP_TYPE_DOWNSTREAM) && |
375 | d33d9156 | Michael S. Tsirkin | !pcie_aer_msg_vbridge(dev, msg)) { |
376 | d33d9156 | Michael S. Tsirkin | return;
|
377 | d33d9156 | Michael S. Tsirkin | } |
378 | d33d9156 | Michael S. Tsirkin | if (!pcie_aer_msg_alldev(dev, msg)) {
|
379 | d33d9156 | Michael S. Tsirkin | return;
|
380 | d33d9156 | Michael S. Tsirkin | } |
381 | d33d9156 | Michael S. Tsirkin | if (type == PCI_EXP_TYPE_ROOT_PORT) {
|
382 | d33d9156 | Michael S. Tsirkin | pcie_aer_msg_root_port(dev, msg); |
383 | d33d9156 | Michael S. Tsirkin | /* Root port can notify system itself,
|
384 | d33d9156 | Michael S. Tsirkin | or send the error message to root complex event collector. */
|
385 | d33d9156 | Michael S. Tsirkin | /*
|
386 | d33d9156 | Michael S. Tsirkin | * if root port is associated with an event collector,
|
387 | d33d9156 | Michael S. Tsirkin | * return the root complex event collector here.
|
388 | d33d9156 | Michael S. Tsirkin | * For now root complex event collector isn't supported.
|
389 | d33d9156 | Michael S. Tsirkin | */
|
390 | 247c97f3 | Michael S. Tsirkin | return;
|
391 | 247c97f3 | Michael S. Tsirkin | } |
392 | d33d9156 | Michael S. Tsirkin | dev = pci_bridge_get_device(dev->bus); |
393 | 247c97f3 | Michael S. Tsirkin | } |
394 | 34e65944 | Isaku Yamahata | } |
395 | 34e65944 | Isaku Yamahata | |
396 | 34e65944 | Isaku Yamahata | static void pcie_aer_update_log(PCIDevice *dev, const PCIEAERErr *err) |
397 | 34e65944 | Isaku Yamahata | { |
398 | 34e65944 | Isaku Yamahata | uint8_t *aer_cap = dev->config + dev->exp.aer_cap; |
399 | 34e65944 | Isaku Yamahata | uint8_t first_bit = ffsl(err->status) - 1;
|
400 | 34e65944 | Isaku Yamahata | uint32_t errcap = pci_get_long(aer_cap + PCI_ERR_CAP); |
401 | 34e65944 | Isaku Yamahata | int i;
|
402 | 34e65944 | Isaku Yamahata | |
403 | 34e65944 | Isaku Yamahata | assert(err->status); |
404 | 34e65944 | Isaku Yamahata | assert(err->status & (err->status - 1));
|
405 | 34e65944 | Isaku Yamahata | |
406 | 34e65944 | Isaku Yamahata | errcap &= ~(PCI_ERR_CAP_FEP_MASK | PCI_ERR_CAP_TLP); |
407 | 34e65944 | Isaku Yamahata | errcap |= PCI_ERR_CAP_FEP(first_bit); |
408 | 34e65944 | Isaku Yamahata | |
409 | 34e65944 | Isaku Yamahata | if (err->flags & PCIE_AER_ERR_HEADER_VALID) {
|
410 | 34e65944 | Isaku Yamahata | for (i = 0; i < ARRAY_SIZE(err->header); ++i) { |
411 | 34e65944 | Isaku Yamahata | /* 7.10.8 Header Log Register */
|
412 | 34e65944 | Isaku Yamahata | uint8_t *header_log = |
413 | 34e65944 | Isaku Yamahata | aer_cap + PCI_ERR_HEADER_LOG + i * sizeof err->header[0]; |
414 | 34e65944 | Isaku Yamahata | cpu_to_be32wu((uint32_t*)header_log, err->header[i]); |
415 | 34e65944 | Isaku Yamahata | } |
416 | 34e65944 | Isaku Yamahata | } else {
|
417 | 34e65944 | Isaku Yamahata | assert(!(err->flags & PCIE_AER_ERR_TLP_PREFIX_PRESENT)); |
418 | 34e65944 | Isaku Yamahata | memset(aer_cap + PCI_ERR_HEADER_LOG, 0, PCI_ERR_HEADER_LOG_SIZE);
|
419 | 34e65944 | Isaku Yamahata | } |
420 | 34e65944 | Isaku Yamahata | |
421 | 34e65944 | Isaku Yamahata | if ((err->flags & PCIE_AER_ERR_TLP_PREFIX_PRESENT) &&
|
422 | 34e65944 | Isaku Yamahata | (pci_get_long(dev->config + dev->exp.exp_cap + PCI_EXP_DEVCTL2) & |
423 | 34e65944 | Isaku Yamahata | PCI_EXP_DEVCAP2_EETLPP)) { |
424 | 34e65944 | Isaku Yamahata | for (i = 0; i < ARRAY_SIZE(err->prefix); ++i) { |
425 | 34e65944 | Isaku Yamahata | /* 7.10.12 tlp prefix log register */
|
426 | 34e65944 | Isaku Yamahata | uint8_t *prefix_log = |
427 | 34e65944 | Isaku Yamahata | aer_cap + PCI_ERR_TLP_PREFIX_LOG + i * sizeof err->prefix[0]; |
428 | 34e65944 | Isaku Yamahata | cpu_to_be32wu((uint32_t*)prefix_log, err->prefix[i]); |
429 | 34e65944 | Isaku Yamahata | } |
430 | 34e65944 | Isaku Yamahata | errcap |= PCI_ERR_CAP_TLP; |
431 | 34e65944 | Isaku Yamahata | } else {
|
432 | 34e65944 | Isaku Yamahata | memset(aer_cap + PCI_ERR_TLP_PREFIX_LOG, 0,
|
433 | 34e65944 | Isaku Yamahata | PCI_ERR_TLP_PREFIX_LOG_SIZE); |
434 | 34e65944 | Isaku Yamahata | } |
435 | 34e65944 | Isaku Yamahata | pci_set_long(aer_cap + PCI_ERR_CAP, errcap); |
436 | 34e65944 | Isaku Yamahata | } |
437 | 34e65944 | Isaku Yamahata | |
438 | 34e65944 | Isaku Yamahata | static void pcie_aer_clear_log(PCIDevice *dev) |
439 | 34e65944 | Isaku Yamahata | { |
440 | 34e65944 | Isaku Yamahata | uint8_t *aer_cap = dev->config + dev->exp.aer_cap; |
441 | 34e65944 | Isaku Yamahata | |
442 | 34e65944 | Isaku Yamahata | pci_long_test_and_clear_mask(aer_cap + PCI_ERR_CAP, |
443 | 34e65944 | Isaku Yamahata | PCI_ERR_CAP_FEP_MASK | PCI_ERR_CAP_TLP); |
444 | 34e65944 | Isaku Yamahata | |
445 | 34e65944 | Isaku Yamahata | memset(aer_cap + PCI_ERR_HEADER_LOG, 0, PCI_ERR_HEADER_LOG_SIZE);
|
446 | 34e65944 | Isaku Yamahata | memset(aer_cap + PCI_ERR_TLP_PREFIX_LOG, 0, PCI_ERR_TLP_PREFIX_LOG_SIZE);
|
447 | 34e65944 | Isaku Yamahata | } |
448 | 34e65944 | Isaku Yamahata | |
449 | 34e65944 | Isaku Yamahata | static void pcie_aer_clear_error(PCIDevice *dev) |
450 | 34e65944 | Isaku Yamahata | { |
451 | 34e65944 | Isaku Yamahata | uint8_t *aer_cap = dev->config + dev->exp.aer_cap; |
452 | 34e65944 | Isaku Yamahata | uint32_t errcap = pci_get_long(aer_cap + PCI_ERR_CAP); |
453 | 34e65944 | Isaku Yamahata | PCIEAERLog *aer_log = &dev->exp.aer_log; |
454 | 34e65944 | Isaku Yamahata | PCIEAERErr err; |
455 | 34e65944 | Isaku Yamahata | |
456 | 34e65944 | Isaku Yamahata | if (!(errcap & PCI_ERR_CAP_MHRE) || !aer_log->log_num) {
|
457 | 34e65944 | Isaku Yamahata | pcie_aer_clear_log(dev); |
458 | 34e65944 | Isaku Yamahata | return;
|
459 | 34e65944 | Isaku Yamahata | } |
460 | 34e65944 | Isaku Yamahata | |
461 | 34e65944 | Isaku Yamahata | /*
|
462 | 34e65944 | Isaku Yamahata | * If more errors are queued, set corresponding bits in uncorrectable
|
463 | 34e65944 | Isaku Yamahata | * error status.
|
464 | 34e65944 | Isaku Yamahata | * We emulate uncorrectable error status register as W1CS.
|
465 | 34e65944 | Isaku Yamahata | * So set bit in uncorrectable error status here again for multiple
|
466 | 34e65944 | Isaku Yamahata | * error recording support.
|
467 | 34e65944 | Isaku Yamahata | *
|
468 | 34e65944 | Isaku Yamahata | * 6.2.4.2 Multiple Error Handling(Advanced Error Reporting Capability)
|
469 | 34e65944 | Isaku Yamahata | */
|
470 | 34e65944 | Isaku Yamahata | pcie_aer_update_uncor_status(dev); |
471 | 34e65944 | Isaku Yamahata | |
472 | 34e65944 | Isaku Yamahata | aer_log_del_err(aer_log, &err); |
473 | 34e65944 | Isaku Yamahata | pcie_aer_update_log(dev, &err); |
474 | 34e65944 | Isaku Yamahata | } |
475 | 34e65944 | Isaku Yamahata | |
476 | 34e65944 | Isaku Yamahata | static int pcie_aer_record_error(PCIDevice *dev, |
477 | 34e65944 | Isaku Yamahata | const PCIEAERErr *err)
|
478 | 34e65944 | Isaku Yamahata | { |
479 | 34e65944 | Isaku Yamahata | uint8_t *aer_cap = dev->config + dev->exp.aer_cap; |
480 | 34e65944 | Isaku Yamahata | uint32_t errcap = pci_get_long(aer_cap + PCI_ERR_CAP); |
481 | 34e65944 | Isaku Yamahata | int fep = PCI_ERR_CAP_FEP(errcap);
|
482 | 34e65944 | Isaku Yamahata | |
483 | 34e65944 | Isaku Yamahata | assert(err->status); |
484 | 34e65944 | Isaku Yamahata | assert(err->status & (err->status - 1));
|
485 | 34e65944 | Isaku Yamahata | |
486 | 34e65944 | Isaku Yamahata | if (errcap & PCI_ERR_CAP_MHRE &&
|
487 | 34e65944 | Isaku Yamahata | (pci_get_long(aer_cap + PCI_ERR_UNCOR_STATUS) & (1U << fep))) {
|
488 | 34e65944 | Isaku Yamahata | /* Not first error. queue error */
|
489 | 34e65944 | Isaku Yamahata | if (aer_log_add_err(&dev->exp.aer_log, err) < 0) { |
490 | 34e65944 | Isaku Yamahata | /* overflow */
|
491 | 34e65944 | Isaku Yamahata | return -1; |
492 | 34e65944 | Isaku Yamahata | } |
493 | 34e65944 | Isaku Yamahata | return 0; |
494 | 34e65944 | Isaku Yamahata | } |
495 | 34e65944 | Isaku Yamahata | |
496 | 34e65944 | Isaku Yamahata | pcie_aer_update_log(dev, err); |
497 | 34e65944 | Isaku Yamahata | return 0; |
498 | 34e65944 | Isaku Yamahata | } |
499 | 34e65944 | Isaku Yamahata | |
500 | 34e65944 | Isaku Yamahata | typedef struct PCIEAERInject { |
501 | 34e65944 | Isaku Yamahata | PCIDevice *dev; |
502 | 34e65944 | Isaku Yamahata | uint8_t *aer_cap; |
503 | 34e65944 | Isaku Yamahata | const PCIEAERErr *err;
|
504 | 34e65944 | Isaku Yamahata | uint16_t devctl; |
505 | 34e65944 | Isaku Yamahata | uint16_t devsta; |
506 | 34e65944 | Isaku Yamahata | uint32_t error_status; |
507 | 34e65944 | Isaku Yamahata | bool unsupported_request;
|
508 | 34e65944 | Isaku Yamahata | bool log_overflow;
|
509 | 34e65944 | Isaku Yamahata | PCIEAERMsg msg; |
510 | 34e65944 | Isaku Yamahata | } PCIEAERInject; |
511 | 34e65944 | Isaku Yamahata | |
512 | 34e65944 | Isaku Yamahata | static bool pcie_aer_inject_cor_error(PCIEAERInject *inj, |
513 | 34e65944 | Isaku Yamahata | uint32_t uncor_status, |
514 | 34e65944 | Isaku Yamahata | bool is_advisory_nonfatal)
|
515 | 34e65944 | Isaku Yamahata | { |
516 | 34e65944 | Isaku Yamahata | PCIDevice *dev = inj->dev; |
517 | 34e65944 | Isaku Yamahata | |
518 | 34e65944 | Isaku Yamahata | inj->devsta |= PCI_EXP_DEVSTA_CED; |
519 | 34e65944 | Isaku Yamahata | if (inj->unsupported_request) {
|
520 | 34e65944 | Isaku Yamahata | inj->devsta |= PCI_EXP_DEVSTA_URD; |
521 | 34e65944 | Isaku Yamahata | } |
522 | 34e65944 | Isaku Yamahata | pci_set_word(dev->config + dev->exp.exp_cap + PCI_EXP_DEVSTA, inj->devsta); |
523 | 34e65944 | Isaku Yamahata | |
524 | 34e65944 | Isaku Yamahata | if (inj->aer_cap) {
|
525 | 34e65944 | Isaku Yamahata | uint32_t mask; |
526 | 34e65944 | Isaku Yamahata | pci_long_test_and_set_mask(inj->aer_cap + PCI_ERR_COR_STATUS, |
527 | 34e65944 | Isaku Yamahata | inj->error_status); |
528 | 34e65944 | Isaku Yamahata | mask = pci_get_long(inj->aer_cap + PCI_ERR_COR_MASK); |
529 | 34e65944 | Isaku Yamahata | if (mask & inj->error_status) {
|
530 | 34e65944 | Isaku Yamahata | return false; |
531 | 34e65944 | Isaku Yamahata | } |
532 | 34e65944 | Isaku Yamahata | if (is_advisory_nonfatal) {
|
533 | 34e65944 | Isaku Yamahata | uint32_t uncor_mask = |
534 | 34e65944 | Isaku Yamahata | pci_get_long(inj->aer_cap + PCI_ERR_UNCOR_MASK); |
535 | 34e65944 | Isaku Yamahata | if (!(uncor_mask & uncor_status)) {
|
536 | 34e65944 | Isaku Yamahata | inj->log_overflow = !!pcie_aer_record_error(dev, inj->err); |
537 | 34e65944 | Isaku Yamahata | } |
538 | 34e65944 | Isaku Yamahata | pci_long_test_and_set_mask(inj->aer_cap + PCI_ERR_UNCOR_STATUS, |
539 | 34e65944 | Isaku Yamahata | uncor_status); |
540 | 34e65944 | Isaku Yamahata | } |
541 | 34e65944 | Isaku Yamahata | } |
542 | 34e65944 | Isaku Yamahata | |
543 | 34e65944 | Isaku Yamahata | if (inj->unsupported_request && !(inj->devctl & PCI_EXP_DEVCTL_URRE)) {
|
544 | 34e65944 | Isaku Yamahata | return false; |
545 | 34e65944 | Isaku Yamahata | } |
546 | 34e65944 | Isaku Yamahata | if (!(inj->devctl & PCI_EXP_DEVCTL_CERE)) {
|
547 | 34e65944 | Isaku Yamahata | return false; |
548 | 34e65944 | Isaku Yamahata | } |
549 | 34e65944 | Isaku Yamahata | |
550 | 34e65944 | Isaku Yamahata | inj->msg.severity = PCI_ERR_ROOT_CMD_COR_EN; |
551 | 34e65944 | Isaku Yamahata | return true; |
552 | 34e65944 | Isaku Yamahata | } |
553 | 34e65944 | Isaku Yamahata | |
554 | 34e65944 | Isaku Yamahata | static bool pcie_aer_inject_uncor_error(PCIEAERInject *inj, bool is_fatal) |
555 | 34e65944 | Isaku Yamahata | { |
556 | 34e65944 | Isaku Yamahata | PCIDevice *dev = inj->dev; |
557 | 34e65944 | Isaku Yamahata | uint16_t cmd; |
558 | 34e65944 | Isaku Yamahata | |
559 | 34e65944 | Isaku Yamahata | if (is_fatal) {
|
560 | 34e65944 | Isaku Yamahata | inj->devsta |= PCI_EXP_DEVSTA_FED; |
561 | 34e65944 | Isaku Yamahata | } else {
|
562 | 34e65944 | Isaku Yamahata | inj->devsta |= PCI_EXP_DEVSTA_NFED; |
563 | 34e65944 | Isaku Yamahata | } |
564 | 34e65944 | Isaku Yamahata | if (inj->unsupported_request) {
|
565 | 34e65944 | Isaku Yamahata | inj->devsta |= PCI_EXP_DEVSTA_URD; |
566 | 34e65944 | Isaku Yamahata | } |
567 | 34e65944 | Isaku Yamahata | pci_set_long(dev->config + dev->exp.exp_cap + PCI_EXP_DEVSTA, inj->devsta); |
568 | 34e65944 | Isaku Yamahata | |
569 | 34e65944 | Isaku Yamahata | if (inj->aer_cap) {
|
570 | 34e65944 | Isaku Yamahata | uint32_t mask = pci_get_long(inj->aer_cap + PCI_ERR_UNCOR_MASK); |
571 | 34e65944 | Isaku Yamahata | if (mask & inj->error_status) {
|
572 | 34e65944 | Isaku Yamahata | pci_long_test_and_set_mask(inj->aer_cap + PCI_ERR_UNCOR_STATUS, |
573 | 34e65944 | Isaku Yamahata | inj->error_status); |
574 | 34e65944 | Isaku Yamahata | return false; |
575 | 34e65944 | Isaku Yamahata | } |
576 | 34e65944 | Isaku Yamahata | |
577 | 34e65944 | Isaku Yamahata | inj->log_overflow = !!pcie_aer_record_error(dev, inj->err); |
578 | 34e65944 | Isaku Yamahata | pci_long_test_and_set_mask(inj->aer_cap + PCI_ERR_UNCOR_STATUS, |
579 | 34e65944 | Isaku Yamahata | inj->error_status); |
580 | 34e65944 | Isaku Yamahata | } |
581 | 34e65944 | Isaku Yamahata | |
582 | 34e65944 | Isaku Yamahata | cmd = pci_get_word(dev->config + PCI_COMMAND); |
583 | 34e65944 | Isaku Yamahata | if (inj->unsupported_request &&
|
584 | 34e65944 | Isaku Yamahata | !(inj->devctl & PCI_EXP_DEVCTL_URRE) && !(cmd & PCI_COMMAND_SERR)) { |
585 | 34e65944 | Isaku Yamahata | return false; |
586 | 34e65944 | Isaku Yamahata | } |
587 | 34e65944 | Isaku Yamahata | if (is_fatal) {
|
588 | 34e65944 | Isaku Yamahata | if (!((cmd & PCI_COMMAND_SERR) ||
|
589 | 34e65944 | Isaku Yamahata | (inj->devctl & PCI_EXP_DEVCTL_FERE))) { |
590 | 34e65944 | Isaku Yamahata | return false; |
591 | 34e65944 | Isaku Yamahata | } |
592 | 34e65944 | Isaku Yamahata | inj->msg.severity = PCI_ERR_ROOT_CMD_FATAL_EN; |
593 | 34e65944 | Isaku Yamahata | } else {
|
594 | 34e65944 | Isaku Yamahata | if (!((cmd & PCI_COMMAND_SERR) ||
|
595 | 34e65944 | Isaku Yamahata | (inj->devctl & PCI_EXP_DEVCTL_NFERE))) { |
596 | 34e65944 | Isaku Yamahata | return false; |
597 | 34e65944 | Isaku Yamahata | } |
598 | 34e65944 | Isaku Yamahata | inj->msg.severity = PCI_ERR_ROOT_CMD_NONFATAL_EN; |
599 | 34e65944 | Isaku Yamahata | } |
600 | 34e65944 | Isaku Yamahata | return true; |
601 | 34e65944 | Isaku Yamahata | } |
602 | 34e65944 | Isaku Yamahata | |
603 | 34e65944 | Isaku Yamahata | /*
|
604 | 34e65944 | Isaku Yamahata | * non-Function specific error must be recorded in all functions.
|
605 | 34e65944 | Isaku Yamahata | * It is the responsibility of the caller of this function.
|
606 | 34e65944 | Isaku Yamahata | * It is also caller's responsiblity to determine which function should
|
607 | 34e65944 | Isaku Yamahata | * report the rerror.
|
608 | 34e65944 | Isaku Yamahata | *
|
609 | 34e65944 | Isaku Yamahata | * 6.2.4 Error Logging
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610 | 34e65944 | Isaku Yamahata | * 6.2.5 Sqeunce of Device Error Signaling and Logging Operations
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611 | 34e65944 | Isaku Yamahata | * table 6-2: Flowchard Showing Sequence of Device Error Signaling and Logging
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612 | 34e65944 | Isaku Yamahata | * Operations
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613 | 34e65944 | Isaku Yamahata | */
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614 | 34e65944 | Isaku Yamahata | int pcie_aer_inject_error(PCIDevice *dev, const PCIEAERErr *err) |
615 | 34e65944 | Isaku Yamahata | { |
616 | 34e65944 | Isaku Yamahata | uint8_t *aer_cap = NULL;
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617 | 34e65944 | Isaku Yamahata | uint16_t devctl = 0;
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618 | 34e65944 | Isaku Yamahata | uint16_t devsta = 0;
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619 | 34e65944 | Isaku Yamahata | uint32_t error_status = err->status; |
620 | 34e65944 | Isaku Yamahata | PCIEAERInject inj; |
621 | 34e65944 | Isaku Yamahata | |
622 | 34e65944 | Isaku Yamahata | if (!pci_is_express(dev)) {
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623 | 34e65944 | Isaku Yamahata | return -ENOSYS;
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624 | 34e65944 | Isaku Yamahata | } |
625 | 34e65944 | Isaku Yamahata | |
626 | 34e65944 | Isaku Yamahata | if (err->flags & PCIE_AER_ERR_IS_CORRECTABLE) {
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627 | 34e65944 | Isaku Yamahata | error_status &= PCI_ERR_COR_SUPPORTED; |
628 | 34e65944 | Isaku Yamahata | } else {
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629 | 34e65944 | Isaku Yamahata | error_status &= PCI_ERR_UNC_SUPPORTED; |
630 | 34e65944 | Isaku Yamahata | } |
631 | 34e65944 | Isaku Yamahata | |
632 | 34e65944 | Isaku Yamahata | /* invalid status bit. one and only one bit must be set */
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633 | 34e65944 | Isaku Yamahata | if (!error_status || (error_status & (error_status - 1))) { |
634 | 34e65944 | Isaku Yamahata | return -EINVAL;
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635 | 34e65944 | Isaku Yamahata | } |
636 | 34e65944 | Isaku Yamahata | |
637 | 34e65944 | Isaku Yamahata | if (dev->exp.aer_cap) {
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638 | 34e65944 | Isaku Yamahata | uint8_t *exp_cap = dev->config + dev->exp.exp_cap; |
639 | 34e65944 | Isaku Yamahata | aer_cap = dev->config + dev->exp.aer_cap; |
640 | 34e65944 | Isaku Yamahata | devctl = pci_get_long(exp_cap + PCI_EXP_DEVCTL); |
641 | 34e65944 | Isaku Yamahata | devsta = pci_get_long(exp_cap + PCI_EXP_DEVSTA); |
642 | 34e65944 | Isaku Yamahata | } |
643 | 34e65944 | Isaku Yamahata | |
644 | 34e65944 | Isaku Yamahata | inj.dev = dev; |
645 | 34e65944 | Isaku Yamahata | inj.aer_cap = aer_cap; |
646 | 34e65944 | Isaku Yamahata | inj.err = err; |
647 | 34e65944 | Isaku Yamahata | inj.devctl = devctl; |
648 | 34e65944 | Isaku Yamahata | inj.devsta = devsta; |
649 | 34e65944 | Isaku Yamahata | inj.error_status = error_status; |
650 | 34e65944 | Isaku Yamahata | inj.unsupported_request = !(err->flags & PCIE_AER_ERR_IS_CORRECTABLE) && |
651 | 34e65944 | Isaku Yamahata | err->status == PCI_ERR_UNC_UNSUP; |
652 | 34e65944 | Isaku Yamahata | inj.log_overflow = false;
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653 | 34e65944 | Isaku Yamahata | |
654 | 34e65944 | Isaku Yamahata | if (err->flags & PCIE_AER_ERR_IS_CORRECTABLE) {
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655 | 34e65944 | Isaku Yamahata | if (!pcie_aer_inject_cor_error(&inj, 0, false)) { |
656 | 34e65944 | Isaku Yamahata | return 0; |
657 | 34e65944 | Isaku Yamahata | } |
658 | 34e65944 | Isaku Yamahata | } else {
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659 | 34e65944 | Isaku Yamahata | bool is_fatal =
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660 | 34e65944 | Isaku Yamahata | pcie_aer_uncor_default_severity(error_status) == |
661 | 34e65944 | Isaku Yamahata | PCI_ERR_ROOT_CMD_FATAL_EN; |
662 | 34e65944 | Isaku Yamahata | if (aer_cap) {
|
663 | 34e65944 | Isaku Yamahata | is_fatal = |
664 | 34e65944 | Isaku Yamahata | error_status & pci_get_long(aer_cap + PCI_ERR_UNCOR_SEVER); |
665 | 34e65944 | Isaku Yamahata | } |
666 | 34e65944 | Isaku Yamahata | if (!is_fatal && (err->flags & PCIE_AER_ERR_MAYBE_ADVISORY)) {
|
667 | 34e65944 | Isaku Yamahata | inj.error_status = PCI_ERR_COR_ADV_NONFATAL; |
668 | 34e65944 | Isaku Yamahata | if (!pcie_aer_inject_cor_error(&inj, error_status, true)) { |
669 | 34e65944 | Isaku Yamahata | return 0; |
670 | 34e65944 | Isaku Yamahata | } |
671 | 34e65944 | Isaku Yamahata | } else {
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672 | 34e65944 | Isaku Yamahata | if (!pcie_aer_inject_uncor_error(&inj, is_fatal)) {
|
673 | 34e65944 | Isaku Yamahata | return 0; |
674 | 34e65944 | Isaku Yamahata | } |
675 | 34e65944 | Isaku Yamahata | } |
676 | 34e65944 | Isaku Yamahata | } |
677 | 34e65944 | Isaku Yamahata | |
678 | 34e65944 | Isaku Yamahata | /* send up error message */
|
679 | 34e65944 | Isaku Yamahata | inj.msg.source_id = err->source_id; |
680 | 34e65944 | Isaku Yamahata | pcie_aer_msg(dev, &inj.msg); |
681 | 34e65944 | Isaku Yamahata | |
682 | 34e65944 | Isaku Yamahata | if (inj.log_overflow) {
|
683 | 34e65944 | Isaku Yamahata | PCIEAERErr header_log_overflow = { |
684 | 34e65944 | Isaku Yamahata | .status = PCI_ERR_COR_HL_OVERFLOW, |
685 | 34e65944 | Isaku Yamahata | .flags = PCIE_AER_ERR_IS_CORRECTABLE, |
686 | 34e65944 | Isaku Yamahata | }; |
687 | 34e65944 | Isaku Yamahata | int ret = pcie_aer_inject_error(dev, &header_log_overflow);
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688 | 34e65944 | Isaku Yamahata | assert(!ret); |
689 | 34e65944 | Isaku Yamahata | } |
690 | 34e65944 | Isaku Yamahata | return 0; |
691 | 34e65944 | Isaku Yamahata | } |
692 | 34e65944 | Isaku Yamahata | |
693 | 34e65944 | Isaku Yamahata | void pcie_aer_write_config(PCIDevice *dev,
|
694 | 34e65944 | Isaku Yamahata | uint32_t addr, uint32_t val, int len)
|
695 | 34e65944 | Isaku Yamahata | { |
696 | 34e65944 | Isaku Yamahata | uint8_t *aer_cap = dev->config + dev->exp.aer_cap; |
697 | 34e65944 | Isaku Yamahata | uint32_t errcap = pci_get_long(aer_cap + PCI_ERR_CAP); |
698 | 34e65944 | Isaku Yamahata | uint32_t first_error = 1U << PCI_ERR_CAP_FEP(errcap);
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699 | 34e65944 | Isaku Yamahata | uint32_t uncorsta = pci_get_long(aer_cap + PCI_ERR_UNCOR_STATUS); |
700 | 34e65944 | Isaku Yamahata | |
701 | 34e65944 | Isaku Yamahata | /* uncorrectable error */
|
702 | 34e65944 | Isaku Yamahata | if (!(uncorsta & first_error)) {
|
703 | 34e65944 | Isaku Yamahata | /* the bit that corresponds to the first error is cleared */
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704 | 34e65944 | Isaku Yamahata | pcie_aer_clear_error(dev); |
705 | 34e65944 | Isaku Yamahata | } else if (errcap & PCI_ERR_CAP_MHRE) { |
706 | 34e65944 | Isaku Yamahata | /* When PCI_ERR_CAP_MHRE is enabled and the first error isn't cleared
|
707 | 34e65944 | Isaku Yamahata | * nothing should happen. So we have to revert the modification to
|
708 | 34e65944 | Isaku Yamahata | * the register.
|
709 | 34e65944 | Isaku Yamahata | */
|
710 | 34e65944 | Isaku Yamahata | pcie_aer_update_uncor_status(dev); |
711 | 34e65944 | Isaku Yamahata | } else {
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712 | 34e65944 | Isaku Yamahata | /* capability & control
|
713 | 34e65944 | Isaku Yamahata | * PCI_ERR_CAP_MHRE might be cleared, so clear of header log.
|
714 | 34e65944 | Isaku Yamahata | */
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715 | 34e65944 | Isaku Yamahata | aer_log_clear_all_err(&dev->exp.aer_log); |
716 | 34e65944 | Isaku Yamahata | } |
717 | 34e65944 | Isaku Yamahata | } |
718 | 34e65944 | Isaku Yamahata | |
719 | 34e65944 | Isaku Yamahata | void pcie_aer_root_init(PCIDevice *dev)
|
720 | 34e65944 | Isaku Yamahata | { |
721 | 34e65944 | Isaku Yamahata | uint16_t pos = dev->exp.aer_cap; |
722 | 34e65944 | Isaku Yamahata | |
723 | 34e65944 | Isaku Yamahata | pci_set_long(dev->wmask + pos + PCI_ERR_ROOT_COMMAND, |
724 | 34e65944 | Isaku Yamahata | PCI_ERR_ROOT_CMD_EN_MASK); |
725 | 34e65944 | Isaku Yamahata | pci_set_long(dev->w1cmask + pos + PCI_ERR_ROOT_STATUS, |
726 | 34e65944 | Isaku Yamahata | PCI_ERR_ROOT_STATUS_REPORT_MASK); |
727 | 34e65944 | Isaku Yamahata | } |
728 | 34e65944 | Isaku Yamahata | |
729 | 34e65944 | Isaku Yamahata | void pcie_aer_root_reset(PCIDevice *dev)
|
730 | 34e65944 | Isaku Yamahata | { |
731 | 34e65944 | Isaku Yamahata | uint8_t* aer_cap = dev->config + dev->exp.aer_cap; |
732 | 34e65944 | Isaku Yamahata | |
733 | 34e65944 | Isaku Yamahata | pci_set_long(aer_cap + PCI_ERR_ROOT_COMMAND, 0);
|
734 | 34e65944 | Isaku Yamahata | |
735 | 34e65944 | Isaku Yamahata | /*
|
736 | 34e65944 | Isaku Yamahata | * Advanced Error Interrupt Message Number in Root Error Status Register
|
737 | 34e65944 | Isaku Yamahata | * must be updated by chip dependent code because it's chip dependent
|
738 | 34e65944 | Isaku Yamahata | * which number is used.
|
739 | 34e65944 | Isaku Yamahata | */
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740 | 34e65944 | Isaku Yamahata | } |
741 | 34e65944 | Isaku Yamahata | |
742 | 34e65944 | Isaku Yamahata | static bool pcie_aer_root_does_trigger(uint32_t cmd, uint32_t status) |
743 | 34e65944 | Isaku Yamahata | { |
744 | 34e65944 | Isaku Yamahata | return
|
745 | 34e65944 | Isaku Yamahata | ((cmd & PCI_ERR_ROOT_CMD_COR_EN) && (status & PCI_ERR_ROOT_COR_RCV)) || |
746 | 34e65944 | Isaku Yamahata | ((cmd & PCI_ERR_ROOT_CMD_NONFATAL_EN) && |
747 | 34e65944 | Isaku Yamahata | (status & PCI_ERR_ROOT_NONFATAL_RCV)) || |
748 | 34e65944 | Isaku Yamahata | ((cmd & PCI_ERR_ROOT_CMD_FATAL_EN) && |
749 | 34e65944 | Isaku Yamahata | (status & PCI_ERR_ROOT_FATAL_RCV)); |
750 | 34e65944 | Isaku Yamahata | } |
751 | 34e65944 | Isaku Yamahata | |
752 | 34e65944 | Isaku Yamahata | void pcie_aer_root_write_config(PCIDevice *dev,
|
753 | 34e65944 | Isaku Yamahata | uint32_t addr, uint32_t val, int len,
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754 | 34e65944 | Isaku Yamahata | uint32_t root_cmd_prev) |
755 | 34e65944 | Isaku Yamahata | { |
756 | 34e65944 | Isaku Yamahata | uint8_t *aer_cap = dev->config + dev->exp.aer_cap; |
757 | 34e65944 | Isaku Yamahata | |
758 | 34e65944 | Isaku Yamahata | /* root command register */
|
759 | 34e65944 | Isaku Yamahata | uint32_t root_cmd = pci_get_long(aer_cap + PCI_ERR_ROOT_COMMAND); |
760 | 34e65944 | Isaku Yamahata | if (root_cmd & PCI_ERR_ROOT_CMD_EN_MASK) {
|
761 | 34e65944 | Isaku Yamahata | /* 6.2.4.1.2 Interrupt Generation */
|
762 | 34e65944 | Isaku Yamahata | |
763 | 34e65944 | Isaku Yamahata | /* 0 -> 1 */
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764 | 34e65944 | Isaku Yamahata | uint32_t root_cmd_set = (root_cmd_prev ^ root_cmd) & root_cmd; |
765 | 34e65944 | Isaku Yamahata | uint32_t root_status = pci_get_long(aer_cap + PCI_ERR_ROOT_STATUS); |
766 | 34e65944 | Isaku Yamahata | |
767 | 34e65944 | Isaku Yamahata | if (pci_msi_enabled(dev)) {
|
768 | 34e65944 | Isaku Yamahata | if (pcie_aer_root_does_trigger(root_cmd_set, root_status)) {
|
769 | 34e65944 | Isaku Yamahata | pci_msi_notify(dev, pcie_aer_root_get_vector(dev)); |
770 | 34e65944 | Isaku Yamahata | } |
771 | 34e65944 | Isaku Yamahata | } else {
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772 | 34e65944 | Isaku Yamahata | int int_level = pcie_aer_root_does_trigger(root_cmd, root_status);
|
773 | 34e65944 | Isaku Yamahata | qemu_set_irq(dev->irq[dev->exp.aer_intx], int_level); |
774 | 34e65944 | Isaku Yamahata | } |
775 | 34e65944 | Isaku Yamahata | } |
776 | 34e65944 | Isaku Yamahata | } |
777 | 34e65944 | Isaku Yamahata | |
778 | 34e65944 | Isaku Yamahata | static const VMStateDescription vmstate_pcie_aer_err = { |
779 | 34e65944 | Isaku Yamahata | .name = "PCIE_AER_ERROR",
|
780 | 34e65944 | Isaku Yamahata | .version_id = 1,
|
781 | 34e65944 | Isaku Yamahata | .minimum_version_id = 1,
|
782 | 34e65944 | Isaku Yamahata | .minimum_version_id_old = 1,
|
783 | 34e65944 | Isaku Yamahata | .fields = (VMStateField[]) { |
784 | 34e65944 | Isaku Yamahata | VMSTATE_UINT32(status, PCIEAERErr), |
785 | 34e65944 | Isaku Yamahata | VMSTATE_UINT16(source_id, PCIEAERErr), |
786 | 34e65944 | Isaku Yamahata | VMSTATE_UINT16(flags, PCIEAERErr), |
787 | 34e65944 | Isaku Yamahata | VMSTATE_UINT32_ARRAY(header, PCIEAERErr, 4),
|
788 | 34e65944 | Isaku Yamahata | VMSTATE_UINT32_ARRAY(prefix, PCIEAERErr, 4),
|
789 | 34e65944 | Isaku Yamahata | VMSTATE_END_OF_LIST() |
790 | 34e65944 | Isaku Yamahata | } |
791 | 34e65944 | Isaku Yamahata | }; |
792 | 34e65944 | Isaku Yamahata | |
793 | 34e65944 | Isaku Yamahata | #define VMSTATE_PCIE_AER_ERRS(_field, _state, _field_num, _vmsd, _type) { \
|
794 | 34e65944 | Isaku Yamahata | .name = (stringify(_field)), \ |
795 | 34e65944 | Isaku Yamahata | .version_id = 0, \
|
796 | 34e65944 | Isaku Yamahata | .num_offset = vmstate_offset_value(_state, _field_num, uint16_t), \ |
797 | 34e65944 | Isaku Yamahata | .size = sizeof(_type), \
|
798 | 34e65944 | Isaku Yamahata | .vmsd = &(_vmsd), \ |
799 | 34e65944 | Isaku Yamahata | .flags = VMS_POINTER | VMS_VARRAY_UINT16 | VMS_STRUCT, \ |
800 | 34e65944 | Isaku Yamahata | .offset = vmstate_offset_pointer(_state, _field, _type), \ |
801 | 34e65944 | Isaku Yamahata | } |
802 | 34e65944 | Isaku Yamahata | |
803 | 34e65944 | Isaku Yamahata | const VMStateDescription vmstate_pcie_aer_log = {
|
804 | 34e65944 | Isaku Yamahata | .name = "PCIE_AER_ERROR_LOG",
|
805 | 34e65944 | Isaku Yamahata | .version_id = 1,
|
806 | 34e65944 | Isaku Yamahata | .minimum_version_id = 1,
|
807 | 34e65944 | Isaku Yamahata | .minimum_version_id_old = 1,
|
808 | 34e65944 | Isaku Yamahata | .fields = (VMStateField[]) { |
809 | 34e65944 | Isaku Yamahata | VMSTATE_UINT16(log_num, PCIEAERLog), |
810 | 34e65944 | Isaku Yamahata | VMSTATE_UINT16(log_max, PCIEAERLog), |
811 | 34e65944 | Isaku Yamahata | VMSTATE_PCIE_AER_ERRS(log, PCIEAERLog, log_num, |
812 | 34e65944 | Isaku Yamahata | vmstate_pcie_aer_err, PCIEAERErr), |
813 | 34e65944 | Isaku Yamahata | VMSTATE_END_OF_LIST() |
814 | 34e65944 | Isaku Yamahata | } |
815 | 34e65944 | Isaku Yamahata | }; |