Revision 81a322d4 hw/grackle_pci.c

b/hw/grackle_pci.c
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    return d->host_state.bus;
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}
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static void pci_grackle_init_device(SysBusDevice *dev)
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static int pci_grackle_init_device(SysBusDevice *dev)
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{
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    GrackleState *s;
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    int pci_mem_config, pci_mem_data;
......
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                    &s->host_state);
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    qemu_register_reset(pci_grackle_reset, &s->host_state);
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    pci_grackle_reset(&s->host_state);
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    return 0;
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}
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static void pci_dec_21154_init_device(SysBusDevice *dev)
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static int pci_dec_21154_init_device(SysBusDevice *dev)
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{
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    GrackleState *s;
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    int pci_mem_config, pci_mem_data;
......
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                                          &s->host_state);
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    sysbus_init_mmio(dev, 0x1000, pci_mem_config);
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    sysbus_init_mmio(dev, 0x1000, pci_mem_data);
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    return 0;
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}
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static void grackle_pci_host_init(PCIDevice *d)
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static int grackle_pci_host_init(PCIDevice *d)
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{
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    pci_config_set_vendor_id(d->config, PCI_VENDOR_ID_MOTOROLA);
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    pci_config_set_device_id(d->config, PCI_DEVICE_ID_MOTOROLA_MPC106);
......
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    d->config[0x09] = 0x01;
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    pci_config_set_class(d->config, PCI_CLASS_BRIDGE_HOST);
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    d->config[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_NORMAL; // header_type
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    return 0;
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}
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static void dec_21154_pci_host_init(PCIDevice *d)
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static int dec_21154_pci_host_init(PCIDevice *d)
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{
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    /* PCI2PCI bridge same values as PearPC - check this */
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    pci_config_set_vendor_id(d->config, PCI_VENDOR_ID_DEC);
......
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    d->config[0x25] = 0x84;
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    d->config[0x26] = 0x00; // prefetchable_memory_limit
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    d->config[0x27] = 0x85;
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    return 0;
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}
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static PCIDeviceInfo grackle_pci_host_info = {

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