root / hw / lan9118.c @ 81b1008d
History | View | Annotate | Download (31.9 kB)
1 | 2a424990 | Paul Brook | /*
|
---|---|---|---|
2 | 2a424990 | Paul Brook | * SMSC LAN9118 Ethernet interface emulation
|
3 | 2a424990 | Paul Brook | *
|
4 | 2a424990 | Paul Brook | * Copyright (c) 2009 CodeSourcery, LLC.
|
5 | 2a424990 | Paul Brook | * Written by Paul Brook
|
6 | 2a424990 | Paul Brook | *
|
7 | 8e31bf38 | Matthew Fernandez | * This code is licensed under the GNU GPL v2
|
8 | 2a424990 | Paul Brook | */
|
9 | 2a424990 | Paul Brook | |
10 | 2a424990 | Paul Brook | #include "sysbus.h" |
11 | 2a424990 | Paul Brook | #include "net.h" |
12 | 2a424990 | Paul Brook | #include "devices.h" |
13 | 666daa68 | Markus Armbruster | #include "sysemu.h" |
14 | 2a424990 | Paul Brook | /* For crc32 */
|
15 | 2a424990 | Paul Brook | #include <zlib.h> |
16 | 2a424990 | Paul Brook | |
17 | 2a424990 | Paul Brook | //#define DEBUG_LAN9118
|
18 | 2a424990 | Paul Brook | |
19 | 2a424990 | Paul Brook | #ifdef DEBUG_LAN9118
|
20 | 2a424990 | Paul Brook | #define DPRINTF(fmt, ...) \
|
21 | 2a424990 | Paul Brook | do { printf("lan9118: " fmt , ## __VA_ARGS__); } while (0) |
22 | 2a424990 | Paul Brook | #define BADF(fmt, ...) \
|
23 | 2a424990 | Paul Brook | do { hw_error("lan9118: error: " fmt , ## __VA_ARGS__);} while (0) |
24 | 2a424990 | Paul Brook | #else
|
25 | 2a424990 | Paul Brook | #define DPRINTF(fmt, ...) do {} while(0) |
26 | 2a424990 | Paul Brook | #define BADF(fmt, ...) \
|
27 | 2a424990 | Paul Brook | do { fprintf(stderr, "lan9118: error: " fmt , ## __VA_ARGS__);} while (0) |
28 | 2a424990 | Paul Brook | #endif
|
29 | 2a424990 | Paul Brook | |
30 | 2a424990 | Paul Brook | #define CSR_ID_REV 0x50 |
31 | 2a424990 | Paul Brook | #define CSR_IRQ_CFG 0x54 |
32 | 2a424990 | Paul Brook | #define CSR_INT_STS 0x58 |
33 | 2a424990 | Paul Brook | #define CSR_INT_EN 0x5c |
34 | 2a424990 | Paul Brook | #define CSR_BYTE_TEST 0x64 |
35 | 2a424990 | Paul Brook | #define CSR_FIFO_INT 0x68 |
36 | 2a424990 | Paul Brook | #define CSR_RX_CFG 0x6c |
37 | 2a424990 | Paul Brook | #define CSR_TX_CFG 0x70 |
38 | 2a424990 | Paul Brook | #define CSR_HW_CFG 0x74 |
39 | 2a424990 | Paul Brook | #define CSR_RX_DP_CTRL 0x78 |
40 | 2a424990 | Paul Brook | #define CSR_RX_FIFO_INF 0x7c |
41 | 2a424990 | Paul Brook | #define CSR_TX_FIFO_INF 0x80 |
42 | 2a424990 | Paul Brook | #define CSR_PMT_CTRL 0x84 |
43 | 2a424990 | Paul Brook | #define CSR_GPIO_CFG 0x88 |
44 | 209bf965 | Paul Brook | #define CSR_GPT_CFG 0x8c |
45 | 209bf965 | Paul Brook | #define CSR_GPT_CNT 0x90 |
46 | 2a424990 | Paul Brook | #define CSR_WORD_SWAP 0x98 |
47 | 2a424990 | Paul Brook | #define CSR_FREE_RUN 0x9c |
48 | 2a424990 | Paul Brook | #define CSR_RX_DROP 0xa0 |
49 | 2a424990 | Paul Brook | #define CSR_MAC_CSR_CMD 0xa4 |
50 | 2a424990 | Paul Brook | #define CSR_MAC_CSR_DATA 0xa8 |
51 | 2a424990 | Paul Brook | #define CSR_AFC_CFG 0xac |
52 | 2a424990 | Paul Brook | #define CSR_E2P_CMD 0xb0 |
53 | 2a424990 | Paul Brook | #define CSR_E2P_DATA 0xb4 |
54 | 2a424990 | Paul Brook | |
55 | 2a424990 | Paul Brook | /* IRQ_CFG */
|
56 | 209bf965 | Paul Brook | #define IRQ_INT 0x00001000 |
57 | 2a424990 | Paul Brook | #define IRQ_EN 0x00000100 |
58 | 2a424990 | Paul Brook | #define IRQ_POL 0x00000010 |
59 | 2a424990 | Paul Brook | #define IRQ_TYPE 0x00000001 |
60 | 2a424990 | Paul Brook | |
61 | 2a424990 | Paul Brook | /* INT_STS/INT_EN */
|
62 | 2a424990 | Paul Brook | #define SW_INT 0x80000000 |
63 | 2a424990 | Paul Brook | #define TXSTOP_INT 0x02000000 |
64 | 2a424990 | Paul Brook | #define RXSTOP_INT 0x01000000 |
65 | 2a424990 | Paul Brook | #define RXDFH_INT 0x00800000 |
66 | 2a424990 | Paul Brook | #define TX_IOC_INT 0x00200000 |
67 | 2a424990 | Paul Brook | #define RXD_INT 0x00100000 |
68 | 2a424990 | Paul Brook | #define GPT_INT 0x00080000 |
69 | 2a424990 | Paul Brook | #define PHY_INT 0x00040000 |
70 | 2a424990 | Paul Brook | #define PME_INT 0x00020000 |
71 | 2a424990 | Paul Brook | #define TXSO_INT 0x00010000 |
72 | 2a424990 | Paul Brook | #define RWT_INT 0x00008000 |
73 | 2a424990 | Paul Brook | #define RXE_INT 0x00004000 |
74 | 2a424990 | Paul Brook | #define TXE_INT 0x00002000 |
75 | 2a424990 | Paul Brook | #define TDFU_INT 0x00000800 |
76 | 2a424990 | Paul Brook | #define TDFO_INT 0x00000400 |
77 | 2a424990 | Paul Brook | #define TDFA_INT 0x00000200 |
78 | 2a424990 | Paul Brook | #define TSFF_INT 0x00000100 |
79 | 2a424990 | Paul Brook | #define TSFL_INT 0x00000080 |
80 | 2a424990 | Paul Brook | #define RXDF_INT 0x00000040 |
81 | 2a424990 | Paul Brook | #define RDFL_INT 0x00000020 |
82 | 2a424990 | Paul Brook | #define RSFF_INT 0x00000010 |
83 | 2a424990 | Paul Brook | #define RSFL_INT 0x00000008 |
84 | 2a424990 | Paul Brook | #define GPIO2_INT 0x00000004 |
85 | 2a424990 | Paul Brook | #define GPIO1_INT 0x00000002 |
86 | 2a424990 | Paul Brook | #define GPIO0_INT 0x00000001 |
87 | 2a424990 | Paul Brook | #define RESERVED_INT 0x7c001000 |
88 | 2a424990 | Paul Brook | |
89 | 2a424990 | Paul Brook | #define MAC_CR 1 |
90 | 2a424990 | Paul Brook | #define MAC_ADDRH 2 |
91 | 2a424990 | Paul Brook | #define MAC_ADDRL 3 |
92 | 2a424990 | Paul Brook | #define MAC_HASHH 4 |
93 | 2a424990 | Paul Brook | #define MAC_HASHL 5 |
94 | 2a424990 | Paul Brook | #define MAC_MII_ACC 6 |
95 | 2a424990 | Paul Brook | #define MAC_MII_DATA 7 |
96 | 2a424990 | Paul Brook | #define MAC_FLOW 8 |
97 | 2a424990 | Paul Brook | #define MAC_VLAN1 9 /* TODO */ |
98 | 2a424990 | Paul Brook | #define MAC_VLAN2 10 /* TODO */ |
99 | 2a424990 | Paul Brook | #define MAC_WUFF 11 /* TODO */ |
100 | 2a424990 | Paul Brook | #define MAC_WUCSR 12 /* TODO */ |
101 | 2a424990 | Paul Brook | |
102 | 2a424990 | Paul Brook | #define MAC_CR_RXALL 0x80000000 |
103 | 2a424990 | Paul Brook | #define MAC_CR_RCVOWN 0x00800000 |
104 | 2a424990 | Paul Brook | #define MAC_CR_LOOPBK 0x00200000 |
105 | 2a424990 | Paul Brook | #define MAC_CR_FDPX 0x00100000 |
106 | 2a424990 | Paul Brook | #define MAC_CR_MCPAS 0x00080000 |
107 | 2a424990 | Paul Brook | #define MAC_CR_PRMS 0x00040000 |
108 | 2a424990 | Paul Brook | #define MAC_CR_INVFILT 0x00020000 |
109 | 2a424990 | Paul Brook | #define MAC_CR_PASSBAD 0x00010000 |
110 | 2a424990 | Paul Brook | #define MAC_CR_HO 0x00008000 |
111 | 2a424990 | Paul Brook | #define MAC_CR_HPFILT 0x00002000 |
112 | 2a424990 | Paul Brook | #define MAC_CR_LCOLL 0x00001000 |
113 | 2a424990 | Paul Brook | #define MAC_CR_BCAST 0x00000800 |
114 | 2a424990 | Paul Brook | #define MAC_CR_DISRTY 0x00000400 |
115 | 2a424990 | Paul Brook | #define MAC_CR_PADSTR 0x00000100 |
116 | 2a424990 | Paul Brook | #define MAC_CR_BOLMT 0x000000c0 |
117 | 2a424990 | Paul Brook | #define MAC_CR_DFCHK 0x00000020 |
118 | 2a424990 | Paul Brook | #define MAC_CR_TXEN 0x00000008 |
119 | 2a424990 | Paul Brook | #define MAC_CR_RXEN 0x00000004 |
120 | 2a424990 | Paul Brook | #define MAC_CR_RESERVED 0x7f404213 |
121 | 2a424990 | Paul Brook | |
122 | 209bf965 | Paul Brook | #define PHY_INT_ENERGYON 0x80 |
123 | 209bf965 | Paul Brook | #define PHY_INT_AUTONEG_COMPLETE 0x40 |
124 | 209bf965 | Paul Brook | #define PHY_INT_FAULT 0x20 |
125 | 209bf965 | Paul Brook | #define PHY_INT_DOWN 0x10 |
126 | 209bf965 | Paul Brook | #define PHY_INT_AUTONEG_LP 0x08 |
127 | 209bf965 | Paul Brook | #define PHY_INT_PARFAULT 0x04 |
128 | 209bf965 | Paul Brook | #define PHY_INT_AUTONEG_PAGE 0x02 |
129 | 209bf965 | Paul Brook | |
130 | 209bf965 | Paul Brook | #define GPT_TIMER_EN 0x20000000 |
131 | 209bf965 | Paul Brook | |
132 | 2a424990 | Paul Brook | enum tx_state {
|
133 | 2a424990 | Paul Brook | TX_IDLE, |
134 | 2a424990 | Paul Brook | TX_B, |
135 | 2a424990 | Paul Brook | TX_DATA |
136 | 2a424990 | Paul Brook | }; |
137 | 2a424990 | Paul Brook | |
138 | 2a424990 | Paul Brook | typedef struct { |
139 | 2a424990 | Paul Brook | enum tx_state state;
|
140 | 2a424990 | Paul Brook | uint32_t cmd_a; |
141 | 2a424990 | Paul Brook | uint32_t cmd_b; |
142 | 2a424990 | Paul Brook | int buffer_size;
|
143 | 2a424990 | Paul Brook | int offset;
|
144 | 2a424990 | Paul Brook | int pad;
|
145 | 2a424990 | Paul Brook | int fifo_used;
|
146 | 2a424990 | Paul Brook | int len;
|
147 | 2a424990 | Paul Brook | uint8_t data[2048];
|
148 | 2a424990 | Paul Brook | } LAN9118Packet; |
149 | 2a424990 | Paul Brook | |
150 | 2a424990 | Paul Brook | typedef struct { |
151 | 2a424990 | Paul Brook | SysBusDevice busdev; |
152 | 83b9f88c | Mark McLoughlin | NICState *nic; |
153 | 2a424990 | Paul Brook | NICConf conf; |
154 | 2a424990 | Paul Brook | qemu_irq irq; |
155 | 2a424990 | Paul Brook | int mmio_index;
|
156 | 209bf965 | Paul Brook | ptimer_state *timer; |
157 | 2a424990 | Paul Brook | |
158 | 2a424990 | Paul Brook | uint32_t irq_cfg; |
159 | 2a424990 | Paul Brook | uint32_t int_sts; |
160 | 2a424990 | Paul Brook | uint32_t int_en; |
161 | 2a424990 | Paul Brook | uint32_t fifo_int; |
162 | 2a424990 | Paul Brook | uint32_t rx_cfg; |
163 | 2a424990 | Paul Brook | uint32_t tx_cfg; |
164 | 2a424990 | Paul Brook | uint32_t hw_cfg; |
165 | 2a424990 | Paul Brook | uint32_t pmt_ctrl; |
166 | 2a424990 | Paul Brook | uint32_t gpio_cfg; |
167 | 209bf965 | Paul Brook | uint32_t gpt_cfg; |
168 | 2a424990 | Paul Brook | uint32_t word_swap; |
169 | 2a424990 | Paul Brook | uint32_t free_timer_start; |
170 | 2a424990 | Paul Brook | uint32_t mac_cmd; |
171 | 2a424990 | Paul Brook | uint32_t mac_data; |
172 | 2a424990 | Paul Brook | uint32_t afc_cfg; |
173 | 2a424990 | Paul Brook | uint32_t e2p_cmd; |
174 | 2a424990 | Paul Brook | uint32_t e2p_data; |
175 | 2a424990 | Paul Brook | |
176 | 2a424990 | Paul Brook | uint32_t mac_cr; |
177 | 2a424990 | Paul Brook | uint32_t mac_hashh; |
178 | 2a424990 | Paul Brook | uint32_t mac_hashl; |
179 | 2a424990 | Paul Brook | uint32_t mac_mii_acc; |
180 | 2a424990 | Paul Brook | uint32_t mac_mii_data; |
181 | 2a424990 | Paul Brook | uint32_t mac_flow; |
182 | 2a424990 | Paul Brook | |
183 | 2a424990 | Paul Brook | uint32_t phy_status; |
184 | 2a424990 | Paul Brook | uint32_t phy_control; |
185 | 2a424990 | Paul Brook | uint32_t phy_advertise; |
186 | 209bf965 | Paul Brook | uint32_t phy_int; |
187 | 209bf965 | Paul Brook | uint32_t phy_int_mask; |
188 | 2a424990 | Paul Brook | |
189 | 2a424990 | Paul Brook | int eeprom_writable;
|
190 | c46a3ea0 | Blue Swirl | uint8_t eeprom[128];
|
191 | 2a424990 | Paul Brook | |
192 | 2a424990 | Paul Brook | int tx_fifo_size;
|
193 | 2a424990 | Paul Brook | LAN9118Packet *txp; |
194 | 2a424990 | Paul Brook | LAN9118Packet tx_packet; |
195 | 2a424990 | Paul Brook | |
196 | 2a424990 | Paul Brook | int tx_status_fifo_used;
|
197 | 2a424990 | Paul Brook | int tx_status_fifo_head;
|
198 | 2a424990 | Paul Brook | uint32_t tx_status_fifo[512];
|
199 | 2a424990 | Paul Brook | |
200 | 2a424990 | Paul Brook | int rx_status_fifo_size;
|
201 | 2a424990 | Paul Brook | int rx_status_fifo_used;
|
202 | 2a424990 | Paul Brook | int rx_status_fifo_head;
|
203 | 2a424990 | Paul Brook | uint32_t rx_status_fifo[896];
|
204 | 2a424990 | Paul Brook | int rx_fifo_size;
|
205 | 2a424990 | Paul Brook | int rx_fifo_used;
|
206 | 2a424990 | Paul Brook | int rx_fifo_head;
|
207 | 2a424990 | Paul Brook | uint32_t rx_fifo[3360];
|
208 | 2a424990 | Paul Brook | int rx_packet_size_head;
|
209 | 2a424990 | Paul Brook | int rx_packet_size_tail;
|
210 | 2a424990 | Paul Brook | int rx_packet_size[1024]; |
211 | 2a424990 | Paul Brook | |
212 | 2a424990 | Paul Brook | int rxp_offset;
|
213 | 2a424990 | Paul Brook | int rxp_size;
|
214 | 2a424990 | Paul Brook | int rxp_pad;
|
215 | 2a424990 | Paul Brook | } lan9118_state; |
216 | 2a424990 | Paul Brook | |
217 | 2a424990 | Paul Brook | static void lan9118_update(lan9118_state *s) |
218 | 2a424990 | Paul Brook | { |
219 | 2a424990 | Paul Brook | int level;
|
220 | 2a424990 | Paul Brook | |
221 | 2a424990 | Paul Brook | /* TODO: Implement FIFO level IRQs. */
|
222 | 2a424990 | Paul Brook | level = (s->int_sts & s->int_en) != 0;
|
223 | 209bf965 | Paul Brook | if (level) {
|
224 | 209bf965 | Paul Brook | s->irq_cfg |= IRQ_INT; |
225 | 209bf965 | Paul Brook | } else {
|
226 | 209bf965 | Paul Brook | s->irq_cfg &= ~IRQ_INT; |
227 | 209bf965 | Paul Brook | } |
228 | 2a424990 | Paul Brook | if ((s->irq_cfg & IRQ_EN) == 0) { |
229 | 2a424990 | Paul Brook | level = 0;
|
230 | 2a424990 | Paul Brook | } |
231 | eb47d7c5 | Peter Maydell | if ((s->irq_cfg & (IRQ_TYPE | IRQ_POL)) != (IRQ_TYPE | IRQ_POL)) {
|
232 | eb47d7c5 | Peter Maydell | /* Interrupt is active low unless we're configured as
|
233 | eb47d7c5 | Peter Maydell | * active-high polarity, push-pull type.
|
234 | eb47d7c5 | Peter Maydell | */
|
235 | eb47d7c5 | Peter Maydell | level = !level; |
236 | eb47d7c5 | Peter Maydell | } |
237 | 2a424990 | Paul Brook | qemu_set_irq(s->irq, level); |
238 | 2a424990 | Paul Brook | } |
239 | 2a424990 | Paul Brook | |
240 | 2a424990 | Paul Brook | static void lan9118_mac_changed(lan9118_state *s) |
241 | 2a424990 | Paul Brook | { |
242 | 83b9f88c | Mark McLoughlin | qemu_format_nic_info_str(&s->nic->nc, s->conf.macaddr.a); |
243 | 2a424990 | Paul Brook | } |
244 | 2a424990 | Paul Brook | |
245 | 2a424990 | Paul Brook | static void lan9118_reload_eeprom(lan9118_state *s) |
246 | 2a424990 | Paul Brook | { |
247 | 2a424990 | Paul Brook | int i;
|
248 | 2a424990 | Paul Brook | if (s->eeprom[0] != 0xa5) { |
249 | 2a424990 | Paul Brook | s->e2p_cmd &= ~0x10;
|
250 | 2a424990 | Paul Brook | DPRINTF("MACADDR load failed\n");
|
251 | 2a424990 | Paul Brook | return;
|
252 | 2a424990 | Paul Brook | } |
253 | 2a424990 | Paul Brook | for (i = 0; i < 6; i++) { |
254 | 2a424990 | Paul Brook | s->conf.macaddr.a[i] = s->eeprom[i + 1];
|
255 | 2a424990 | Paul Brook | } |
256 | 2a424990 | Paul Brook | s->e2p_cmd |= 0x10;
|
257 | 2a424990 | Paul Brook | DPRINTF("MACADDR loaded from eeprom\n");
|
258 | 2a424990 | Paul Brook | lan9118_mac_changed(s); |
259 | 2a424990 | Paul Brook | } |
260 | 2a424990 | Paul Brook | |
261 | 209bf965 | Paul Brook | static void phy_update_irq(lan9118_state *s) |
262 | 209bf965 | Paul Brook | { |
263 | 209bf965 | Paul Brook | if (s->phy_int & s->phy_int_mask) {
|
264 | 209bf965 | Paul Brook | s->int_sts |= PHY_INT; |
265 | 209bf965 | Paul Brook | } else {
|
266 | 209bf965 | Paul Brook | s->int_sts &= ~PHY_INT; |
267 | 209bf965 | Paul Brook | } |
268 | 209bf965 | Paul Brook | lan9118_update(s); |
269 | 209bf965 | Paul Brook | } |
270 | 209bf965 | Paul Brook | |
271 | 2a424990 | Paul Brook | static void phy_update_link(lan9118_state *s) |
272 | 2a424990 | Paul Brook | { |
273 | 2a424990 | Paul Brook | /* Autonegotiation status mirrors link status. */
|
274 | 83b9f88c | Mark McLoughlin | if (s->nic->nc.link_down) {
|
275 | 2a424990 | Paul Brook | s->phy_status &= ~0x0024;
|
276 | 209bf965 | Paul Brook | s->phy_int |= PHY_INT_DOWN; |
277 | 2a424990 | Paul Brook | } else {
|
278 | 2a424990 | Paul Brook | s->phy_status |= 0x0024;
|
279 | 209bf965 | Paul Brook | s->phy_int |= PHY_INT_ENERGYON; |
280 | 209bf965 | Paul Brook | s->phy_int |= PHY_INT_AUTONEG_COMPLETE; |
281 | 2a424990 | Paul Brook | } |
282 | 209bf965 | Paul Brook | phy_update_irq(s); |
283 | 2a424990 | Paul Brook | } |
284 | 2a424990 | Paul Brook | |
285 | 83b9f88c | Mark McLoughlin | static void lan9118_set_link(VLANClientState *nc) |
286 | 2a424990 | Paul Brook | { |
287 | 83b9f88c | Mark McLoughlin | phy_update_link(DO_UPCAST(NICState, nc, nc)->opaque); |
288 | 2a424990 | Paul Brook | } |
289 | 2a424990 | Paul Brook | |
290 | 2a424990 | Paul Brook | static void phy_reset(lan9118_state *s) |
291 | 2a424990 | Paul Brook | { |
292 | 209bf965 | Paul Brook | s->phy_status = 0x7809;
|
293 | 2a424990 | Paul Brook | s->phy_control = 0x3000;
|
294 | 2a424990 | Paul Brook | s->phy_advertise = 0x01e1;
|
295 | 209bf965 | Paul Brook | s->phy_int_mask = 0;
|
296 | 209bf965 | Paul Brook | s->phy_int = 0;
|
297 | 2a424990 | Paul Brook | phy_update_link(s); |
298 | 2a424990 | Paul Brook | } |
299 | 2a424990 | Paul Brook | |
300 | 2a424990 | Paul Brook | static void lan9118_reset(DeviceState *d) |
301 | 2a424990 | Paul Brook | { |
302 | 2a424990 | Paul Brook | lan9118_state *s = FROM_SYSBUS(lan9118_state, sysbus_from_qdev(d)); |
303 | eb47d7c5 | Peter Maydell | s->irq_cfg &= (IRQ_TYPE | IRQ_POL); |
304 | 2a424990 | Paul Brook | s->int_sts = 0;
|
305 | 2a424990 | Paul Brook | s->int_en = 0;
|
306 | 2a424990 | Paul Brook | s->fifo_int = 0x48000000;
|
307 | 2a424990 | Paul Brook | s->rx_cfg = 0;
|
308 | 2a424990 | Paul Brook | s->tx_cfg = 0;
|
309 | 2a424990 | Paul Brook | s->hw_cfg = 0x00050000;
|
310 | 2a424990 | Paul Brook | s->pmt_ctrl &= 0x45;
|
311 | 2a424990 | Paul Brook | s->gpio_cfg = 0;
|
312 | 2a424990 | Paul Brook | s->txp->fifo_used = 0;
|
313 | 2a424990 | Paul Brook | s->txp->state = TX_IDLE; |
314 | 2a424990 | Paul Brook | s->txp->cmd_a = 0xffffffffu;
|
315 | 2a424990 | Paul Brook | s->txp->cmd_b = 0xffffffffu;
|
316 | 2a424990 | Paul Brook | s->txp->len = 0;
|
317 | 2a424990 | Paul Brook | s->txp->fifo_used = 0;
|
318 | 2a424990 | Paul Brook | s->tx_fifo_size = 4608;
|
319 | 2a424990 | Paul Brook | s->tx_status_fifo_used = 0;
|
320 | 2a424990 | Paul Brook | s->rx_status_fifo_size = 704;
|
321 | 2a424990 | Paul Brook | s->rx_fifo_size = 2640;
|
322 | 2a424990 | Paul Brook | s->rx_fifo_used = 0;
|
323 | 2a424990 | Paul Brook | s->rx_status_fifo_size = 176;
|
324 | 2a424990 | Paul Brook | s->rx_status_fifo_used = 0;
|
325 | 2a424990 | Paul Brook | s->rxp_offset = 0;
|
326 | 2a424990 | Paul Brook | s->rxp_size = 0;
|
327 | 2a424990 | Paul Brook | s->rxp_pad = 0;
|
328 | 2a424990 | Paul Brook | s->rx_packet_size_tail = s->rx_packet_size_head; |
329 | 2a424990 | Paul Brook | s->rx_packet_size[s->rx_packet_size_head] = 0;
|
330 | 2a424990 | Paul Brook | s->mac_cmd = 0;
|
331 | 2a424990 | Paul Brook | s->mac_data = 0;
|
332 | 2a424990 | Paul Brook | s->afc_cfg = 0;
|
333 | 2a424990 | Paul Brook | s->e2p_cmd = 0;
|
334 | 2a424990 | Paul Brook | s->e2p_data = 0;
|
335 | 74475455 | Paolo Bonzini | s->free_timer_start = qemu_get_clock_ns(vm_clock) / 40;
|
336 | 2a424990 | Paul Brook | |
337 | 209bf965 | Paul Brook | ptimer_stop(s->timer); |
338 | 209bf965 | Paul Brook | ptimer_set_count(s->timer, 0xffff);
|
339 | 209bf965 | Paul Brook | s->gpt_cfg = 0xffff;
|
340 | 209bf965 | Paul Brook | |
341 | 2a424990 | Paul Brook | s->mac_cr = MAC_CR_PRMS; |
342 | 2a424990 | Paul Brook | s->mac_hashh = 0;
|
343 | 2a424990 | Paul Brook | s->mac_hashl = 0;
|
344 | 2a424990 | Paul Brook | s->mac_mii_acc = 0;
|
345 | 2a424990 | Paul Brook | s->mac_mii_data = 0;
|
346 | 2a424990 | Paul Brook | s->mac_flow = 0;
|
347 | 2a424990 | Paul Brook | |
348 | 2a424990 | Paul Brook | phy_reset(s); |
349 | 2a424990 | Paul Brook | |
350 | 2a424990 | Paul Brook | s->eeprom_writable = 0;
|
351 | 2a424990 | Paul Brook | lan9118_reload_eeprom(s); |
352 | 2a424990 | Paul Brook | } |
353 | 2a424990 | Paul Brook | |
354 | 83b9f88c | Mark McLoughlin | static int lan9118_can_receive(VLANClientState *nc) |
355 | 2a424990 | Paul Brook | { |
356 | 2a424990 | Paul Brook | return 1; |
357 | 2a424990 | Paul Brook | } |
358 | 2a424990 | Paul Brook | |
359 | 2a424990 | Paul Brook | static void rx_fifo_push(lan9118_state *s, uint32_t val) |
360 | 2a424990 | Paul Brook | { |
361 | 2a424990 | Paul Brook | int fifo_pos;
|
362 | 2a424990 | Paul Brook | fifo_pos = s->rx_fifo_head + s->rx_fifo_used; |
363 | 2a424990 | Paul Brook | if (fifo_pos >= s->rx_fifo_size)
|
364 | 2a424990 | Paul Brook | fifo_pos -= s->rx_fifo_size; |
365 | 2a424990 | Paul Brook | s->rx_fifo[fifo_pos] = val; |
366 | 2a424990 | Paul Brook | s->rx_fifo_used++; |
367 | 2a424990 | Paul Brook | } |
368 | 2a424990 | Paul Brook | |
369 | 2a424990 | Paul Brook | /* Return nonzero if the packet is accepted by the filter. */
|
370 | 2a424990 | Paul Brook | static int lan9118_filter(lan9118_state *s, const uint8_t *addr) |
371 | 2a424990 | Paul Brook | { |
372 | 2a424990 | Paul Brook | int multicast;
|
373 | 2a424990 | Paul Brook | uint32_t hash; |
374 | 2a424990 | Paul Brook | |
375 | 2a424990 | Paul Brook | if (s->mac_cr & MAC_CR_PRMS) {
|
376 | 2a424990 | Paul Brook | return 1; |
377 | 2a424990 | Paul Brook | } |
378 | 2a424990 | Paul Brook | if (addr[0] == 0xff && addr[1] == 0xff && addr[2] == 0xff && |
379 | 2a424990 | Paul Brook | addr[3] == 0xff && addr[4] == 0xff && addr[5] == 0xff) { |
380 | 2a424990 | Paul Brook | return (s->mac_cr & MAC_CR_BCAST) == 0; |
381 | 2a424990 | Paul Brook | } |
382 | 2a424990 | Paul Brook | |
383 | 2a424990 | Paul Brook | multicast = addr[0] & 1; |
384 | 2a424990 | Paul Brook | if (multicast &&s->mac_cr & MAC_CR_MCPAS) {
|
385 | 2a424990 | Paul Brook | return 1; |
386 | 2a424990 | Paul Brook | } |
387 | 2a424990 | Paul Brook | if (multicast ? (s->mac_cr & MAC_CR_HPFILT) == 0 |
388 | 2a424990 | Paul Brook | : (s->mac_cr & MAC_CR_HO) == 0) {
|
389 | 2a424990 | Paul Brook | /* Exact matching. */
|
390 | 2a424990 | Paul Brook | hash = memcmp(addr, s->conf.macaddr.a, 6);
|
391 | 2a424990 | Paul Brook | if (s->mac_cr & MAC_CR_INVFILT) {
|
392 | 2a424990 | Paul Brook | return hash != 0; |
393 | 2a424990 | Paul Brook | } else {
|
394 | 2a424990 | Paul Brook | return hash == 0; |
395 | 2a424990 | Paul Brook | } |
396 | 2a424990 | Paul Brook | } else {
|
397 | 2a424990 | Paul Brook | /* Hash matching */
|
398 | 2a424990 | Paul Brook | hash = (crc32(~0, addr, 6) >> 26); |
399 | 2a424990 | Paul Brook | if (hash & 0x20) { |
400 | 2a424990 | Paul Brook | return (s->mac_hashh >> (hash & 0x1f)) & 1; |
401 | 2a424990 | Paul Brook | } else {
|
402 | 2a424990 | Paul Brook | return (s->mac_hashl >> (hash & 0x1f)) & 1; |
403 | 2a424990 | Paul Brook | } |
404 | 2a424990 | Paul Brook | } |
405 | 2a424990 | Paul Brook | } |
406 | 2a424990 | Paul Brook | |
407 | 83b9f88c | Mark McLoughlin | static ssize_t lan9118_receive(VLANClientState *nc, const uint8_t *buf, |
408 | 2a424990 | Paul Brook | size_t size) |
409 | 2a424990 | Paul Brook | { |
410 | 83b9f88c | Mark McLoughlin | lan9118_state *s = DO_UPCAST(NICState, nc, nc)->opaque; |
411 | 2a424990 | Paul Brook | int fifo_len;
|
412 | 2a424990 | Paul Brook | int offset;
|
413 | 2a424990 | Paul Brook | int src_pos;
|
414 | 2a424990 | Paul Brook | int n;
|
415 | 2a424990 | Paul Brook | int filter;
|
416 | 2a424990 | Paul Brook | uint32_t val; |
417 | 2a424990 | Paul Brook | uint32_t crc; |
418 | 2a424990 | Paul Brook | uint32_t status; |
419 | 2a424990 | Paul Brook | |
420 | 2a424990 | Paul Brook | if ((s->mac_cr & MAC_CR_RXEN) == 0) { |
421 | 2a424990 | Paul Brook | return -1; |
422 | 2a424990 | Paul Brook | } |
423 | 2a424990 | Paul Brook | |
424 | 2a424990 | Paul Brook | if (size >= 2048 || size < 14) { |
425 | 2a424990 | Paul Brook | return -1; |
426 | 2a424990 | Paul Brook | } |
427 | 2a424990 | Paul Brook | |
428 | 2a424990 | Paul Brook | /* TODO: Implement FIFO overflow notification. */
|
429 | 2a424990 | Paul Brook | if (s->rx_status_fifo_used == s->rx_status_fifo_size) {
|
430 | 2a424990 | Paul Brook | return -1; |
431 | 2a424990 | Paul Brook | } |
432 | 2a424990 | Paul Brook | |
433 | 2a424990 | Paul Brook | filter = lan9118_filter(s, buf); |
434 | 2a424990 | Paul Brook | if (!filter && (s->mac_cr & MAC_CR_RXALL) == 0) { |
435 | 2a424990 | Paul Brook | return size;
|
436 | 2a424990 | Paul Brook | } |
437 | 2a424990 | Paul Brook | |
438 | 2a424990 | Paul Brook | offset = (s->rx_cfg >> 8) & 0x1f; |
439 | 2a424990 | Paul Brook | n = offset & 3;
|
440 | 2a424990 | Paul Brook | fifo_len = (size + n + 3) >> 2; |
441 | 2a424990 | Paul Brook | /* Add a word for the CRC. */
|
442 | 2a424990 | Paul Brook | fifo_len++; |
443 | 2a424990 | Paul Brook | if (s->rx_fifo_size - s->rx_fifo_used < fifo_len) {
|
444 | 2a424990 | Paul Brook | return -1; |
445 | 2a424990 | Paul Brook | } |
446 | 2a424990 | Paul Brook | |
447 | 2a424990 | Paul Brook | DPRINTF("Got packet len:%d fifo:%d filter:%s\n",
|
448 | 2a424990 | Paul Brook | (int)size, fifo_len, filter ? "pass" : "fail"); |
449 | 2a424990 | Paul Brook | val = 0;
|
450 | 2a424990 | Paul Brook | crc = bswap32(crc32(~0, buf, size));
|
451 | 2a424990 | Paul Brook | for (src_pos = 0; src_pos < size; src_pos++) { |
452 | 2a424990 | Paul Brook | val = (val >> 8) | ((uint32_t)buf[src_pos] << 24); |
453 | 2a424990 | Paul Brook | n++; |
454 | 2a424990 | Paul Brook | if (n == 4) { |
455 | 2a424990 | Paul Brook | n = 0;
|
456 | 2a424990 | Paul Brook | rx_fifo_push(s, val); |
457 | 2a424990 | Paul Brook | val = 0;
|
458 | 2a424990 | Paul Brook | } |
459 | 2a424990 | Paul Brook | } |
460 | 2a424990 | Paul Brook | if (n) {
|
461 | 2a424990 | Paul Brook | val >>= ((4 - n) * 8); |
462 | 2a424990 | Paul Brook | val |= crc << (n * 8);
|
463 | 2a424990 | Paul Brook | rx_fifo_push(s, val); |
464 | 2a424990 | Paul Brook | val = crc >> ((4 - n) * 8); |
465 | 2a424990 | Paul Brook | rx_fifo_push(s, val); |
466 | 2a424990 | Paul Brook | } else {
|
467 | 2a424990 | Paul Brook | rx_fifo_push(s, crc); |
468 | 2a424990 | Paul Brook | } |
469 | 2a424990 | Paul Brook | n = s->rx_status_fifo_head + s->rx_status_fifo_used; |
470 | 2a424990 | Paul Brook | if (n >= s->rx_status_fifo_size) {
|
471 | 2a424990 | Paul Brook | n -= s->rx_status_fifo_size; |
472 | 2a424990 | Paul Brook | } |
473 | 2a424990 | Paul Brook | s->rx_packet_size[s->rx_packet_size_tail] = fifo_len; |
474 | 2a424990 | Paul Brook | s->rx_packet_size_tail = (s->rx_packet_size_tail + 1023) & 1023; |
475 | 2a424990 | Paul Brook | s->rx_status_fifo_used++; |
476 | 2a424990 | Paul Brook | |
477 | 2a424990 | Paul Brook | status = (size + 4) << 16; |
478 | 2a424990 | Paul Brook | if (buf[0] == 0xff && buf[1] == 0xff && buf[2] == 0xff && |
479 | 2a424990 | Paul Brook | buf[3] == 0xff && buf[4] == 0xff && buf[5] == 0xff) { |
480 | 2a424990 | Paul Brook | status |= 0x00002000;
|
481 | 2a424990 | Paul Brook | } else if (buf[0] & 1) { |
482 | 2a424990 | Paul Brook | status |= 0x00000400;
|
483 | 2a424990 | Paul Brook | } |
484 | 2a424990 | Paul Brook | if (!filter) {
|
485 | 2a424990 | Paul Brook | status |= 0x40000000;
|
486 | 2a424990 | Paul Brook | } |
487 | 2a424990 | Paul Brook | s->rx_status_fifo[n] = status; |
488 | 2a424990 | Paul Brook | |
489 | 2a424990 | Paul Brook | if (s->rx_status_fifo_used > (s->fifo_int & 0xff)) { |
490 | 2a424990 | Paul Brook | s->int_sts |= RSFL_INT; |
491 | 2a424990 | Paul Brook | } |
492 | 2a424990 | Paul Brook | lan9118_update(s); |
493 | 2a424990 | Paul Brook | |
494 | 2a424990 | Paul Brook | return size;
|
495 | 2a424990 | Paul Brook | } |
496 | 2a424990 | Paul Brook | |
497 | 2a424990 | Paul Brook | static uint32_t rx_fifo_pop(lan9118_state *s)
|
498 | 2a424990 | Paul Brook | { |
499 | 2a424990 | Paul Brook | int n;
|
500 | 2a424990 | Paul Brook | uint32_t val; |
501 | 2a424990 | Paul Brook | |
502 | 2a424990 | Paul Brook | if (s->rxp_size == 0 && s->rxp_pad == 0) { |
503 | 2a424990 | Paul Brook | s->rxp_size = s->rx_packet_size[s->rx_packet_size_head]; |
504 | 2a424990 | Paul Brook | s->rx_packet_size[s->rx_packet_size_head] = 0;
|
505 | 2a424990 | Paul Brook | if (s->rxp_size != 0) { |
506 | 2a424990 | Paul Brook | s->rx_packet_size_head = (s->rx_packet_size_head + 1023) & 1023; |
507 | 2a424990 | Paul Brook | s->rxp_offset = (s->rx_cfg >> 10) & 7; |
508 | 2a424990 | Paul Brook | n = s->rxp_offset + s->rxp_size; |
509 | 2a424990 | Paul Brook | switch (s->rx_cfg >> 30) { |
510 | 2a424990 | Paul Brook | case 1: |
511 | 2a424990 | Paul Brook | n = (-n) & 3;
|
512 | 2a424990 | Paul Brook | break;
|
513 | 2a424990 | Paul Brook | case 2: |
514 | 2a424990 | Paul Brook | n = (-n) & 7;
|
515 | 2a424990 | Paul Brook | break;
|
516 | 2a424990 | Paul Brook | default:
|
517 | 2a424990 | Paul Brook | n = 0;
|
518 | 2a424990 | Paul Brook | break;
|
519 | 2a424990 | Paul Brook | } |
520 | 2a424990 | Paul Brook | s->rxp_pad = n; |
521 | 2a424990 | Paul Brook | DPRINTF("Pop packet size:%d offset:%d pad: %d\n",
|
522 | 2a424990 | Paul Brook | s->rxp_size, s->rxp_offset, s->rxp_pad); |
523 | 2a424990 | Paul Brook | } |
524 | 2a424990 | Paul Brook | } |
525 | 2a424990 | Paul Brook | if (s->rxp_offset > 0) { |
526 | 2a424990 | Paul Brook | s->rxp_offset--; |
527 | 2a424990 | Paul Brook | val = 0;
|
528 | 2a424990 | Paul Brook | } else if (s->rxp_size > 0) { |
529 | 2a424990 | Paul Brook | s->rxp_size--; |
530 | 2a424990 | Paul Brook | val = s->rx_fifo[s->rx_fifo_head++]; |
531 | 2a424990 | Paul Brook | if (s->rx_fifo_head >= s->rx_fifo_size) {
|
532 | 2a424990 | Paul Brook | s->rx_fifo_head -= s->rx_fifo_size; |
533 | 2a424990 | Paul Brook | } |
534 | 2a424990 | Paul Brook | s->rx_fifo_used--; |
535 | 2a424990 | Paul Brook | } else if (s->rxp_pad > 0) { |
536 | 2a424990 | Paul Brook | s->rxp_pad--; |
537 | 2a424990 | Paul Brook | val = 0;
|
538 | 2a424990 | Paul Brook | } else {
|
539 | 2a424990 | Paul Brook | DPRINTF("RX underflow\n");
|
540 | 2a424990 | Paul Brook | s->int_sts |= RXE_INT; |
541 | 2a424990 | Paul Brook | val = 0;
|
542 | 2a424990 | Paul Brook | } |
543 | 2a424990 | Paul Brook | lan9118_update(s); |
544 | 2a424990 | Paul Brook | return val;
|
545 | 2a424990 | Paul Brook | } |
546 | 2a424990 | Paul Brook | |
547 | 2a424990 | Paul Brook | static void do_tx_packet(lan9118_state *s) |
548 | 2a424990 | Paul Brook | { |
549 | 2a424990 | Paul Brook | int n;
|
550 | 2a424990 | Paul Brook | uint32_t status; |
551 | 2a424990 | Paul Brook | |
552 | 2a424990 | Paul Brook | /* FIXME: Honor TX disable, and allow queueing of packets. */
|
553 | 2a424990 | Paul Brook | if (s->phy_control & 0x4000) { |
554 | 2a424990 | Paul Brook | /* This assumes the receive routine doesn't touch the VLANClient. */
|
555 | 83b9f88c | Mark McLoughlin | lan9118_receive(&s->nic->nc, s->txp->data, s->txp->len); |
556 | 2a424990 | Paul Brook | } else {
|
557 | 83b9f88c | Mark McLoughlin | qemu_send_packet(&s->nic->nc, s->txp->data, s->txp->len); |
558 | 2a424990 | Paul Brook | } |
559 | 2a424990 | Paul Brook | s->txp->fifo_used = 0;
|
560 | 2a424990 | Paul Brook | |
561 | 2a424990 | Paul Brook | if (s->tx_status_fifo_used == 512) { |
562 | 2a424990 | Paul Brook | /* Status FIFO full */
|
563 | 2a424990 | Paul Brook | return;
|
564 | 2a424990 | Paul Brook | } |
565 | 2a424990 | Paul Brook | /* Add entry to status FIFO. */
|
566 | 2a424990 | Paul Brook | status = s->txp->cmd_b & 0xffff0000u;
|
567 | 2a424990 | Paul Brook | DPRINTF("Sent packet tag:%04x len %d\n", status >> 16, s->txp->len); |
568 | 2a424990 | Paul Brook | n = (s->tx_status_fifo_head + s->tx_status_fifo_used) & 511;
|
569 | 2a424990 | Paul Brook | s->tx_status_fifo[n] = status; |
570 | 2a424990 | Paul Brook | s->tx_status_fifo_used++; |
571 | 2a424990 | Paul Brook | if (s->tx_status_fifo_used == 512) { |
572 | 2a424990 | Paul Brook | s->int_sts |= TSFF_INT; |
573 | 2a424990 | Paul Brook | /* TODO: Stop transmission. */
|
574 | 2a424990 | Paul Brook | } |
575 | 2a424990 | Paul Brook | } |
576 | 2a424990 | Paul Brook | |
577 | 2a424990 | Paul Brook | static uint32_t rx_status_fifo_pop(lan9118_state *s)
|
578 | 2a424990 | Paul Brook | { |
579 | 2a424990 | Paul Brook | uint32_t val; |
580 | 2a424990 | Paul Brook | |
581 | 2a424990 | Paul Brook | val = s->rx_status_fifo[s->rx_status_fifo_head]; |
582 | 2a424990 | Paul Brook | if (s->rx_status_fifo_used != 0) { |
583 | 2a424990 | Paul Brook | s->rx_status_fifo_used--; |
584 | 2a424990 | Paul Brook | s->rx_status_fifo_head++; |
585 | 2a424990 | Paul Brook | if (s->rx_status_fifo_head >= s->rx_status_fifo_size) {
|
586 | 2a424990 | Paul Brook | s->rx_status_fifo_head -= s->rx_status_fifo_size; |
587 | 2a424990 | Paul Brook | } |
588 | 2a424990 | Paul Brook | /* ??? What value should be returned when the FIFO is empty? */
|
589 | 2a424990 | Paul Brook | DPRINTF("RX status pop 0x%08x\n", val);
|
590 | 2a424990 | Paul Brook | } |
591 | 2a424990 | Paul Brook | return val;
|
592 | 2a424990 | Paul Brook | } |
593 | 2a424990 | Paul Brook | |
594 | 2a424990 | Paul Brook | static uint32_t tx_status_fifo_pop(lan9118_state *s)
|
595 | 2a424990 | Paul Brook | { |
596 | 2a424990 | Paul Brook | uint32_t val; |
597 | 2a424990 | Paul Brook | |
598 | 2a424990 | Paul Brook | val = s->tx_status_fifo[s->tx_status_fifo_head]; |
599 | 2a424990 | Paul Brook | if (s->tx_status_fifo_used != 0) { |
600 | 2a424990 | Paul Brook | s->tx_status_fifo_used--; |
601 | 2a424990 | Paul Brook | s->tx_status_fifo_head = (s->tx_status_fifo_head + 1) & 511; |
602 | 2a424990 | Paul Brook | /* ??? What value should be returned when the FIFO is empty? */
|
603 | 2a424990 | Paul Brook | } |
604 | 2a424990 | Paul Brook | return val;
|
605 | 2a424990 | Paul Brook | } |
606 | 2a424990 | Paul Brook | |
607 | 2a424990 | Paul Brook | static void tx_fifo_push(lan9118_state *s, uint32_t val) |
608 | 2a424990 | Paul Brook | { |
609 | 2a424990 | Paul Brook | int n;
|
610 | 2a424990 | Paul Brook | |
611 | 2a424990 | Paul Brook | if (s->txp->fifo_used == s->tx_fifo_size) {
|
612 | 2a424990 | Paul Brook | s->int_sts |= TDFO_INT; |
613 | 2a424990 | Paul Brook | return;
|
614 | 2a424990 | Paul Brook | } |
615 | 2a424990 | Paul Brook | switch (s->txp->state) {
|
616 | 2a424990 | Paul Brook | case TX_IDLE:
|
617 | 2a424990 | Paul Brook | s->txp->cmd_a = val & 0x831f37ff;
|
618 | 2a424990 | Paul Brook | s->txp->fifo_used++; |
619 | 2a424990 | Paul Brook | s->txp->state = TX_B; |
620 | 2a424990 | Paul Brook | break;
|
621 | 2a424990 | Paul Brook | case TX_B:
|
622 | 2a424990 | Paul Brook | if (s->txp->cmd_a & 0x2000) { |
623 | 2a424990 | Paul Brook | /* First segment */
|
624 | 2a424990 | Paul Brook | s->txp->cmd_b = val; |
625 | 2a424990 | Paul Brook | s->txp->fifo_used++; |
626 | 2a424990 | Paul Brook | s->txp->buffer_size = s->txp->cmd_a & 0x7ff;
|
627 | 2a424990 | Paul Brook | s->txp->offset = (s->txp->cmd_a >> 16) & 0x1f; |
628 | 2a424990 | Paul Brook | /* End alignment does not include command words. */
|
629 | 2a424990 | Paul Brook | n = (s->txp->buffer_size + s->txp->offset + 3) >> 2; |
630 | 2a424990 | Paul Brook | switch ((n >> 24) & 3) { |
631 | 2a424990 | Paul Brook | case 1: |
632 | 2a424990 | Paul Brook | n = (-n) & 3;
|
633 | 2a424990 | Paul Brook | break;
|
634 | 2a424990 | Paul Brook | case 2: |
635 | 2a424990 | Paul Brook | n = (-n) & 7;
|
636 | 2a424990 | Paul Brook | break;
|
637 | 2a424990 | Paul Brook | default:
|
638 | 2a424990 | Paul Brook | n = 0;
|
639 | 2a424990 | Paul Brook | } |
640 | 2a424990 | Paul Brook | s->txp->pad = n; |
641 | 2a424990 | Paul Brook | s->txp->len = 0;
|
642 | 2a424990 | Paul Brook | } |
643 | 2a424990 | Paul Brook | DPRINTF("Block len:%d offset:%d pad:%d cmd %08x\n",
|
644 | 2a424990 | Paul Brook | s->txp->buffer_size, s->txp->offset, s->txp->pad, |
645 | 2a424990 | Paul Brook | s->txp->cmd_a); |
646 | 2a424990 | Paul Brook | s->txp->state = TX_DATA; |
647 | 2a424990 | Paul Brook | break;
|
648 | 2a424990 | Paul Brook | case TX_DATA:
|
649 | 2a424990 | Paul Brook | if (s->txp->offset >= 4) { |
650 | 2a424990 | Paul Brook | s->txp->offset -= 4;
|
651 | 2a424990 | Paul Brook | break;
|
652 | 2a424990 | Paul Brook | } |
653 | 2a424990 | Paul Brook | if (s->txp->buffer_size <= 0 && s->txp->pad != 0) { |
654 | 2a424990 | Paul Brook | s->txp->pad--; |
655 | 2a424990 | Paul Brook | } else {
|
656 | 2a424990 | Paul Brook | n = 4;
|
657 | 2a424990 | Paul Brook | while (s->txp->offset) {
|
658 | 2a424990 | Paul Brook | val >>= 8;
|
659 | 2a424990 | Paul Brook | n--; |
660 | 2a424990 | Paul Brook | s->txp->offset--; |
661 | 2a424990 | Paul Brook | } |
662 | 2a424990 | Paul Brook | /* Documentation is somewhat unclear on the ordering of bytes
|
663 | 2a424990 | Paul Brook | in FIFO words. Empirical results show it to be little-endian.
|
664 | 2a424990 | Paul Brook | */
|
665 | 2a424990 | Paul Brook | /* TODO: FIFO overflow checking. */
|
666 | 2a424990 | Paul Brook | while (n--) {
|
667 | 2a424990 | Paul Brook | s->txp->data[s->txp->len] = val & 0xff;
|
668 | 2a424990 | Paul Brook | s->txp->len++; |
669 | 2a424990 | Paul Brook | val >>= 8;
|
670 | 2a424990 | Paul Brook | s->txp->buffer_size--; |
671 | 2a424990 | Paul Brook | } |
672 | 2a424990 | Paul Brook | s->txp->fifo_used++; |
673 | 2a424990 | Paul Brook | } |
674 | 2a424990 | Paul Brook | if (s->txp->buffer_size <= 0 && s->txp->pad == 0) { |
675 | 2a424990 | Paul Brook | if (s->txp->cmd_a & 0x1000) { |
676 | 2a424990 | Paul Brook | do_tx_packet(s); |
677 | 2a424990 | Paul Brook | } |
678 | 2a424990 | Paul Brook | if (s->txp->cmd_a & 0x80000000) { |
679 | 2a424990 | Paul Brook | s->int_sts |= TX_IOC_INT; |
680 | 2a424990 | Paul Brook | } |
681 | 2a424990 | Paul Brook | s->txp->state = TX_IDLE; |
682 | 2a424990 | Paul Brook | } |
683 | 2a424990 | Paul Brook | break;
|
684 | 2a424990 | Paul Brook | } |
685 | 2a424990 | Paul Brook | } |
686 | 2a424990 | Paul Brook | |
687 | 2a424990 | Paul Brook | static uint32_t do_phy_read(lan9118_state *s, int reg) |
688 | 2a424990 | Paul Brook | { |
689 | 209bf965 | Paul Brook | uint32_t val; |
690 | 209bf965 | Paul Brook | |
691 | 2a424990 | Paul Brook | switch (reg) {
|
692 | 2a424990 | Paul Brook | case 0: /* Basic Control */ |
693 | 2a424990 | Paul Brook | return s->phy_control;
|
694 | 2a424990 | Paul Brook | case 1: /* Basic Status */ |
695 | 2a424990 | Paul Brook | return s->phy_status;
|
696 | 2a424990 | Paul Brook | case 2: /* ID1 */ |
697 | 2a424990 | Paul Brook | return 0x0007; |
698 | 2a424990 | Paul Brook | case 3: /* ID2 */ |
699 | 2a424990 | Paul Brook | return 0xc0d1; |
700 | 2a424990 | Paul Brook | case 4: /* Auto-neg advertisment */ |
701 | 2a424990 | Paul Brook | return s->phy_advertise;
|
702 | 2a424990 | Paul Brook | case 5: /* Auto-neg Link Partner Ability */ |
703 | 2a424990 | Paul Brook | return 0x0f71; |
704 | 2a424990 | Paul Brook | case 6: /* Auto-neg Expansion */ |
705 | 2a424990 | Paul Brook | return 1; |
706 | 2a424990 | Paul Brook | /* TODO 17, 18, 27, 29, 30, 31 */
|
707 | 209bf965 | Paul Brook | case 29: /* Interrupt source. */ |
708 | 209bf965 | Paul Brook | val = s->phy_int; |
709 | 209bf965 | Paul Brook | s->phy_int = 0;
|
710 | 209bf965 | Paul Brook | phy_update_irq(s); |
711 | 209bf965 | Paul Brook | return val;
|
712 | 209bf965 | Paul Brook | case 30: /* Interrupt mask */ |
713 | 209bf965 | Paul Brook | return s->phy_int_mask;
|
714 | 2a424990 | Paul Brook | default:
|
715 | 2a424990 | Paul Brook | BADF("PHY read reg %d\n", reg);
|
716 | 2a424990 | Paul Brook | return 0; |
717 | 2a424990 | Paul Brook | } |
718 | 2a424990 | Paul Brook | } |
719 | 2a424990 | Paul Brook | |
720 | 2a424990 | Paul Brook | static void do_phy_write(lan9118_state *s, int reg, uint32_t val) |
721 | 2a424990 | Paul Brook | { |
722 | 2a424990 | Paul Brook | switch (reg) {
|
723 | 2a424990 | Paul Brook | case 0: /* Basic Control */ |
724 | 2a424990 | Paul Brook | if (val & 0x8000) { |
725 | 2a424990 | Paul Brook | phy_reset(s); |
726 | 2a424990 | Paul Brook | break;
|
727 | 2a424990 | Paul Brook | } |
728 | 2a424990 | Paul Brook | s->phy_control = val & 0x7980;
|
729 | 4b71051e | Stefan Weil | /* Complete autonegotiation immediately. */
|
730 | 2a424990 | Paul Brook | if (val & 0x1000) { |
731 | 2a424990 | Paul Brook | s->phy_status |= 0x0020;
|
732 | 2a424990 | Paul Brook | } |
733 | 2a424990 | Paul Brook | break;
|
734 | 2a424990 | Paul Brook | case 4: /* Auto-neg advertisment */ |
735 | 2a424990 | Paul Brook | s->phy_advertise = (val & 0x2d7f) | 0x80; |
736 | 2a424990 | Paul Brook | break;
|
737 | 209bf965 | Paul Brook | /* TODO 17, 18, 27, 31 */
|
738 | 209bf965 | Paul Brook | case 30: /* Interrupt mask */ |
739 | 209bf965 | Paul Brook | s->phy_int_mask = val & 0xff;
|
740 | 209bf965 | Paul Brook | phy_update_irq(s); |
741 | 209bf965 | Paul Brook | break;
|
742 | 2a424990 | Paul Brook | default:
|
743 | 2a424990 | Paul Brook | BADF("PHY write reg %d = 0x%04x\n", reg, val);
|
744 | 2a424990 | Paul Brook | } |
745 | 2a424990 | Paul Brook | } |
746 | 2a424990 | Paul Brook | |
747 | 2a424990 | Paul Brook | static void do_mac_write(lan9118_state *s, int reg, uint32_t val) |
748 | 2a424990 | Paul Brook | { |
749 | 2a424990 | Paul Brook | switch (reg) {
|
750 | 2a424990 | Paul Brook | case MAC_CR:
|
751 | 2a424990 | Paul Brook | if ((s->mac_cr & MAC_CR_RXEN) != 0 && (val & MAC_CR_RXEN) == 0) { |
752 | 2a424990 | Paul Brook | s->int_sts |= RXSTOP_INT; |
753 | 2a424990 | Paul Brook | } |
754 | 2a424990 | Paul Brook | s->mac_cr = val & ~MAC_CR_RESERVED; |
755 | 2a424990 | Paul Brook | DPRINTF("MAC_CR: %08x\n", val);
|
756 | 2a424990 | Paul Brook | break;
|
757 | 2a424990 | Paul Brook | case MAC_ADDRH:
|
758 | 2a424990 | Paul Brook | s->conf.macaddr.a[4] = val & 0xff; |
759 | 2a424990 | Paul Brook | s->conf.macaddr.a[5] = (val >> 8) & 0xff; |
760 | 2a424990 | Paul Brook | lan9118_mac_changed(s); |
761 | 2a424990 | Paul Brook | break;
|
762 | 2a424990 | Paul Brook | case MAC_ADDRL:
|
763 | 2a424990 | Paul Brook | s->conf.macaddr.a[0] = val & 0xff; |
764 | 2a424990 | Paul Brook | s->conf.macaddr.a[1] = (val >> 8) & 0xff; |
765 | 2a424990 | Paul Brook | s->conf.macaddr.a[2] = (val >> 16) & 0xff; |
766 | 2a424990 | Paul Brook | s->conf.macaddr.a[3] = (val >> 24) & 0xff; |
767 | 2a424990 | Paul Brook | lan9118_mac_changed(s); |
768 | 2a424990 | Paul Brook | break;
|
769 | 2a424990 | Paul Brook | case MAC_HASHH:
|
770 | 2a424990 | Paul Brook | s->mac_hashh = val; |
771 | 2a424990 | Paul Brook | break;
|
772 | 2a424990 | Paul Brook | case MAC_HASHL:
|
773 | 2a424990 | Paul Brook | s->mac_hashl = val; |
774 | 2a424990 | Paul Brook | break;
|
775 | 2a424990 | Paul Brook | case MAC_MII_ACC:
|
776 | 2a424990 | Paul Brook | s->mac_mii_acc = val & 0xffc2;
|
777 | 2a424990 | Paul Brook | if (val & 2) { |
778 | 2a424990 | Paul Brook | DPRINTF("PHY write %d = 0x%04x\n",
|
779 | 2a424990 | Paul Brook | (val >> 6) & 0x1f, s->mac_mii_data); |
780 | 2a424990 | Paul Brook | do_phy_write(s, (val >> 6) & 0x1f, s->mac_mii_data); |
781 | 2a424990 | Paul Brook | } else {
|
782 | 2a424990 | Paul Brook | s->mac_mii_data = do_phy_read(s, (val >> 6) & 0x1f); |
783 | 2a424990 | Paul Brook | DPRINTF("PHY read %d = 0x%04x\n",
|
784 | 2a424990 | Paul Brook | (val >> 6) & 0x1f, s->mac_mii_data); |
785 | 2a424990 | Paul Brook | } |
786 | 2a424990 | Paul Brook | break;
|
787 | 2a424990 | Paul Brook | case MAC_MII_DATA:
|
788 | 2a424990 | Paul Brook | s->mac_mii_data = val & 0xffff;
|
789 | 2a424990 | Paul Brook | break;
|
790 | 2a424990 | Paul Brook | case MAC_FLOW:
|
791 | 2a424990 | Paul Brook | s->mac_flow = val & 0xffff0000;
|
792 | 2a424990 | Paul Brook | break;
|
793 | a0313c00 | Atsushi Nemoto | case MAC_VLAN1:
|
794 | a0313c00 | Atsushi Nemoto | /* Writing to this register changes a condition for
|
795 | a0313c00 | Atsushi Nemoto | * FrameTooLong bit in rx_status. Since we do not set
|
796 | a0313c00 | Atsushi Nemoto | * FrameTooLong anyway, just ignore write to this.
|
797 | a0313c00 | Atsushi Nemoto | */
|
798 | a0313c00 | Atsushi Nemoto | break;
|
799 | 2a424990 | Paul Brook | default:
|
800 | 2a424990 | Paul Brook | hw_error("lan9118: Unimplemented MAC register write: %d = 0x%x\n",
|
801 | 2a424990 | Paul Brook | s->mac_cmd & 0xf, val);
|
802 | 2a424990 | Paul Brook | } |
803 | 2a424990 | Paul Brook | } |
804 | 2a424990 | Paul Brook | |
805 | 2a424990 | Paul Brook | static uint32_t do_mac_read(lan9118_state *s, int reg) |
806 | 2a424990 | Paul Brook | { |
807 | 2a424990 | Paul Brook | switch (reg) {
|
808 | 2a424990 | Paul Brook | case MAC_CR:
|
809 | 2a424990 | Paul Brook | return s->mac_cr;
|
810 | 2a424990 | Paul Brook | case MAC_ADDRH:
|
811 | 2a424990 | Paul Brook | return s->conf.macaddr.a[4] | (s->conf.macaddr.a[5] << 8); |
812 | 2a424990 | Paul Brook | case MAC_ADDRL:
|
813 | 2a424990 | Paul Brook | return s->conf.macaddr.a[0] | (s->conf.macaddr.a[1] << 8) |
814 | 2a424990 | Paul Brook | | (s->conf.macaddr.a[2] << 16) | (s->conf.macaddr.a[3] << 24); |
815 | 2a424990 | Paul Brook | case MAC_HASHH:
|
816 | 2a424990 | Paul Brook | return s->mac_hashh;
|
817 | 2a424990 | Paul Brook | break;
|
818 | 2a424990 | Paul Brook | case MAC_HASHL:
|
819 | 2a424990 | Paul Brook | return s->mac_hashl;
|
820 | 2a424990 | Paul Brook | break;
|
821 | 2a424990 | Paul Brook | case MAC_MII_ACC:
|
822 | 2a424990 | Paul Brook | return s->mac_mii_acc;
|
823 | 2a424990 | Paul Brook | case MAC_MII_DATA:
|
824 | 2a424990 | Paul Brook | return s->mac_mii_data;
|
825 | 2a424990 | Paul Brook | case MAC_FLOW:
|
826 | 2a424990 | Paul Brook | return s->mac_flow;
|
827 | 2a424990 | Paul Brook | default:
|
828 | 2a424990 | Paul Brook | hw_error("lan9118: Unimplemented MAC register read: %d\n",
|
829 | 2a424990 | Paul Brook | s->mac_cmd & 0xf);
|
830 | 2a424990 | Paul Brook | } |
831 | 2a424990 | Paul Brook | } |
832 | 2a424990 | Paul Brook | |
833 | 2a424990 | Paul Brook | static void lan9118_eeprom_cmd(lan9118_state *s, int cmd, int addr) |
834 | 2a424990 | Paul Brook | { |
835 | 2a424990 | Paul Brook | s->e2p_cmd = (s->e2p_cmd & 0x10) | (cmd << 28) | addr; |
836 | 2a424990 | Paul Brook | switch (cmd) {
|
837 | 2a424990 | Paul Brook | case 0: |
838 | 2a424990 | Paul Brook | s->e2p_data = s->eeprom[addr]; |
839 | 2a424990 | Paul Brook | DPRINTF("EEPROM Read %d = 0x%02x\n", addr, s->e2p_data);
|
840 | 2a424990 | Paul Brook | break;
|
841 | 2a424990 | Paul Brook | case 1: |
842 | 2a424990 | Paul Brook | s->eeprom_writable = 0;
|
843 | 2a424990 | Paul Brook | DPRINTF("EEPROM Write Disable\n");
|
844 | 2a424990 | Paul Brook | break;
|
845 | 2a424990 | Paul Brook | case 2: /* EWEN */ |
846 | 2a424990 | Paul Brook | s->eeprom_writable = 1;
|
847 | 2a424990 | Paul Brook | DPRINTF("EEPROM Write Enable\n");
|
848 | 2a424990 | Paul Brook | break;
|
849 | 2a424990 | Paul Brook | case 3: /* WRITE */ |
850 | 2a424990 | Paul Brook | if (s->eeprom_writable) {
|
851 | 2a424990 | Paul Brook | s->eeprom[addr] &= s->e2p_data; |
852 | 2a424990 | Paul Brook | DPRINTF("EEPROM Write %d = 0x%02x\n", addr, s->e2p_data);
|
853 | 2a424990 | Paul Brook | } else {
|
854 | 2a424990 | Paul Brook | DPRINTF("EEPROM Write %d (ignored)\n", addr);
|
855 | 2a424990 | Paul Brook | } |
856 | 2a424990 | Paul Brook | break;
|
857 | 2a424990 | Paul Brook | case 4: /* WRAL */ |
858 | 2a424990 | Paul Brook | if (s->eeprom_writable) {
|
859 | 2a424990 | Paul Brook | for (addr = 0; addr < 128; addr++) { |
860 | 2a424990 | Paul Brook | s->eeprom[addr] &= s->e2p_data; |
861 | 2a424990 | Paul Brook | } |
862 | 2a424990 | Paul Brook | DPRINTF("EEPROM Write All 0x%02x\n", s->e2p_data);
|
863 | 2a424990 | Paul Brook | } else {
|
864 | 2a424990 | Paul Brook | DPRINTF("EEPROM Write All (ignored)\n");
|
865 | 2a424990 | Paul Brook | } |
866 | 2a424990 | Paul Brook | case 5: /* ERASE */ |
867 | 2a424990 | Paul Brook | if (s->eeprom_writable) {
|
868 | 2a424990 | Paul Brook | s->eeprom[addr] = 0xff;
|
869 | 2a424990 | Paul Brook | DPRINTF("EEPROM Erase %d\n", addr);
|
870 | 2a424990 | Paul Brook | } else {
|
871 | 2a424990 | Paul Brook | DPRINTF("EEPROM Erase %d (ignored)\n", addr);
|
872 | 2a424990 | Paul Brook | } |
873 | 2a424990 | Paul Brook | break;
|
874 | 2a424990 | Paul Brook | case 6: /* ERAL */ |
875 | 2a424990 | Paul Brook | if (s->eeprom_writable) {
|
876 | 2a424990 | Paul Brook | memset(s->eeprom, 0xff, 128); |
877 | 2a424990 | Paul Brook | DPRINTF("EEPROM Erase All\n");
|
878 | 2a424990 | Paul Brook | } else {
|
879 | 2a424990 | Paul Brook | DPRINTF("EEPROM Erase All (ignored)\n");
|
880 | 2a424990 | Paul Brook | } |
881 | 2a424990 | Paul Brook | break;
|
882 | 2a424990 | Paul Brook | case 7: /* RELOAD */ |
883 | 2a424990 | Paul Brook | lan9118_reload_eeprom(s); |
884 | 2a424990 | Paul Brook | break;
|
885 | 2a424990 | Paul Brook | } |
886 | 2a424990 | Paul Brook | } |
887 | 2a424990 | Paul Brook | |
888 | 209bf965 | Paul Brook | static void lan9118_tick(void *opaque) |
889 | 209bf965 | Paul Brook | { |
890 | 209bf965 | Paul Brook | lan9118_state *s = (lan9118_state *)opaque; |
891 | 209bf965 | Paul Brook | if (s->int_en & GPT_INT) {
|
892 | 209bf965 | Paul Brook | s->int_sts |= GPT_INT; |
893 | 209bf965 | Paul Brook | } |
894 | 209bf965 | Paul Brook | lan9118_update(s); |
895 | 209bf965 | Paul Brook | } |
896 | 209bf965 | Paul Brook | |
897 | 2a424990 | Paul Brook | static void lan9118_writel(void *opaque, target_phys_addr_t offset, |
898 | 2a424990 | Paul Brook | uint32_t val) |
899 | 2a424990 | Paul Brook | { |
900 | 2a424990 | Paul Brook | lan9118_state *s = (lan9118_state *)opaque; |
901 | 2a424990 | Paul Brook | offset &= 0xff;
|
902 | 2a424990 | Paul Brook | |
903 | 2a424990 | Paul Brook | //DPRINTF("Write reg 0x%02x = 0x%08x\n", (int)offset, val);
|
904 | 2a424990 | Paul Brook | if (offset >= 0x20 && offset < 0x40) { |
905 | 2a424990 | Paul Brook | /* TX FIFO */
|
906 | 2a424990 | Paul Brook | tx_fifo_push(s, val); |
907 | 2a424990 | Paul Brook | return;
|
908 | 2a424990 | Paul Brook | } |
909 | 2a424990 | Paul Brook | switch (offset) {
|
910 | 2a424990 | Paul Brook | case CSR_IRQ_CFG:
|
911 | 2a424990 | Paul Brook | /* TODO: Implement interrupt deassertion intervals. */
|
912 | eb47d7c5 | Peter Maydell | val &= (IRQ_EN | IRQ_POL | IRQ_TYPE); |
913 | eb47d7c5 | Peter Maydell | s->irq_cfg = (s->irq_cfg & IRQ_INT) | val; |
914 | 2a424990 | Paul Brook | break;
|
915 | 2a424990 | Paul Brook | case CSR_INT_STS:
|
916 | 2a424990 | Paul Brook | s->int_sts &= ~val; |
917 | 2a424990 | Paul Brook | break;
|
918 | 2a424990 | Paul Brook | case CSR_INT_EN:
|
919 | 2a424990 | Paul Brook | s->int_en = val & ~RESERVED_INT; |
920 | 2a424990 | Paul Brook | s->int_sts |= val & SW_INT; |
921 | 2a424990 | Paul Brook | break;
|
922 | 2a424990 | Paul Brook | case CSR_FIFO_INT:
|
923 | 2a424990 | Paul Brook | DPRINTF("FIFO INT levels %08x\n", val);
|
924 | 2a424990 | Paul Brook | s->fifo_int = val; |
925 | 2a424990 | Paul Brook | break;
|
926 | 2a424990 | Paul Brook | case CSR_RX_CFG:
|
927 | 2a424990 | Paul Brook | if (val & 0x8000) { |
928 | 2a424990 | Paul Brook | /* RX_DUMP */
|
929 | 2a424990 | Paul Brook | s->rx_fifo_used = 0;
|
930 | 2a424990 | Paul Brook | s->rx_status_fifo_used = 0;
|
931 | 2a424990 | Paul Brook | s->rx_packet_size_tail = s->rx_packet_size_head; |
932 | 2a424990 | Paul Brook | s->rx_packet_size[s->rx_packet_size_head] = 0;
|
933 | 2a424990 | Paul Brook | } |
934 | 2a424990 | Paul Brook | s->rx_cfg = val & 0xcfff1ff0;
|
935 | 2a424990 | Paul Brook | break;
|
936 | 2a424990 | Paul Brook | case CSR_TX_CFG:
|
937 | 2a424990 | Paul Brook | if (val & 0x8000) { |
938 | 2a424990 | Paul Brook | s->tx_status_fifo_used = 0;
|
939 | 2a424990 | Paul Brook | } |
940 | 2a424990 | Paul Brook | if (val & 0x4000) { |
941 | 2a424990 | Paul Brook | s->txp->state = TX_IDLE; |
942 | 2a424990 | Paul Brook | s->txp->fifo_used = 0;
|
943 | 2a424990 | Paul Brook | s->txp->cmd_a = 0xffffffff;
|
944 | 2a424990 | Paul Brook | } |
945 | 2a424990 | Paul Brook | s->tx_cfg = val & 6;
|
946 | 2a424990 | Paul Brook | break;
|
947 | 2a424990 | Paul Brook | case CSR_HW_CFG:
|
948 | 2a424990 | Paul Brook | if (val & 1) { |
949 | 2a424990 | Paul Brook | /* SRST */
|
950 | 2a424990 | Paul Brook | lan9118_reset(&s->busdev.qdev); |
951 | 2a424990 | Paul Brook | } else {
|
952 | 2a424990 | Paul Brook | s->hw_cfg = val & 0x003f300;
|
953 | 2a424990 | Paul Brook | } |
954 | 2a424990 | Paul Brook | break;
|
955 | 2a424990 | Paul Brook | case CSR_RX_DP_CTRL:
|
956 | 2a424990 | Paul Brook | if (val & 0x80000000) { |
957 | 2a424990 | Paul Brook | /* Skip forward to next packet. */
|
958 | 2a424990 | Paul Brook | s->rxp_pad = 0;
|
959 | 2a424990 | Paul Brook | s->rxp_offset = 0;
|
960 | 2a424990 | Paul Brook | if (s->rxp_size == 0) { |
961 | 2a424990 | Paul Brook | /* Pop a word to start the next packet. */
|
962 | 2a424990 | Paul Brook | rx_fifo_pop(s); |
963 | 2a424990 | Paul Brook | s->rxp_pad = 0;
|
964 | 2a424990 | Paul Brook | s->rxp_offset = 0;
|
965 | 2a424990 | Paul Brook | } |
966 | 2a424990 | Paul Brook | s->rx_fifo_head += s->rxp_size; |
967 | 2a424990 | Paul Brook | if (s->rx_fifo_head >= s->rx_fifo_size) {
|
968 | 2a424990 | Paul Brook | s->rx_fifo_head -= s->rx_fifo_size; |
969 | 2a424990 | Paul Brook | } |
970 | 2a424990 | Paul Brook | } |
971 | 2a424990 | Paul Brook | break;
|
972 | 2a424990 | Paul Brook | case CSR_PMT_CTRL:
|
973 | 2a424990 | Paul Brook | if (val & 0x400) { |
974 | 2a424990 | Paul Brook | phy_reset(s); |
975 | 2a424990 | Paul Brook | } |
976 | 2a424990 | Paul Brook | s->pmt_ctrl &= ~0x34e;
|
977 | 2a424990 | Paul Brook | s->pmt_ctrl |= (val & 0x34e);
|
978 | 2a424990 | Paul Brook | break;
|
979 | 2a424990 | Paul Brook | case CSR_GPIO_CFG:
|
980 | 2a424990 | Paul Brook | /* Probably just enabling LEDs. */
|
981 | 2a424990 | Paul Brook | s->gpio_cfg = val & 0x7777071f;
|
982 | 2a424990 | Paul Brook | break;
|
983 | 209bf965 | Paul Brook | case CSR_GPT_CFG:
|
984 | 209bf965 | Paul Brook | if ((s->gpt_cfg ^ val) & GPT_TIMER_EN) {
|
985 | 209bf965 | Paul Brook | if (val & GPT_TIMER_EN) {
|
986 | 209bf965 | Paul Brook | ptimer_set_count(s->timer, val & 0xffff);
|
987 | 209bf965 | Paul Brook | ptimer_run(s->timer, 0);
|
988 | 209bf965 | Paul Brook | } else {
|
989 | 209bf965 | Paul Brook | ptimer_stop(s->timer); |
990 | 209bf965 | Paul Brook | ptimer_set_count(s->timer, 0xffff);
|
991 | 209bf965 | Paul Brook | } |
992 | 209bf965 | Paul Brook | } |
993 | 209bf965 | Paul Brook | s->gpt_cfg = val & (GPT_TIMER_EN | 0xffff);
|
994 | 209bf965 | Paul Brook | break;
|
995 | 2a424990 | Paul Brook | case CSR_WORD_SWAP:
|
996 | 2a424990 | Paul Brook | /* Ignored because we're in 32-bit mode. */
|
997 | 2a424990 | Paul Brook | s->word_swap = val; |
998 | 2a424990 | Paul Brook | break;
|
999 | 2a424990 | Paul Brook | case CSR_MAC_CSR_CMD:
|
1000 | 2a424990 | Paul Brook | s->mac_cmd = val & 0x4000000f;
|
1001 | 2a424990 | Paul Brook | if (val & 0x80000000) { |
1002 | 2a424990 | Paul Brook | if (val & 0x40000000) { |
1003 | 2a424990 | Paul Brook | s->mac_data = do_mac_read(s, val & 0xf);
|
1004 | 2a424990 | Paul Brook | DPRINTF("MAC read %d = 0x%08x\n", val & 0xf, s->mac_data); |
1005 | 2a424990 | Paul Brook | } else {
|
1006 | 2a424990 | Paul Brook | DPRINTF("MAC write %d = 0x%08x\n", val & 0xf, s->mac_data); |
1007 | 2a424990 | Paul Brook | do_mac_write(s, val & 0xf, s->mac_data);
|
1008 | 2a424990 | Paul Brook | } |
1009 | 2a424990 | Paul Brook | } |
1010 | 2a424990 | Paul Brook | break;
|
1011 | 2a424990 | Paul Brook | case CSR_MAC_CSR_DATA:
|
1012 | 2a424990 | Paul Brook | s->mac_data = val; |
1013 | 2a424990 | Paul Brook | break;
|
1014 | 2a424990 | Paul Brook | case CSR_AFC_CFG:
|
1015 | 2a424990 | Paul Brook | s->afc_cfg = val & 0x00ffffff;
|
1016 | 2a424990 | Paul Brook | break;
|
1017 | 2a424990 | Paul Brook | case CSR_E2P_CMD:
|
1018 | c46a3ea0 | Blue Swirl | lan9118_eeprom_cmd(s, (val >> 28) & 7, val & 0x7f); |
1019 | 2a424990 | Paul Brook | break;
|
1020 | 2a424990 | Paul Brook | case CSR_E2P_DATA:
|
1021 | 2a424990 | Paul Brook | s->e2p_data = val & 0xff;
|
1022 | 2a424990 | Paul Brook | break;
|
1023 | 2a424990 | Paul Brook | |
1024 | 2a424990 | Paul Brook | default:
|
1025 | 2a424990 | Paul Brook | hw_error("lan9118_write: Bad reg 0x%x = %x\n", (int)offset, val); |
1026 | 2a424990 | Paul Brook | break;
|
1027 | 2a424990 | Paul Brook | } |
1028 | 2a424990 | Paul Brook | lan9118_update(s); |
1029 | 2a424990 | Paul Brook | } |
1030 | 2a424990 | Paul Brook | |
1031 | 2a424990 | Paul Brook | static uint32_t lan9118_readl(void *opaque, target_phys_addr_t offset) |
1032 | 2a424990 | Paul Brook | { |
1033 | 2a424990 | Paul Brook | lan9118_state *s = (lan9118_state *)opaque; |
1034 | 2a424990 | Paul Brook | |
1035 | 2a424990 | Paul Brook | //DPRINTF("Read reg 0x%02x\n", (int)offset);
|
1036 | 2a424990 | Paul Brook | if (offset < 0x20) { |
1037 | 2a424990 | Paul Brook | /* RX FIFO */
|
1038 | 2a424990 | Paul Brook | return rx_fifo_pop(s);
|
1039 | 2a424990 | Paul Brook | } |
1040 | 2a424990 | Paul Brook | switch (offset) {
|
1041 | 2a424990 | Paul Brook | case 0x40: |
1042 | 2a424990 | Paul Brook | return rx_status_fifo_pop(s);
|
1043 | 2a424990 | Paul Brook | case 0x44: |
1044 | 2a424990 | Paul Brook | return s->rx_status_fifo[s->tx_status_fifo_head];
|
1045 | 2a424990 | Paul Brook | case 0x48: |
1046 | 2a424990 | Paul Brook | return tx_status_fifo_pop(s);
|
1047 | 2a424990 | Paul Brook | case 0x4c: |
1048 | 2a424990 | Paul Brook | return s->tx_status_fifo[s->tx_status_fifo_head];
|
1049 | 2a424990 | Paul Brook | case CSR_ID_REV:
|
1050 | 2a424990 | Paul Brook | return 0x01180001; |
1051 | 2a424990 | Paul Brook | case CSR_IRQ_CFG:
|
1052 | 2a424990 | Paul Brook | return s->irq_cfg;
|
1053 | 2a424990 | Paul Brook | case CSR_INT_STS:
|
1054 | 2a424990 | Paul Brook | return s->int_sts;
|
1055 | 2a424990 | Paul Brook | case CSR_INT_EN:
|
1056 | 2a424990 | Paul Brook | return s->int_en;
|
1057 | 2a424990 | Paul Brook | case CSR_BYTE_TEST:
|
1058 | 2a424990 | Paul Brook | return 0x87654321; |
1059 | 2a424990 | Paul Brook | case CSR_FIFO_INT:
|
1060 | 2a424990 | Paul Brook | return s->fifo_int;
|
1061 | 2a424990 | Paul Brook | case CSR_RX_CFG:
|
1062 | 2a424990 | Paul Brook | return s->rx_cfg;
|
1063 | 2a424990 | Paul Brook | case CSR_TX_CFG:
|
1064 | 2a424990 | Paul Brook | return s->tx_cfg;
|
1065 | 2a424990 | Paul Brook | case CSR_HW_CFG:
|
1066 | 2a424990 | Paul Brook | return s->hw_cfg | 0x4; |
1067 | 2a424990 | Paul Brook | case CSR_RX_DP_CTRL:
|
1068 | 2a424990 | Paul Brook | return 0; |
1069 | 2a424990 | Paul Brook | case CSR_RX_FIFO_INF:
|
1070 | 2a424990 | Paul Brook | return (s->rx_status_fifo_used << 16) | (s->rx_fifo_used << 2); |
1071 | 2a424990 | Paul Brook | case CSR_TX_FIFO_INF:
|
1072 | 2a424990 | Paul Brook | return (s->tx_status_fifo_used << 16) |
1073 | 2a424990 | Paul Brook | | (s->tx_fifo_size - s->txp->fifo_used); |
1074 | 2a424990 | Paul Brook | case CSR_PMT_CTRL:
|
1075 | 2a424990 | Paul Brook | return s->pmt_ctrl;
|
1076 | 2a424990 | Paul Brook | case CSR_GPIO_CFG:
|
1077 | 2a424990 | Paul Brook | return s->gpio_cfg;
|
1078 | 209bf965 | Paul Brook | case CSR_GPT_CFG:
|
1079 | 209bf965 | Paul Brook | return s->gpt_cfg;
|
1080 | 209bf965 | Paul Brook | case CSR_GPT_CNT:
|
1081 | 209bf965 | Paul Brook | return ptimer_get_count(s->timer);
|
1082 | 2a424990 | Paul Brook | case CSR_WORD_SWAP:
|
1083 | 2a424990 | Paul Brook | return s->word_swap;
|
1084 | 2a424990 | Paul Brook | case CSR_FREE_RUN:
|
1085 | 74475455 | Paolo Bonzini | return (qemu_get_clock_ns(vm_clock) / 40) - s->free_timer_start; |
1086 | 2a424990 | Paul Brook | case CSR_RX_DROP:
|
1087 | 2a424990 | Paul Brook | /* TODO: Implement dropped frames counter. */
|
1088 | 2a424990 | Paul Brook | return 0; |
1089 | 2a424990 | Paul Brook | case CSR_MAC_CSR_CMD:
|
1090 | 2a424990 | Paul Brook | return s->mac_cmd;
|
1091 | 2a424990 | Paul Brook | case CSR_MAC_CSR_DATA:
|
1092 | 2a424990 | Paul Brook | return s->mac_data;
|
1093 | 2a424990 | Paul Brook | case CSR_AFC_CFG:
|
1094 | 2a424990 | Paul Brook | return s->afc_cfg;
|
1095 | 2a424990 | Paul Brook | case CSR_E2P_CMD:
|
1096 | 2a424990 | Paul Brook | return s->e2p_cmd;
|
1097 | 2a424990 | Paul Brook | case CSR_E2P_DATA:
|
1098 | 2a424990 | Paul Brook | return s->e2p_data;
|
1099 | 2a424990 | Paul Brook | } |
1100 | 2a424990 | Paul Brook | hw_error("lan9118_read: Bad reg 0x%x\n", (int)offset); |
1101 | 2a424990 | Paul Brook | return 0; |
1102 | 2a424990 | Paul Brook | } |
1103 | 2a424990 | Paul Brook | |
1104 | 2a424990 | Paul Brook | static CPUReadMemoryFunc * const lan9118_readfn[] = { |
1105 | 2a424990 | Paul Brook | lan9118_readl, |
1106 | 2a424990 | Paul Brook | lan9118_readl, |
1107 | 2a424990 | Paul Brook | lan9118_readl |
1108 | 2a424990 | Paul Brook | }; |
1109 | 2a424990 | Paul Brook | |
1110 | 2a424990 | Paul Brook | static CPUWriteMemoryFunc * const lan9118_writefn[] = { |
1111 | 2a424990 | Paul Brook | lan9118_writel, |
1112 | 2a424990 | Paul Brook | lan9118_writel, |
1113 | 2a424990 | Paul Brook | lan9118_writel |
1114 | 2a424990 | Paul Brook | }; |
1115 | 2a424990 | Paul Brook | |
1116 | 83b9f88c | Mark McLoughlin | static void lan9118_cleanup(VLANClientState *nc) |
1117 | 2a424990 | Paul Brook | { |
1118 | 83b9f88c | Mark McLoughlin | lan9118_state *s = DO_UPCAST(NICState, nc, nc)->opaque; |
1119 | 2a424990 | Paul Brook | |
1120 | 83b9f88c | Mark McLoughlin | s->nic = NULL;
|
1121 | 2a424990 | Paul Brook | } |
1122 | 2a424990 | Paul Brook | |
1123 | 83b9f88c | Mark McLoughlin | static NetClientInfo net_lan9118_info = {
|
1124 | 83b9f88c | Mark McLoughlin | .type = NET_CLIENT_TYPE_NIC, |
1125 | 83b9f88c | Mark McLoughlin | .size = sizeof(NICState),
|
1126 | 83b9f88c | Mark McLoughlin | .can_receive = lan9118_can_receive, |
1127 | 83b9f88c | Mark McLoughlin | .receive = lan9118_receive, |
1128 | 83b9f88c | Mark McLoughlin | .cleanup = lan9118_cleanup, |
1129 | 83b9f88c | Mark McLoughlin | .link_status_changed = lan9118_set_link, |
1130 | 83b9f88c | Mark McLoughlin | }; |
1131 | 83b9f88c | Mark McLoughlin | |
1132 | 2a424990 | Paul Brook | static int lan9118_init1(SysBusDevice *dev) |
1133 | 2a424990 | Paul Brook | { |
1134 | 2a424990 | Paul Brook | lan9118_state *s = FROM_SYSBUS(lan9118_state, dev); |
1135 | 209bf965 | Paul Brook | QEMUBH *bh; |
1136 | 2a424990 | Paul Brook | int i;
|
1137 | 2a424990 | Paul Brook | |
1138 | 2a424990 | Paul Brook | s->mmio_index = cpu_register_io_memory(lan9118_readfn, |
1139 | 2507c12a | Alexander Graf | lan9118_writefn, s, |
1140 | 2507c12a | Alexander Graf | DEVICE_NATIVE_ENDIAN); |
1141 | 2a424990 | Paul Brook | sysbus_init_mmio(dev, 0x100, s->mmio_index);
|
1142 | 2a424990 | Paul Brook | sysbus_init_irq(dev, &s->irq); |
1143 | 2a424990 | Paul Brook | qemu_macaddr_default_if_unset(&s->conf.macaddr); |
1144 | 2a424990 | Paul Brook | |
1145 | 83b9f88c | Mark McLoughlin | s->nic = qemu_new_nic(&net_lan9118_info, &s->conf, |
1146 | 83b9f88c | Mark McLoughlin | dev->qdev.info->name, dev->qdev.id, s); |
1147 | 83b9f88c | Mark McLoughlin | qemu_format_nic_info_str(&s->nic->nc, s->conf.macaddr.a); |
1148 | 2a424990 | Paul Brook | s->eeprom[0] = 0xa5; |
1149 | 2a424990 | Paul Brook | for (i = 0; i < 6; i++) { |
1150 | 2a424990 | Paul Brook | s->eeprom[i + 1] = s->conf.macaddr.a[i];
|
1151 | 2a424990 | Paul Brook | } |
1152 | 2a424990 | Paul Brook | s->pmt_ctrl = 1;
|
1153 | 2a424990 | Paul Brook | s->txp = &s->tx_packet; |
1154 | 2a424990 | Paul Brook | |
1155 | 209bf965 | Paul Brook | bh = qemu_bh_new(lan9118_tick, s); |
1156 | 209bf965 | Paul Brook | s->timer = ptimer_init(bh); |
1157 | 209bf965 | Paul Brook | ptimer_set_freq(s->timer, 10000);
|
1158 | 209bf965 | Paul Brook | ptimer_set_limit(s->timer, 0xffff, 1); |
1159 | 209bf965 | Paul Brook | |
1160 | 2a424990 | Paul Brook | /* ??? Save/restore. */
|
1161 | 2a424990 | Paul Brook | return 0; |
1162 | 2a424990 | Paul Brook | } |
1163 | 2a424990 | Paul Brook | |
1164 | 2a424990 | Paul Brook | static SysBusDeviceInfo lan9118_info = {
|
1165 | 2a424990 | Paul Brook | .init = lan9118_init1, |
1166 | 2a424990 | Paul Brook | .qdev.name = "lan9118",
|
1167 | 2a424990 | Paul Brook | .qdev.size = sizeof(lan9118_state),
|
1168 | 2a424990 | Paul Brook | .qdev.reset = lan9118_reset, |
1169 | 2a424990 | Paul Brook | .qdev.props = (Property[]) { |
1170 | 2a424990 | Paul Brook | DEFINE_NIC_PROPERTIES(lan9118_state, conf), |
1171 | 2a424990 | Paul Brook | DEFINE_PROP_END_OF_LIST(), |
1172 | 2a424990 | Paul Brook | } |
1173 | 2a424990 | Paul Brook | }; |
1174 | 2a424990 | Paul Brook | |
1175 | 2a424990 | Paul Brook | static void lan9118_register_devices(void) |
1176 | 2a424990 | Paul Brook | { |
1177 | 2a424990 | Paul Brook | sysbus_register_withprop(&lan9118_info); |
1178 | 2a424990 | Paul Brook | } |
1179 | 2a424990 | Paul Brook | |
1180 | 2a424990 | Paul Brook | /* Legacy helper function. Should go away when machine config files are
|
1181 | 2a424990 | Paul Brook | implemented. */
|
1182 | 2a424990 | Paul Brook | void lan9118_init(NICInfo *nd, uint32_t base, qemu_irq irq)
|
1183 | 2a424990 | Paul Brook | { |
1184 | 2a424990 | Paul Brook | DeviceState *dev; |
1185 | 2a424990 | Paul Brook | SysBusDevice *s; |
1186 | 2a424990 | Paul Brook | |
1187 | 2a424990 | Paul Brook | qemu_check_nic_model(nd, "lan9118");
|
1188 | 2a424990 | Paul Brook | dev = qdev_create(NULL, "lan9118"); |
1189 | 2a424990 | Paul Brook | qdev_set_nic_properties(dev, nd); |
1190 | 2a424990 | Paul Brook | qdev_init_nofail(dev); |
1191 | 2a424990 | Paul Brook | s = sysbus_from_qdev(dev); |
1192 | 2a424990 | Paul Brook | sysbus_mmio_map(s, 0, base);
|
1193 | 2a424990 | Paul Brook | sysbus_connect_irq(s, 0, irq);
|
1194 | 2a424990 | Paul Brook | } |
1195 | 2a424990 | Paul Brook | |
1196 | 2a424990 | Paul Brook | device_init(lan9118_register_devices) |