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1 | 02645926 | balrog | /*
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2 | 02645926 | balrog | * TI OMAP on-chip I2C controller. Only "new I2C" mode supported.
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3 | 02645926 | balrog | *
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4 | 02645926 | balrog | * Copyright (C) 2007 Andrzej Zaborowski <balrog@zabor.org>
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5 | 02645926 | balrog | *
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6 | 02645926 | balrog | * This program is free software; you can redistribute it and/or
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7 | 02645926 | balrog | * modify it under the terms of the GNU General Public License as
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8 | 02645926 | balrog | * published by the Free Software Foundation; either version 2 of
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9 | 02645926 | balrog | * the License, or (at your option) any later version.
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10 | 02645926 | balrog | *
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11 | 02645926 | balrog | * This program is distributed in the hope that it will be useful,
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12 | 02645926 | balrog | * but WITHOUT ANY WARRANTY; without even the implied warranty of
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13 | 02645926 | balrog | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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14 | 02645926 | balrog | * GNU General Public License for more details.
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15 | 02645926 | balrog | *
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16 | fad6cb1a | aurel32 | * You should have received a copy of the GNU General Public License along
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17 | 8167ee88 | Blue Swirl | * with this program; if not, see <http://www.gnu.org/licenses/>.
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18 | 02645926 | balrog | */
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19 | 87ecb68b | pbrook | #include "hw.h" |
20 | 87ecb68b | pbrook | #include "i2c.h" |
21 | 87ecb68b | pbrook | #include "omap.h" |
22 | 02645926 | balrog | |
23 | 02645926 | balrog | struct omap_i2c_s {
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24 | 74878139 | Benoît Canet | MemoryRegion iomem; |
25 | 02645926 | balrog | qemu_irq irq; |
26 | 02645926 | balrog | qemu_irq drq[2];
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27 | 02645926 | balrog | i2c_bus *bus; |
28 | 02645926 | balrog | |
29 | 29885477 | balrog | uint8_t revision; |
30 | 02645926 | balrog | uint8_t mask; |
31 | 02645926 | balrog | uint16_t stat; |
32 | 02645926 | balrog | uint16_t dma; |
33 | 02645926 | balrog | uint16_t count; |
34 | 02645926 | balrog | int count_cur;
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35 | 02645926 | balrog | uint32_t fifo; |
36 | 02645926 | balrog | int rxlen;
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37 | 02645926 | balrog | int txlen;
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38 | 02645926 | balrog | uint16_t control; |
39 | 02645926 | balrog | uint16_t addr[2];
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40 | 02645926 | balrog | uint8_t divider; |
41 | 02645926 | balrog | uint8_t times[2];
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42 | 02645926 | balrog | uint16_t test; |
43 | 02645926 | balrog | }; |
44 | 02645926 | balrog | |
45 | 29885477 | balrog | #define OMAP2_INTR_REV 0x34 |
46 | 29885477 | balrog | #define OMAP2_GC_REV 0x34 |
47 | 29885477 | balrog | |
48 | 02645926 | balrog | static void omap_i2c_interrupts_update(struct omap_i2c_s *s) |
49 | 02645926 | balrog | { |
50 | 02645926 | balrog | qemu_set_irq(s->irq, s->stat & s->mask); |
51 | 02645926 | balrog | if ((s->dma >> 15) & 1) /* RDMA_EN */ |
52 | 02645926 | balrog | qemu_set_irq(s->drq[0], (s->stat >> 3) & 1); /* RRDY */ |
53 | 02645926 | balrog | if ((s->dma >> 7) & 1) /* XDMA_EN */ |
54 | 02645926 | balrog | qemu_set_irq(s->drq[1], (s->stat >> 4) & 1); /* XRDY */ |
55 | 02645926 | balrog | } |
56 | 02645926 | balrog | |
57 | 02645926 | balrog | static void omap_i2c_fifo_run(struct omap_i2c_s *s) |
58 | 02645926 | balrog | { |
59 | 02645926 | balrog | int ack = 1; |
60 | 02645926 | balrog | |
61 | 02645926 | balrog | if (!i2c_bus_busy(s->bus))
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62 | 02645926 | balrog | return;
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63 | 02645926 | balrog | |
64 | 02645926 | balrog | if ((s->control >> 2) & 1) { /* RM */ |
65 | 02645926 | balrog | if ((s->control >> 1) & 1) { /* STP */ |
66 | 02645926 | balrog | i2c_end_transfer(s->bus); |
67 | 02645926 | balrog | s->control &= ~(1 << 1); /* STP */ |
68 | 02645926 | balrog | s->count_cur = s->count; |
69 | 29885477 | balrog | s->txlen = 0;
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70 | 02645926 | balrog | } else if ((s->control >> 9) & 1) { /* TRX */ |
71 | 02645926 | balrog | while (ack && s->txlen)
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72 | 02645926 | balrog | ack = (i2c_send(s->bus, |
73 | 02645926 | balrog | (s->fifo >> ((-- s->txlen) << 3)) &
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74 | 02645926 | balrog | 0xff) >= 0); |
75 | 02645926 | balrog | s->stat |= 1 << 4; /* XRDY */ |
76 | 02645926 | balrog | } else {
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77 | 02645926 | balrog | while (s->rxlen < 4) |
78 | 02645926 | balrog | s->fifo |= i2c_recv(s->bus) << ((s->rxlen ++) << 3);
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79 | 02645926 | balrog | s->stat |= 1 << 3; /* RRDY */ |
80 | 02645926 | balrog | } |
81 | 02645926 | balrog | } else {
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82 | 02645926 | balrog | if ((s->control >> 9) & 1) { /* TRX */ |
83 | 02645926 | balrog | while (ack && s->count_cur && s->txlen) {
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84 | 02645926 | balrog | ack = (i2c_send(s->bus, |
85 | 02645926 | balrog | (s->fifo >> ((-- s->txlen) << 3)) &
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86 | 02645926 | balrog | 0xff) >= 0); |
87 | 02645926 | balrog | s->count_cur --; |
88 | 02645926 | balrog | } |
89 | 02645926 | balrog | if (ack && s->count_cur)
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90 | 02645926 | balrog | s->stat |= 1 << 4; /* XRDY */ |
91 | 827df9f3 | balrog | else
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92 | 827df9f3 | balrog | s->stat &= ~(1 << 4); /* XRDY */ |
93 | 02645926 | balrog | if (!s->count_cur) {
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94 | 02645926 | balrog | s->stat |= 1 << 2; /* ARDY */ |
95 | 02645926 | balrog | s->control &= ~(1 << 10); /* MST */ |
96 | 02645926 | balrog | } |
97 | 02645926 | balrog | } else {
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98 | 02645926 | balrog | while (s->count_cur && s->rxlen < 4) { |
99 | 02645926 | balrog | s->fifo |= i2c_recv(s->bus) << ((s->rxlen ++) << 3);
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100 | 02645926 | balrog | s->count_cur --; |
101 | 02645926 | balrog | } |
102 | 02645926 | balrog | if (s->rxlen)
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103 | 02645926 | balrog | s->stat |= 1 << 3; /* RRDY */ |
104 | 827df9f3 | balrog | else
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105 | 827df9f3 | balrog | s->stat &= ~(1 << 3); /* RRDY */ |
106 | 02645926 | balrog | } |
107 | 02645926 | balrog | if (!s->count_cur) {
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108 | 02645926 | balrog | if ((s->control >> 1) & 1) { /* STP */ |
109 | 02645926 | balrog | i2c_end_transfer(s->bus); |
110 | 02645926 | balrog | s->control &= ~(1 << 1); /* STP */ |
111 | 02645926 | balrog | s->count_cur = s->count; |
112 | 29885477 | balrog | s->txlen = 0;
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113 | 02645926 | balrog | } else {
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114 | 02645926 | balrog | s->stat |= 1 << 2; /* ARDY */ |
115 | 02645926 | balrog | s->control &= ~(1 << 10); /* MST */ |
116 | 02645926 | balrog | } |
117 | 02645926 | balrog | } |
118 | 02645926 | balrog | } |
119 | 02645926 | balrog | |
120 | 02645926 | balrog | s->stat |= (!ack) << 1; /* NACK */ |
121 | 02645926 | balrog | if (!ack)
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122 | 02645926 | balrog | s->control &= ~(1 << 1); /* STP */ |
123 | 02645926 | balrog | } |
124 | 02645926 | balrog | |
125 | 02645926 | balrog | void omap_i2c_reset(struct omap_i2c_s *s) |
126 | 02645926 | balrog | { |
127 | 02645926 | balrog | s->mask = 0;
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128 | 02645926 | balrog | s->stat = 0;
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129 | 02645926 | balrog | s->dma = 0;
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130 | 02645926 | balrog | s->count = 0;
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131 | 02645926 | balrog | s->count_cur = 0;
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132 | 02645926 | balrog | s->fifo = 0;
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133 | 02645926 | balrog | s->rxlen = 0;
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134 | 02645926 | balrog | s->txlen = 0;
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135 | 02645926 | balrog | s->control = 0;
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136 | 02645926 | balrog | s->addr[0] = 0; |
137 | 02645926 | balrog | s->addr[1] = 0; |
138 | 02645926 | balrog | s->divider = 0;
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139 | 02645926 | balrog | s->times[0] = 0; |
140 | 02645926 | balrog | s->times[1] = 0; |
141 | 02645926 | balrog | s->test = 0;
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142 | 02645926 | balrog | } |
143 | 02645926 | balrog | |
144 | c227f099 | Anthony Liguori | static uint32_t omap_i2c_read(void *opaque, target_phys_addr_t addr) |
145 | 02645926 | balrog | { |
146 | 02645926 | balrog | struct omap_i2c_s *s = (struct omap_i2c_s *) opaque; |
147 | cf965d24 | balrog | int offset = addr & OMAP_MPUI_REG_MASK;
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148 | 02645926 | balrog | uint16_t ret; |
149 | 02645926 | balrog | |
150 | 02645926 | balrog | switch (offset) {
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151 | 02645926 | balrog | case 0x00: /* I2C_REV */ |
152 | 29885477 | balrog | return s->revision; /* REV */ |
153 | 02645926 | balrog | |
154 | 02645926 | balrog | case 0x04: /* I2C_IE */ |
155 | 02645926 | balrog | return s->mask;
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156 | 02645926 | balrog | |
157 | 02645926 | balrog | case 0x08: /* I2C_STAT */ |
158 | 02645926 | balrog | return s->stat | (i2c_bus_busy(s->bus) << 12); |
159 | 02645926 | balrog | |
160 | 02645926 | balrog | case 0x0c: /* I2C_IV */ |
161 | 29885477 | balrog | if (s->revision >= OMAP2_INTR_REV)
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162 | 29885477 | balrog | break;
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163 | 02645926 | balrog | ret = ffs(s->stat & s->mask); |
164 | 02645926 | balrog | if (ret)
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165 | 02645926 | balrog | s->stat ^= 1 << (ret - 1); |
166 | 02645926 | balrog | omap_i2c_interrupts_update(s); |
167 | 02645926 | balrog | return ret;
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168 | 02645926 | balrog | |
169 | 29885477 | balrog | case 0x10: /* I2C_SYSS */ |
170 | 29885477 | balrog | return (s->control >> 15) & 1; /* I2C_EN */ |
171 | 29885477 | balrog | |
172 | 02645926 | balrog | case 0x14: /* I2C_BUF */ |
173 | 02645926 | balrog | return s->dma;
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174 | 02645926 | balrog | |
175 | 02645926 | balrog | case 0x18: /* I2C_CNT */ |
176 | 02645926 | balrog | return s->count_cur; /* DCOUNT */ |
177 | 02645926 | balrog | |
178 | 02645926 | balrog | case 0x1c: /* I2C_DATA */ |
179 | 02645926 | balrog | ret = 0;
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180 | 02645926 | balrog | if (s->control & (1 << 14)) { /* BE */ |
181 | 02645926 | balrog | ret |= ((s->fifo >> 0) & 0xff) << 8; |
182 | 02645926 | balrog | ret |= ((s->fifo >> 8) & 0xff) << 0; |
183 | 02645926 | balrog | } else {
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184 | 02645926 | balrog | ret |= ((s->fifo >> 8) & 0xff) << 8; |
185 | 02645926 | balrog | ret |= ((s->fifo >> 0) & 0xff) << 0; |
186 | 02645926 | balrog | } |
187 | 02645926 | balrog | if (s->rxlen == 1) { |
188 | 02645926 | balrog | s->stat |= 1 << 15; /* SBD */ |
189 | 02645926 | balrog | s->rxlen = 0;
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190 | 02645926 | balrog | } else if (s->rxlen > 1) { |
191 | 02645926 | balrog | if (s->rxlen > 2) |
192 | 02645926 | balrog | s->fifo >>= 16;
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193 | 02645926 | balrog | s->rxlen -= 2;
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194 | 3ffd710e | Blue Swirl | } else {
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195 | 3ffd710e | Blue Swirl | /* XXX: remote access (qualifier) error - what's that? */
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196 | 3ffd710e | Blue Swirl | } |
197 | 02645926 | balrog | if (!s->rxlen) {
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198 | 29885477 | balrog | s->stat &= ~(1 << 3); /* RRDY */ |
199 | 02645926 | balrog | if (((s->control >> 10) & 1) && /* MST */ |
200 | 02645926 | balrog | ((~s->control >> 9) & 1)) { /* TRX */ |
201 | 02645926 | balrog | s->stat |= 1 << 2; /* ARDY */ |
202 | 02645926 | balrog | s->control &= ~(1 << 10); /* MST */ |
203 | 02645926 | balrog | } |
204 | 02645926 | balrog | } |
205 | 02645926 | balrog | s->stat &= ~(1 << 11); /* ROVR */ |
206 | 02645926 | balrog | omap_i2c_fifo_run(s); |
207 | 02645926 | balrog | omap_i2c_interrupts_update(s); |
208 | 02645926 | balrog | return ret;
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209 | 02645926 | balrog | |
210 | 29885477 | balrog | case 0x20: /* I2C_SYSC */ |
211 | 29885477 | balrog | return 0; |
212 | 29885477 | balrog | |
213 | 02645926 | balrog | case 0x24: /* I2C_CON */ |
214 | 02645926 | balrog | return s->control;
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215 | 02645926 | balrog | |
216 | 02645926 | balrog | case 0x28: /* I2C_OA */ |
217 | 02645926 | balrog | return s->addr[0]; |
218 | 02645926 | balrog | |
219 | 02645926 | balrog | case 0x2c: /* I2C_SA */ |
220 | 02645926 | balrog | return s->addr[1]; |
221 | 02645926 | balrog | |
222 | 02645926 | balrog | case 0x30: /* I2C_PSC */ |
223 | 02645926 | balrog | return s->divider;
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224 | 02645926 | balrog | |
225 | 02645926 | balrog | case 0x34: /* I2C_SCLL */ |
226 | 02645926 | balrog | return s->times[0]; |
227 | 02645926 | balrog | |
228 | 02645926 | balrog | case 0x38: /* I2C_SCLH */ |
229 | 02645926 | balrog | return s->times[1]; |
230 | 02645926 | balrog | |
231 | 02645926 | balrog | case 0x3c: /* I2C_SYSTEST */ |
232 | 02645926 | balrog | if (s->test & (1 << 15)) { /* ST_EN */ |
233 | 02645926 | balrog | s->test ^= 0xa;
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234 | 02645926 | balrog | return s->test;
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235 | 02645926 | balrog | } else
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236 | 02645926 | balrog | return s->test & ~0x300f; |
237 | 02645926 | balrog | } |
238 | 02645926 | balrog | |
239 | 02645926 | balrog | OMAP_BAD_REG(addr); |
240 | 02645926 | balrog | return 0; |
241 | 02645926 | balrog | } |
242 | 02645926 | balrog | |
243 | c227f099 | Anthony Liguori | static void omap_i2c_write(void *opaque, target_phys_addr_t addr, |
244 | 02645926 | balrog | uint32_t value) |
245 | 02645926 | balrog | { |
246 | 02645926 | balrog | struct omap_i2c_s *s = (struct omap_i2c_s *) opaque; |
247 | cf965d24 | balrog | int offset = addr & OMAP_MPUI_REG_MASK;
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248 | 02645926 | balrog | int nack;
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249 | 02645926 | balrog | |
250 | 02645926 | balrog | switch (offset) {
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251 | 02645926 | balrog | case 0x00: /* I2C_REV */ |
252 | 02645926 | balrog | case 0x0c: /* I2C_IV */ |
253 | 29885477 | balrog | case 0x10: /* I2C_SYSS */ |
254 | 29885477 | balrog | OMAP_RO_REG(addr); |
255 | 02645926 | balrog | return;
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256 | 02645926 | balrog | |
257 | 02645926 | balrog | case 0x04: /* I2C_IE */ |
258 | 29885477 | balrog | s->mask = value & (s->revision < OMAP2_GC_REV ? 0x1f : 0x3f); |
259 | 29885477 | balrog | break;
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260 | 29885477 | balrog | |
261 | 29885477 | balrog | case 0x08: /* I2C_STAT */ |
262 | 29885477 | balrog | if (s->revision < OMAP2_INTR_REV) {
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263 | 29885477 | balrog | OMAP_RO_REG(addr); |
264 | 29885477 | balrog | return;
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265 | 29885477 | balrog | } |
266 | 29885477 | balrog | |
267 | 827df9f3 | balrog | /* RRDY and XRDY are reset by hardware. (in all versions???) */
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268 | 827df9f3 | balrog | s->stat &= ~(value & 0x27);
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269 | 29885477 | balrog | omap_i2c_interrupts_update(s); |
270 | 02645926 | balrog | break;
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271 | 02645926 | balrog | |
272 | 02645926 | balrog | case 0x14: /* I2C_BUF */ |
273 | 02645926 | balrog | s->dma = value & 0x8080;
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274 | 02645926 | balrog | if (value & (1 << 15)) /* RDMA_EN */ |
275 | 02645926 | balrog | s->mask &= ~(1 << 3); /* RRDY_IE */ |
276 | 02645926 | balrog | if (value & (1 << 7)) /* XDMA_EN */ |
277 | 02645926 | balrog | s->mask &= ~(1 << 4); /* XRDY_IE */ |
278 | 02645926 | balrog | break;
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279 | 02645926 | balrog | |
280 | 02645926 | balrog | case 0x18: /* I2C_CNT */ |
281 | 02645926 | balrog | s->count = value; /* DCOUNT */
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282 | 02645926 | balrog | break;
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283 | 02645926 | balrog | |
284 | 02645926 | balrog | case 0x1c: /* I2C_DATA */ |
285 | 02645926 | balrog | if (s->txlen > 2) { |
286 | 02645926 | balrog | /* XXX: remote access (qualifier) error - what's that? */
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287 | 02645926 | balrog | break;
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288 | 02645926 | balrog | } |
289 | 02645926 | balrog | s->fifo <<= 16;
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290 | 02645926 | balrog | s->txlen += 2;
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291 | 02645926 | balrog | if (s->control & (1 << 14)) { /* BE */ |
292 | 02645926 | balrog | s->fifo |= ((value >> 8) & 0xff) << 8; |
293 | 02645926 | balrog | s->fifo |= ((value >> 0) & 0xff) << 0; |
294 | 02645926 | balrog | } else {
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295 | 02645926 | balrog | s->fifo |= ((value >> 0) & 0xff) << 8; |
296 | 02645926 | balrog | s->fifo |= ((value >> 8) & 0xff) << 0; |
297 | 02645926 | balrog | } |
298 | 02645926 | balrog | s->stat &= ~(1 << 10); /* XUDF */ |
299 | 02645926 | balrog | if (s->txlen > 2) |
300 | 02645926 | balrog | s->stat &= ~(1 << 4); /* XRDY */ |
301 | 02645926 | balrog | omap_i2c_fifo_run(s); |
302 | 02645926 | balrog | omap_i2c_interrupts_update(s); |
303 | 02645926 | balrog | break;
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304 | 02645926 | balrog | |
305 | 29885477 | balrog | case 0x20: /* I2C_SYSC */ |
306 | 29885477 | balrog | if (s->revision < OMAP2_INTR_REV) {
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307 | 29885477 | balrog | OMAP_BAD_REG(addr); |
308 | 29885477 | balrog | return;
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309 | 29885477 | balrog | } |
310 | 29885477 | balrog | |
311 | 29885477 | balrog | if (value & 2) |
312 | 29885477 | balrog | omap_i2c_reset(s); |
313 | 29885477 | balrog | break;
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314 | 29885477 | balrog | |
315 | 02645926 | balrog | case 0x24: /* I2C_CON */ |
316 | 29885477 | balrog | s->control = value & 0xcf87;
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317 | 02645926 | balrog | if (~value & (1 << 15)) { /* I2C_EN */ |
318 | 29885477 | balrog | if (s->revision < OMAP2_INTR_REV)
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319 | 29885477 | balrog | omap_i2c_reset(s); |
320 | 02645926 | balrog | break;
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321 | 02645926 | balrog | } |
322 | 29885477 | balrog | if ((value & (1 << 15)) && !(value & (1 << 10))) { /* MST */ |
323 | 827df9f3 | balrog | fprintf(stderr, "%s: I^2C slave mode not supported\n",
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324 | 827df9f3 | balrog | __FUNCTION__); |
325 | 02645926 | balrog | break;
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326 | 02645926 | balrog | } |
327 | 29885477 | balrog | if ((value & (1 << 15)) && value & (1 << 8)) { /* XA */ |
328 | 827df9f3 | balrog | fprintf(stderr, "%s: 10-bit addressing mode not supported\n",
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329 | 827df9f3 | balrog | __FUNCTION__); |
330 | 02645926 | balrog | break;
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331 | 02645926 | balrog | } |
332 | 29885477 | balrog | if ((value & (1 << 15)) && value & (1 << 0)) { /* STT */ |
333 | 02645926 | balrog | nack = !!i2c_start_transfer(s->bus, s->addr[1], /* SA */ |
334 | 02645926 | balrog | (~value >> 9) & 1); /* TRX */ |
335 | 02645926 | balrog | s->stat |= nack << 1; /* NACK */ |
336 | 02645926 | balrog | s->control &= ~(1 << 0); /* STT */ |
337 | 51fec3cc | balrog | s->fifo = 0;
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338 | 02645926 | balrog | if (nack)
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339 | 02645926 | balrog | s->control &= ~(1 << 1); /* STP */ |
340 | 29885477 | balrog | else {
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341 | 29885477 | balrog | s->count_cur = s->count; |
342 | 02645926 | balrog | omap_i2c_fifo_run(s); |
343 | 29885477 | balrog | } |
344 | 02645926 | balrog | omap_i2c_interrupts_update(s); |
345 | 02645926 | balrog | } |
346 | 02645926 | balrog | break;
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347 | 02645926 | balrog | |
348 | 02645926 | balrog | case 0x28: /* I2C_OA */ |
349 | 02645926 | balrog | s->addr[0] = value & 0x3ff; |
350 | 02645926 | balrog | break;
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351 | 02645926 | balrog | |
352 | 02645926 | balrog | case 0x2c: /* I2C_SA */ |
353 | 02645926 | balrog | s->addr[1] = value & 0x3ff; |
354 | 02645926 | balrog | break;
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355 | 02645926 | balrog | |
356 | 02645926 | balrog | case 0x30: /* I2C_PSC */ |
357 | 02645926 | balrog | s->divider = value; |
358 | 02645926 | balrog | break;
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359 | 02645926 | balrog | |
360 | 02645926 | balrog | case 0x34: /* I2C_SCLL */ |
361 | 02645926 | balrog | s->times[0] = value;
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362 | 02645926 | balrog | break;
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363 | 02645926 | balrog | |
364 | 02645926 | balrog | case 0x38: /* I2C_SCLH */ |
365 | 02645926 | balrog | s->times[1] = value;
|
366 | 02645926 | balrog | break;
|
367 | 02645926 | balrog | |
368 | 02645926 | balrog | case 0x3c: /* I2C_SYSTEST */ |
369 | 29885477 | balrog | s->test = value & 0xf80f;
|
370 | 29885477 | balrog | if (value & (1 << 11)) /* SBB */ |
371 | 29885477 | balrog | if (s->revision >= OMAP2_INTR_REV) {
|
372 | 29885477 | balrog | s->stat |= 0x3f;
|
373 | 29885477 | balrog | omap_i2c_interrupts_update(s); |
374 | 29885477 | balrog | } |
375 | 02645926 | balrog | if (value & (1 << 15)) /* ST_EN */ |
376 | 827df9f3 | balrog | fprintf(stderr, "%s: System Test not supported\n", __FUNCTION__);
|
377 | 02645926 | balrog | break;
|
378 | 02645926 | balrog | |
379 | 02645926 | balrog | default:
|
380 | 02645926 | balrog | OMAP_BAD_REG(addr); |
381 | 02645926 | balrog | return;
|
382 | 02645926 | balrog | } |
383 | 02645926 | balrog | } |
384 | 02645926 | balrog | |
385 | c227f099 | Anthony Liguori | static void omap_i2c_writeb(void *opaque, target_phys_addr_t addr, |
386 | 29885477 | balrog | uint32_t value) |
387 | 29885477 | balrog | { |
388 | 29885477 | balrog | struct omap_i2c_s *s = (struct omap_i2c_s *) opaque; |
389 | 29885477 | balrog | int offset = addr & OMAP_MPUI_REG_MASK;
|
390 | 29885477 | balrog | |
391 | 29885477 | balrog | switch (offset) {
|
392 | 29885477 | balrog | case 0x1c: /* I2C_DATA */ |
393 | 29885477 | balrog | if (s->txlen > 2) { |
394 | 29885477 | balrog | /* XXX: remote access (qualifier) error - what's that? */
|
395 | 29885477 | balrog | break;
|
396 | 29885477 | balrog | } |
397 | 29885477 | balrog | s->fifo <<= 8;
|
398 | 29885477 | balrog | s->txlen += 1;
|
399 | 29885477 | balrog | s->fifo |= value & 0xff;
|
400 | 29885477 | balrog | s->stat &= ~(1 << 10); /* XUDF */ |
401 | 29885477 | balrog | if (s->txlen > 2) |
402 | 29885477 | balrog | s->stat &= ~(1 << 4); /* XRDY */ |
403 | 29885477 | balrog | omap_i2c_fifo_run(s); |
404 | 29885477 | balrog | omap_i2c_interrupts_update(s); |
405 | 29885477 | balrog | break;
|
406 | 29885477 | balrog | |
407 | 29885477 | balrog | default:
|
408 | 29885477 | balrog | OMAP_BAD_REG(addr); |
409 | 29885477 | balrog | return;
|
410 | 29885477 | balrog | } |
411 | 29885477 | balrog | } |
412 | 29885477 | balrog | |
413 | 74878139 | Benoît Canet | static const MemoryRegionOps omap_i2c_ops = { |
414 | 74878139 | Benoît Canet | .old_mmio = { |
415 | 74878139 | Benoît Canet | .read = { |
416 | 74878139 | Benoît Canet | omap_badwidth_read16, |
417 | 74878139 | Benoît Canet | omap_i2c_read, |
418 | 74878139 | Benoît Canet | omap_badwidth_read16, |
419 | 74878139 | Benoît Canet | }, |
420 | 74878139 | Benoît Canet | .write = { |
421 | 74878139 | Benoît Canet | omap_i2c_writeb, /* Only the last fifo write can be 8 bit. */
|
422 | 74878139 | Benoît Canet | omap_i2c_write, |
423 | 74878139 | Benoît Canet | omap_badwidth_write16, |
424 | 74878139 | Benoît Canet | }, |
425 | 74878139 | Benoît Canet | }, |
426 | 74878139 | Benoît Canet | .endianness = DEVICE_NATIVE_ENDIAN, |
427 | 02645926 | balrog | }; |
428 | 02645926 | balrog | |
429 | 74878139 | Benoît Canet | struct omap_i2c_s *omap_i2c_init(MemoryRegion *sysmem,
|
430 | 74878139 | Benoît Canet | target_phys_addr_t base, |
431 | 74878139 | Benoît Canet | qemu_irq irq, |
432 | 74878139 | Benoît Canet | qemu_irq *dma, |
433 | 74878139 | Benoît Canet | omap_clk clk) |
434 | 02645926 | balrog | { |
435 | 02645926 | balrog | struct omap_i2c_s *s = (struct omap_i2c_s *) |
436 | 7267c094 | Anthony Liguori | g_malloc0(sizeof(struct omap_i2c_s)); |
437 | 02645926 | balrog | |
438 | 29885477 | balrog | /* TODO: set a value greater or equal to real hardware */
|
439 | 29885477 | balrog | s->revision = 0x11;
|
440 | 02645926 | balrog | s->irq = irq; |
441 | 02645926 | balrog | s->drq[0] = dma[0]; |
442 | 02645926 | balrog | s->drq[1] = dma[1]; |
443 | 02e2da45 | Paul Brook | s->bus = i2c_init_bus(NULL, "i2c"); |
444 | 02645926 | balrog | omap_i2c_reset(s); |
445 | 02645926 | balrog | |
446 | 74878139 | Benoît Canet | memory_region_init_io(&s->iomem, &omap_i2c_ops, s, "omap.i2c", 0x800); |
447 | 74878139 | Benoît Canet | memory_region_add_subregion(sysmem, base, &s->iomem); |
448 | 02645926 | balrog | |
449 | 02645926 | balrog | return s;
|
450 | 02645926 | balrog | } |
451 | 02645926 | balrog | |
452 | 29885477 | balrog | struct omap_i2c_s *omap2_i2c_init(struct omap_target_agent_s *ta, |
453 | 29885477 | balrog | qemu_irq irq, qemu_irq *dma, omap_clk fclk, omap_clk iclk) |
454 | 29885477 | balrog | { |
455 | 29885477 | balrog | struct omap_i2c_s *s = (struct omap_i2c_s *) |
456 | 7267c094 | Anthony Liguori | g_malloc0(sizeof(struct omap_i2c_s)); |
457 | 29885477 | balrog | |
458 | 29885477 | balrog | s->revision = 0x34;
|
459 | 29885477 | balrog | s->irq = irq; |
460 | 29885477 | balrog | s->drq[0] = dma[0]; |
461 | 29885477 | balrog | s->drq[1] = dma[1]; |
462 | 02e2da45 | Paul Brook | s->bus = i2c_init_bus(NULL, "i2c"); |
463 | 29885477 | balrog | omap_i2c_reset(s); |
464 | 29885477 | balrog | |
465 | 74878139 | Benoît Canet | memory_region_init_io(&s->iomem, &omap_i2c_ops, s, "omap2.i2c",
|
466 | 74878139 | Benoît Canet | omap_l4_region_size(ta, 0));
|
467 | f44336c5 | Avi Kivity | omap_l4_attach(ta, 0, &s->iomem);
|
468 | 29885477 | balrog | |
469 | 29885477 | balrog | return s;
|
470 | 29885477 | balrog | } |
471 | 29885477 | balrog | |
472 | 02645926 | balrog | i2c_bus *omap_i2c_bus(struct omap_i2c_s *s)
|
473 | 02645926 | balrog | { |
474 | 02645926 | balrog | return s->bus;
|
475 | 02645926 | balrog | } |