Revision 82600641

b/hw/openpic.c
242 242
    int max_irq;
243 243
    int irq_ipi0;
244 244
    int irq_tim0;
245
    int need_swap;
246 245
    void (*reset) (void *);
247 246
    void (*irq_raise) (struct openpic_t *, int, IRQ_src_t *);
248 247
} openpic_t;
249 248

  
250
static inline uint32_t openpic_swap32(openpic_t *opp, uint32_t val)
251
{
252
    if (opp->need_swap)
253
        return bswap32(val);
254

  
255
    return val;
256
}
257

  
258 249
static inline void IRQ_setbit (IRQ_queue_t *q, int n_IRQ)
259 250
{
260 251
    set_bit(q->queue, n_IRQ);
......
599 590
    DPRINTF("%s: addr " TARGET_FMT_plx " <= %08x\n", __func__, addr, val);
600 591
    if (addr & 0xF)
601 592
        return;
602
    val = openpic_swap32(opp, val);
603 593
    addr &= 0xFF;
604 594
    switch (addr) {
605 595
    case 0x00: /* FREP */
......
693 683
        break;
694 684
    }
695 685
    DPRINTF("%s: => %08x\n", __func__, retval);
696
    retval = openpic_swap32(opp, retval);
697 686

  
698 687
    return retval;
699 688
}
......
706 695
    DPRINTF("%s: addr %08x <= %08x\n", __func__, addr, val);
707 696
    if (addr & 0xF)
708 697
        return;
709
    val = openpic_swap32(opp, val);
710 698
    addr -= 0x1100;
711 699
    addr &= 0xFFFF;
712 700
    idx = (addr & 0xFFF0) >> 6;
......
759 747
        break;
760 748
    }
761 749
    DPRINTF("%s: => %08x\n", __func__, retval);
762
    retval = openpic_swap32(opp, retval);
763 750

  
764 751
    return retval;
765 752
}
......
772 759
    DPRINTF("%s: addr %08x <= %08x\n", __func__, addr, val);
773 760
    if (addr & 0xF)
774 761
        return;
775
    val = openpic_swap32(opp, val);
776 762
    addr = addr & 0xFFF0;
777 763
    idx = addr >> 5;
778 764
    if (addr & 0x10) {
......
804 790
        retval = read_IRQreg(opp, idx, IRQ_IPVP);
805 791
    }
806 792
    DPRINTF("%s: => %08x\n", __func__, retval);
807
    retval = openpic_swap32(opp, retval);
808 793

  
809 794
    return retval;
810 795
}
......
819 804
    DPRINTF("%s: addr " TARGET_FMT_plx " <= %08x\n", __func__, addr, val);
820 805
    if (addr & 0xF)
821 806
        return;
822
    val = openpic_swap32(opp, val);
823 807
    addr &= 0x1FFF0;
824 808
    idx = addr / 0x1000;
825 809
    dst = &opp->dst[idx];
......
937 921
        break;
938 922
    }
939 923
    DPRINTF("%s: => %08x\n", __func__, retval);
940
    retval = openpic_swap32(opp, retval);
941 924

  
942 925
    return retval;
943 926
}
......
1204 1187
        opp = qemu_mallocz(sizeof(openpic_t));
1205 1188
    }
1206 1189
    opp->mem_index = cpu_register_io_memory(openpic_read, openpic_write, opp,
1207
                                            DEVICE_NATIVE_ENDIAN);
1190
                                            DEVICE_LITTLE_ENDIAN);
1208 1191

  
1209 1192
    //    isu_base &= 0xFFFC0000;
1210 1193
    opp->nb_cpus = nb_cpus;
......
1232 1215
    for (i = 0; i < nb_cpus; i++)
1233 1216
        opp->dst[i].irqs = irqs[i];
1234 1217
    opp->irq_out = irq_out;
1235
    opp->need_swap = 1;
1236 1218

  
1237 1219
    register_savevm(&opp->pci_dev.qdev, "openpic", 0, 2,
1238 1220
                    openpic_save, openpic_load, opp);
......
1673 1655
        int mem_index;
1674 1656

  
1675 1657
        mem_index = cpu_register_io_memory(list[i].read, list[i].write, mpp,
1676
                                           DEVICE_NATIVE_ENDIAN);
1658
                                           DEVICE_BIG_ENDIAN);
1677 1659
        if (mem_index < 0) {
1678 1660
            goto free;
1679 1661
        }
......
1689 1671
    for (i = 0; i < nb_cpus; i++)
1690 1672
        mpp->dst[i].irqs = irqs[i];
1691 1673
    mpp->irq_out = irq_out;
1692
    mpp->need_swap = 0;    /* MPIC has the same endian as target */
1693 1674

  
1694 1675
    mpp->irq_raise = mpic_irq_raise;
1695 1676
    mpp->reset = mpic_reset;

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