Revision 827df9f3 hw/omap_dma.c
b/hw/omap_dma.c | ||
---|---|---|
28 | 28 |
/* transfer data */ |
29 | 29 |
int burst[2]; |
30 | 30 |
int pack[2]; |
31 |
int endian[2]; |
|
32 |
int endian_lock[2]; |
|
33 |
int translate[2]; |
|
31 | 34 |
enum omap_dma_port port[2]; |
32 | 35 |
target_phys_addr_t addr[2]; |
33 | 36 |
omap_dma_addressing_t mode[2]; |
34 |
uint16_t elements;
|
|
37 |
uint32_t elements;
|
|
35 | 38 |
uint16_t frames; |
36 |
int16_t frame_index[2];
|
|
39 |
int32_t frame_index[2];
|
|
37 | 40 |
int16_t element_index[2]; |
38 | 41 |
int data_type; |
39 | 42 |
|
... | ... | |
41 | 44 |
int transparent_copy; |
42 | 45 |
int constant_fill; |
43 | 46 |
uint32_t color; |
47 |
int prefetch; |
|
44 | 48 |
|
45 | 49 |
/* auto init and linked channel data */ |
46 | 50 |
int end_prog; |
... | ... | |
52 | 56 |
/* interruption data */ |
53 | 57 |
int interrupts; |
54 | 58 |
int status; |
59 |
int cstatus; |
|
55 | 60 |
|
56 | 61 |
/* state data */ |
57 | 62 |
int active; |
58 | 63 |
int enable; |
59 | 64 |
int sync; |
65 |
int src_sync; |
|
60 | 66 |
int pending_request; |
61 | 67 |
int waiting_end_prog; |
62 | 68 |
uint16_t cpc; |
... | ... | |
75 | 81 |
target_phys_addr_t src, dest; |
76 | 82 |
int frame; |
77 | 83 |
int element; |
84 |
int pck_element; |
|
78 | 85 |
int frame_delta[2]; |
79 | 86 |
int elem_delta[2]; |
80 | 87 |
int frames; |
81 | 88 |
int elements; |
89 |
int pck_elements; |
|
82 | 90 |
} active_set; |
83 | 91 |
|
84 | 92 |
/* unused parameters */ |
93 |
int write_mode; |
|
85 | 94 |
int priority; |
86 | 95 |
int interleave_disabled; |
87 | 96 |
int type; |
97 |
int suspend; |
|
98 |
int buf_disable; |
|
88 | 99 |
}; |
89 | 100 |
|
90 | 101 |
struct omap_dma_s { |
... | ... | |
93 | 104 |
target_phys_addr_t base; |
94 | 105 |
omap_clk clk; |
95 | 106 |
int64_t delay; |
96 |
uint32_t drq; |
|
107 |
uint64_t drq; |
|
108 |
qemu_irq irq[4]; |
|
109 |
void (*intr_update)(struct omap_dma_s *s); |
|
97 | 110 |
enum omap_dma_model model; |
98 | 111 |
int omap_3_1_mapping_disabled; |
99 | 112 |
|
100 |
uint16_t gcr; |
|
113 |
uint32_t gcr; |
|
114 |
uint32_t ocp; |
|
115 |
uint32_t caps[5]; |
|
116 |
uint32_t irqen[4]; |
|
117 |
uint32_t irqstat[4]; |
|
101 | 118 |
int run_count; |
102 | 119 |
|
103 | 120 |
int chans; |
104 |
struct omap_dma_channel_s ch[16];
|
|
121 |
struct omap_dma_channel_s ch[32];
|
|
105 | 122 |
struct omap_dma_lcd_channel_s lcd_ch; |
106 | 123 |
}; |
107 | 124 |
|
... | ... | |
113 | 130 |
#define LAST_FRAME_INTR (1 << 4) |
114 | 131 |
#define END_BLOCK_INTR (1 << 5) |
115 | 132 |
#define SYNC (1 << 6) |
133 |
#define END_PKT_INTR (1 << 7) |
|
134 |
#define TRANS_ERR_INTR (1 << 8) |
|
135 |
#define MISALIGN_INTR (1 << 11) |
|
116 | 136 |
|
117 |
static void omap_dma_interrupts_update(struct omap_dma_s *s) |
|
137 |
static inline void omap_dma_interrupts_update(struct omap_dma_s *s)
|
|
118 | 138 |
{ |
119 |
struct omap_dma_channel_s *ch = s->ch; |
|
120 |
int i; |
|
121 |
|
|
122 |
if (s->omap_3_1_mapping_disabled) { |
|
123 |
for (i = 0; i < s->chans; i ++, ch ++) |
|
124 |
if (ch->status) |
|
125 |
qemu_irq_raise(ch->irq); |
|
126 |
} else { |
|
127 |
/* First three interrupts are shared between two channels each. */ |
|
128 |
for (i = 0; i < 6; i ++, ch ++) { |
|
129 |
if (ch->status || (ch->sibling && ch->sibling->status)) |
|
130 |
qemu_irq_raise(ch->irq); |
|
131 |
} |
|
132 |
} |
|
139 |
return s->intr_update(s); |
|
133 | 140 |
} |
134 | 141 |
|
135 | 142 |
static void omap_dma_channel_load(struct omap_dma_s *s, |
... | ... | |
148 | 155 |
a->dest = ch->addr[1]; |
149 | 156 |
a->frames = ch->frames; |
150 | 157 |
a->elements = ch->elements; |
158 |
a->pck_elements = ch->frame_index[!ch->src_sync]; |
|
151 | 159 |
a->frame = 0; |
152 | 160 |
a->element = 0; |
161 |
a->pck_element = 0; |
|
153 | 162 |
|
154 | 163 |
if (unlikely(!ch->elements || !ch->frames)) { |
155 | 164 |
printf("%s: bad DMA request\n", __FUNCTION__); |
... | ... | |
202 | 211 |
/* Update cpc */ |
203 | 212 |
ch->cpc = ch->active_set.dest & 0xffff; |
204 | 213 |
|
205 |
if (ch->pending_request && !ch->waiting_end_prog) { |
|
214 |
if (ch->pending_request && !ch->waiting_end_prog && ch->enable) {
|
|
206 | 215 |
/* Don't deactivate the channel */ |
207 | 216 |
ch->pending_request = 0; |
208 |
if (ch->enable) |
|
209 |
return; |
|
217 |
return; |
|
210 | 218 |
} |
211 | 219 |
|
212 | 220 |
/* Don't deactive the channel if it is synchronized and the DMA request is |
213 | 221 |
active */ |
214 |
if (ch->sync && (s->drq & (1 << ch->sync)) && ch->enable)
|
|
222 |
if (ch->sync && ch->enable && (s->drq & (1 << ch->sync)))
|
|
215 | 223 |
return; |
216 | 224 |
|
217 | 225 |
if (ch->active) { |
... | ... | |
231 | 239 |
ch->enable = 1; |
232 | 240 |
ch->waiting_end_prog = 0; |
233 | 241 |
omap_dma_channel_load(s, ch); |
242 |
/* TODO: theoretically if ch->sync && ch->prefetch && |
|
243 |
* !s->drq[ch->sync], we should also activate and fetch from source |
|
244 |
* and then stall until signalled. */ |
|
234 | 245 |
if ((!ch->sync) || (s->drq & (1 << ch->sync))) |
235 | 246 |
omap_dma_activate_channel(s, ch); |
236 | 247 |
} |
... | ... | |
259 | 270 |
} |
260 | 271 |
} |
261 | 272 |
|
273 |
static void omap_dma_interrupts_3_1_update(struct omap_dma_s *s) |
|
274 |
{ |
|
275 |
struct omap_dma_channel_s *ch = s->ch; |
|
276 |
|
|
277 |
/* First three interrupts are shared between two channels each. */ |
|
278 |
if (ch[0].status | ch[6].status) |
|
279 |
qemu_irq_raise(ch[0].irq); |
|
280 |
if (ch[1].status | ch[7].status) |
|
281 |
qemu_irq_raise(ch[1].irq); |
|
282 |
if (ch[2].status | ch[8].status) |
|
283 |
qemu_irq_raise(ch[2].irq); |
|
284 |
if (ch[3].status) |
|
285 |
qemu_irq_raise(ch[3].irq); |
|
286 |
if (ch[4].status) |
|
287 |
qemu_irq_raise(ch[4].irq); |
|
288 |
if (ch[5].status) |
|
289 |
qemu_irq_raise(ch[5].irq); |
|
290 |
} |
|
291 |
|
|
292 |
static void omap_dma_interrupts_3_2_update(struct omap_dma_s *s) |
|
293 |
{ |
|
294 |
struct omap_dma_channel_s *ch = s->ch; |
|
295 |
int i; |
|
296 |
|
|
297 |
for (i = s->chans; i; ch ++, i --) |
|
298 |
if (ch->status) |
|
299 |
qemu_irq_raise(ch->irq); |
|
300 |
} |
|
301 |
|
|
262 | 302 |
static void omap_dma_enable_3_1_mapping(struct omap_dma_s *s) |
263 | 303 |
{ |
264 | 304 |
s->omap_3_1_mapping_disabled = 0; |
265 | 305 |
s->chans = 9; |
306 |
s->intr_update = omap_dma_interrupts_3_1_update; |
|
266 | 307 |
} |
267 | 308 |
|
268 | 309 |
static void omap_dma_disable_3_1_mapping(struct omap_dma_s *s) |
269 | 310 |
{ |
270 | 311 |
s->omap_3_1_mapping_disabled = 1; |
271 | 312 |
s->chans = 16; |
313 |
s->intr_update = omap_dma_interrupts_3_2_update; |
|
272 | 314 |
} |
273 | 315 |
|
274 | 316 |
static void omap_dma_process_request(struct omap_dma_s *s, int request) |
... | ... | |
358 | 400 |
if (ch->interrupts & HALF_FRAME_INTR) |
359 | 401 |
ch->status |= HALF_FRAME_INTR; |
360 | 402 |
|
403 |
if (ch->fs && ch->bs) { |
|
404 |
a->pck_element ++; |
|
405 |
/* Check if a full packet has beed transferred. */ |
|
406 |
if (a->pck_element == a->pck_elements) { |
|
407 |
a->pck_element = 0; |
|
408 |
|
|
409 |
/* Set the END_PKT interrupt */ |
|
410 |
if ((ch->interrupts & END_PKT_INTR) && !ch->src_sync) |
|
411 |
ch->status |= END_PKT_INTR; |
|
412 |
|
|
413 |
/* If the channel is packet-synchronized, deactivate it */ |
|
414 |
if (ch->sync) |
|
415 |
omap_dma_deactivate_channel(s, ch); |
|
416 |
} |
|
417 |
} |
|
418 |
|
|
361 | 419 |
if (a->element == a->elements) { |
362 | 420 |
/* End of Frame */ |
363 | 421 |
a->element = 0; |
... | ... | |
366 | 424 |
a->frame ++; |
367 | 425 |
|
368 | 426 |
/* If the channel is frame synchronized, deactivate it */ |
369 |
if (ch->sync && ch->fs) |
|
427 |
if (ch->sync && ch->fs && !ch->bs)
|
|
370 | 428 |
omap_dma_deactivate_channel(s, ch); |
371 | 429 |
|
372 | 430 |
/* If the channel is async, update cpc */ |
... | ... | |
414 | 472 |
int i; |
415 | 473 |
|
416 | 474 |
qemu_del_timer(s->tm); |
417 |
s->gcr = 0x0004; |
|
475 |
if (s->model < omap_dma_4) |
|
476 |
s->gcr = 0x0004; |
|
477 |
else |
|
478 |
s->gcr = 0x00010010; |
|
479 |
s->ocp = 0x00000000; |
|
480 |
memset(&s->irqstat, 0, sizeof(s->irqstat)); |
|
481 |
memset(&s->irqen, 0, sizeof(s->irqen)); |
|
418 | 482 |
s->drq = 0x00000000; |
419 | 483 |
s->run_count = 0; |
420 | 484 |
s->lcd_ch.src = emiff; |
421 | 485 |
s->lcd_ch.condition = 0; |
422 | 486 |
s->lcd_ch.interrupts = 0; |
423 | 487 |
s->lcd_ch.dual = 0; |
424 |
omap_dma_enable_3_1_mapping(s); |
|
488 |
if (s->model < omap_dma_4) |
|
489 |
omap_dma_enable_3_1_mapping(s); |
|
425 | 490 |
for (i = 0; i < s->chans; i ++) { |
491 |
s->ch[i].suspend = 0; |
|
492 |
s->ch[i].prefetch = 0; |
|
493 |
s->ch[i].buf_disable = 0; |
|
494 |
s->ch[i].src_sync = 0; |
|
426 | 495 |
memset(&s->ch[i].burst, 0, sizeof(s->ch[i].burst)); |
427 | 496 |
memset(&s->ch[i].port, 0, sizeof(s->ch[i].port)); |
428 | 497 |
memset(&s->ch[i].mode, 0, sizeof(s->ch[i].mode)); |
429 |
memset(&s->ch[i].elements, 0, sizeof(s->ch[i].elements)); |
|
430 |
memset(&s->ch[i].frames, 0, sizeof(s->ch[i].frames)); |
|
431 | 498 |
memset(&s->ch[i].frame_index, 0, sizeof(s->ch[i].frame_index)); |
432 | 499 |
memset(&s->ch[i].element_index, 0, sizeof(s->ch[i].element_index)); |
433 |
memset(&s->ch[i].data_type, 0, sizeof(s->ch[i].data_type)); |
|
434 |
memset(&s->ch[i].transparent_copy, 0, |
|
435 |
sizeof(s->ch[i].transparent_copy)); |
|
436 |
memset(&s->ch[i].constant_fill, 0, sizeof(s->ch[i].constant_fill)); |
|
437 |
memset(&s->ch[i].color, 0, sizeof(s->ch[i].color)); |
|
438 |
memset(&s->ch[i].end_prog, 0, sizeof(s->ch[i].end_prog)); |
|
439 |
memset(&s->ch[i].repeat, 0, sizeof(s->ch[i].repeat)); |
|
440 |
memset(&s->ch[i].auto_init, 0, sizeof(s->ch[i].auto_init)); |
|
441 |
memset(&s->ch[i].link_enabled, 0, sizeof(s->ch[i].link_enabled)); |
|
442 |
memset(&s->ch[i].link_next_ch, 0, sizeof(s->ch[i].link_next_ch)); |
|
443 |
s->ch[i].interrupts = 0x0003; |
|
444 |
memset(&s->ch[i].status, 0, sizeof(s->ch[i].status)); |
|
445 |
memset(&s->ch[i].active, 0, sizeof(s->ch[i].active)); |
|
446 |
memset(&s->ch[i].enable, 0, sizeof(s->ch[i].enable)); |
|
447 |
memset(&s->ch[i].sync, 0, sizeof(s->ch[i].sync)); |
|
448 |
memset(&s->ch[i].pending_request, 0, sizeof(s->ch[i].pending_request)); |
|
449 |
memset(&s->ch[i].waiting_end_prog, 0, |
|
450 |
sizeof(s->ch[i].waiting_end_prog)); |
|
451 |
memset(&s->ch[i].cpc, 0, sizeof(s->ch[i].cpc)); |
|
452 |
memset(&s->ch[i].fs, 0, sizeof(s->ch[i].fs)); |
|
453 |
memset(&s->ch[i].bs, 0, sizeof(s->ch[i].bs)); |
|
454 |
memset(&s->ch[i].omap_3_1_compatible_disable, 0, |
|
455 |
sizeof(s->ch[i].omap_3_1_compatible_disable)); |
|
500 |
memset(&s->ch[i].endian, 0, sizeof(s->ch[i].endian)); |
|
501 |
memset(&s->ch[i].endian_lock, 0, sizeof(s->ch[i].endian_lock)); |
|
502 |
memset(&s->ch[i].translate, 0, sizeof(s->ch[i].translate)); |
|
503 |
s->ch[i].write_mode = 0; |
|
504 |
s->ch[i].data_type = 0; |
|
505 |
s->ch[i].transparent_copy = 0; |
|
506 |
s->ch[i].constant_fill = 0; |
|
507 |
s->ch[i].color = 0x00000000; |
|
508 |
s->ch[i].end_prog = 0; |
|
509 |
s->ch[i].repeat = 0; |
|
510 |
s->ch[i].auto_init = 0; |
|
511 |
s->ch[i].link_enabled = 0; |
|
512 |
if (s->model < omap_dma_4) |
|
513 |
s->ch[i].interrupts = 0x0003; |
|
514 |
else |
|
515 |
s->ch[i].interrupts = 0x0000; |
|
516 |
s->ch[i].status = 0; |
|
517 |
s->ch[i].cstatus = 0; |
|
518 |
s->ch[i].active = 0; |
|
519 |
s->ch[i].enable = 0; |
|
520 |
s->ch[i].sync = 0; |
|
521 |
s->ch[i].pending_request = 0; |
|
522 |
s->ch[i].waiting_end_prog = 0; |
|
523 |
s->ch[i].cpc = 0x0000; |
|
524 |
s->ch[i].fs = 0; |
|
525 |
s->ch[i].bs = 0; |
|
526 |
s->ch[i].omap_3_1_compatible_disable = 0; |
|
456 | 527 |
memset(&s->ch[i].active_set, 0, sizeof(s->ch[i].active_set)); |
457 |
memset(&s->ch[i].priority, 0, sizeof(s->ch[i].priority)); |
|
458 |
memset(&s->ch[i].interleave_disabled, 0, |
|
459 |
sizeof(s->ch[i].interleave_disabled)); |
|
460 |
memset(&s->ch[i].type, 0, sizeof(s->ch[i].type)); |
|
528 |
s->ch[i].priority = 0; |
|
529 |
s->ch[i].interleave_disabled = 0; |
|
530 |
s->ch[i].type = 0; |
|
461 | 531 |
} |
462 | 532 |
} |
463 | 533 |
|
... | ... | |
476 | 546 |
break; |
477 | 547 |
|
478 | 548 |
case 0x02: /* SYS_DMA_CCR_CH0 */ |
479 |
if (s->model == omap_dma_3_1)
|
|
549 |
if (s->model <= omap_dma_3_1)
|
|
480 | 550 |
*value = 0 << 10; /* FIFO_FLUSH reads as 0 */ |
481 | 551 |
else |
482 | 552 |
*value = ch->omap_3_1_compatible_disable << 10; |
... | ... | |
596 | 666 |
ch->burst[0] = (value & 0x0180) >> 7; |
597 | 667 |
ch->pack[0] = (value & 0x0040) >> 6; |
598 | 668 |
ch->port[0] = (enum omap_dma_port) ((value & 0x003c) >> 2); |
599 |
ch->data_type = (1 << (value & 3));
|
|
600 |
if (ch->port[0] >= omap_dma_port_last) |
|
669 |
ch->data_type = 1 << (value & 3);
|
|
670 |
if (ch->port[0] >= __omap_dma_port_last)
|
|
601 | 671 |
printf("%s: invalid DMA port %i\n", __FUNCTION__, |
602 | 672 |
ch->port[0]); |
603 |
if (ch->port[1] >= omap_dma_port_last) |
|
673 |
if (ch->port[1] >= __omap_dma_port_last)
|
|
604 | 674 |
printf("%s: invalid DMA port %i\n", __FUNCTION__, |
605 | 675 |
ch->port[1]); |
606 | 676 |
if ((value & 3) == 3) |
... | ... | |
611 | 681 |
ch->mode[1] = (omap_dma_addressing_t) ((value & 0xc000) >> 14); |
612 | 682 |
ch->mode[0] = (omap_dma_addressing_t) ((value & 0x3000) >> 12); |
613 | 683 |
ch->end_prog = (value & 0x0800) >> 11; |
614 |
if (s->model > omap_dma_3_1)
|
|
684 |
if (s->model >= omap_dma_3_2)
|
|
615 | 685 |
ch->omap_3_1_compatible_disable = (value >> 10) & 0x1; |
616 | 686 |
ch->repeat = (value & 0x0200) >> 9; |
617 | 687 |
ch->auto_init = (value & 0x0100) >> 8; |
... | ... | |
630 | 700 |
break; |
631 | 701 |
|
632 | 702 |
case 0x04: /* SYS_DMA_CICR_CH0 */ |
633 |
ch->interrupts = value; |
|
703 |
ch->interrupts = value & 0x3f;
|
|
634 | 704 |
break; |
635 | 705 |
|
636 | 706 |
case 0x06: /* SYS_DMA_CSR_CH0 */ |
... | ... | |
696 | 766 |
break; |
697 | 767 |
|
698 | 768 |
case 0x24: /* DMA_CCR2 */ |
699 |
ch->bs = (value >> 2) & 0x1;
|
|
769 |
ch->bs = (value >> 2) & 0x1; |
|
700 | 770 |
ch->transparent_copy = (value >> 1) & 0x1; |
701 | 771 |
ch->constant_fill = value & 0x1; |
702 | 772 |
break; |
... | ... | |
1126 | 1196 |
break; |
1127 | 1197 |
|
1128 | 1198 |
case 0x44e: /* DMA_CAPS_0_U */ |
1129 |
*ret = (1 << 3) | /* Constant Fill Capacity */ |
|
1130 |
(1 << 2); /* Transparent BLT Capacity */ |
|
1199 |
*ret = (s->caps[0] >> 16) & 0xffff; |
|
1131 | 1200 |
break; |
1132 |
|
|
1133 | 1201 |
case 0x450: /* DMA_CAPS_0_L */ |
1134 |
case 0x452: /* DMA_CAPS_1_U */ |
|
1135 |
*ret = 0; |
|
1202 |
*ret = (s->caps[0] >> 0) & 0xffff; |
|
1136 | 1203 |
break; |
1137 | 1204 |
|
1205 |
case 0x452: /* DMA_CAPS_1_U */ |
|
1206 |
*ret = (s->caps[1] >> 16) & 0xffff; |
|
1207 |
break; |
|
1138 | 1208 |
case 0x454: /* DMA_CAPS_1_L */ |
1139 |
*ret = (1 << 1); /* 1-bit palletized capability */
|
|
1209 |
*ret = (s->caps[1] >> 0) & 0xffff;
|
|
1140 | 1210 |
break; |
1141 | 1211 |
|
1142 | 1212 |
case 0x456: /* DMA_CAPS_2 */ |
1143 |
*ret = (1 << 8) | /* SSDIC */ |
|
1144 |
(1 << 7) | /* DDIAC */ |
|
1145 |
(1 << 6) | /* DSIAC */ |
|
1146 |
(1 << 5) | /* DPIAC */ |
|
1147 |
(1 << 4) | /* DCAC */ |
|
1148 |
(1 << 3) | /* SDIAC */ |
|
1149 |
(1 << 2) | /* SSIAC */ |
|
1150 |
(1 << 1) | /* SPIAC */ |
|
1151 |
1; /* SCAC */ |
|
1213 |
*ret = s->caps[2]; |
|
1152 | 1214 |
break; |
1153 | 1215 |
|
1154 | 1216 |
case 0x458: /* DMA_CAPS_3 */ |
1155 |
*ret = (1 << 5) | /* CCC */ |
|
1156 |
(1 << 4) | /* IC */ |
|
1157 |
(1 << 3) | /* ARC */ |
|
1158 |
(1 << 2) | /* AEC */ |
|
1159 |
(1 << 1) | /* FSC */ |
|
1160 |
1; /* ESC */ |
|
1217 |
*ret = s->caps[3]; |
|
1161 | 1218 |
break; |
1162 | 1219 |
|
1163 | 1220 |
case 0x45a: /* DMA_CAPS_4 */ |
1164 |
*ret = (1 << 6) | /* SSC */ |
|
1165 |
(1 << 5) | /* BIC */ |
|
1166 |
(1 << 4) | /* LFIC */ |
|
1167 |
(1 << 3) | /* FIC */ |
|
1168 |
(1 << 2) | /* HFIC */ |
|
1169 |
(1 << 1) | /* EDIC */ |
|
1170 |
1; /* TOIC */ |
|
1221 |
*ret = s->caps[4]; |
|
1171 | 1222 |
break; |
1172 | 1223 |
|
1173 | 1224 |
case 0x460: /* DMA_PCh2_SR */ |
... | ... | |
1193 | 1244 |
|
1194 | 1245 |
switch (offset) { |
1195 | 1246 |
case 0x300 ... 0x3fe: |
1196 |
if (s->model == omap_dma_3_1 || !s->omap_3_1_mapping_disabled) {
|
|
1247 |
if (s->model <= omap_dma_3_1 || !s->omap_3_1_mapping_disabled) {
|
|
1197 | 1248 |
if (omap_dma_3_1_lcd_read(&s->lcd_ch, offset, &ret)) |
1198 | 1249 |
break; |
1199 | 1250 |
return ret; |
... | ... | |
1207 | 1258 |
return ret; |
1208 | 1259 |
|
1209 | 1260 |
case 0x404 ... 0x4fe: |
1210 |
if (s->model == omap_dma_3_1)
|
|
1261 |
if (s->model <= omap_dma_3_1)
|
|
1211 | 1262 |
break; |
1212 | 1263 |
/* Fall through. */ |
1213 | 1264 |
case 0x400: |
... | ... | |
1236 | 1287 |
|
1237 | 1288 |
switch (offset) { |
1238 | 1289 |
case 0x300 ... 0x3fe: |
1239 |
if (s->model == omap_dma_3_1 || !s->omap_3_1_mapping_disabled) {
|
|
1290 |
if (s->model <= omap_dma_3_1 || !s->omap_3_1_mapping_disabled) {
|
|
1240 | 1291 |
if (omap_dma_3_1_lcd_write(&s->lcd_ch, offset, value)) |
1241 | 1292 |
break; |
1242 | 1293 |
return; |
... | ... | |
1250 | 1301 |
return; |
1251 | 1302 |
|
1252 | 1303 |
case 0x404 ... 0x4fe: |
1253 |
if (s->model == omap_dma_3_1)
|
|
1304 |
if (s->model <= omap_dma_3_1)
|
|
1254 | 1305 |
break; |
1255 | 1306 |
case 0x400: |
1256 | 1307 |
/* Fall through. */ |
... | ... | |
1285 | 1336 |
static void omap_dma_request(void *opaque, int drq, int req) |
1286 | 1337 |
{ |
1287 | 1338 |
struct omap_dma_s *s = (struct omap_dma_s *) opaque; |
1288 |
/* The request pins are level triggered. */ |
|
1339 |
/* The request pins are level triggered in QEMU. */
|
|
1289 | 1340 |
if (req) { |
1290 | 1341 |
if (~s->drq & (1 << drq)) { |
1291 | 1342 |
s->drq |= 1 << drq; |
... | ... | |
1310 | 1361 |
} |
1311 | 1362 |
} |
1312 | 1363 |
|
1364 |
static void omap_dma_setcaps(struct omap_dma_s *s) |
|
1365 |
{ |
|
1366 |
switch (s->model) { |
|
1367 |
default: |
|
1368 |
case omap_dma_3_1: |
|
1369 |
break; |
|
1370 |
case omap_dma_3_2: |
|
1371 |
case omap_dma_4: |
|
1372 |
/* XXX Only available for sDMA */ |
|
1373 |
s->caps[0] = |
|
1374 |
(1 << 19) | /* Constant Fill Capability */ |
|
1375 |
(1 << 18); /* Transparent BLT Capability */ |
|
1376 |
s->caps[1] = |
|
1377 |
(1 << 1); /* 1-bit palettized capability (DMA 3.2 only) */ |
|
1378 |
s->caps[2] = |
|
1379 |
(1 << 8) | /* SEPARATE_SRC_AND_DST_INDEX_CPBLTY */ |
|
1380 |
(1 << 7) | /* DST_DOUBLE_INDEX_ADRS_CPBLTY */ |
|
1381 |
(1 << 6) | /* DST_SINGLE_INDEX_ADRS_CPBLTY */ |
|
1382 |
(1 << 5) | /* DST_POST_INCRMNT_ADRS_CPBLTY */ |
|
1383 |
(1 << 4) | /* DST_CONST_ADRS_CPBLTY */ |
|
1384 |
(1 << 3) | /* SRC_DOUBLE_INDEX_ADRS_CPBLTY */ |
|
1385 |
(1 << 2) | /* SRC_SINGLE_INDEX_ADRS_CPBLTY */ |
|
1386 |
(1 << 1) | /* SRC_POST_INCRMNT_ADRS_CPBLTY */ |
|
1387 |
(1 << 0); /* SRC_CONST_ADRS_CPBLTY */ |
|
1388 |
s->caps[3] = |
|
1389 |
(1 << 6) | /* BLOCK_SYNCHR_CPBLTY (DMA 4 only) */ |
|
1390 |
(1 << 7) | /* PKT_SYNCHR_CPBLTY (DMA 4 only) */ |
|
1391 |
(1 << 5) | /* CHANNEL_CHAINING_CPBLTY */ |
|
1392 |
(1 << 4) | /* LCh_INTERLEAVE_CPBLTY */ |
|
1393 |
(1 << 3) | /* AUTOINIT_REPEAT_CPBLTY (DMA 3.2 only) */ |
|
1394 |
(1 << 2) | /* AUTOINIT_ENDPROG_CPBLTY (DMA 3.2 only) */ |
|
1395 |
(1 << 1) | /* FRAME_SYNCHR_CPBLTY */ |
|
1396 |
(1 << 0); /* ELMNT_SYNCHR_CPBLTY */ |
|
1397 |
s->caps[4] = |
|
1398 |
(1 << 7) | /* PKT_INTERRUPT_CPBLTY (DMA 4 only) */ |
|
1399 |
(1 << 6) | /* SYNC_STATUS_CPBLTY */ |
|
1400 |
(1 << 5) | /* BLOCK_INTERRUPT_CPBLTY */ |
|
1401 |
(1 << 4) | /* LAST_FRAME_INTERRUPT_CPBLTY */ |
|
1402 |
(1 << 3) | /* FRAME_INTERRUPT_CPBLTY */ |
|
1403 |
(1 << 2) | /* HALF_FRAME_INTERRUPT_CPBLTY */ |
|
1404 |
(1 << 1) | /* EVENT_DROP_INTERRUPT_CPBLTY */ |
|
1405 |
(1 << 0); /* TIMEOUT_INTERRUPT_CPBLTY (DMA 3.2 only) */ |
|
1406 |
break; |
|
1407 |
} |
|
1408 |
} |
|
1409 |
|
|
1313 | 1410 |
struct omap_dma_s *omap_dma_init(target_phys_addr_t base, qemu_irq *irqs, |
1314 | 1411 |
qemu_irq lcd_irq, struct omap_mpu_state_s *mpu, omap_clk clk, |
1315 | 1412 |
enum omap_dma_model model) |
... | ... | |
1318 | 1415 |
struct omap_dma_s *s = (struct omap_dma_s *) |
1319 | 1416 |
qemu_mallocz(sizeof(struct omap_dma_s)); |
1320 | 1417 |
|
1321 |
if (model == omap_dma_3_1) {
|
|
1418 |
if (model <= omap_dma_3_1) {
|
|
1322 | 1419 |
num_irqs = 6; |
1323 | 1420 |
memsize = 0x800; |
1324 | 1421 |
} else { |
... | ... | |
1331 | 1428 |
s->clk = clk; |
1332 | 1429 |
s->lcd_ch.irq = lcd_irq; |
1333 | 1430 |
s->lcd_ch.mpu = mpu; |
1431 |
omap_dma_setcaps(s); |
|
1334 | 1432 |
while (num_irqs --) |
1335 | 1433 |
s->ch[num_irqs].irq = irqs[num_irqs]; |
1336 | 1434 |
for (i = 0; i < 3; i ++) { |
... | ... | |
1350 | 1448 |
return s; |
1351 | 1449 |
} |
1352 | 1450 |
|
1451 |
static void omap_dma_interrupts_4_update(struct omap_dma_s *s) |
|
1452 |
{ |
|
1453 |
struct omap_dma_channel_s *ch = s->ch; |
|
1454 |
uint32_t bmp, bit; |
|
1455 |
|
|
1456 |
for (bmp = 0, bit = 1; bit; ch ++, bit <<= 1) |
|
1457 |
if (ch->status) { |
|
1458 |
bmp |= bit; |
|
1459 |
ch->cstatus |= ch->status; |
|
1460 |
ch->status = 0; |
|
1461 |
} |
|
1462 |
if ((s->irqstat[0] |= s->irqen[0] & bmp)) |
|
1463 |
qemu_irq_raise(s->irq[0]); |
|
1464 |
if ((s->irqstat[1] |= s->irqen[1] & bmp)) |
|
1465 |
qemu_irq_raise(s->irq[1]); |
|
1466 |
if ((s->irqstat[2] |= s->irqen[2] & bmp)) |
|
1467 |
qemu_irq_raise(s->irq[2]); |
|
1468 |
if ((s->irqstat[3] |= s->irqen[3] & bmp)) |
|
1469 |
qemu_irq_raise(s->irq[3]); |
|
1470 |
} |
|
1471 |
|
|
1472 |
static uint32_t omap_dma4_read(void *opaque, target_phys_addr_t addr) |
|
1473 |
{ |
|
1474 |
struct omap_dma_s *s = (struct omap_dma_s *) opaque; |
|
1475 |
int irqn = 0, chnum, offset = addr - s->base; |
|
1476 |
struct omap_dma_channel_s *ch; |
|
1477 |
|
|
1478 |
switch (offset) { |
|
1479 |
case 0x00: /* DMA4_REVISION */ |
|
1480 |
return 0x40; |
|
1481 |
|
|
1482 |
case 0x14: /* DMA4_IRQSTATUS_L3 */ |
|
1483 |
irqn ++; |
|
1484 |
case 0x10: /* DMA4_IRQSTATUS_L2 */ |
|
1485 |
irqn ++; |
|
1486 |
case 0x0c: /* DMA4_IRQSTATUS_L1 */ |
|
1487 |
irqn ++; |
|
1488 |
case 0x08: /* DMA4_IRQSTATUS_L0 */ |
|
1489 |
return s->irqstat[irqn]; |
|
1490 |
|
|
1491 |
case 0x24: /* DMA4_IRQENABLE_L3 */ |
|
1492 |
irqn ++; |
|
1493 |
case 0x20: /* DMA4_IRQENABLE_L2 */ |
|
1494 |
irqn ++; |
|
1495 |
case 0x1c: /* DMA4_IRQENABLE_L1 */ |
|
1496 |
irqn ++; |
|
1497 |
case 0x18: /* DMA4_IRQENABLE_L0 */ |
|
1498 |
return s->irqen[irqn]; |
|
1499 |
|
|
1500 |
case 0x28: /* DMA4_SYSSTATUS */ |
|
1501 |
return 1; /* RESETDONE */ |
|
1502 |
|
|
1503 |
case 0x2c: /* DMA4_OCP_SYSCONFIG */ |
|
1504 |
return s->ocp; |
|
1505 |
|
|
1506 |
case 0x64: /* DMA4_CAPS_0 */ |
|
1507 |
return s->caps[0]; |
|
1508 |
case 0x6c: /* DMA4_CAPS_2 */ |
|
1509 |
return s->caps[2]; |
|
1510 |
case 0x70: /* DMA4_CAPS_3 */ |
|
1511 |
return s->caps[3]; |
|
1512 |
case 0x74: /* DMA4_CAPS_4 */ |
|
1513 |
return s->caps[4]; |
|
1514 |
|
|
1515 |
case 0x78: /* DMA4_GCR */ |
|
1516 |
return s->gcr; |
|
1517 |
|
|
1518 |
case 0x80 ... 0xfff: |
|
1519 |
offset -= 0x80; |
|
1520 |
chnum = offset / 0x60; |
|
1521 |
ch = s->ch + chnum; |
|
1522 |
offset -= chnum * 0x60; |
|
1523 |
break; |
|
1524 |
|
|
1525 |
default: |
|
1526 |
OMAP_BAD_REG(addr); |
|
1527 |
return 0; |
|
1528 |
} |
|
1529 |
|
|
1530 |
/* Per-channel registers */ |
|
1531 |
switch (offset) { |
|
1532 |
case 0x00: /* DMA4_CCR */ |
|
1533 |
return (ch->buf_disable << 25) | |
|
1534 |
(ch->src_sync << 24) | |
|
1535 |
(ch->prefetch << 23) | |
|
1536 |
((ch->sync & 0x60) << 14) | |
|
1537 |
(ch->bs << 18) | |
|
1538 |
(ch->transparent_copy << 17) | |
|
1539 |
(ch->constant_fill << 16) | |
|
1540 |
(ch->mode[1] << 14) | |
|
1541 |
(ch->mode[0] << 12) | |
|
1542 |
(0 << 10) | (0 << 9) | |
|
1543 |
(ch->suspend << 8) | |
|
1544 |
(ch->enable << 7) | |
|
1545 |
(ch->priority << 6) | |
|
1546 |
(ch->fs << 5) | (ch->sync & 0x1f); |
|
1547 |
|
|
1548 |
case 0x04: /* DMA4_CLNK_CTRL */ |
|
1549 |
return (ch->link_enabled << 15) | ch->link_next_ch; |
|
1550 |
|
|
1551 |
case 0x08: /* DMA4_CICR */ |
|
1552 |
return ch->interrupts; |
|
1553 |
|
|
1554 |
case 0x0c: /* DMA4_CSR */ |
|
1555 |
return ch->cstatus; |
|
1556 |
|
|
1557 |
case 0x10: /* DMA4_CSDP */ |
|
1558 |
return (ch->endian[0] << 21) | |
|
1559 |
(ch->endian_lock[0] << 20) | |
|
1560 |
(ch->endian[1] << 19) | |
|
1561 |
(ch->endian_lock[1] << 18) | |
|
1562 |
(ch->write_mode << 16) | |
|
1563 |
(ch->burst[1] << 14) | |
|
1564 |
(ch->pack[1] << 13) | |
|
1565 |
(ch->translate[1] << 9) | |
|
1566 |
(ch->burst[0] << 7) | |
|
1567 |
(ch->pack[0] << 6) | |
|
1568 |
(ch->translate[0] << 2) | |
|
1569 |
(ch->data_type >> 1); |
|
1570 |
|
|
1571 |
case 0x14: /* DMA4_CEN */ |
|
1572 |
return ch->elements; |
|
1573 |
|
|
1574 |
case 0x18: /* DMA4_CFN */ |
|
1575 |
return ch->frames; |
|
1576 |
|
|
1577 |
case 0x1c: /* DMA4_CSSA */ |
|
1578 |
return ch->addr[0]; |
|
1579 |
|
|
1580 |
case 0x20: /* DMA4_CDSA */ |
|
1581 |
return ch->addr[1]; |
|
1582 |
|
|
1583 |
case 0x24: /* DMA4_CSEI */ |
|
1584 |
return ch->element_index[0]; |
|
1585 |
|
|
1586 |
case 0x28: /* DMA4_CSFI */ |
|
1587 |
return ch->frame_index[0]; |
|
1588 |
|
|
1589 |
case 0x2c: /* DMA4_CDEI */ |
|
1590 |
return ch->element_index[1]; |
|
1591 |
|
|
1592 |
case 0x30: /* DMA4_CDFI */ |
|
1593 |
return ch->frame_index[1]; |
|
1594 |
|
|
1595 |
case 0x34: /* DMA4_CSAC */ |
|
1596 |
return ch->active_set.src & 0xffff; |
|
1597 |
|
|
1598 |
case 0x38: /* DMA4_CDAC */ |
|
1599 |
return ch->active_set.dest & 0xffff; |
|
1600 |
|
|
1601 |
case 0x3c: /* DMA4_CCEN */ |
|
1602 |
return ch->active_set.element; |
|
1603 |
|
|
1604 |
case 0x40: /* DMA4_CCFN */ |
|
1605 |
return ch->active_set.frame; |
|
1606 |
|
|
1607 |
case 0x44: /* DMA4_COLOR */ |
|
1608 |
/* XXX only in sDMA */ |
|
1609 |
return ch->color; |
|
1610 |
|
|
1611 |
default: |
|
1612 |
OMAP_BAD_REG(addr); |
|
1613 |
return 0; |
|
1614 |
} |
|
1615 |
} |
|
1616 |
|
|
1617 |
static void omap_dma4_write(void *opaque, target_phys_addr_t addr, |
|
1618 |
uint32_t value) |
|
1619 |
{ |
|
1620 |
struct omap_dma_s *s = (struct omap_dma_s *) opaque; |
|
1621 |
int chnum, irqn = 0, offset = addr - s->base; |
|
1622 |
struct omap_dma_channel_s *ch; |
|
1623 |
|
|
1624 |
switch (offset) { |
|
1625 |
case 0x14: /* DMA4_IRQSTATUS_L3 */ |
|
1626 |
irqn ++; |
|
1627 |
case 0x10: /* DMA4_IRQSTATUS_L2 */ |
|
1628 |
irqn ++; |
|
1629 |
case 0x0c: /* DMA4_IRQSTATUS_L1 */ |
|
1630 |
irqn ++; |
|
1631 |
case 0x08: /* DMA4_IRQSTATUS_L0 */ |
|
1632 |
s->irqstat[irqn] &= ~value; |
|
1633 |
if (!s->irqstat[irqn]) |
|
1634 |
qemu_irq_lower(s->irq[irqn]); |
|
1635 |
return; |
|
1636 |
|
|
1637 |
case 0x24: /* DMA4_IRQENABLE_L3 */ |
|
1638 |
irqn ++; |
|
1639 |
case 0x20: /* DMA4_IRQENABLE_L2 */ |
|
1640 |
irqn ++; |
|
1641 |
case 0x1c: /* DMA4_IRQENABLE_L1 */ |
|
1642 |
irqn ++; |
|
1643 |
case 0x18: /* DMA4_IRQENABLE_L0 */ |
|
1644 |
s->irqen[irqn] = value; |
|
1645 |
return; |
|
1646 |
|
|
1647 |
case 0x2c: /* DMA4_OCP_SYSCONFIG */ |
|
1648 |
if (value & 2) /* SOFTRESET */ |
|
1649 |
omap_dma_reset(s); |
|
1650 |
s->ocp = value & 0x3321; |
|
1651 |
if (((s->ocp >> 12) & 3) == 3) /* MIDLEMODE */ |
|
1652 |
fprintf(stderr, "%s: invalid DMA power mode\n", __FUNCTION__); |
|
1653 |
return; |
|
1654 |
|
|
1655 |
case 0x78: /* DMA4_GCR */ |
|
1656 |
s->gcr = value & 0x00ff00ff; |
|
1657 |
if ((value & 0xff) == 0x00) /* MAX_CHANNEL_FIFO_DEPTH */ |
|
1658 |
fprintf(stderr, "%s: wrong FIFO depth in GCR\n", __FUNCTION__); |
|
1659 |
return; |
|
1660 |
|
|
1661 |
case 0x80 ... 0xfff: |
|
1662 |
offset -= 0x80; |
|
1663 |
chnum = offset / 0x60; |
|
1664 |
ch = s->ch + chnum; |
|
1665 |
offset -= chnum * 0x60; |
|
1666 |
break; |
|
1667 |
|
|
1668 |
case 0x00: /* DMA4_REVISION */ |
|
1669 |
case 0x28: /* DMA4_SYSSTATUS */ |
|
1670 |
case 0x64: /* DMA4_CAPS_0 */ |
|
1671 |
case 0x6c: /* DMA4_CAPS_2 */ |
|
1672 |
case 0x70: /* DMA4_CAPS_3 */ |
|
1673 |
case 0x74: /* DMA4_CAPS_4 */ |
|
1674 |
OMAP_RO_REG(addr); |
|
1675 |
return; |
|
1676 |
|
|
1677 |
default: |
|
1678 |
OMAP_BAD_REG(addr); |
|
1679 |
return; |
|
1680 |
} |
|
1681 |
|
|
1682 |
/* Per-channel registers */ |
|
1683 |
switch (offset) { |
|
1684 |
case 0x00: /* DMA4_CCR */ |
|
1685 |
ch->buf_disable = (value >> 25) & 1; |
|
1686 |
ch->src_sync = (value >> 24) & 1; /* XXX For CamDMA must be 1 */ |
|
1687 |
if (ch->buf_disable && !ch->src_sync) |
|
1688 |
fprintf(stderr, "%s: Buffering disable is not allowed in " |
|
1689 |
"destination synchronised mode\n", __FUNCTION__); |
|
1690 |
ch->prefetch = (value >> 23) & 1; |
|
1691 |
ch->bs = (value >> 18) & 1; |
|
1692 |
ch->transparent_copy = (value >> 17) & 1; |
|
1693 |
ch->constant_fill = (value >> 16) & 1; |
|
1694 |
ch->mode[1] = (omap_dma_addressing_t) ((value & 0xc000) >> 14); |
|
1695 |
ch->mode[0] = (omap_dma_addressing_t) ((value & 0x3000) >> 12); |
|
1696 |
ch->suspend = (value & 0x0100) >> 8; |
|
1697 |
ch->priority = (value & 0x0040) >> 6; |
|
1698 |
ch->fs = (value & 0x0020) >> 5; |
|
1699 |
if (ch->fs && ch->bs && ch->mode[0] && ch->mode[1]) |
|
1700 |
fprintf(stderr, "%s: For a packet transfer at least one port " |
|
1701 |
"must be constant-addressed\n", __FUNCTION__); |
|
1702 |
ch->sync = (value & 0x001f) | ((value >> 14) & 0x0060); |
|
1703 |
/* XXX must be 0x01 for CamDMA */ |
|
1704 |
|
|
1705 |
if (value & 0x0080) |
|
1706 |
omap_dma_enable_channel(s, ch); |
|
1707 |
else |
|
1708 |
omap_dma_disable_channel(s, ch); |
|
1709 |
|
|
1710 |
break; |
|
1711 |
|
|
1712 |
case 0x04: /* DMA4_CLNK_CTRL */ |
|
1713 |
ch->link_enabled = (value >> 15) & 0x1; |
|
1714 |
ch->link_next_ch = value & 0x1f; |
|
1715 |
break; |
|
1716 |
|
|
1717 |
case 0x08: /* DMA4_CICR */ |
|
1718 |
ch->interrupts = value & 0x09be; |
|
1719 |
break; |
|
1720 |
|
|
1721 |
case 0x0c: /* DMA4_CSR */ |
|
1722 |
ch->cstatus &= ~value; |
|
1723 |
break; |
|
1724 |
|
|
1725 |
case 0x10: /* DMA4_CSDP */ |
|
1726 |
ch->endian[0] =(value >> 21) & 1; |
|
1727 |
ch->endian_lock[0] =(value >> 20) & 1; |
|
1728 |
ch->endian[1] =(value >> 19) & 1; |
|
1729 |
ch->endian_lock[1] =(value >> 18) & 1; |
|
1730 |
if (ch->endian[0] != ch->endian[1]) |
|
1731 |
fprintf(stderr, "%s: DMA endianned conversion enable attempt\n", |
|
1732 |
__FUNCTION__); |
|
1733 |
ch->write_mode = (value >> 16) & 3; |
|
1734 |
ch->burst[1] = (value & 0xc000) >> 14; |
|
1735 |
ch->pack[1] = (value & 0x2000) >> 13; |
|
1736 |
ch->translate[1] = (value & 0x1e00) >> 9; |
|
1737 |
ch->burst[0] = (value & 0x0180) >> 7; |
|
1738 |
ch->pack[0] = (value & 0x0040) >> 6; |
|
1739 |
ch->translate[0] = (value & 0x003c) >> 2; |
|
1740 |
if (ch->translate[0] | ch->translate[1]) |
|
1741 |
fprintf(stderr, "%s: bad MReqAddressTranslate sideband signal\n", |
|
1742 |
__FUNCTION__); |
|
1743 |
ch->data_type = 1 << (value & 3); |
|
1744 |
if ((value & 3) == 3) |
|
1745 |
printf("%s: bad data_type for DMA channel\n", __FUNCTION__); |
|
1746 |
break; |
|
1747 |
|
|
1748 |
case 0x14: /* DMA4_CEN */ |
|
1749 |
ch->elements = value & 0xffffff; |
|
1750 |
break; |
|
1751 |
|
|
1752 |
case 0x18: /* DMA4_CFN */ |
|
1753 |
ch->frames = value & 0xffff; |
|
1754 |
break; |
|
1755 |
|
|
1756 |
case 0x1c: /* DMA4_CSSA */ |
|
1757 |
ch->addr[0] = (target_phys_addr_t) (uint32_t) value; |
|
1758 |
break; |
|
1759 |
|
|
1760 |
case 0x20: /* DMA4_CDSA */ |
|
1761 |
ch->addr[1] = (target_phys_addr_t) (uint32_t) value; |
|
1762 |
break; |
|
1763 |
|
|
1764 |
case 0x24: /* DMA4_CSEI */ |
|
1765 |
ch->element_index[0] = (int16_t) value; |
|
1766 |
break; |
|
1767 |
|
|
1768 |
case 0x28: /* DMA4_CSFI */ |
|
1769 |
ch->frame_index[0] = (int32_t) value; |
|
1770 |
break; |
|
1771 |
|
|
1772 |
case 0x2c: /* DMA4_CDEI */ |
|
1773 |
ch->element_index[1] = (int16_t) value; |
|
1774 |
break; |
|
1775 |
|
|
1776 |
case 0x30: /* DMA4_CDFI */ |
|
1777 |
ch->frame_index[1] = (int32_t) value; |
|
1778 |
break; |
|
1779 |
|
|
1780 |
case 0x44: /* DMA4_COLOR */ |
|
1781 |
/* XXX only in sDMA */ |
|
1782 |
ch->color = value; |
|
1783 |
break; |
|
1784 |
|
|
1785 |
case 0x34: /* DMA4_CSAC */ |
|
1786 |
case 0x38: /* DMA4_CDAC */ |
|
1787 |
case 0x3c: /* DMA4_CCEN */ |
|
1788 |
case 0x40: /* DMA4_CCFN */ |
|
1789 |
OMAP_RO_REG(addr); |
|
1790 |
break; |
|
1791 |
|
|
1792 |
default: |
|
1793 |
OMAP_BAD_REG(addr); |
|
1794 |
} |
|
1795 |
} |
|
1796 |
|
|
1797 |
static CPUReadMemoryFunc *omap_dma4_readfn[] = { |
|
1798 |
omap_badwidth_read16, |
|
1799 |
omap_dma4_read, |
|
1800 |
omap_dma4_read, |
|
1801 |
}; |
|
1802 |
|
|
1803 |
static CPUWriteMemoryFunc *omap_dma4_writefn[] = { |
|
1804 |
omap_badwidth_write16, |
|
1805 |
omap_dma4_write, |
|
1806 |
omap_dma4_write, |
|
1807 |
}; |
|
1808 |
|
|
1809 |
struct omap_dma_s *omap_dma4_init(target_phys_addr_t base, qemu_irq *irqs, |
|
1810 |
struct omap_mpu_state_s *mpu, int fifo, |
|
1811 |
int chans, omap_clk iclk, omap_clk fclk) |
|
1812 |
{ |
|
1813 |
int iomemtype; |
|
1814 |
struct omap_dma_s *s = (struct omap_dma_s *) |
|
1815 |
qemu_mallocz(sizeof(struct omap_dma_s)); |
|
1816 |
|
|
1817 |
s->base = base; |
|
1818 |
s->model = omap_dma_4; |
|
1819 |
s->chans = chans; |
|
1820 |
s->mpu = mpu; |
|
1821 |
s->clk = fclk; |
|
1822 |
memcpy(&s->irq, irqs, sizeof(s->irq)); |
|
1823 |
s->intr_update = omap_dma_interrupts_4_update; |
|
1824 |
omap_dma_setcaps(s); |
|
1825 |
s->tm = qemu_new_timer(vm_clock, (QEMUTimerCB *) omap_dma_channel_run, s); |
|
1826 |
omap_clk_adduser(s->clk, qemu_allocate_irqs(omap_dma_clk_update, s, 1)[0]); |
|
1827 |
mpu->drq = qemu_allocate_irqs(omap_dma_request, s, 64); |
|
1828 |
omap_dma_reset(s); |
|
1829 |
omap_dma_clk_update(s, 0, 1); |
|
1830 |
|
|
1831 |
iomemtype = cpu_register_io_memory(0, omap_dma4_readfn, |
|
1832 |
omap_dma4_writefn, s); |
|
1833 |
cpu_register_physical_memory(s->base, 0x1000, iomemtype); |
|
1834 |
|
|
1835 |
return s; |
|
1836 |
} |
|
1837 |
|
|
1353 | 1838 |
struct omap_dma_lcd_channel_s *omap_dma_get_lcdch(struct omap_dma_s *s) |
1354 | 1839 |
{ |
1355 | 1840 |
return &s->lcd_ch; |
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