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1 | aa0aa4fa | bellard | /* Instruction printing code for the ARM
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2 | aa0aa4fa | bellard | Copyright 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002
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3 | aa0aa4fa | bellard | Free Software Foundation, Inc.
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4 | aa0aa4fa | bellard | Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
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5 | aa0aa4fa | bellard | Modification by James G. Smith (jsmith@cygnus.co.uk)
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6 | aa0aa4fa | bellard | |
7 | aa0aa4fa | bellard | This file is part of libopcodes.
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8 | aa0aa4fa | bellard | |
9 | aa0aa4fa | bellard | This program is free software; you can redistribute it and/or modify it under
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10 | aa0aa4fa | bellard | the terms of the GNU General Public License as published by the Free
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11 | aa0aa4fa | bellard | Software Foundation; either version 2 of the License, or (at your option)
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12 | aa0aa4fa | bellard | any later version.
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13 | aa0aa4fa | bellard | |
14 | aa0aa4fa | bellard | This program is distributed in the hope that it will be useful, but WITHOUT
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15 | aa0aa4fa | bellard | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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16 | aa0aa4fa | bellard | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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17 | aa0aa4fa | bellard | more details.
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18 | aa0aa4fa | bellard | |
19 | aa0aa4fa | bellard | You should have received a copy of the GNU General Public License
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20 | aa0aa4fa | bellard | along with this program; if not, write to the Free Software
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21 | aa0aa4fa | bellard | Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
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22 | aa0aa4fa | bellard | |
23 | aa0aa4fa | bellard | #include "dis-asm.h" |
24 | aa0aa4fa | bellard | |
25 | aa0aa4fa | bellard | struct arm_opcode {
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26 | aa0aa4fa | bellard | unsigned long value, mask; /* recognise instruction if (op&mask)==value */ |
27 | aa0aa4fa | bellard | char *assembler; /* how to disassemble this instruction */ |
28 | aa0aa4fa | bellard | }; |
29 | aa0aa4fa | bellard | |
30 | aa0aa4fa | bellard | struct thumb_opcode
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31 | aa0aa4fa | bellard | { |
32 | aa0aa4fa | bellard | unsigned short value, mask; /* recognise instruction if (op&mask)==value */ |
33 | aa0aa4fa | bellard | char * assembler; /* how to disassemble this instruction */ |
34 | aa0aa4fa | bellard | }; |
35 | aa0aa4fa | bellard | |
36 | aa0aa4fa | bellard | /* format of the assembler string :
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37 | aa0aa4fa | bellard |
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38 | aa0aa4fa | bellard | %% %
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39 | aa0aa4fa | bellard | %<bitfield>d print the bitfield in decimal
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40 | aa0aa4fa | bellard | %<bitfield>x print the bitfield in hex
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41 | aa0aa4fa | bellard | %<bitfield>X print the bitfield as 1 hex digit without leading "0x"
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42 | aa0aa4fa | bellard | %<bitfield>r print as an ARM register
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43 | aa0aa4fa | bellard | %<bitfield>f print a floating point constant if >7 else a
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44 | aa0aa4fa | bellard | floating point register
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45 | aa0aa4fa | bellard | %<code>y print a single precision VFP reg.
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46 | aa0aa4fa | bellard | Codes: 0=>Sm, 1=>Sd, 2=>Sn, 3=>multi-list, 4=>Sm pair
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47 | aa0aa4fa | bellard | %<code>z print a double precision VFP reg
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48 | aa0aa4fa | bellard | Codes: 0=>Dm, 1=>Dd, 2=>Dn, 3=>multi-list
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49 | aa0aa4fa | bellard | %c print condition code (always bits 28-31)
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50 | aa0aa4fa | bellard | %P print floating point precision in arithmetic insn
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51 | aa0aa4fa | bellard | %Q print floating point precision in ldf/stf insn
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52 | aa0aa4fa | bellard | %R print floating point rounding mode
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53 | aa0aa4fa | bellard | %<bitnum>'c print specified char iff bit is one
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54 | aa0aa4fa | bellard | %<bitnum>`c print specified char iff bit is zero
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55 | aa0aa4fa | bellard | %<bitnum>?ab print a if bit is one else print b
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56 | aa0aa4fa | bellard | %p print 'p' iff bits 12-15 are 15
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57 | aa0aa4fa | bellard | %t print 't' iff bit 21 set and bit 24 clear
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58 | aa0aa4fa | bellard | %o print operand2 (immediate or register + shift)
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59 | aa0aa4fa | bellard | %a print address for ldr/str instruction
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60 | aa0aa4fa | bellard | %s print address for ldr/str halfword/signextend instruction
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61 | aa0aa4fa | bellard | %b print branch destination
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62 | aa0aa4fa | bellard | %B print arm BLX(1) destination
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63 | aa0aa4fa | bellard | %A print address for ldc/stc/ldf/stf instruction
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64 | aa0aa4fa | bellard | %m print register mask for ldm/stm instruction
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65 | aa0aa4fa | bellard | %C print the PSR sub type.
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66 | aa0aa4fa | bellard | %F print the COUNT field of a LFM/SFM instruction.
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67 | aa0aa4fa | bellard | Thumb specific format options:
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68 | aa0aa4fa | bellard | %D print Thumb register (bits 0..2 as high number if bit 7 set)
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69 | aa0aa4fa | bellard | %S print Thumb register (bits 3..5 as high number if bit 6 set)
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70 | aa0aa4fa | bellard | %<bitfield>I print bitfield as a signed decimal
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71 | aa0aa4fa | bellard | (top bit of range being the sign bit)
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72 | aa0aa4fa | bellard | %M print Thumb register mask
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73 | aa0aa4fa | bellard | %N print Thumb register mask (with LR)
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74 | aa0aa4fa | bellard | %O print Thumb register mask (with PC)
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75 | aa0aa4fa | bellard | %T print Thumb condition code (always bits 8-11)
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76 | aa0aa4fa | bellard | %I print cirrus signed shift immediate: bits 0..3|4..6
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77 | aa0aa4fa | bellard | %<bitfield>B print Thumb branch destination (signed displacement)
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78 | aa0aa4fa | bellard | %<bitfield>W print (bitfield * 4) as a decimal
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79 | aa0aa4fa | bellard | %<bitfield>H print (bitfield * 2) as a decimal
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80 | aa0aa4fa | bellard | %<bitfield>a print (bitfield * 4) as a pc-rel offset + decoded symbol
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81 | aa0aa4fa | bellard | */
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82 | aa0aa4fa | bellard | |
83 | aa0aa4fa | bellard | /* Note: There is a partial ordering in this table - it must be searched from
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84 | aa0aa4fa | bellard | the top to obtain a correct match. */
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85 | aa0aa4fa | bellard | |
86 | aa0aa4fa | bellard | static struct arm_opcode arm_opcodes[] = |
87 | aa0aa4fa | bellard | { |
88 | aa0aa4fa | bellard | /* ARM instructions. */
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89 | aa0aa4fa | bellard | {0xe1a00000, 0xffffffff, "nop\t\t\t(mov r0,r0)"}, |
90 | aa0aa4fa | bellard | {0x012FFF10, 0x0ffffff0, "bx%c\t%0-3r"}, |
91 | aa0aa4fa | bellard | {0x00000090, 0x0fe000f0, "mul%c%20's\t%16-19r, %0-3r, %8-11r"}, |
92 | aa0aa4fa | bellard | {0x00200090, 0x0fe000f0, "mla%c%20's\t%16-19r, %0-3r, %8-11r, %12-15r"}, |
93 | aa0aa4fa | bellard | {0x01000090, 0x0fb00ff0, "swp%c%22'b\t%12-15r, %0-3r, [%16-19r]"}, |
94 | aa0aa4fa | bellard | {0x00800090, 0x0fa000f0, "%22?sumull%c%20's\t%12-15r, %16-19r, %0-3r, %8-11r"}, |
95 | aa0aa4fa | bellard | {0x00a00090, 0x0fa000f0, "%22?sumlal%c%20's\t%12-15r, %16-19r, %0-3r, %8-11r"}, |
96 | aa0aa4fa | bellard | |
97 | aa0aa4fa | bellard | /* V5J instruction. */
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98 | aa0aa4fa | bellard | {0x012fff20, 0x0ffffff0, "bxj%c\t%0-3r"}, |
99 | aa0aa4fa | bellard | |
100 | aa0aa4fa | bellard | /* XScale instructions. */
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101 | aa0aa4fa | bellard | {0x0e200010, 0x0fff0ff0, "mia%c\tacc0, %0-3r, %12-15r"}, |
102 | aa0aa4fa | bellard | {0x0e280010, 0x0fff0ff0, "miaph%c\tacc0, %0-3r, %12-15r"}, |
103 | aa0aa4fa | bellard | {0x0e2c0010, 0x0ffc0ff0, "mia%17'T%17`B%16'T%16`B%c\tacc0, %0-3r, %12-15r"}, |
104 | aa0aa4fa | bellard | {0x0c400000, 0x0ff00fff, "mar%c\tacc0, %12-15r, %16-19r"}, |
105 | aa0aa4fa | bellard | {0x0c500000, 0x0ff00fff, "mra%c\t%12-15r, %16-19r, acc0"}, |
106 | aa0aa4fa | bellard | {0xf450f000, 0xfc70f000, "pld\t%a"}, |
107 | aa0aa4fa | bellard | |
108 | aa0aa4fa | bellard | /* V5 Instructions. */
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109 | aa0aa4fa | bellard | {0xe1200070, 0xfff000f0, "bkpt\t0x%16-19X%12-15X%8-11X%0-3X"}, |
110 | aa0aa4fa | bellard | {0xfa000000, 0xfe000000, "blx\t%B"}, |
111 | aa0aa4fa | bellard | {0x012fff30, 0x0ffffff0, "blx%c\t%0-3r"}, |
112 | aa0aa4fa | bellard | {0x016f0f10, 0x0fff0ff0, "clz%c\t%12-15r, %0-3r"}, |
113 | aa0aa4fa | bellard | {0xfc100000, 0xfe100000, "ldc2%22'l\t%8-11d, cr%12-15d, %A"}, |
114 | aa0aa4fa | bellard | {0xfc000000, 0xfe100000, "stc2%22'l\t%8-11d, cr%12-15d, %A"}, |
115 | aa0aa4fa | bellard | {0xfe000000, 0xff000010, "cdp2\t%8-11d, %20-23d, cr%12-15d, cr%16-19d, cr%0-3d, {%5-7d}"}, |
116 | aa0aa4fa | bellard | {0xfe000010, 0xff100010, "mcr2\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"}, |
117 | aa0aa4fa | bellard | {0xfe100010, 0xff100010, "mrc2\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"}, |
118 | aa0aa4fa | bellard | |
119 | aa0aa4fa | bellard | /* V5E "El Segundo" Instructions. */
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120 | aa0aa4fa | bellard | {0x000000d0, 0x0e1000f0, "ldr%cd\t%12-15r, %s"}, |
121 | aa0aa4fa | bellard | {0x000000f0, 0x0e1000f0, "str%cd\t%12-15r, %s"}, |
122 | aa0aa4fa | bellard | {0x01000080, 0x0ff000f0, "smlabb%c\t%16-19r, %0-3r, %8-11r, %12-15r"}, |
123 | aa0aa4fa | bellard | {0x010000a0, 0x0ff000f0, "smlatb%c\t%16-19r, %0-3r, %8-11r, %12-15r"}, |
124 | aa0aa4fa | bellard | {0x010000c0, 0x0ff000f0, "smlabt%c\t%16-19r, %0-3r, %8-11r, %12-15r"}, |
125 | aa0aa4fa | bellard | {0x010000e0, 0x0ff000f0, "smlatt%c\t%16-19r, %0-3r, %8-11r, %12-15r"}, |
126 | aa0aa4fa | bellard | |
127 | aa0aa4fa | bellard | {0x01200080, 0x0ff000f0, "smlawb%c\t%16-19r, %0-3r, %8-11r, %12-15r"}, |
128 | aa0aa4fa | bellard | {0x012000c0, 0x0ff000f0, "smlawt%c\t%16-19r, %0-3r, %8-11r, %12-15r"}, |
129 | aa0aa4fa | bellard | |
130 | aa0aa4fa | bellard | {0x01400080, 0x0ff000f0, "smlalbb%c\t%12-15r, %16-19r, %0-3r, %8-11r"}, |
131 | aa0aa4fa | bellard | {0x014000a0, 0x0ff000f0, "smlaltb%c\t%12-15r, %16-19r, %0-3r, %8-11r"}, |
132 | aa0aa4fa | bellard | {0x014000c0, 0x0ff000f0, "smlalbt%c\t%12-15r, %16-19r, %0-3r, %8-11r"}, |
133 | aa0aa4fa | bellard | {0x014000e0, 0x0ff000f0, "smlaltt%c\t%12-15r, %16-19r, %0-3r, %8-11r"}, |
134 | aa0aa4fa | bellard | |
135 | aa0aa4fa | bellard | {0x01600080, 0x0ff0f0f0, "smulbb%c\t%16-19r, %0-3r, %8-11r"}, |
136 | aa0aa4fa | bellard | {0x016000a0, 0x0ff0f0f0, "smultb%c\t%16-19r, %0-3r, %8-11r"}, |
137 | aa0aa4fa | bellard | {0x016000c0, 0x0ff0f0f0, "smulbt%c\t%16-19r, %0-3r, %8-11r"}, |
138 | aa0aa4fa | bellard | {0x016000e0, 0x0ff0f0f0, "smultt%c\t%16-19r, %0-3r, %8-11r"}, |
139 | aa0aa4fa | bellard | |
140 | aa0aa4fa | bellard | {0x012000a0, 0x0ff0f0f0, "smulwb%c\t%16-19r, %0-3r, %8-11r"}, |
141 | aa0aa4fa | bellard | {0x012000e0, 0x0ff0f0f0, "smulwt%c\t%16-19r, %0-3r, %8-11r"}, |
142 | aa0aa4fa | bellard | |
143 | aa0aa4fa | bellard | {0x01000050, 0x0ff00ff0, "qadd%c\t%12-15r, %0-3r, %16-19r"}, |
144 | aa0aa4fa | bellard | {0x01400050, 0x0ff00ff0, "qdadd%c\t%12-15r, %0-3r, %16-19r"}, |
145 | aa0aa4fa | bellard | {0x01200050, 0x0ff00ff0, "qsub%c\t%12-15r, %0-3r, %16-19r"}, |
146 | aa0aa4fa | bellard | {0x01600050, 0x0ff00ff0, "qdsub%c\t%12-15r, %0-3r, %16-19r"}, |
147 | aa0aa4fa | bellard | |
148 | aa0aa4fa | bellard | {0x0c400000, 0x0ff00000, "mcrr%c\t%8-11d, %4-7d, %12-15r, %16-19r, cr%0-3d"}, |
149 | aa0aa4fa | bellard | {0x0c500000, 0x0ff00000, "mrrc%c\t%8-11d, %4-7d, %12-15r, %16-19r, cr%0-3d"}, |
150 | aa0aa4fa | bellard | |
151 | aa0aa4fa | bellard | /* ARM Instructions. */
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152 | aa0aa4fa | bellard | {0x00000090, 0x0e100090, "str%c%6's%5?hb\t%12-15r, %s"}, |
153 | aa0aa4fa | bellard | {0x00100090, 0x0e100090, "ldr%c%6's%5?hb\t%12-15r, %s"}, |
154 | aa0aa4fa | bellard | {0x00000000, 0x0de00000, "and%c%20's\t%12-15r, %16-19r, %o"}, |
155 | aa0aa4fa | bellard | {0x00200000, 0x0de00000, "eor%c%20's\t%12-15r, %16-19r, %o"}, |
156 | aa0aa4fa | bellard | {0x00400000, 0x0de00000, "sub%c%20's\t%12-15r, %16-19r, %o"}, |
157 | aa0aa4fa | bellard | {0x00600000, 0x0de00000, "rsb%c%20's\t%12-15r, %16-19r, %o"}, |
158 | aa0aa4fa | bellard | {0x00800000, 0x0de00000, "add%c%20's\t%12-15r, %16-19r, %o"}, |
159 | aa0aa4fa | bellard | {0x00a00000, 0x0de00000, "adc%c%20's\t%12-15r, %16-19r, %o"}, |
160 | aa0aa4fa | bellard | {0x00c00000, 0x0de00000, "sbc%c%20's\t%12-15r, %16-19r, %o"}, |
161 | aa0aa4fa | bellard | {0x00e00000, 0x0de00000, "rsc%c%20's\t%12-15r, %16-19r, %o"}, |
162 | aa0aa4fa | bellard | {0x0120f000, 0x0db0f000, "msr%c\t%22?SCPSR%C, %o"}, |
163 | aa0aa4fa | bellard | {0x010f0000, 0x0fbf0fff, "mrs%c\t%12-15r, %22?SCPSR"}, |
164 | aa0aa4fa | bellard | {0x01000000, 0x0de00000, "tst%c%p\t%16-19r, %o"}, |
165 | aa0aa4fa | bellard | {0x01200000, 0x0de00000, "teq%c%p\t%16-19r, %o"}, |
166 | aa0aa4fa | bellard | {0x01400000, 0x0de00000, "cmp%c%p\t%16-19r, %o"}, |
167 | aa0aa4fa | bellard | {0x01600000, 0x0de00000, "cmn%c%p\t%16-19r, %o"}, |
168 | aa0aa4fa | bellard | {0x01800000, 0x0de00000, "orr%c%20's\t%12-15r, %16-19r, %o"}, |
169 | aa0aa4fa | bellard | {0x01a00000, 0x0de00000, "mov%c%20's\t%12-15r, %o"}, |
170 | aa0aa4fa | bellard | {0x01c00000, 0x0de00000, "bic%c%20's\t%12-15r, %16-19r, %o"}, |
171 | aa0aa4fa | bellard | {0x01e00000, 0x0de00000, "mvn%c%20's\t%12-15r, %o"}, |
172 | aa0aa4fa | bellard | {0x04000000, 0x0e100000, "str%c%22'b%t\t%12-15r, %a"}, |
173 | aa0aa4fa | bellard | {0x06000000, 0x0e100ff0, "str%c%22'b%t\t%12-15r, %a"}, |
174 | aa0aa4fa | bellard | {0x04000000, 0x0c100010, "str%c%22'b%t\t%12-15r, %a"}, |
175 | aa0aa4fa | bellard | {0x06000010, 0x0e000010, "undefined"}, |
176 | aa0aa4fa | bellard | {0x04100000, 0x0c100000, "ldr%c%22'b%t\t%12-15r, %a"}, |
177 | aa0aa4fa | bellard | {0x08000000, 0x0e100000, "stm%c%23?id%24?ba\t%16-19r%21'!, %m%22'^"}, |
178 | aa0aa4fa | bellard | {0x08100000, 0x0e100000, "ldm%c%23?id%24?ba\t%16-19r%21'!, %m%22'^"}, |
179 | aa0aa4fa | bellard | {0x0a000000, 0x0e000000, "b%24'l%c\t%b"}, |
180 | aa0aa4fa | bellard | {0x0f000000, 0x0f000000, "swi%c\t%0-23x"}, |
181 | aa0aa4fa | bellard | |
182 | aa0aa4fa | bellard | /* Floating point coprocessor (FPA) instructions */
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183 | aa0aa4fa | bellard | {0x0e000100, 0x0ff08f10, "adf%c%P%R\t%12-14f, %16-18f, %0-3f"}, |
184 | aa0aa4fa | bellard | {0x0e100100, 0x0ff08f10, "muf%c%P%R\t%12-14f, %16-18f, %0-3f"}, |
185 | aa0aa4fa | bellard | {0x0e200100, 0x0ff08f10, "suf%c%P%R\t%12-14f, %16-18f, %0-3f"}, |
186 | aa0aa4fa | bellard | {0x0e300100, 0x0ff08f10, "rsf%c%P%R\t%12-14f, %16-18f, %0-3f"}, |
187 | aa0aa4fa | bellard | {0x0e400100, 0x0ff08f10, "dvf%c%P%R\t%12-14f, %16-18f, %0-3f"}, |
188 | aa0aa4fa | bellard | {0x0e500100, 0x0ff08f10, "rdf%c%P%R\t%12-14f, %16-18f, %0-3f"}, |
189 | aa0aa4fa | bellard | {0x0e600100, 0x0ff08f10, "pow%c%P%R\t%12-14f, %16-18f, %0-3f"}, |
190 | aa0aa4fa | bellard | {0x0e700100, 0x0ff08f10, "rpw%c%P%R\t%12-14f, %16-18f, %0-3f"}, |
191 | aa0aa4fa | bellard | {0x0e800100, 0x0ff08f10, "rmf%c%P%R\t%12-14f, %16-18f, %0-3f"}, |
192 | aa0aa4fa | bellard | {0x0e900100, 0x0ff08f10, "fml%c%P%R\t%12-14f, %16-18f, %0-3f"}, |
193 | aa0aa4fa | bellard | {0x0ea00100, 0x0ff08f10, "fdv%c%P%R\t%12-14f, %16-18f, %0-3f"}, |
194 | aa0aa4fa | bellard | {0x0eb00100, 0x0ff08f10, "frd%c%P%R\t%12-14f, %16-18f, %0-3f"}, |
195 | aa0aa4fa | bellard | {0x0ec00100, 0x0ff08f10, "pol%c%P%R\t%12-14f, %16-18f, %0-3f"}, |
196 | aa0aa4fa | bellard | {0x0e008100, 0x0ff08f10, "mvf%c%P%R\t%12-14f, %0-3f"}, |
197 | aa0aa4fa | bellard | {0x0e108100, 0x0ff08f10, "mnf%c%P%R\t%12-14f, %0-3f"}, |
198 | aa0aa4fa | bellard | {0x0e208100, 0x0ff08f10, "abs%c%P%R\t%12-14f, %0-3f"}, |
199 | aa0aa4fa | bellard | {0x0e308100, 0x0ff08f10, "rnd%c%P%R\t%12-14f, %0-3f"}, |
200 | aa0aa4fa | bellard | {0x0e408100, 0x0ff08f10, "sqt%c%P%R\t%12-14f, %0-3f"}, |
201 | aa0aa4fa | bellard | {0x0e508100, 0x0ff08f10, "log%c%P%R\t%12-14f, %0-3f"}, |
202 | aa0aa4fa | bellard | {0x0e608100, 0x0ff08f10, "lgn%c%P%R\t%12-14f, %0-3f"}, |
203 | aa0aa4fa | bellard | {0x0e708100, 0x0ff08f10, "exp%c%P%R\t%12-14f, %0-3f"}, |
204 | aa0aa4fa | bellard | {0x0e808100, 0x0ff08f10, "sin%c%P%R\t%12-14f, %0-3f"}, |
205 | aa0aa4fa | bellard | {0x0e908100, 0x0ff08f10, "cos%c%P%R\t%12-14f, %0-3f"}, |
206 | aa0aa4fa | bellard | {0x0ea08100, 0x0ff08f10, "tan%c%P%R\t%12-14f, %0-3f"}, |
207 | aa0aa4fa | bellard | {0x0eb08100, 0x0ff08f10, "asn%c%P%R\t%12-14f, %0-3f"}, |
208 | aa0aa4fa | bellard | {0x0ec08100, 0x0ff08f10, "acs%c%P%R\t%12-14f, %0-3f"}, |
209 | aa0aa4fa | bellard | {0x0ed08100, 0x0ff08f10, "atn%c%P%R\t%12-14f, %0-3f"}, |
210 | aa0aa4fa | bellard | {0x0ee08100, 0x0ff08f10, "urd%c%P%R\t%12-14f, %0-3f"}, |
211 | aa0aa4fa | bellard | {0x0ef08100, 0x0ff08f10, "nrm%c%P%R\t%12-14f, %0-3f"}, |
212 | aa0aa4fa | bellard | {0x0e000110, 0x0ff00f1f, "flt%c%P%R\t%16-18f, %12-15r"}, |
213 | aa0aa4fa | bellard | {0x0e100110, 0x0fff0f98, "fix%c%R\t%12-15r, %0-2f"}, |
214 | aa0aa4fa | bellard | {0x0e200110, 0x0fff0fff, "wfs%c\t%12-15r"}, |
215 | aa0aa4fa | bellard | {0x0e300110, 0x0fff0fff, "rfs%c\t%12-15r"}, |
216 | aa0aa4fa | bellard | {0x0e400110, 0x0fff0fff, "wfc%c\t%12-15r"}, |
217 | aa0aa4fa | bellard | {0x0e500110, 0x0fff0fff, "rfc%c\t%12-15r"}, |
218 | aa0aa4fa | bellard | {0x0e90f110, 0x0ff8fff0, "cmf%c\t%16-18f, %0-3f"}, |
219 | aa0aa4fa | bellard | {0x0eb0f110, 0x0ff8fff0, "cnf%c\t%16-18f, %0-3f"}, |
220 | aa0aa4fa | bellard | {0x0ed0f110, 0x0ff8fff0, "cmfe%c\t%16-18f, %0-3f"}, |
221 | aa0aa4fa | bellard | {0x0ef0f110, 0x0ff8fff0, "cnfe%c\t%16-18f, %0-3f"}, |
222 | aa0aa4fa | bellard | {0x0c000100, 0x0e100f00, "stf%c%Q\t%12-14f, %A"}, |
223 | aa0aa4fa | bellard | {0x0c100100, 0x0e100f00, "ldf%c%Q\t%12-14f, %A"}, |
224 | aa0aa4fa | bellard | {0x0c000200, 0x0e100f00, "sfm%c\t%12-14f, %F, %A"}, |
225 | aa0aa4fa | bellard | {0x0c100200, 0x0e100f00, "lfm%c\t%12-14f, %F, %A"}, |
226 | aa0aa4fa | bellard | |
227 | aa0aa4fa | bellard | /* Floating point coprocessor (VFP) instructions */
|
228 | aa0aa4fa | bellard | {0x0eb00bc0, 0x0fff0ff0, "fabsd%c\t%1z, %0z"}, |
229 | aa0aa4fa | bellard | {0x0eb00ac0, 0x0fbf0fd0, "fabss%c\t%1y, %0y"}, |
230 | aa0aa4fa | bellard | {0x0e300b00, 0x0ff00ff0, "faddd%c\t%1z, %2z, %0z"}, |
231 | aa0aa4fa | bellard | {0x0e300a00, 0x0fb00f50, "fadds%c\t%1y, %2y, %1y"}, |
232 | aa0aa4fa | bellard | {0x0eb40b40, 0x0fff0f70, "fcmp%7'ed%c\t%1z, %0z"}, |
233 | aa0aa4fa | bellard | {0x0eb40a40, 0x0fbf0f50, "fcmp%7'es%c\t%1y, %0y"}, |
234 | aa0aa4fa | bellard | {0x0eb50b40, 0x0fff0f70, "fcmp%7'ezd%c\t%1z"}, |
235 | aa0aa4fa | bellard | {0x0eb50a40, 0x0fbf0f70, "fcmp%7'ezs%c\t%1y"}, |
236 | aa0aa4fa | bellard | {0x0eb00b40, 0x0fff0ff0, "fcpyd%c\t%1z, %0z"}, |
237 | aa0aa4fa | bellard | {0x0eb00a40, 0x0fbf0fd0, "fcpys%c\t%1y, %0y"}, |
238 | aa0aa4fa | bellard | {0x0eb70ac0, 0x0fff0fd0, "fcvtds%c\t%1z, %0y"}, |
239 | aa0aa4fa | bellard | {0x0eb70bc0, 0x0fbf0ff0, "fcvtsd%c\t%1y, %0z"}, |
240 | aa0aa4fa | bellard | {0x0e800b00, 0x0ff00ff0, "fdivd%c\t%1z, %2z, %0z"}, |
241 | aa0aa4fa | bellard | {0x0e800a00, 0x0fb00f50, "fdivs%c\t%1y, %2y, %0y"}, |
242 | aa0aa4fa | bellard | {0x0d100b00, 0x0f700f00, "fldd%c\t%1z, %A"}, |
243 | aa0aa4fa | bellard | {0x0c900b00, 0x0fd00f00, "fldmia%0?xd%c\t%16-19r%21'!, %3z"}, |
244 | aa0aa4fa | bellard | {0x0d300b00, 0x0ff00f00, "fldmdb%0?xd%c\t%16-19r!, %3z"}, |
245 | aa0aa4fa | bellard | {0x0d100a00, 0x0f300f00, "flds%c\t%1y, %A"}, |
246 | aa0aa4fa | bellard | {0x0c900a00, 0x0f900f00, "fldmias%c\t%16-19r%21'!, %3y"}, |
247 | aa0aa4fa | bellard | {0x0d300a00, 0x0fb00f00, "fldmdbs%c\t%16-19r!, %3y"}, |
248 | aa0aa4fa | bellard | {0x0e000b00, 0x0ff00ff0, "fmacd%c\t%1z, %2z, %0z"}, |
249 | aa0aa4fa | bellard | {0x0e000a00, 0x0fb00f50, "fmacs%c\t%1y, %2y, %0y"}, |
250 | aa0aa4fa | bellard | {0x0e200b10, 0x0ff00fff, "fmdhr%c\t%2z, %12-15r"}, |
251 | aa0aa4fa | bellard | {0x0e000b10, 0x0ff00fff, "fmdlr%c\t%2z, %12-15r"}, |
252 | aa0aa4fa | bellard | {0x0c400b10, 0x0ff00ff0, "fmdrr%c\t%0z, %12-15r, %16-19r"}, |
253 | aa0aa4fa | bellard | {0x0e300b10, 0x0ff00fff, "fmrdh%c\t%12-15r, %2z"}, |
254 | aa0aa4fa | bellard | {0x0e100b10, 0x0ff00fff, "fmrdl%c\t%12-15r, %2z"}, |
255 | aa0aa4fa | bellard | {0x0c500b10, 0x0ff00ff0, "fmrrd%c\t%12-15r, %16-19r, %0z"}, |
256 | aa0aa4fa | bellard | {0x0c500a10, 0x0ff00fd0, "fmrrs%c\t%12-15r, %16-19r, %4y"}, |
257 | aa0aa4fa | bellard | {0x0e100a10, 0x0ff00f7f, "fmrs%c\t%12-15r, %2y"}, |
258 | aa0aa4fa | bellard | {0x0ef1fa10, 0x0fffffff, "fmstat%c"}, |
259 | aa0aa4fa | bellard | {0x0ef00a10, 0x0fff0fff, "fmrx%c\t%12-15r, fpsid"}, |
260 | aa0aa4fa | bellard | {0x0ef10a10, 0x0fff0fff, "fmrx%c\t%12-15r, fpscr"}, |
261 | aa0aa4fa | bellard | {0x0ef80a10, 0x0fff0fff, "fmrx%c\t%12-15r, fpexc"}, |
262 | aa0aa4fa | bellard | {0x0ef90a10, 0x0fff0fff, "fmrx%c\t%12-15r, fpinst\t@ Impl def"}, |
263 | aa0aa4fa | bellard | {0x0efa0a10, 0x0fff0fff, "fmrx%c\t%12-15r, fpinst2\t@ Impl def"}, |
264 | aa0aa4fa | bellard | {0x0ef00a10, 0x0ff00fff, "fmrx%c\t%12-15r, <impl def 0x%16-19x>"}, |
265 | aa0aa4fa | bellard | {0x0e100b00, 0x0ff00ff0, "fmscd%c\t%1z, %2z, %0z"}, |
266 | aa0aa4fa | bellard | {0x0e100a00, 0x0fb00f50, "fmscs%c\t%1y, %2y, %0y"}, |
267 | aa0aa4fa | bellard | {0x0e000a10, 0x0ff00f7f, "fmsr%c\t%2y, %12-15r"}, |
268 | aa0aa4fa | bellard | {0x0c400a10, 0x0ff00fd0, "fmsrr%c\t%12-15r, %16-19r, %4y"}, |
269 | aa0aa4fa | bellard | {0x0e200b00, 0x0ff00ff0, "fmuld%c\t%1z, %2z, %0z"}, |
270 | aa0aa4fa | bellard | {0x0e200a00, 0x0fb00f50, "fmuls%c\t%1y, %2y, %0y"}, |
271 | aa0aa4fa | bellard | {0x0ee00a10, 0x0fff0fff, "fmxr%c\tfpsid, %12-15r"}, |
272 | aa0aa4fa | bellard | {0x0ee10a10, 0x0fff0fff, "fmxr%c\tfpscr, %12-15r"}, |
273 | aa0aa4fa | bellard | {0x0ee80a10, 0x0fff0fff, "fmxr%c\tfpexc, %12-15r"}, |
274 | aa0aa4fa | bellard | {0x0ee90a10, 0x0fff0fff, "fmxr%c\tfpinst, %12-15r\t@ Impl def"}, |
275 | aa0aa4fa | bellard | {0x0eea0a10, 0x0fff0fff, "fmxr%c\tfpinst2, %12-15r\t@ Impl def"}, |
276 | aa0aa4fa | bellard | {0x0ee00a10, 0x0ff00fff, "fmxr%c\t<impl def 0x%16-19x>, %12-15r"}, |
277 | aa0aa4fa | bellard | {0x0eb10b40, 0x0fff0ff0, "fnegd%c\t%1z, %0z"}, |
278 | aa0aa4fa | bellard | {0x0eb10a40, 0x0fbf0fd0, "fnegs%c\t%1y, %0y"}, |
279 | aa0aa4fa | bellard | {0x0e000b40, 0x0ff00ff0, "fnmacd%c\t%1z, %2z, %0z"}, |
280 | aa0aa4fa | bellard | {0x0e000a40, 0x0fb00f50, "fnmacs%c\t%1y, %2y, %0y"}, |
281 | aa0aa4fa | bellard | {0x0e100b40, 0x0ff00ff0, "fnmscd%c\t%1z, %2z, %0z"}, |
282 | aa0aa4fa | bellard | {0x0e100a40, 0x0fb00f50, "fnmscs%c\t%1y, %2y, %0y"}, |
283 | aa0aa4fa | bellard | {0x0e200b40, 0x0ff00ff0, "fnmuld%c\t%1z, %2z, %0z"}, |
284 | aa0aa4fa | bellard | {0x0e200a40, 0x0fb00f50, "fnmuls%c\t%1y, %2y, %0y"}, |
285 | aa0aa4fa | bellard | {0x0eb80bc0, 0x0fff0fd0, "fsitod%c\t%1z, %0y"}, |
286 | aa0aa4fa | bellard | {0x0eb80ac0, 0x0fbf0fd0, "fsitos%c\t%1y, %0y"}, |
287 | aa0aa4fa | bellard | {0x0eb10bc0, 0x0fff0ff0, "fsqrtd%c\t%1z, %0z"}, |
288 | aa0aa4fa | bellard | {0x0eb10ac0, 0x0fbf0fd0, "fsqrts%c\t%1y, %0y"}, |
289 | aa0aa4fa | bellard | {0x0d000b00, 0x0f700f00, "fstd%c\t%1z, %A"}, |
290 | aa0aa4fa | bellard | {0x0c800b00, 0x0fd00f00, "fstmia%0?xd%c\t%16-19r%21'!, %3z"}, |
291 | aa0aa4fa | bellard | {0x0d200b00, 0x0ff00f00, "fstmdb%0?xd%c\t%16-19r!, %3z"}, |
292 | aa0aa4fa | bellard | {0x0d000a00, 0x0f300f00, "fsts%c\t%1y, %A"}, |
293 | aa0aa4fa | bellard | {0x0c800a00, 0x0f900f00, "fstmias%c\t%16-19r%21'!, %3y"}, |
294 | aa0aa4fa | bellard | {0x0d200a00, 0x0fb00f00, "fstmdbs%c\t%16-19r!, %3y"}, |
295 | aa0aa4fa | bellard | {0x0e300b40, 0x0ff00ff0, "fsubd%c\t%1z, %2z, %0z"}, |
296 | aa0aa4fa | bellard | {0x0e300a40, 0x0fb00f50, "fsubs%c\t%1y, %2y, %0y"}, |
297 | aa0aa4fa | bellard | {0x0ebc0b40, 0x0fbe0f70, "fto%16?sui%7'zd%c\t%1y, %0z"}, |
298 | aa0aa4fa | bellard | {0x0ebc0a40, 0x0fbe0f50, "fto%16?sui%7'zs%c\t%1y, %0y"}, |
299 | aa0aa4fa | bellard | {0x0eb80b40, 0x0fff0fd0, "fuitod%c\t%1z, %0y"}, |
300 | aa0aa4fa | bellard | {0x0eb80a40, 0x0fbf0fd0, "fuitos%c\t%1y, %0y"}, |
301 | aa0aa4fa | bellard | |
302 | aa0aa4fa | bellard | /* Cirrus coprocessor instructions. */
|
303 | aa0aa4fa | bellard | {0x0d100400, 0x0f500f00, "cfldrs%c\tmvf%12-15d, %A"}, |
304 | aa0aa4fa | bellard | {0x0c100400, 0x0f500f00, "cfldrs%c\tmvf%12-15d, %A"}, |
305 | aa0aa4fa | bellard | {0x0d500400, 0x0f500f00, "cfldrd%c\tmvd%12-15d, %A"}, |
306 | aa0aa4fa | bellard | {0x0c500400, 0x0f500f00, "cfldrd%c\tmvd%12-15d, %A"}, |
307 | aa0aa4fa | bellard | {0x0d100500, 0x0f500f00, "cfldr32%c\tmvfx%12-15d, %A"}, |
308 | aa0aa4fa | bellard | {0x0c100500, 0x0f500f00, "cfldr32%c\tmvfx%12-15d, %A"}, |
309 | aa0aa4fa | bellard | {0x0d500500, 0x0f500f00, "cfldr64%c\tmvdx%12-15d, %A"}, |
310 | aa0aa4fa | bellard | {0x0c500500, 0x0f500f00, "cfldr64%c\tmvdx%12-15d, %A"}, |
311 | aa0aa4fa | bellard | {0x0d000400, 0x0f500f00, "cfstrs%c\tmvf%12-15d, %A"}, |
312 | aa0aa4fa | bellard | {0x0c000400, 0x0f500f00, "cfstrs%c\tmvf%12-15d, %A"}, |
313 | aa0aa4fa | bellard | {0x0d400400, 0x0f500f00, "cfstrd%c\tmvd%12-15d, %A"}, |
314 | aa0aa4fa | bellard | {0x0c400400, 0x0f500f00, "cfstrd%c\tmvd%12-15d, %A"}, |
315 | aa0aa4fa | bellard | {0x0d000500, 0x0f500f00, "cfstr32%c\tmvfx%12-15d, %A"}, |
316 | aa0aa4fa | bellard | {0x0c000500, 0x0f500f00, "cfstr32%c\tmvfx%12-15d, %A"}, |
317 | aa0aa4fa | bellard | {0x0d400500, 0x0f500f00, "cfstr64%c\tmvdx%12-15d, %A"}, |
318 | aa0aa4fa | bellard | {0x0c400500, 0x0f500f00, "cfstr64%c\tmvdx%12-15d, %A"}, |
319 | aa0aa4fa | bellard | {0x0e000450, 0x0ff00ff0, "cfmvsr%c\tmvf%16-19d, %12-15r"}, |
320 | aa0aa4fa | bellard | {0x0e100450, 0x0ff00ff0, "cfmvrs%c\t%12-15r, mvf%16-19d"}, |
321 | aa0aa4fa | bellard | {0x0e000410, 0x0ff00ff0, "cfmvdlr%c\tmvd%16-19d, %12-15r"}, |
322 | aa0aa4fa | bellard | {0x0e100410, 0x0ff00ff0, "cfmvrdl%c\t%12-15r, mvd%16-19d"}, |
323 | aa0aa4fa | bellard | {0x0e000430, 0x0ff00ff0, "cfmvdhr%c\tmvd%16-19d, %12-15r"}, |
324 | aa0aa4fa | bellard | {0x0e100430, 0x0ff00fff, "cfmvrdh%c\t%12-15r, mvd%16-19d"}, |
325 | aa0aa4fa | bellard | {0x0e000510, 0x0ff00fff, "cfmv64lr%c\tmvdx%16-19d, %12-15r"}, |
326 | aa0aa4fa | bellard | {0x0e100510, 0x0ff00fff, "cfmvr64l%c\t%12-15r, mvdx%16-19d"}, |
327 | aa0aa4fa | bellard | {0x0e000530, 0x0ff00fff, "cfmv64hr%c\tmvdx%16-19d, %12-15r"}, |
328 | aa0aa4fa | bellard | {0x0e100530, 0x0ff00fff, "cfmvr64h%c\t%12-15r, mvdx%16-19d"}, |
329 | aa0aa4fa | bellard | {0x0e100610, 0x0ff0fff0, "cfmval32%c\tmvax%0-3d, mvfx%16-19d"}, |
330 | aa0aa4fa | bellard | {0x0e000610, 0x0ff0fff0, "cfmv32al%c\tmvfx%0-3d, mvax%16-19d"}, |
331 | aa0aa4fa | bellard | {0x0e100630, 0x0ff0fff0, "cfmvam32%c\tmvax%0-3d, mvfx%16-19d"}, |
332 | aa0aa4fa | bellard | {0x0e000630, 0x0ff0fff0, "cfmv32am%c\tmvfx%0-3d, mvax%16-19d"}, |
333 | aa0aa4fa | bellard | {0x0e100650, 0x0ff0fff0, "cfmvah32%c\tmvax%0-3d, mvfx%16-19d"}, |
334 | aa0aa4fa | bellard | {0x0e000650, 0x0ff0fff0, "cfmv32ah%c\tmvfx%0-3d, mvax%16-19d"}, |
335 | aa0aa4fa | bellard | {0x0e000670, 0x0ff0fff0, "cfmv32a%c\tmvfx%0-3d, mvax%16-19d"}, |
336 | aa0aa4fa | bellard | {0x0e100670, 0x0ff0fff0, "cfmva32%c\tmvax%0-3d, mvfx%16-19d"}, |
337 | aa0aa4fa | bellard | {0x0e000690, 0x0ff0fff0, "cfmv64a%c\tmvdx%0-3d, mvax%16-19d"}, |
338 | aa0aa4fa | bellard | {0x0e100690, 0x0ff0fff0, "cfmva64%c\tmvax%0-3d, mvdx%16-19d"}, |
339 | aa0aa4fa | bellard | {0x0e1006b0, 0x0ff0fff0, "cfmvsc32%c\tdspsc, mvfx%16-19d"}, |
340 | aa0aa4fa | bellard | {0x0e0006b0, 0x0ff0fff0, "cfmv32sc%c\tmvfx%0-3d, dspsc"}, |
341 | aa0aa4fa | bellard | {0x0e000400, 0x0ff00fff, "cfcpys%c\tmvf%12-15d, mvf%16-19d"}, |
342 | aa0aa4fa | bellard | {0x0e000420, 0x0ff00fff, "cfcpyd%c\tmvd%12-15d, mvd%16-19d"}, |
343 | aa0aa4fa | bellard | {0x0e000460, 0x0ff00fff, "cfcvtsd%c\tmvd%12-15d, mvf%16-19d"}, |
344 | aa0aa4fa | bellard | {0x0e000440, 0x0ff00fff, "cfcvtds%c\tmvf%12-15d, mvd%16-19d"}, |
345 | aa0aa4fa | bellard | {0x0e000480, 0x0ff00fff, "cfcvt32s%c\tmvf%12-15d, mvfx%16-19d"}, |
346 | aa0aa4fa | bellard | {0x0e0004a0, 0x0ff00fff, "cfcvt32d%c\tmvd%12-15d, mvfx%16-19d"}, |
347 | aa0aa4fa | bellard | {0x0e0004c0, 0x0ff00fff, "cfcvt64s%c\tmvf%12-15d, mvdx%16-19d"}, |
348 | aa0aa4fa | bellard | {0x0e0004e0, 0x0ff00fff, "cfcvt64d%c\tmvd%12-15d, mvdx%16-19d"}, |
349 | aa0aa4fa | bellard | {0x0e100580, 0x0ff00fff, "cfcvts32%c\tmvfx%12-15d, mvf%16-19d"}, |
350 | aa0aa4fa | bellard | {0x0e1005a0, 0x0ff00fff, "cfcvtd32%c\tmvfx%12-15d, mvd%16-19d"}, |
351 | aa0aa4fa | bellard | {0x0e1005c0, 0x0ff00fff, "cftruncs32%c\tmvfx%12-15d, mvf%16-19d"}, |
352 | aa0aa4fa | bellard | {0x0e1005e0, 0x0ff00fff, "cftruncd32%c\tmvfx%12-15d, mvd%16-19d"}, |
353 | aa0aa4fa | bellard | {0x0e000550, 0x0ff00ff0, "cfrshl32%c\tmvfx%16-19d, mvfx%0-3d, %12-15r"}, |
354 | aa0aa4fa | bellard | {0x0e000570, 0x0ff00ff0, "cfrshl64%c\tmvdx%16-19d, mvdx%0-3d, %12-15r"}, |
355 | aa0aa4fa | bellard | {0x0e000500, 0x0ff00f00, "cfsh32%c\tmvfx%12-15d, mvfx%16-19d, #%I"}, |
356 | aa0aa4fa | bellard | {0x0e200500, 0x0ff00f00, "cfsh64%c\tmvdx%12-15d, mvdx%16-19d, #%I"}, |
357 | aa0aa4fa | bellard | {0x0e100490, 0x0ff00ff0, "cfcmps%c\t%12-15r, mvf%16-19d, mvf%0-3d"}, |
358 | aa0aa4fa | bellard | {0x0e1004b0, 0x0ff00ff0, "cfcmpd%c\t%12-15r, mvd%16-19d, mvd%0-3d"}, |
359 | aa0aa4fa | bellard | {0x0e100590, 0x0ff00ff0, "cfcmp32%c\t%12-15r, mvfx%16-19d, mvfx%0-3d"}, |
360 | aa0aa4fa | bellard | {0x0e1005b0, 0x0ff00ff0, "cfcmp64%c\t%12-15r, mvdx%16-19d, mvdx%0-3d"}, |
361 | aa0aa4fa | bellard | {0x0e300400, 0x0ff00fff, "cfabss%c\tmvf%12-15d, mvf%16-19d"}, |
362 | aa0aa4fa | bellard | {0x0e300420, 0x0ff00fff, "cfabsd%c\tmvd%12-15d, mvd%16-19d"}, |
363 | aa0aa4fa | bellard | {0x0e300440, 0x0ff00fff, "cfnegs%c\tmvf%12-15d, mvf%16-19d"}, |
364 | aa0aa4fa | bellard | {0x0e300460, 0x0ff00fff, "cfnegd%c\tmvd%12-15d, mvd%16-19d"}, |
365 | aa0aa4fa | bellard | {0x0e300480, 0x0ff00ff0, "cfadds%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"}, |
366 | aa0aa4fa | bellard | {0x0e3004a0, 0x0ff00ff0, "cfaddd%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"}, |
367 | aa0aa4fa | bellard | {0x0e3004c0, 0x0ff00ff0, "cfsubs%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"}, |
368 | aa0aa4fa | bellard | {0x0e3004e0, 0x0ff00ff0, "cfsubd%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"}, |
369 | aa0aa4fa | bellard | {0x0e100400, 0x0ff00ff0, "cfmuls%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"}, |
370 | aa0aa4fa | bellard | {0x0e100420, 0x0ff00ff0, "cfmuld%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"}, |
371 | aa0aa4fa | bellard | {0x0e300500, 0x0ff00fff, "cfabs32%c\tmvfx%12-15d, mvfx%16-19d"}, |
372 | aa0aa4fa | bellard | {0x0e300520, 0x0ff00fff, "cfabs64%c\tmvdx%12-15d, mvdx%16-19d"}, |
373 | aa0aa4fa | bellard | {0x0e300540, 0x0ff00fff, "cfneg32%c\tmvfx%12-15d, mvfx%16-19d"}, |
374 | aa0aa4fa | bellard | {0x0e300560, 0x0ff00fff, "cfneg64%c\tmvdx%12-15d, mvdx%16-19d"}, |
375 | aa0aa4fa | bellard | {0x0e300580, 0x0ff00ff0, "cfadd32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"}, |
376 | aa0aa4fa | bellard | {0x0e3005a0, 0x0ff00ff0, "cfadd64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"}, |
377 | aa0aa4fa | bellard | {0x0e3005c0, 0x0ff00ff0, "cfsub32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"}, |
378 | aa0aa4fa | bellard | {0x0e3005e0, 0x0ff00ff0, "cfsub64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"}, |
379 | aa0aa4fa | bellard | {0x0e100500, 0x0ff00ff0, "cfmul32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"}, |
380 | aa0aa4fa | bellard | {0x0e100520, 0x0ff00ff0, "cfmul64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"}, |
381 | aa0aa4fa | bellard | {0x0e100540, 0x0ff00ff0, "cfmac32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"}, |
382 | aa0aa4fa | bellard | {0x0e100560, 0x0ff00ff0, "cfmsc32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"}, |
383 | aa0aa4fa | bellard | {0x0e000600, 0x0ff00f00, "cfmadd32%c\tmvax%5-7d, mvfx%12-15d, mvfx%16-19d, mvfx%0-3d"}, |
384 | aa0aa4fa | bellard | {0x0e100600, 0x0ff00f00, "cfmsub32%c\tmvax%5-7d, mvfx%12-15d, mvfx%16-19d, mvfx%0-3d"}, |
385 | aa0aa4fa | bellard | {0x0e200600, 0x0ff00f00, "cfmadda32%c\tmvax%5-7d, mvax%12-15d, mvfx%16-19d, mvfx%0-3d"}, |
386 | aa0aa4fa | bellard | {0x0e300600, 0x0ff00f00, "cfmsuba32%c\tmvax%5-7d, mvax%12-15d, mvfx%16-19d, mvfx%0-3d"}, |
387 | aa0aa4fa | bellard | |
388 | aa0aa4fa | bellard | /* Generic coprocessor instructions */
|
389 | aa0aa4fa | bellard | {0x0e000000, 0x0f000010, "cdp%c\t%8-11d, %20-23d, cr%12-15d, cr%16-19d, cr%0-3d, {%5-7d}"}, |
390 | aa0aa4fa | bellard | {0x0e100010, 0x0f100010, "mrc%c\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"}, |
391 | aa0aa4fa | bellard | {0x0e000010, 0x0f100010, "mcr%c\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"}, |
392 | aa0aa4fa | bellard | {0x0c000000, 0x0e100000, "stc%c%22'l\t%8-11d, cr%12-15d, %A"}, |
393 | aa0aa4fa | bellard | {0x0c100000, 0x0e100000, "ldc%c%22'l\t%8-11d, cr%12-15d, %A"}, |
394 | aa0aa4fa | bellard | |
395 | aa0aa4fa | bellard | /* The rest. */
|
396 | aa0aa4fa | bellard | {0x00000000, 0x00000000, "undefined instruction %0-31x"}, |
397 | aa0aa4fa | bellard | {0x00000000, 0x00000000, 0} |
398 | aa0aa4fa | bellard | }; |
399 | aa0aa4fa | bellard | |
400 | aa0aa4fa | bellard | #define BDISP(x) ((((x) & 0xffffff) ^ 0x800000) - 0x800000) /* 26 bit */ |
401 | aa0aa4fa | bellard | |
402 | aa0aa4fa | bellard | static struct thumb_opcode thumb_opcodes[] = |
403 | aa0aa4fa | bellard | { |
404 | aa0aa4fa | bellard | /* Thumb instructions. */
|
405 | aa0aa4fa | bellard | |
406 | aa0aa4fa | bellard | /* ARM V5 ISA extends Thumb. */
|
407 | aa0aa4fa | bellard | {0xbe00, 0xff00, "bkpt\t%0-7x"}, |
408 | aa0aa4fa | bellard | {0x4780, 0xff87, "blx\t%3-6r"}, /* note: 4 bit register number. */ |
409 | aa0aa4fa | bellard | /* Note: this is BLX(2). BLX(1) is done in arm-dis.c/print_insn_thumb()
|
410 | aa0aa4fa | bellard | as an extension of the special processing there for Thumb BL.
|
411 | aa0aa4fa | bellard | BL and BLX(1) involve 2 successive 16-bit instructions, which must
|
412 | aa0aa4fa | bellard | always appear together in the correct order. So, the empty
|
413 | aa0aa4fa | bellard | string is put in this table, and the string interpreter takes <empty>
|
414 | aa0aa4fa | bellard | to mean it has a pair of BL-ish instructions. */
|
415 | aa0aa4fa | bellard | {0x46C0, 0xFFFF, "nop\t\t\t(mov r8, r8)"}, |
416 | aa0aa4fa | bellard | /* Format 5 instructions do not update the PSR. */
|
417 | aa0aa4fa | bellard | {0x1C00, 0xFFC0, "mov\t%0-2r, %3-5r\t\t(add %0-2r, %3-5r, #%6-8d)"}, |
418 | aa0aa4fa | bellard | /* Format 4. */
|
419 | aa0aa4fa | bellard | {0x4000, 0xFFC0, "and\t%0-2r, %3-5r"}, |
420 | aa0aa4fa | bellard | {0x4040, 0xFFC0, "eor\t%0-2r, %3-5r"}, |
421 | aa0aa4fa | bellard | {0x4080, 0xFFC0, "lsl\t%0-2r, %3-5r"}, |
422 | aa0aa4fa | bellard | {0x40C0, 0xFFC0, "lsr\t%0-2r, %3-5r"}, |
423 | aa0aa4fa | bellard | {0x4100, 0xFFC0, "asr\t%0-2r, %3-5r"}, |
424 | aa0aa4fa | bellard | {0x4140, 0xFFC0, "adc\t%0-2r, %3-5r"}, |
425 | aa0aa4fa | bellard | {0x4180, 0xFFC0, "sbc\t%0-2r, %3-5r"}, |
426 | aa0aa4fa | bellard | {0x41C0, 0xFFC0, "ror\t%0-2r, %3-5r"}, |
427 | aa0aa4fa | bellard | {0x4200, 0xFFC0, "tst\t%0-2r, %3-5r"}, |
428 | aa0aa4fa | bellard | {0x4240, 0xFFC0, "neg\t%0-2r, %3-5r"}, |
429 | aa0aa4fa | bellard | {0x4280, 0xFFC0, "cmp\t%0-2r, %3-5r"}, |
430 | aa0aa4fa | bellard | {0x42C0, 0xFFC0, "cmn\t%0-2r, %3-5r"}, |
431 | aa0aa4fa | bellard | {0x4300, 0xFFC0, "orr\t%0-2r, %3-5r"}, |
432 | aa0aa4fa | bellard | {0x4340, 0xFFC0, "mul\t%0-2r, %3-5r"}, |
433 | aa0aa4fa | bellard | {0x4380, 0xFFC0, "bic\t%0-2r, %3-5r"}, |
434 | aa0aa4fa | bellard | {0x43C0, 0xFFC0, "mvn\t%0-2r, %3-5r"}, |
435 | aa0aa4fa | bellard | /* format 13 */
|
436 | aa0aa4fa | bellard | {0xB000, 0xFF80, "add\tsp, #%0-6W"}, |
437 | aa0aa4fa | bellard | {0xB080, 0xFF80, "sub\tsp, #%0-6W"}, |
438 | aa0aa4fa | bellard | /* format 5 */
|
439 | aa0aa4fa | bellard | {0x4700, 0xFF80, "bx\t%S"}, |
440 | aa0aa4fa | bellard | {0x4400, 0xFF00, "add\t%D, %S"}, |
441 | aa0aa4fa | bellard | {0x4500, 0xFF00, "cmp\t%D, %S"}, |
442 | aa0aa4fa | bellard | {0x4600, 0xFF00, "mov\t%D, %S"}, |
443 | aa0aa4fa | bellard | /* format 14 */
|
444 | aa0aa4fa | bellard | {0xB400, 0xFE00, "push\t%N"}, |
445 | aa0aa4fa | bellard | {0xBC00, 0xFE00, "pop\t%O"}, |
446 | aa0aa4fa | bellard | /* format 2 */
|
447 | aa0aa4fa | bellard | {0x1800, 0xFE00, "add\t%0-2r, %3-5r, %6-8r"}, |
448 | aa0aa4fa | bellard | {0x1A00, 0xFE00, "sub\t%0-2r, %3-5r, %6-8r"}, |
449 | aa0aa4fa | bellard | {0x1C00, 0xFE00, "add\t%0-2r, %3-5r, #%6-8d"}, |
450 | aa0aa4fa | bellard | {0x1E00, 0xFE00, "sub\t%0-2r, %3-5r, #%6-8d"}, |
451 | aa0aa4fa | bellard | /* format 8 */
|
452 | aa0aa4fa | bellard | {0x5200, 0xFE00, "strh\t%0-2r, [%3-5r, %6-8r]"}, |
453 | aa0aa4fa | bellard | {0x5A00, 0xFE00, "ldrh\t%0-2r, [%3-5r, %6-8r]"}, |
454 | aa0aa4fa | bellard | {0x5600, 0xF600, "ldrs%11?hb\t%0-2r, [%3-5r, %6-8r]"}, |
455 | aa0aa4fa | bellard | /* format 7 */
|
456 | aa0aa4fa | bellard | {0x5000, 0xFA00, "str%10'b\t%0-2r, [%3-5r, %6-8r]"}, |
457 | aa0aa4fa | bellard | {0x5800, 0xFA00, "ldr%10'b\t%0-2r, [%3-5r, %6-8r]"}, |
458 | aa0aa4fa | bellard | /* format 1 */
|
459 | aa0aa4fa | bellard | {0x0000, 0xF800, "lsl\t%0-2r, %3-5r, #%6-10d"}, |
460 | aa0aa4fa | bellard | {0x0800, 0xF800, "lsr\t%0-2r, %3-5r, #%6-10d"}, |
461 | aa0aa4fa | bellard | {0x1000, 0xF800, "asr\t%0-2r, %3-5r, #%6-10d"}, |
462 | aa0aa4fa | bellard | /* format 3 */
|
463 | aa0aa4fa | bellard | {0x2000, 0xF800, "mov\t%8-10r, #%0-7d"}, |
464 | aa0aa4fa | bellard | {0x2800, 0xF800, "cmp\t%8-10r, #%0-7d"}, |
465 | aa0aa4fa | bellard | {0x3000, 0xF800, "add\t%8-10r, #%0-7d"}, |
466 | aa0aa4fa | bellard | {0x3800, 0xF800, "sub\t%8-10r, #%0-7d"}, |
467 | aa0aa4fa | bellard | /* format 6 */
|
468 | aa0aa4fa | bellard | {0x4800, 0xF800, "ldr\t%8-10r, [pc, #%0-7W]\t(%0-7a)"}, /* TODO: Disassemble PC relative "LDR rD,=<symbolic>" */ |
469 | aa0aa4fa | bellard | /* format 9 */
|
470 | aa0aa4fa | bellard | {0x6000, 0xF800, "str\t%0-2r, [%3-5r, #%6-10W]"}, |
471 | aa0aa4fa | bellard | {0x6800, 0xF800, "ldr\t%0-2r, [%3-5r, #%6-10W]"}, |
472 | aa0aa4fa | bellard | {0x7000, 0xF800, "strb\t%0-2r, [%3-5r, #%6-10d]"}, |
473 | aa0aa4fa | bellard | {0x7800, 0xF800, "ldrb\t%0-2r, [%3-5r, #%6-10d]"}, |
474 | aa0aa4fa | bellard | /* format 10 */
|
475 | aa0aa4fa | bellard | {0x8000, 0xF800, "strh\t%0-2r, [%3-5r, #%6-10H]"}, |
476 | aa0aa4fa | bellard | {0x8800, 0xF800, "ldrh\t%0-2r, [%3-5r, #%6-10H]"}, |
477 | aa0aa4fa | bellard | /* format 11 */
|
478 | aa0aa4fa | bellard | {0x9000, 0xF800, "str\t%8-10r, [sp, #%0-7W]"}, |
479 | aa0aa4fa | bellard | {0x9800, 0xF800, "ldr\t%8-10r, [sp, #%0-7W]"}, |
480 | aa0aa4fa | bellard | /* format 12 */
|
481 | aa0aa4fa | bellard | {0xA000, 0xF800, "add\t%8-10r, pc, #%0-7W\t(adr %8-10r,%0-7a)"}, |
482 | aa0aa4fa | bellard | {0xA800, 0xF800, "add\t%8-10r, sp, #%0-7W"}, |
483 | aa0aa4fa | bellard | /* format 15 */
|
484 | aa0aa4fa | bellard | {0xC000, 0xF800, "stmia\t%8-10r!,%M"}, |
485 | aa0aa4fa | bellard | {0xC800, 0xF800, "ldmia\t%8-10r!,%M"}, |
486 | aa0aa4fa | bellard | /* format 18 */
|
487 | aa0aa4fa | bellard | {0xE000, 0xF800, "b\t%0-10B"}, |
488 | aa0aa4fa | bellard | {0xE800, 0xF800, "undefined"}, |
489 | aa0aa4fa | bellard | /* format 19 */
|
490 | aa0aa4fa | bellard | {0xF000, 0xF800, ""}, /* special processing required in disassembler */ |
491 | aa0aa4fa | bellard | {0xF800, 0xF800, "second half of BL instruction %0-15x"}, |
492 | aa0aa4fa | bellard | /* format 16 */
|
493 | aa0aa4fa | bellard | {0xD000, 0xFF00, "beq\t%0-7B"}, |
494 | aa0aa4fa | bellard | {0xD100, 0xFF00, "bne\t%0-7B"}, |
495 | aa0aa4fa | bellard | {0xD200, 0xFF00, "bcs\t%0-7B"}, |
496 | aa0aa4fa | bellard | {0xD300, 0xFF00, "bcc\t%0-7B"}, |
497 | aa0aa4fa | bellard | {0xD400, 0xFF00, "bmi\t%0-7B"}, |
498 | aa0aa4fa | bellard | {0xD500, 0xFF00, "bpl\t%0-7B"}, |
499 | aa0aa4fa | bellard | {0xD600, 0xFF00, "bvs\t%0-7B"}, |
500 | aa0aa4fa | bellard | {0xD700, 0xFF00, "bvc\t%0-7B"}, |
501 | aa0aa4fa | bellard | {0xD800, 0xFF00, "bhi\t%0-7B"}, |
502 | aa0aa4fa | bellard | {0xD900, 0xFF00, "bls\t%0-7B"}, |
503 | aa0aa4fa | bellard | {0xDA00, 0xFF00, "bge\t%0-7B"}, |
504 | aa0aa4fa | bellard | {0xDB00, 0xFF00, "blt\t%0-7B"}, |
505 | aa0aa4fa | bellard | {0xDC00, 0xFF00, "bgt\t%0-7B"}, |
506 | aa0aa4fa | bellard | {0xDD00, 0xFF00, "ble\t%0-7B"}, |
507 | aa0aa4fa | bellard | /* format 17 */
|
508 | aa0aa4fa | bellard | {0xDE00, 0xFF00, "bal\t%0-7B"}, |
509 | aa0aa4fa | bellard | {0xDF00, 0xFF00, "swi\t%0-7d"}, |
510 | aa0aa4fa | bellard | /* format 9 */
|
511 | aa0aa4fa | bellard | {0x6000, 0xF800, "str\t%0-2r, [%3-5r, #%6-10W]"}, |
512 | aa0aa4fa | bellard | {0x6800, 0xF800, "ldr\t%0-2r, [%3-5r, #%6-10W]"}, |
513 | aa0aa4fa | bellard | {0x7000, 0xF800, "strb\t%0-2r, [%3-5r, #%6-10d]"}, |
514 | aa0aa4fa | bellard | {0x7800, 0xF800, "ldrb\t%0-2r, [%3-5r, #%6-10d]"}, |
515 | aa0aa4fa | bellard | /* the rest */
|
516 | aa0aa4fa | bellard | {0x0000, 0x0000, "undefined instruction %0-15x"}, |
517 | aa0aa4fa | bellard | {0x0000, 0x0000, 0} |
518 | aa0aa4fa | bellard | }; |
519 | aa0aa4fa | bellard | |
520 | aa0aa4fa | bellard | #define BDISP23(x) ((((((x) & 0x07ff) << 11) | (((x) & 0x07ff0000) >> 16)) \ |
521 | aa0aa4fa | bellard | ^ 0x200000) - 0x200000) /* 23bit */ |
522 | aa0aa4fa | bellard | |
523 | aa0aa4fa | bellard | #ifndef streq
|
524 | aa0aa4fa | bellard | #define streq(a,b) (strcmp ((a), (b)) == 0) |
525 | aa0aa4fa | bellard | #endif
|
526 | aa0aa4fa | bellard | |
527 | aa0aa4fa | bellard | #ifndef strneq
|
528 | aa0aa4fa | bellard | #define strneq(a,b,n) (strncmp ((a), (b), (n)) == 0) |
529 | aa0aa4fa | bellard | #endif
|
530 | aa0aa4fa | bellard | |
531 | aa0aa4fa | bellard | #ifndef NUM_ELEM
|
532 | aa0aa4fa | bellard | #define NUM_ELEM(a) (sizeof (a) / sizeof (a)[0]) |
533 | aa0aa4fa | bellard | #endif
|
534 | aa0aa4fa | bellard | |
535 | aa0aa4fa | bellard | static char * arm_conditional[] = |
536 | aa0aa4fa | bellard | {"eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc", |
537 | aa0aa4fa | bellard | "hi", "ls", "ge", "lt", "gt", "le", "", "nv"}; |
538 | aa0aa4fa | bellard | |
539 | aa0aa4fa | bellard | typedef struct |
540 | aa0aa4fa | bellard | { |
541 | aa0aa4fa | bellard | const char * name; |
542 | aa0aa4fa | bellard | const char * description; |
543 | aa0aa4fa | bellard | const char * reg_names[16]; |
544 | aa0aa4fa | bellard | } |
545 | aa0aa4fa | bellard | arm_regname; |
546 | aa0aa4fa | bellard | |
547 | aa0aa4fa | bellard | static arm_regname regnames[] =
|
548 | aa0aa4fa | bellard | { |
549 | aa0aa4fa | bellard | { "raw" , "Select raw register names", |
550 | aa0aa4fa | bellard | { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"}}, |
551 | aa0aa4fa | bellard | { "gcc", "Select register names used by GCC", |
552 | aa0aa4fa | bellard | { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "sl", "fp", "ip", "sp", "lr", "pc" }}, |
553 | aa0aa4fa | bellard | { "std", "Select register names used in ARM's ISA documentation", |
554 | aa0aa4fa | bellard | { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "sp", "lr", "pc" }}, |
555 | aa0aa4fa | bellard | { "apcs", "Select register names used in the APCS", |
556 | aa0aa4fa | bellard | { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "v4", "v5", "v6", "sl", "fp", "ip", "sp", "lr", "pc" }}, |
557 | aa0aa4fa | bellard | { "atpcs", "Select register names used in the ATPCS", |
558 | aa0aa4fa | bellard | { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "IP", "SP", "LR", "PC" }}, |
559 | aa0aa4fa | bellard | { "special-atpcs", "Select special register names used in the ATPCS", |
560 | aa0aa4fa | bellard | { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "WR", "v5", "SB", "SL", "FP", "IP", "SP", "LR", "PC" }} |
561 | aa0aa4fa | bellard | }; |
562 | aa0aa4fa | bellard | |
563 | 6e295807 | bellard | /* Default to STD register name set. */
|
564 | 6e295807 | bellard | static unsigned int regname_selected = 2; |
565 | aa0aa4fa | bellard | |
566 | aa0aa4fa | bellard | #define NUM_ARM_REGNAMES NUM_ELEM (regnames)
|
567 | aa0aa4fa | bellard | #define arm_regnames regnames[regname_selected].reg_names
|
568 | aa0aa4fa | bellard | |
569 | aa0aa4fa | bellard | static boolean force_thumb = false; |
570 | aa0aa4fa | bellard | |
571 | aa0aa4fa | bellard | static char * arm_fp_const[] = |
572 | aa0aa4fa | bellard | {"0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0"}; |
573 | aa0aa4fa | bellard | |
574 | aa0aa4fa | bellard | static char * arm_shift[] = |
575 | aa0aa4fa | bellard | {"lsl", "lsr", "asr", "ror"}; |
576 | aa0aa4fa | bellard | |
577 | aa0aa4fa | bellard | /* Forward declarations. */
|
578 | aa0aa4fa | bellard | static void arm_decode_shift PARAMS ((long, fprintf_ftype, void *)); |
579 | aa0aa4fa | bellard | static int print_insn_arm1 PARAMS ((bfd_vma, struct disassemble_info *, long)); |
580 | aa0aa4fa | bellard | static int print_insn_thumb PARAMS ((bfd_vma, struct disassemble_info *, long)); |
581 | aa0aa4fa | bellard | static void parse_disassembler_options PARAMS ((char *)); |
582 | aa0aa4fa | bellard | int get_arm_regname_num_options (void); |
583 | aa0aa4fa | bellard | int set_arm_regname_option (int option); |
584 | aa0aa4fa | bellard | int get_arm_regnames (int option, const char **setname, |
585 | aa0aa4fa | bellard | const char **setdescription, |
586 | aa0aa4fa | bellard | const char ***register_names); |
587 | aa0aa4fa | bellard | |
588 | aa0aa4fa | bellard | /* Functions. */
|
589 | aa0aa4fa | bellard | int
|
590 | aa0aa4fa | bellard | get_arm_regname_num_options () |
591 | aa0aa4fa | bellard | { |
592 | aa0aa4fa | bellard | return NUM_ARM_REGNAMES;
|
593 | aa0aa4fa | bellard | } |
594 | aa0aa4fa | bellard | |
595 | aa0aa4fa | bellard | int
|
596 | aa0aa4fa | bellard | set_arm_regname_option (option) |
597 | aa0aa4fa | bellard | int option;
|
598 | aa0aa4fa | bellard | { |
599 | aa0aa4fa | bellard | int old = regname_selected;
|
600 | aa0aa4fa | bellard | regname_selected = option; |
601 | aa0aa4fa | bellard | return old;
|
602 | aa0aa4fa | bellard | } |
603 | aa0aa4fa | bellard | |
604 | aa0aa4fa | bellard | int
|
605 | aa0aa4fa | bellard | get_arm_regnames (option, setname, setdescription, register_names) |
606 | aa0aa4fa | bellard | int option;
|
607 | aa0aa4fa | bellard | const char **setname; |
608 | aa0aa4fa | bellard | const char **setdescription; |
609 | aa0aa4fa | bellard | const char ***register_names; |
610 | aa0aa4fa | bellard | { |
611 | aa0aa4fa | bellard | *setname = regnames[option].name; |
612 | aa0aa4fa | bellard | *setdescription = regnames[option].description; |
613 | aa0aa4fa | bellard | *register_names = regnames[option].reg_names; |
614 | aa0aa4fa | bellard | return 16; |
615 | aa0aa4fa | bellard | } |
616 | aa0aa4fa | bellard | |
617 | aa0aa4fa | bellard | static void |
618 | aa0aa4fa | bellard | arm_decode_shift (given, func, stream) |
619 | aa0aa4fa | bellard | long given;
|
620 | aa0aa4fa | bellard | fprintf_ftype func; |
621 | aa0aa4fa | bellard | void * stream;
|
622 | aa0aa4fa | bellard | { |
623 | aa0aa4fa | bellard | func (stream, "%s", arm_regnames[given & 0xf]); |
624 | aa0aa4fa | bellard | |
625 | aa0aa4fa | bellard | if ((given & 0xff0) != 0) |
626 | aa0aa4fa | bellard | { |
627 | aa0aa4fa | bellard | if ((given & 0x10) == 0) |
628 | aa0aa4fa | bellard | { |
629 | aa0aa4fa | bellard | int amount = (given & 0xf80) >> 7; |
630 | aa0aa4fa | bellard | int shift = (given & 0x60) >> 5; |
631 | aa0aa4fa | bellard | |
632 | aa0aa4fa | bellard | if (amount == 0) |
633 | aa0aa4fa | bellard | { |
634 | aa0aa4fa | bellard | if (shift == 3) |
635 | aa0aa4fa | bellard | { |
636 | aa0aa4fa | bellard | func (stream, ", rrx");
|
637 | aa0aa4fa | bellard | return;
|
638 | aa0aa4fa | bellard | } |
639 | aa0aa4fa | bellard | |
640 | aa0aa4fa | bellard | amount = 32;
|
641 | aa0aa4fa | bellard | } |
642 | aa0aa4fa | bellard | |
643 | aa0aa4fa | bellard | func (stream, ", %s #%d", arm_shift[shift], amount);
|
644 | aa0aa4fa | bellard | } |
645 | aa0aa4fa | bellard | else
|
646 | aa0aa4fa | bellard | func (stream, ", %s %s", arm_shift[(given & 0x60) >> 5], |
647 | aa0aa4fa | bellard | arm_regnames[(given & 0xf00) >> 8]); |
648 | aa0aa4fa | bellard | } |
649 | aa0aa4fa | bellard | } |
650 | aa0aa4fa | bellard | |
651 | aa0aa4fa | bellard | /* Print one instruction from PC on INFO->STREAM.
|
652 | aa0aa4fa | bellard | Return the size of the instruction (always 4 on ARM). */
|
653 | aa0aa4fa | bellard | |
654 | aa0aa4fa | bellard | static int |
655 | aa0aa4fa | bellard | print_insn_arm1 (pc, info, given) |
656 | aa0aa4fa | bellard | bfd_vma pc; |
657 | aa0aa4fa | bellard | struct disassemble_info * info;
|
658 | aa0aa4fa | bellard | long given;
|
659 | aa0aa4fa | bellard | { |
660 | aa0aa4fa | bellard | struct arm_opcode * insn;
|
661 | aa0aa4fa | bellard | void * stream = info->stream;
|
662 | aa0aa4fa | bellard | fprintf_ftype func = info->fprintf_func; |
663 | aa0aa4fa | bellard | |
664 | aa0aa4fa | bellard | for (insn = arm_opcodes; insn->assembler; insn++)
|
665 | aa0aa4fa | bellard | { |
666 | aa0aa4fa | bellard | if ((given & insn->mask) == insn->value)
|
667 | aa0aa4fa | bellard | { |
668 | aa0aa4fa | bellard | char * c;
|
669 | aa0aa4fa | bellard | |
670 | aa0aa4fa | bellard | for (c = insn->assembler; *c; c++)
|
671 | aa0aa4fa | bellard | { |
672 | aa0aa4fa | bellard | if (*c == '%') |
673 | aa0aa4fa | bellard | { |
674 | aa0aa4fa | bellard | switch (*++c)
|
675 | aa0aa4fa | bellard | { |
676 | aa0aa4fa | bellard | case '%': |
677 | aa0aa4fa | bellard | func (stream, "%%");
|
678 | aa0aa4fa | bellard | break;
|
679 | aa0aa4fa | bellard | |
680 | aa0aa4fa | bellard | case 'a': |
681 | aa0aa4fa | bellard | if (((given & 0x000f0000) == 0x000f0000) |
682 | aa0aa4fa | bellard | && ((given & 0x02000000) == 0)) |
683 | aa0aa4fa | bellard | { |
684 | aa0aa4fa | bellard | int offset = given & 0xfff; |
685 | aa0aa4fa | bellard | |
686 | aa0aa4fa | bellard | func (stream, "[pc");
|
687 | aa0aa4fa | bellard | |
688 | aa0aa4fa | bellard | if (given & 0x01000000) |
689 | aa0aa4fa | bellard | { |
690 | aa0aa4fa | bellard | if ((given & 0x00800000) == 0) |
691 | aa0aa4fa | bellard | offset = - offset; |
692 | aa0aa4fa | bellard | |
693 | aa0aa4fa | bellard | /* Pre-indexed. */
|
694 | aa0aa4fa | bellard | func (stream, ", #%d]", offset);
|
695 | aa0aa4fa | bellard | |
696 | aa0aa4fa | bellard | offset += pc + 8;
|
697 | aa0aa4fa | bellard | |
698 | aa0aa4fa | bellard | /* Cope with the possibility of write-back
|
699 | aa0aa4fa | bellard | being used. Probably a very dangerous thing
|
700 | aa0aa4fa | bellard | for the programmer to do, but who are we to
|
701 | aa0aa4fa | bellard | argue ? */
|
702 | aa0aa4fa | bellard | if (given & 0x00200000) |
703 | aa0aa4fa | bellard | func (stream, "!");
|
704 | aa0aa4fa | bellard | } |
705 | aa0aa4fa | bellard | else
|
706 | aa0aa4fa | bellard | { |
707 | aa0aa4fa | bellard | /* Post indexed. */
|
708 | aa0aa4fa | bellard | func (stream, "], #%d", offset);
|
709 | aa0aa4fa | bellard | |
710 | aa0aa4fa | bellard | /* ie ignore the offset. */
|
711 | aa0aa4fa | bellard | offset = pc + 8;
|
712 | aa0aa4fa | bellard | } |
713 | aa0aa4fa | bellard | |
714 | aa0aa4fa | bellard | func (stream, "\t; ");
|
715 | aa0aa4fa | bellard | info->print_address_func (offset, info); |
716 | aa0aa4fa | bellard | } |
717 | aa0aa4fa | bellard | else
|
718 | aa0aa4fa | bellard | { |
719 | aa0aa4fa | bellard | func (stream, "[%s",
|
720 | aa0aa4fa | bellard | arm_regnames[(given >> 16) & 0xf]); |
721 | aa0aa4fa | bellard | if ((given & 0x01000000) != 0) |
722 | aa0aa4fa | bellard | { |
723 | aa0aa4fa | bellard | if ((given & 0x02000000) == 0) |
724 | aa0aa4fa | bellard | { |
725 | aa0aa4fa | bellard | int offset = given & 0xfff; |
726 | aa0aa4fa | bellard | if (offset)
|
727 | aa0aa4fa | bellard | func (stream, ", %s#%d",
|
728 | aa0aa4fa | bellard | (((given & 0x00800000) == 0) |
729 | aa0aa4fa | bellard | ? "-" : ""), offset); |
730 | aa0aa4fa | bellard | } |
731 | aa0aa4fa | bellard | else
|
732 | aa0aa4fa | bellard | { |
733 | aa0aa4fa | bellard | func (stream, ", %s",
|
734 | aa0aa4fa | bellard | (((given & 0x00800000) == 0) |
735 | aa0aa4fa | bellard | ? "-" : "")); |
736 | aa0aa4fa | bellard | arm_decode_shift (given, func, stream); |
737 | aa0aa4fa | bellard | } |
738 | aa0aa4fa | bellard | |
739 | aa0aa4fa | bellard | func (stream, "]%s",
|
740 | aa0aa4fa | bellard | ((given & 0x00200000) != 0) ? "!" : ""); |
741 | aa0aa4fa | bellard | } |
742 | aa0aa4fa | bellard | else
|
743 | aa0aa4fa | bellard | { |
744 | aa0aa4fa | bellard | if ((given & 0x02000000) == 0) |
745 | aa0aa4fa | bellard | { |
746 | aa0aa4fa | bellard | int offset = given & 0xfff; |
747 | aa0aa4fa | bellard | if (offset)
|
748 | aa0aa4fa | bellard | func (stream, "], %s#%d",
|
749 | aa0aa4fa | bellard | (((given & 0x00800000) == 0) |
750 | aa0aa4fa | bellard | ? "-" : ""), offset); |
751 | aa0aa4fa | bellard | else
|
752 | aa0aa4fa | bellard | func (stream, "]");
|
753 | aa0aa4fa | bellard | } |
754 | aa0aa4fa | bellard | else
|
755 | aa0aa4fa | bellard | { |
756 | aa0aa4fa | bellard | func (stream, "], %s",
|
757 | aa0aa4fa | bellard | (((given & 0x00800000) == 0) |
758 | aa0aa4fa | bellard | ? "-" : "")); |
759 | aa0aa4fa | bellard | arm_decode_shift (given, func, stream); |
760 | aa0aa4fa | bellard | } |
761 | aa0aa4fa | bellard | } |
762 | aa0aa4fa | bellard | } |
763 | aa0aa4fa | bellard | break;
|
764 | aa0aa4fa | bellard | |
765 | aa0aa4fa | bellard | case 's': |
766 | aa0aa4fa | bellard | if ((given & 0x004f0000) == 0x004f0000) |
767 | aa0aa4fa | bellard | { |
768 | aa0aa4fa | bellard | /* PC relative with immediate offset. */
|
769 | aa0aa4fa | bellard | int offset = ((given & 0xf00) >> 4) | (given & 0xf); |
770 | aa0aa4fa | bellard | |
771 | aa0aa4fa | bellard | if ((given & 0x00800000) == 0) |
772 | aa0aa4fa | bellard | offset = -offset; |
773 | aa0aa4fa | bellard | |
774 | aa0aa4fa | bellard | func (stream, "[pc, #%d]\t; ", offset);
|
775 | aa0aa4fa | bellard | |
776 | aa0aa4fa | bellard | (*info->print_address_func) |
777 | aa0aa4fa | bellard | (offset + pc + 8, info);
|
778 | aa0aa4fa | bellard | } |
779 | aa0aa4fa | bellard | else
|
780 | aa0aa4fa | bellard | { |
781 | aa0aa4fa | bellard | func (stream, "[%s",
|
782 | aa0aa4fa | bellard | arm_regnames[(given >> 16) & 0xf]); |
783 | aa0aa4fa | bellard | if ((given & 0x01000000) != 0) |
784 | aa0aa4fa | bellard | { |
785 | aa0aa4fa | bellard | /* Pre-indexed. */
|
786 | aa0aa4fa | bellard | if ((given & 0x00400000) == 0x00400000) |
787 | aa0aa4fa | bellard | { |
788 | aa0aa4fa | bellard | /* Immediate. */
|
789 | aa0aa4fa | bellard | int offset = ((given & 0xf00) >> 4) | (given & 0xf); |
790 | aa0aa4fa | bellard | if (offset)
|
791 | aa0aa4fa | bellard | func (stream, ", %s#%d",
|
792 | aa0aa4fa | bellard | (((given & 0x00800000) == 0) |
793 | aa0aa4fa | bellard | ? "-" : ""), offset); |
794 | aa0aa4fa | bellard | } |
795 | aa0aa4fa | bellard | else
|
796 | aa0aa4fa | bellard | { |
797 | aa0aa4fa | bellard | /* Register. */
|
798 | aa0aa4fa | bellard | func (stream, ", %s%s",
|
799 | aa0aa4fa | bellard | (((given & 0x00800000) == 0) |
800 | aa0aa4fa | bellard | ? "-" : ""), |
801 | aa0aa4fa | bellard | arm_regnames[given & 0xf]);
|
802 | aa0aa4fa | bellard | } |
803 | aa0aa4fa | bellard | |
804 | aa0aa4fa | bellard | func (stream, "]%s",
|
805 | aa0aa4fa | bellard | ((given & 0x00200000) != 0) ? "!" : ""); |
806 | aa0aa4fa | bellard | } |
807 | aa0aa4fa | bellard | else
|
808 | aa0aa4fa | bellard | { |
809 | aa0aa4fa | bellard | /* Post-indexed. */
|
810 | aa0aa4fa | bellard | if ((given & 0x00400000) == 0x00400000) |
811 | aa0aa4fa | bellard | { |
812 | aa0aa4fa | bellard | /* Immediate. */
|
813 | aa0aa4fa | bellard | int offset = ((given & 0xf00) >> 4) | (given & 0xf); |
814 | aa0aa4fa | bellard | if (offset)
|
815 | aa0aa4fa | bellard | func (stream, "], %s#%d",
|
816 | aa0aa4fa | bellard | (((given & 0x00800000) == 0) |
817 | aa0aa4fa | bellard | ? "-" : ""), offset); |
818 | aa0aa4fa | bellard | else
|
819 | aa0aa4fa | bellard | func (stream, "]");
|
820 | aa0aa4fa | bellard | } |
821 | aa0aa4fa | bellard | else
|
822 | aa0aa4fa | bellard | { |
823 | aa0aa4fa | bellard | /* Register. */
|
824 | aa0aa4fa | bellard | func (stream, "], %s%s",
|
825 | aa0aa4fa | bellard | (((given & 0x00800000) == 0) |
826 | aa0aa4fa | bellard | ? "-" : ""), |
827 | aa0aa4fa | bellard | arm_regnames[given & 0xf]);
|
828 | aa0aa4fa | bellard | } |
829 | aa0aa4fa | bellard | } |
830 | aa0aa4fa | bellard | } |
831 | aa0aa4fa | bellard | break;
|
832 | aa0aa4fa | bellard | |
833 | aa0aa4fa | bellard | case 'b': |
834 | aa0aa4fa | bellard | (*info->print_address_func) |
835 | aa0aa4fa | bellard | (BDISP (given) * 4 + pc + 8, info); |
836 | aa0aa4fa | bellard | break;
|
837 | aa0aa4fa | bellard | |
838 | aa0aa4fa | bellard | case 'c': |
839 | aa0aa4fa | bellard | func (stream, "%s",
|
840 | aa0aa4fa | bellard | arm_conditional [(given >> 28) & 0xf]); |
841 | aa0aa4fa | bellard | break;
|
842 | aa0aa4fa | bellard | |
843 | aa0aa4fa | bellard | case 'm': |
844 | aa0aa4fa | bellard | { |
845 | aa0aa4fa | bellard | int started = 0; |
846 | aa0aa4fa | bellard | int reg;
|
847 | aa0aa4fa | bellard | |
848 | aa0aa4fa | bellard | func (stream, "{");
|
849 | aa0aa4fa | bellard | for (reg = 0; reg < 16; reg++) |
850 | aa0aa4fa | bellard | if ((given & (1 << reg)) != 0) |
851 | aa0aa4fa | bellard | { |
852 | aa0aa4fa | bellard | if (started)
|
853 | aa0aa4fa | bellard | func (stream, ", ");
|
854 | aa0aa4fa | bellard | started = 1;
|
855 | aa0aa4fa | bellard | func (stream, "%s", arm_regnames[reg]);
|
856 | aa0aa4fa | bellard | } |
857 | aa0aa4fa | bellard | func (stream, "}");
|
858 | aa0aa4fa | bellard | } |
859 | aa0aa4fa | bellard | break;
|
860 | aa0aa4fa | bellard | |
861 | aa0aa4fa | bellard | case 'o': |
862 | aa0aa4fa | bellard | if ((given & 0x02000000) != 0) |
863 | aa0aa4fa | bellard | { |
864 | aa0aa4fa | bellard | int rotate = (given & 0xf00) >> 7; |
865 | aa0aa4fa | bellard | int immed = (given & 0xff); |
866 | aa0aa4fa | bellard | immed = (((immed << (32 - rotate))
|
867 | aa0aa4fa | bellard | | (immed >> rotate)) & 0xffffffff);
|
868 | aa0aa4fa | bellard | func (stream, "#%d\t; 0x%x", immed, immed);
|
869 | aa0aa4fa | bellard | } |
870 | aa0aa4fa | bellard | else
|
871 | aa0aa4fa | bellard | arm_decode_shift (given, func, stream); |
872 | aa0aa4fa | bellard | break;
|
873 | aa0aa4fa | bellard | |
874 | aa0aa4fa | bellard | case 'p': |
875 | aa0aa4fa | bellard | if ((given & 0x0000f000) == 0x0000f000) |
876 | aa0aa4fa | bellard | func (stream, "p");
|
877 | aa0aa4fa | bellard | break;
|
878 | aa0aa4fa | bellard | |
879 | aa0aa4fa | bellard | case 't': |
880 | aa0aa4fa | bellard | if ((given & 0x01200000) == 0x00200000) |
881 | aa0aa4fa | bellard | func (stream, "t");
|
882 | aa0aa4fa | bellard | break;
|
883 | aa0aa4fa | bellard | |
884 | aa0aa4fa | bellard | case 'A': |
885 | aa0aa4fa | bellard | func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]); |
886 | aa0aa4fa | bellard | if ((given & 0x01000000) != 0) |
887 | aa0aa4fa | bellard | { |
888 | aa0aa4fa | bellard | int offset = given & 0xff; |
889 | aa0aa4fa | bellard | if (offset)
|
890 | aa0aa4fa | bellard | func (stream, ", %s#%d]%s",
|
891 | aa0aa4fa | bellard | ((given & 0x00800000) == 0 ? "-" : ""), |
892 | aa0aa4fa | bellard | offset * 4,
|
893 | aa0aa4fa | bellard | ((given & 0x00200000) != 0 ? "!" : "")); |
894 | aa0aa4fa | bellard | else
|
895 | aa0aa4fa | bellard | func (stream, "]");
|
896 | aa0aa4fa | bellard | } |
897 | aa0aa4fa | bellard | else
|
898 | aa0aa4fa | bellard | { |
899 | aa0aa4fa | bellard | int offset = given & 0xff; |
900 | aa0aa4fa | bellard | if (offset)
|
901 | aa0aa4fa | bellard | func (stream, "], %s#%d",
|
902 | aa0aa4fa | bellard | ((given & 0x00800000) == 0 ? "-" : ""), |
903 | aa0aa4fa | bellard | offset * 4);
|
904 | aa0aa4fa | bellard | else
|
905 | aa0aa4fa | bellard | func (stream, "]");
|
906 | aa0aa4fa | bellard | } |
907 | aa0aa4fa | bellard | break;
|
908 | aa0aa4fa | bellard | |
909 | aa0aa4fa | bellard | case 'B': |
910 | aa0aa4fa | bellard | /* Print ARM V5 BLX(1) address: pc+25 bits. */
|
911 | aa0aa4fa | bellard | { |
912 | aa0aa4fa | bellard | bfd_vma address; |
913 | aa0aa4fa | bellard | bfd_vma offset = 0;
|
914 | aa0aa4fa | bellard | |
915 | aa0aa4fa | bellard | if (given & 0x00800000) |
916 | aa0aa4fa | bellard | /* Is signed, hi bits should be ones. */
|
917 | aa0aa4fa | bellard | offset = (-1) ^ 0x00ffffff; |
918 | aa0aa4fa | bellard | |
919 | aa0aa4fa | bellard | /* Offset is (SignExtend(offset field)<<2). */
|
920 | aa0aa4fa | bellard | offset += given & 0x00ffffff;
|
921 | aa0aa4fa | bellard | offset <<= 2;
|
922 | aa0aa4fa | bellard | address = offset + pc + 8;
|
923 | aa0aa4fa | bellard | |
924 | aa0aa4fa | bellard | if (given & 0x01000000) |
925 | aa0aa4fa | bellard | /* H bit allows addressing to 2-byte boundaries. */
|
926 | aa0aa4fa | bellard | address += 2;
|
927 | aa0aa4fa | bellard | |
928 | aa0aa4fa | bellard | info->print_address_func (address, info); |
929 | aa0aa4fa | bellard | } |
930 | aa0aa4fa | bellard | break;
|
931 | aa0aa4fa | bellard | |
932 | aa0aa4fa | bellard | case 'I': |
933 | aa0aa4fa | bellard | /* Print a Cirrus/DSP shift immediate. */
|
934 | aa0aa4fa | bellard | /* Immediates are 7bit signed ints with bits 0..3 in
|
935 | aa0aa4fa | bellard | bits 0..3 of opcode and bits 4..6 in bits 5..7
|
936 | aa0aa4fa | bellard | of opcode. */
|
937 | aa0aa4fa | bellard | { |
938 | aa0aa4fa | bellard | int imm;
|
939 | aa0aa4fa | bellard | |
940 | aa0aa4fa | bellard | imm = (given & 0xf) | ((given & 0xe0) >> 1); |
941 | aa0aa4fa | bellard | |
942 | aa0aa4fa | bellard | /* Is ``imm'' a negative number? */
|
943 | aa0aa4fa | bellard | if (imm & 0x40) |
944 | aa0aa4fa | bellard | imm |= (-1 << 7); |
945 | aa0aa4fa | bellard | |
946 | aa0aa4fa | bellard | func (stream, "%d", imm);
|
947 | aa0aa4fa | bellard | } |
948 | aa0aa4fa | bellard | |
949 | aa0aa4fa | bellard | break;
|
950 | aa0aa4fa | bellard | |
951 | aa0aa4fa | bellard | case 'C': |
952 | aa0aa4fa | bellard | func (stream, "_");
|
953 | aa0aa4fa | bellard | if (given & 0x80000) |
954 | aa0aa4fa | bellard | func (stream, "f");
|
955 | aa0aa4fa | bellard | if (given & 0x40000) |
956 | aa0aa4fa | bellard | func (stream, "s");
|
957 | aa0aa4fa | bellard | if (given & 0x20000) |
958 | aa0aa4fa | bellard | func (stream, "x");
|
959 | aa0aa4fa | bellard | if (given & 0x10000) |
960 | aa0aa4fa | bellard | func (stream, "c");
|
961 | aa0aa4fa | bellard | break;
|
962 | aa0aa4fa | bellard | |
963 | aa0aa4fa | bellard | case 'F': |
964 | aa0aa4fa | bellard | switch (given & 0x00408000) |
965 | aa0aa4fa | bellard | { |
966 | aa0aa4fa | bellard | case 0: |
967 | aa0aa4fa | bellard | func (stream, "4");
|
968 | aa0aa4fa | bellard | break;
|
969 | aa0aa4fa | bellard | case 0x8000: |
970 | aa0aa4fa | bellard | func (stream, "1");
|
971 | aa0aa4fa | bellard | break;
|
972 | aa0aa4fa | bellard | case 0x00400000: |
973 | aa0aa4fa | bellard | func (stream, "2");
|
974 | aa0aa4fa | bellard | break;
|
975 | aa0aa4fa | bellard | default:
|
976 | aa0aa4fa | bellard | func (stream, "3");
|
977 | aa0aa4fa | bellard | } |
978 | aa0aa4fa | bellard | break;
|
979 | aa0aa4fa | bellard | |
980 | aa0aa4fa | bellard | case 'P': |
981 | aa0aa4fa | bellard | switch (given & 0x00080080) |
982 | aa0aa4fa | bellard | { |
983 | aa0aa4fa | bellard | case 0: |
984 | aa0aa4fa | bellard | func (stream, "s");
|
985 | aa0aa4fa | bellard | break;
|
986 | aa0aa4fa | bellard | case 0x80: |
987 | aa0aa4fa | bellard | func (stream, "d");
|
988 | aa0aa4fa | bellard | break;
|
989 | aa0aa4fa | bellard | case 0x00080000: |
990 | aa0aa4fa | bellard | func (stream, "e");
|
991 | aa0aa4fa | bellard | break;
|
992 | aa0aa4fa | bellard | default:
|
993 | aa0aa4fa | bellard | func (stream, _("<illegal precision>"));
|
994 | aa0aa4fa | bellard | break;
|
995 | aa0aa4fa | bellard | } |
996 | aa0aa4fa | bellard | break;
|
997 | aa0aa4fa | bellard | case 'Q': |
998 | aa0aa4fa | bellard | switch (given & 0x00408000) |
999 | aa0aa4fa | bellard | { |
1000 | aa0aa4fa | bellard | case 0: |
1001 | aa0aa4fa | bellard | func (stream, "s");
|
1002 | aa0aa4fa | bellard | break;
|
1003 | aa0aa4fa | bellard | case 0x8000: |
1004 | aa0aa4fa | bellard | func (stream, "d");
|
1005 | aa0aa4fa | bellard | break;
|
1006 | aa0aa4fa | bellard | case 0x00400000: |
1007 | aa0aa4fa | bellard | func (stream, "e");
|
1008 | aa0aa4fa | bellard | break;
|
1009 | aa0aa4fa | bellard | default:
|
1010 | aa0aa4fa | bellard | func (stream, "p");
|
1011 | aa0aa4fa | bellard | break;
|
1012 | aa0aa4fa | bellard | } |
1013 | aa0aa4fa | bellard | break;
|
1014 | aa0aa4fa | bellard | case 'R': |
1015 | aa0aa4fa | bellard | switch (given & 0x60) |
1016 | aa0aa4fa | bellard | { |
1017 | aa0aa4fa | bellard | case 0: |
1018 | aa0aa4fa | bellard | break;
|
1019 | aa0aa4fa | bellard | case 0x20: |
1020 | aa0aa4fa | bellard | func (stream, "p");
|
1021 | aa0aa4fa | bellard | break;
|
1022 | aa0aa4fa | bellard | case 0x40: |
1023 | aa0aa4fa | bellard | func (stream, "m");
|
1024 | aa0aa4fa | bellard | break;
|
1025 | aa0aa4fa | bellard | default:
|
1026 | aa0aa4fa | bellard | func (stream, "z");
|
1027 | aa0aa4fa | bellard | break;
|
1028 | aa0aa4fa | bellard | } |
1029 | aa0aa4fa | bellard | break;
|
1030 | aa0aa4fa | bellard | |
1031 | aa0aa4fa | bellard | case '0': case '1': case '2': case '3': case '4': |
1032 | aa0aa4fa | bellard | case '5': case '6': case '7': case '8': case '9': |
1033 | aa0aa4fa | bellard | { |
1034 | aa0aa4fa | bellard | int bitstart = *c++ - '0'; |
1035 | aa0aa4fa | bellard | int bitend = 0; |
1036 | aa0aa4fa | bellard | while (*c >= '0' && *c <= '9') |
1037 | aa0aa4fa | bellard | bitstart = (bitstart * 10) + *c++ - '0'; |
1038 | aa0aa4fa | bellard | |
1039 | aa0aa4fa | bellard | switch (*c)
|
1040 | aa0aa4fa | bellard | { |
1041 | aa0aa4fa | bellard | case '-': |
1042 | aa0aa4fa | bellard | c++; |
1043 | aa0aa4fa | bellard | |
1044 | aa0aa4fa | bellard | while (*c >= '0' && *c <= '9') |
1045 | aa0aa4fa | bellard | bitend = (bitend * 10) + *c++ - '0'; |
1046 | aa0aa4fa | bellard | |
1047 | aa0aa4fa | bellard | if (!bitend)
|
1048 | aa0aa4fa | bellard | abort (); |
1049 | aa0aa4fa | bellard | |
1050 | aa0aa4fa | bellard | switch (*c)
|
1051 | aa0aa4fa | bellard | { |
1052 | aa0aa4fa | bellard | case 'r': |
1053 | aa0aa4fa | bellard | { |
1054 | aa0aa4fa | bellard | long reg;
|
1055 | aa0aa4fa | bellard | |
1056 | aa0aa4fa | bellard | reg = given >> bitstart; |
1057 | aa0aa4fa | bellard | reg &= (2 << (bitend - bitstart)) - 1; |
1058 | aa0aa4fa | bellard | |
1059 | aa0aa4fa | bellard | func (stream, "%s", arm_regnames[reg]);
|
1060 | aa0aa4fa | bellard | } |
1061 | aa0aa4fa | bellard | break;
|
1062 | aa0aa4fa | bellard | case 'd': |
1063 | aa0aa4fa | bellard | { |
1064 | aa0aa4fa | bellard | long reg;
|
1065 | aa0aa4fa | bellard | |
1066 | aa0aa4fa | bellard | reg = given >> bitstart; |
1067 | aa0aa4fa | bellard | reg &= (2 << (bitend - bitstart)) - 1; |
1068 | aa0aa4fa | bellard | |
1069 | aa0aa4fa | bellard | func (stream, "%d", reg);
|
1070 | aa0aa4fa | bellard | } |
1071 | aa0aa4fa | bellard | break;
|
1072 | aa0aa4fa | bellard | case 'x': |
1073 | aa0aa4fa | bellard | { |
1074 | aa0aa4fa | bellard | long reg;
|
1075 | aa0aa4fa | bellard | |
1076 | aa0aa4fa | bellard | reg = given >> bitstart; |
1077 | aa0aa4fa | bellard | reg &= (2 << (bitend - bitstart)) - 1; |
1078 | aa0aa4fa | bellard | |
1079 | aa0aa4fa | bellard | func (stream, "0x%08x", reg);
|
1080 | aa0aa4fa | bellard | |
1081 | aa0aa4fa | bellard | /* Some SWI instructions have special
|
1082 | aa0aa4fa | bellard | meanings. */
|
1083 | aa0aa4fa | bellard | if ((given & 0x0fffffff) == 0x0FF00000) |
1084 | aa0aa4fa | bellard | func (stream, "\t; IMB");
|
1085 | aa0aa4fa | bellard | else if ((given & 0x0fffffff) == 0x0FF00001) |
1086 | aa0aa4fa | bellard | func (stream, "\t; IMBRange");
|
1087 | aa0aa4fa | bellard | } |
1088 | aa0aa4fa | bellard | break;
|
1089 | aa0aa4fa | bellard | case 'X': |
1090 | aa0aa4fa | bellard | { |
1091 | aa0aa4fa | bellard | long reg;
|
1092 | aa0aa4fa | bellard | |
1093 | aa0aa4fa | bellard | reg = given >> bitstart; |
1094 | aa0aa4fa | bellard | reg &= (2 << (bitend - bitstart)) - 1; |
1095 | aa0aa4fa | bellard | |
1096 | aa0aa4fa | bellard | func (stream, "%01x", reg & 0xf); |
1097 | aa0aa4fa | bellard | } |
1098 | aa0aa4fa | bellard | break;
|
1099 | aa0aa4fa | bellard | case 'f': |
1100 | aa0aa4fa | bellard | { |
1101 | aa0aa4fa | bellard | long reg;
|
1102 | aa0aa4fa | bellard | |
1103 | aa0aa4fa | bellard | reg = given >> bitstart; |
1104 | aa0aa4fa | bellard | reg &= (2 << (bitend - bitstart)) - 1; |
1105 | aa0aa4fa | bellard | |
1106 | aa0aa4fa | bellard | if (reg > 7) |
1107 | aa0aa4fa | bellard | func (stream, "#%s",
|
1108 | aa0aa4fa | bellard | arm_fp_const[reg & 7]);
|
1109 | aa0aa4fa | bellard | else
|
1110 | aa0aa4fa | bellard | func (stream, "f%d", reg);
|
1111 | aa0aa4fa | bellard | } |
1112 | aa0aa4fa | bellard | break;
|
1113 | aa0aa4fa | bellard | default:
|
1114 | aa0aa4fa | bellard | abort (); |
1115 | aa0aa4fa | bellard | } |
1116 | aa0aa4fa | bellard | break;
|
1117 | aa0aa4fa | bellard | |
1118 | aa0aa4fa | bellard | case 'y': |
1119 | aa0aa4fa | bellard | case 'z': |
1120 | aa0aa4fa | bellard | { |
1121 | aa0aa4fa | bellard | int single = *c == 'y'; |
1122 | aa0aa4fa | bellard | int regno;
|
1123 | aa0aa4fa | bellard | |
1124 | aa0aa4fa | bellard | switch (bitstart)
|
1125 | aa0aa4fa | bellard | { |
1126 | aa0aa4fa | bellard | case 4: /* Sm pair */ |
1127 | aa0aa4fa | bellard | func (stream, "{");
|
1128 | aa0aa4fa | bellard | /* Fall through. */
|
1129 | aa0aa4fa | bellard | case 0: /* Sm, Dm */ |
1130 | aa0aa4fa | bellard | regno = given & 0x0000000f;
|
1131 | aa0aa4fa | bellard | if (single)
|
1132 | aa0aa4fa | bellard | { |
1133 | aa0aa4fa | bellard | regno <<= 1;
|
1134 | aa0aa4fa | bellard | regno += (given >> 5) & 1; |
1135 | aa0aa4fa | bellard | } |
1136 | aa0aa4fa | bellard | break;
|
1137 | aa0aa4fa | bellard | |
1138 | aa0aa4fa | bellard | case 1: /* Sd, Dd */ |
1139 | aa0aa4fa | bellard | regno = (given >> 12) & 0x0000000f; |
1140 | aa0aa4fa | bellard | if (single)
|
1141 | aa0aa4fa | bellard | { |
1142 | aa0aa4fa | bellard | regno <<= 1;
|
1143 | aa0aa4fa | bellard | regno += (given >> 22) & 1; |
1144 | aa0aa4fa | bellard | } |
1145 | aa0aa4fa | bellard | break;
|
1146 | aa0aa4fa | bellard | |
1147 | aa0aa4fa | bellard | case 2: /* Sn, Dn */ |
1148 | aa0aa4fa | bellard | regno = (given >> 16) & 0x0000000f; |
1149 | aa0aa4fa | bellard | if (single)
|
1150 | aa0aa4fa | bellard | { |
1151 | aa0aa4fa | bellard | regno <<= 1;
|
1152 | aa0aa4fa | bellard | regno += (given >> 7) & 1; |
1153 | aa0aa4fa | bellard | } |
1154 | aa0aa4fa | bellard | break;
|
1155 | aa0aa4fa | bellard | |
1156 | aa0aa4fa | bellard | case 3: /* List */ |
1157 | aa0aa4fa | bellard | func (stream, "{");
|
1158 | aa0aa4fa | bellard | regno = (given >> 12) & 0x0000000f; |
1159 | aa0aa4fa | bellard | if (single)
|
1160 | aa0aa4fa | bellard | { |
1161 | aa0aa4fa | bellard | regno <<= 1;
|
1162 | aa0aa4fa | bellard | regno += (given >> 22) & 1; |
1163 | aa0aa4fa | bellard | } |
1164 | aa0aa4fa | bellard | break;
|
1165 | aa0aa4fa | bellard | |
1166 | aa0aa4fa | bellard | |
1167 | aa0aa4fa | bellard | default:
|
1168 | aa0aa4fa | bellard | abort (); |
1169 | aa0aa4fa | bellard | } |
1170 | aa0aa4fa | bellard | |
1171 | aa0aa4fa | bellard | func (stream, "%c%d", single ? 's' : 'd', regno); |
1172 | aa0aa4fa | bellard | |
1173 | aa0aa4fa | bellard | if (bitstart == 3) |
1174 | aa0aa4fa | bellard | { |
1175 | aa0aa4fa | bellard | int count = given & 0xff; |
1176 | aa0aa4fa | bellard | |
1177 | aa0aa4fa | bellard | if (single == 0) |
1178 | aa0aa4fa | bellard | count >>= 1;
|
1179 | aa0aa4fa | bellard | |
1180 | aa0aa4fa | bellard | if (--count)
|
1181 | aa0aa4fa | bellard | { |
1182 | aa0aa4fa | bellard | func (stream, "-%c%d",
|
1183 | aa0aa4fa | bellard | single ? 's' : 'd', |
1184 | aa0aa4fa | bellard | regno + count); |
1185 | aa0aa4fa | bellard | } |
1186 | aa0aa4fa | bellard | |
1187 | aa0aa4fa | bellard | func (stream, "}");
|
1188 | aa0aa4fa | bellard | } |
1189 | aa0aa4fa | bellard | else if (bitstart == 4) |
1190 | aa0aa4fa | bellard | func (stream, ", %c%d}", single ? 's' : 'd', |
1191 | aa0aa4fa | bellard | regno + 1);
|
1192 | aa0aa4fa | bellard | |
1193 | aa0aa4fa | bellard | break;
|
1194 | aa0aa4fa | bellard | } |
1195 | aa0aa4fa | bellard | |
1196 | aa0aa4fa | bellard | case '`': |
1197 | aa0aa4fa | bellard | c++; |
1198 | aa0aa4fa | bellard | if ((given & (1 << bitstart)) == 0) |
1199 | aa0aa4fa | bellard | func (stream, "%c", *c);
|
1200 | aa0aa4fa | bellard | break;
|
1201 | aa0aa4fa | bellard | case '\'': |
1202 | aa0aa4fa | bellard | c++; |
1203 | aa0aa4fa | bellard | if ((given & (1 << bitstart)) != 0) |
1204 | aa0aa4fa | bellard | func (stream, "%c", *c);
|
1205 | aa0aa4fa | bellard | break;
|
1206 | aa0aa4fa | bellard | case '?': |
1207 | aa0aa4fa | bellard | ++c; |
1208 | aa0aa4fa | bellard | if ((given & (1 << bitstart)) != 0) |
1209 | aa0aa4fa | bellard | func (stream, "%c", *c++);
|
1210 | aa0aa4fa | bellard | else
|
1211 | aa0aa4fa | bellard | func (stream, "%c", *++c);
|
1212 | aa0aa4fa | bellard | break;
|
1213 | aa0aa4fa | bellard | default:
|
1214 | aa0aa4fa | bellard | abort (); |
1215 | aa0aa4fa | bellard | } |
1216 | aa0aa4fa | bellard | break;
|
1217 | aa0aa4fa | bellard | |
1218 | aa0aa4fa | bellard | default:
|
1219 | aa0aa4fa | bellard | abort (); |
1220 | aa0aa4fa | bellard | } |
1221 | aa0aa4fa | bellard | } |
1222 | aa0aa4fa | bellard | } |
1223 | aa0aa4fa | bellard | else
|
1224 | aa0aa4fa | bellard | func (stream, "%c", *c);
|
1225 | aa0aa4fa | bellard | } |
1226 | aa0aa4fa | bellard | return 4; |
1227 | aa0aa4fa | bellard | } |
1228 | aa0aa4fa | bellard | } |
1229 | aa0aa4fa | bellard | abort (); |
1230 | aa0aa4fa | bellard | } |
1231 | aa0aa4fa | bellard | |
1232 | aa0aa4fa | bellard | /* Print one instruction from PC on INFO->STREAM.
|
1233 | aa0aa4fa | bellard | Return the size of the instruction. */
|
1234 | aa0aa4fa | bellard | |
1235 | aa0aa4fa | bellard | static int |
1236 | aa0aa4fa | bellard | print_insn_thumb (pc, info, given) |
1237 | aa0aa4fa | bellard | bfd_vma pc; |
1238 | aa0aa4fa | bellard | struct disassemble_info * info;
|
1239 | aa0aa4fa | bellard | long given;
|
1240 | aa0aa4fa | bellard | { |
1241 | aa0aa4fa | bellard | struct thumb_opcode * insn;
|
1242 | aa0aa4fa | bellard | void * stream = info->stream;
|
1243 | aa0aa4fa | bellard | fprintf_ftype func = info->fprintf_func; |
1244 | aa0aa4fa | bellard | |
1245 | aa0aa4fa | bellard | for (insn = thumb_opcodes; insn->assembler; insn++)
|
1246 | aa0aa4fa | bellard | { |
1247 | aa0aa4fa | bellard | if ((given & insn->mask) == insn->value)
|
1248 | aa0aa4fa | bellard | { |
1249 | aa0aa4fa | bellard | char * c = insn->assembler;
|
1250 | aa0aa4fa | bellard | |
1251 | aa0aa4fa | bellard | /* Special processing for Thumb 2 instruction BL sequence: */
|
1252 | aa0aa4fa | bellard | if (!*c) /* Check for empty (not NULL) assembler string. */ |
1253 | aa0aa4fa | bellard | { |
1254 | aa0aa4fa | bellard | long offset;
|
1255 | aa0aa4fa | bellard | |
1256 | aa0aa4fa | bellard | info->bytes_per_chunk = 4;
|
1257 | aa0aa4fa | bellard | info->bytes_per_line = 4;
|
1258 | aa0aa4fa | bellard | |
1259 | aa0aa4fa | bellard | offset = BDISP23 (given); |
1260 | aa0aa4fa | bellard | offset = offset * 2 + pc + 4; |
1261 | aa0aa4fa | bellard | |
1262 | aa0aa4fa | bellard | if ((given & 0x10000000) == 0) |
1263 | aa0aa4fa | bellard | { |
1264 | aa0aa4fa | bellard | func (stream, "blx\t");
|
1265 | aa0aa4fa | bellard | offset &= 0xfffffffc;
|
1266 | aa0aa4fa | bellard | } |
1267 | aa0aa4fa | bellard | else
|
1268 | aa0aa4fa | bellard | func (stream, "bl\t");
|
1269 | aa0aa4fa | bellard | |
1270 | aa0aa4fa | bellard | info->print_address_func (offset, info); |
1271 | aa0aa4fa | bellard | return 4; |
1272 | aa0aa4fa | bellard | } |
1273 | aa0aa4fa | bellard | else
|
1274 | aa0aa4fa | bellard | { |
1275 | aa0aa4fa | bellard | info->bytes_per_chunk = 2;
|
1276 | aa0aa4fa | bellard | info->bytes_per_line = 4;
|
1277 | aa0aa4fa | bellard | |
1278 | aa0aa4fa | bellard | given &= 0xffff;
|
1279 | aa0aa4fa | bellard | |
1280 | aa0aa4fa | bellard | for (; *c; c++)
|
1281 | aa0aa4fa | bellard | { |
1282 | aa0aa4fa | bellard | if (*c == '%') |
1283 | aa0aa4fa | bellard | { |
1284 | aa0aa4fa | bellard | int domaskpc = 0; |
1285 | aa0aa4fa | bellard | int domasklr = 0; |
1286 | aa0aa4fa | bellard | |
1287 | aa0aa4fa | bellard | switch (*++c)
|
1288 | aa0aa4fa | bellard | { |
1289 | aa0aa4fa | bellard | case '%': |
1290 | aa0aa4fa | bellard | func (stream, "%%");
|
1291 | aa0aa4fa | bellard | break;
|
1292 | aa0aa4fa | bellard | |
1293 | aa0aa4fa | bellard | case 'S': |
1294 | aa0aa4fa | bellard | { |
1295 | aa0aa4fa | bellard | long reg;
|
1296 | aa0aa4fa | bellard | |
1297 | aa0aa4fa | bellard | reg = (given >> 3) & 0x7; |
1298 | aa0aa4fa | bellard | if (given & (1 << 6)) |
1299 | aa0aa4fa | bellard | reg += 8;
|
1300 | aa0aa4fa | bellard | |
1301 | aa0aa4fa | bellard | func (stream, "%s", arm_regnames[reg]);
|
1302 | aa0aa4fa | bellard | } |
1303 | aa0aa4fa | bellard | break;
|
1304 | aa0aa4fa | bellard | |
1305 | aa0aa4fa | bellard | case 'D': |
1306 | aa0aa4fa | bellard | { |
1307 | aa0aa4fa | bellard | long reg;
|
1308 | aa0aa4fa | bellard | |
1309 | aa0aa4fa | bellard | reg = given & 0x7;
|
1310 | aa0aa4fa | bellard | if (given & (1 << 7)) |
1311 | aa0aa4fa | bellard | reg += 8;
|
1312 | aa0aa4fa | bellard | |
1313 | aa0aa4fa | bellard | func (stream, "%s", arm_regnames[reg]);
|
1314 | aa0aa4fa | bellard | } |
1315 | aa0aa4fa | bellard | break;
|
1316 | aa0aa4fa | bellard | |
1317 | aa0aa4fa | bellard | case 'T': |
1318 | aa0aa4fa | bellard | func (stream, "%s",
|
1319 | aa0aa4fa | bellard | arm_conditional [(given >> 8) & 0xf]); |
1320 | aa0aa4fa | bellard | break;
|
1321 | aa0aa4fa | bellard | |
1322 | aa0aa4fa | bellard | case 'N': |
1323 | aa0aa4fa | bellard | if (given & (1 << 8)) |
1324 | aa0aa4fa | bellard | domasklr = 1;
|
1325 | aa0aa4fa | bellard | /* Fall through. */
|
1326 | aa0aa4fa | bellard | case 'O': |
1327 | aa0aa4fa | bellard | if (*c == 'O' && (given & (1 << 8))) |
1328 | aa0aa4fa | bellard | domaskpc = 1;
|
1329 | aa0aa4fa | bellard | /* Fall through. */
|
1330 | aa0aa4fa | bellard | case 'M': |
1331 | aa0aa4fa | bellard | { |
1332 | aa0aa4fa | bellard | int started = 0; |
1333 | aa0aa4fa | bellard | int reg;
|
1334 | aa0aa4fa | bellard | |
1335 | aa0aa4fa | bellard | func (stream, "{");
|
1336 | aa0aa4fa | bellard | |
1337 | aa0aa4fa | bellard | /* It would be nice if we could spot
|
1338 | aa0aa4fa | bellard | ranges, and generate the rS-rE format: */
|
1339 | aa0aa4fa | bellard | for (reg = 0; (reg < 8); reg++) |
1340 | aa0aa4fa | bellard | if ((given & (1 << reg)) != 0) |
1341 | aa0aa4fa | bellard | { |
1342 | aa0aa4fa | bellard | if (started)
|
1343 | aa0aa4fa | bellard | func (stream, ", ");
|
1344 | aa0aa4fa | bellard | started = 1;
|
1345 | aa0aa4fa | bellard | func (stream, "%s", arm_regnames[reg]);
|
1346 | aa0aa4fa | bellard | } |
1347 | aa0aa4fa | bellard | |
1348 | aa0aa4fa | bellard | if (domasklr)
|
1349 | aa0aa4fa | bellard | { |
1350 | aa0aa4fa | bellard | if (started)
|
1351 | aa0aa4fa | bellard | func (stream, ", ");
|
1352 | aa0aa4fa | bellard | started = 1;
|
1353 | aa0aa4fa | bellard | func (stream, arm_regnames[14] /* "lr" */); |
1354 | aa0aa4fa | bellard | } |
1355 | aa0aa4fa | bellard | |
1356 | aa0aa4fa | bellard | if (domaskpc)
|
1357 | aa0aa4fa | bellard | { |
1358 | aa0aa4fa | bellard | if (started)
|
1359 | aa0aa4fa | bellard | func (stream, ", ");
|
1360 | aa0aa4fa | bellard | func (stream, arm_regnames[15] /* "pc" */); |
1361 | aa0aa4fa | bellard | } |
1362 | aa0aa4fa | bellard | |
1363 | aa0aa4fa | bellard | func (stream, "}");
|
1364 | aa0aa4fa | bellard | } |
1365 | aa0aa4fa | bellard | break;
|
1366 | aa0aa4fa | bellard | |
1367 | aa0aa4fa | bellard | |
1368 | aa0aa4fa | bellard | case '0': case '1': case '2': case '3': case '4': |
1369 | aa0aa4fa | bellard | case '5': case '6': case '7': case '8': case '9': |
1370 | aa0aa4fa | bellard | { |
1371 | aa0aa4fa | bellard | int bitstart = *c++ - '0'; |
1372 | aa0aa4fa | bellard | int bitend = 0; |
1373 | aa0aa4fa | bellard | |
1374 | aa0aa4fa | bellard | while (*c >= '0' && *c <= '9') |
1375 | aa0aa4fa | bellard | bitstart = (bitstart * 10) + *c++ - '0'; |
1376 | aa0aa4fa | bellard | |
1377 | aa0aa4fa | bellard | switch (*c)
|
1378 | aa0aa4fa | bellard | { |
1379 | aa0aa4fa | bellard | case '-': |
1380 | aa0aa4fa | bellard | { |
1381 | aa0aa4fa | bellard | long reg;
|
1382 | aa0aa4fa | bellard | |
1383 | aa0aa4fa | bellard | c++; |
1384 | aa0aa4fa | bellard | while (*c >= '0' && *c <= '9') |
1385 | aa0aa4fa | bellard | bitend = (bitend * 10) + *c++ - '0'; |
1386 | aa0aa4fa | bellard | if (!bitend)
|
1387 | aa0aa4fa | bellard | abort (); |
1388 | aa0aa4fa | bellard | reg = given >> bitstart; |
1389 | aa0aa4fa | bellard | reg &= (2 << (bitend - bitstart)) - 1; |
1390 | aa0aa4fa | bellard | switch (*c)
|
1391 | aa0aa4fa | bellard | { |
1392 | aa0aa4fa | bellard | case 'r': |
1393 | aa0aa4fa | bellard | func (stream, "%s", arm_regnames[reg]);
|
1394 | aa0aa4fa | bellard | break;
|
1395 | aa0aa4fa | bellard | |
1396 | aa0aa4fa | bellard | case 'd': |
1397 | aa0aa4fa | bellard | func (stream, "%d", reg);
|
1398 | aa0aa4fa | bellard | break;
|
1399 | aa0aa4fa | bellard | |
1400 | aa0aa4fa | bellard | case 'H': |
1401 | aa0aa4fa | bellard | func (stream, "%d", reg << 1); |
1402 | aa0aa4fa | bellard | break;
|
1403 | aa0aa4fa | bellard | |
1404 | aa0aa4fa | bellard | case 'W': |
1405 | aa0aa4fa | bellard | func (stream, "%d", reg << 2); |
1406 | aa0aa4fa | bellard | break;
|
1407 | aa0aa4fa | bellard | |
1408 | aa0aa4fa | bellard | case 'a': |
1409 | aa0aa4fa | bellard | /* PC-relative address -- the bottom two
|
1410 | aa0aa4fa | bellard | bits of the address are dropped
|
1411 | aa0aa4fa | bellard | before the calculation. */
|
1412 | aa0aa4fa | bellard | info->print_address_func |
1413 | aa0aa4fa | bellard | (((pc + 4) & ~3) + (reg << 2), info); |
1414 | aa0aa4fa | bellard | break;
|
1415 | aa0aa4fa | bellard | |
1416 | aa0aa4fa | bellard | case 'x': |
1417 | aa0aa4fa | bellard | func (stream, "0x%04x", reg);
|
1418 | aa0aa4fa | bellard | break;
|
1419 | aa0aa4fa | bellard | |
1420 | aa0aa4fa | bellard | case 'I': |
1421 | aa0aa4fa | bellard | reg = ((reg ^ (1 << bitend)) - (1 << bitend)); |
1422 | aa0aa4fa | bellard | func (stream, "%d", reg);
|
1423 | aa0aa4fa | bellard | break;
|
1424 | aa0aa4fa | bellard | |
1425 | aa0aa4fa | bellard | case 'B': |
1426 | aa0aa4fa | bellard | reg = ((reg ^ (1 << bitend)) - (1 << bitend)); |
1427 | aa0aa4fa | bellard | (*info->print_address_func) |
1428 | aa0aa4fa | bellard | (reg * 2 + pc + 4, info); |
1429 | aa0aa4fa | bellard | break;
|
1430 | aa0aa4fa | bellard | |
1431 | aa0aa4fa | bellard | default:
|
1432 | aa0aa4fa | bellard | abort (); |
1433 | aa0aa4fa | bellard | } |
1434 | aa0aa4fa | bellard | } |
1435 | aa0aa4fa | bellard | break;
|
1436 | aa0aa4fa | bellard | |
1437 | aa0aa4fa | bellard | case '\'': |
1438 | aa0aa4fa | bellard | c++; |
1439 | aa0aa4fa | bellard | if ((given & (1 << bitstart)) != 0) |
1440 | aa0aa4fa | bellard | func (stream, "%c", *c);
|
1441 | aa0aa4fa | bellard | break;
|
1442 | aa0aa4fa | bellard | |
1443 | aa0aa4fa | bellard | case '?': |
1444 | aa0aa4fa | bellard | ++c; |
1445 | aa0aa4fa | bellard | if ((given & (1 << bitstart)) != 0) |
1446 | aa0aa4fa | bellard | func (stream, "%c", *c++);
|
1447 | aa0aa4fa | bellard | else
|
1448 | aa0aa4fa | bellard | func (stream, "%c", *++c);
|
1449 | aa0aa4fa | bellard | break;
|
1450 | aa0aa4fa | bellard | |
1451 | aa0aa4fa | bellard | default:
|
1452 | aa0aa4fa | bellard | abort (); |
1453 | aa0aa4fa | bellard | } |
1454 | aa0aa4fa | bellard | } |
1455 | aa0aa4fa | bellard | break;
|
1456 | aa0aa4fa | bellard | |
1457 | aa0aa4fa | bellard | default:
|
1458 | aa0aa4fa | bellard | abort (); |
1459 | aa0aa4fa | bellard | } |
1460 | aa0aa4fa | bellard | } |
1461 | aa0aa4fa | bellard | else
|
1462 | aa0aa4fa | bellard | func (stream, "%c", *c);
|
1463 | aa0aa4fa | bellard | } |
1464 | aa0aa4fa | bellard | } |
1465 | aa0aa4fa | bellard | return 2; |
1466 | aa0aa4fa | bellard | } |
1467 | aa0aa4fa | bellard | } |
1468 | aa0aa4fa | bellard | |
1469 | aa0aa4fa | bellard | /* No match. */
|
1470 | aa0aa4fa | bellard | abort (); |
1471 | aa0aa4fa | bellard | } |
1472 | aa0aa4fa | bellard | |
1473 | aa0aa4fa | bellard | /* Parse an individual disassembler option. */
|
1474 | aa0aa4fa | bellard | |
1475 | aa0aa4fa | bellard | void
|
1476 | aa0aa4fa | bellard | parse_arm_disassembler_option (option) |
1477 | aa0aa4fa | bellard | char * option;
|
1478 | aa0aa4fa | bellard | { |
1479 | aa0aa4fa | bellard | if (option == NULL) |
1480 | aa0aa4fa | bellard | return;
|
1481 | aa0aa4fa | bellard | |
1482 | aa0aa4fa | bellard | if (strneq (option, "reg-names-", 10)) |
1483 | aa0aa4fa | bellard | { |
1484 | aa0aa4fa | bellard | int i;
|
1485 | aa0aa4fa | bellard | |
1486 | aa0aa4fa | bellard | option += 10;
|
1487 | aa0aa4fa | bellard | |
1488 | aa0aa4fa | bellard | for (i = NUM_ARM_REGNAMES; i--;)
|
1489 | aa0aa4fa | bellard | if (streq (option, regnames[i].name))
|
1490 | aa0aa4fa | bellard | { |
1491 | aa0aa4fa | bellard | regname_selected = i; |
1492 | aa0aa4fa | bellard | break;
|
1493 | aa0aa4fa | bellard | } |
1494 | aa0aa4fa | bellard | |
1495 | aa0aa4fa | bellard | if (i < 0) |
1496 | aa0aa4fa | bellard | fprintf (stderr, _("Unrecognised register name set: %s\n"), option);
|
1497 | aa0aa4fa | bellard | } |
1498 | aa0aa4fa | bellard | else if (streq (option, "force-thumb")) |
1499 | aa0aa4fa | bellard | force_thumb = 1;
|
1500 | aa0aa4fa | bellard | else if (streq (option, "no-force-thumb")) |
1501 | aa0aa4fa | bellard | force_thumb = 0;
|
1502 | aa0aa4fa | bellard | else
|
1503 | aa0aa4fa | bellard | fprintf (stderr, _("Unrecognised disassembler option: %s\n"), option);
|
1504 | aa0aa4fa | bellard | |
1505 | aa0aa4fa | bellard | return;
|
1506 | aa0aa4fa | bellard | } |
1507 | aa0aa4fa | bellard | |
1508 | aa0aa4fa | bellard | /* Parse the string of disassembler options, spliting it at whitespaces. */
|
1509 | aa0aa4fa | bellard | |
1510 | aa0aa4fa | bellard | static void |
1511 | aa0aa4fa | bellard | parse_disassembler_options (options) |
1512 | aa0aa4fa | bellard | char * options;
|
1513 | aa0aa4fa | bellard | { |
1514 | aa0aa4fa | bellard | char * space;
|
1515 | aa0aa4fa | bellard | |
1516 | aa0aa4fa | bellard | if (options == NULL) |
1517 | aa0aa4fa | bellard | return;
|
1518 | aa0aa4fa | bellard | |
1519 | aa0aa4fa | bellard | do
|
1520 | aa0aa4fa | bellard | { |
1521 | aa0aa4fa | bellard | space = strchr (options, ' ');
|
1522 | aa0aa4fa | bellard | |
1523 | aa0aa4fa | bellard | if (space)
|
1524 | aa0aa4fa | bellard | { |
1525 | aa0aa4fa | bellard | * space = '\0';
|
1526 | aa0aa4fa | bellard | parse_arm_disassembler_option (options); |
1527 | aa0aa4fa | bellard | * space = ' ';
|
1528 | aa0aa4fa | bellard | options = space + 1;
|
1529 | aa0aa4fa | bellard | } |
1530 | aa0aa4fa | bellard | else
|
1531 | aa0aa4fa | bellard | parse_arm_disassembler_option (options); |
1532 | aa0aa4fa | bellard | } |
1533 | aa0aa4fa | bellard | while (space);
|
1534 | aa0aa4fa | bellard | } |
1535 | aa0aa4fa | bellard | |
1536 | aa0aa4fa | bellard | /* NOTE: There are no checks in these routines that
|
1537 | aa0aa4fa | bellard | the relevant number of data bytes exist. */
|
1538 | aa0aa4fa | bellard | |
1539 | aa0aa4fa | bellard | int
|
1540 | aa0aa4fa | bellard | print_insn_arm (pc, info) |
1541 | aa0aa4fa | bellard | bfd_vma pc; |
1542 | aa0aa4fa | bellard | struct disassemble_info * info;
|
1543 | aa0aa4fa | bellard | { |
1544 | aa0aa4fa | bellard | unsigned char b[4]; |
1545 | aa0aa4fa | bellard | long given;
|
1546 | aa0aa4fa | bellard | int status;
|
1547 | aa0aa4fa | bellard | int is_thumb;
|
1548 | aa0aa4fa | bellard | int little;
|
1549 | aa0aa4fa | bellard | |
1550 | aa0aa4fa | bellard | if (info->disassembler_options)
|
1551 | aa0aa4fa | bellard | { |
1552 | aa0aa4fa | bellard | parse_disassembler_options (info->disassembler_options); |
1553 | aa0aa4fa | bellard | |
1554 | aa0aa4fa | bellard | /* To avoid repeated parsing of these options, we remove them here. */
|
1555 | aa0aa4fa | bellard | info->disassembler_options = NULL;
|
1556 | aa0aa4fa | bellard | } |
1557 | aa0aa4fa | bellard | |
1558 | aa0aa4fa | bellard | is_thumb = force_thumb; |
1559 | aa0aa4fa | bellard | |
1560 | aa0aa4fa | bellard | #if 0
|
1561 | aa0aa4fa | bellard | if (!is_thumb && info->symbols != NULL)
|
1562 | aa0aa4fa | bellard | {
|
1563 | aa0aa4fa | bellard | if (bfd_asymbol_flavour (*info->symbols) == bfd_target_coff_flavour)
|
1564 | aa0aa4fa | bellard | {
|
1565 | aa0aa4fa | bellard | coff_symbol_type * cs;
|
1566 | aa0aa4fa | bellard |
|
1567 | aa0aa4fa | bellard | cs = coffsymbol (*info->symbols);
|
1568 | aa0aa4fa | bellard | is_thumb = ( cs->native->u.syment.n_sclass == C_THUMBEXT
|
1569 | aa0aa4fa | bellard | || cs->native->u.syment.n_sclass == C_THUMBSTAT
|
1570 | aa0aa4fa | bellard | || cs->native->u.syment.n_sclass == C_THUMBLABEL
|
1571 | aa0aa4fa | bellard | || cs->native->u.syment.n_sclass == C_THUMBEXTFUNC
|
1572 | aa0aa4fa | bellard | || cs->native->u.syment.n_sclass == C_THUMBSTATFUNC);
|
1573 | aa0aa4fa | bellard | }
|
1574 | aa0aa4fa | bellard | else if (bfd_asymbol_flavour (*info->symbols) == bfd_target_elf_flavour)
|
1575 | aa0aa4fa | bellard | {
|
1576 | aa0aa4fa | bellard | elf_symbol_type * es;
|
1577 | aa0aa4fa | bellard | unsigned int type;
|
1578 | aa0aa4fa | bellard |
|
1579 | aa0aa4fa | bellard | es = *(elf_symbol_type **)(info->symbols);
|
1580 | aa0aa4fa | bellard | type = ELF_ST_TYPE (es->internal_elf_sym.st_info);
|
1581 | aa0aa4fa | bellard |
|
1582 | aa0aa4fa | bellard | is_thumb = (type == STT_ARM_TFUNC) || (type == STT_ARM_16BIT);
|
1583 | aa0aa4fa | bellard | }
|
1584 | aa0aa4fa | bellard | }
|
1585 | aa0aa4fa | bellard | #endif
|
1586 | aa0aa4fa | bellard | |
1587 | aa0aa4fa | bellard | little = (info->endian == BFD_ENDIAN_LITTLE); |
1588 | aa0aa4fa | bellard | info->bytes_per_chunk = 4;
|
1589 | aa0aa4fa | bellard | info->display_endian = little ? BFD_ENDIAN_LITTLE : BFD_ENDIAN_BIG; |
1590 | aa0aa4fa | bellard | |
1591 | aa0aa4fa | bellard | if (little)
|
1592 | aa0aa4fa | bellard | { |
1593 | aa0aa4fa | bellard | status = info->read_memory_func (pc, (bfd_byte *) &b[0], 4, info); |
1594 | aa0aa4fa | bellard | if (status != 0 && is_thumb) |
1595 | aa0aa4fa | bellard | { |
1596 | aa0aa4fa | bellard | info->bytes_per_chunk = 2;
|
1597 | aa0aa4fa | bellard | |
1598 | aa0aa4fa | bellard | status = info->read_memory_func (pc, (bfd_byte *) b, 2, info);
|
1599 | aa0aa4fa | bellard | b[3] = b[2] = 0; |
1600 | aa0aa4fa | bellard | } |
1601 | aa0aa4fa | bellard | |
1602 | aa0aa4fa | bellard | if (status != 0) |
1603 | aa0aa4fa | bellard | { |
1604 | aa0aa4fa | bellard | info->memory_error_func (status, pc, info); |
1605 | aa0aa4fa | bellard | return -1; |
1606 | aa0aa4fa | bellard | } |
1607 | aa0aa4fa | bellard | |
1608 | aa0aa4fa | bellard | given = (b[0]) | (b[1] << 8) | (b[2] << 16) | (b[3] << 24); |
1609 | aa0aa4fa | bellard | } |
1610 | aa0aa4fa | bellard | else
|
1611 | aa0aa4fa | bellard | { |
1612 | aa0aa4fa | bellard | status = info->read_memory_func |
1613 | aa0aa4fa | bellard | (pc & ~ 0x3, (bfd_byte *) &b[0], 4, info); |
1614 | aa0aa4fa | bellard | if (status != 0) |
1615 | aa0aa4fa | bellard | { |
1616 | aa0aa4fa | bellard | info->memory_error_func (status, pc, info); |
1617 | aa0aa4fa | bellard | return -1; |
1618 | aa0aa4fa | bellard | } |
1619 | aa0aa4fa | bellard | |
1620 | aa0aa4fa | bellard | if (is_thumb)
|
1621 | aa0aa4fa | bellard | { |
1622 | aa0aa4fa | bellard | if (pc & 0x2) |
1623 | aa0aa4fa | bellard | { |
1624 | aa0aa4fa | bellard | given = (b[2] << 8) | b[3]; |
1625 | aa0aa4fa | bellard | |
1626 | aa0aa4fa | bellard | status = info->read_memory_func |
1627 | aa0aa4fa | bellard | ((pc + 4) & ~ 0x3, (bfd_byte *) b, 4, info); |
1628 | aa0aa4fa | bellard | if (status != 0) |
1629 | aa0aa4fa | bellard | { |
1630 | aa0aa4fa | bellard | info->memory_error_func (status, pc + 4, info);
|
1631 | aa0aa4fa | bellard | return -1; |
1632 | aa0aa4fa | bellard | } |
1633 | aa0aa4fa | bellard | |
1634 | aa0aa4fa | bellard | given |= (b[0] << 24) | (b[1] << 16); |
1635 | aa0aa4fa | bellard | } |
1636 | aa0aa4fa | bellard | else
|
1637 | aa0aa4fa | bellard | given = (b[0] << 8) | b[1] | (b[2] << 24) | (b[3] << 16); |
1638 | aa0aa4fa | bellard | } |
1639 | aa0aa4fa | bellard | else
|
1640 | aa0aa4fa | bellard | given = (b[0] << 24) | (b[1] << 16) | (b[2] << 8) | (b[3]); |
1641 | aa0aa4fa | bellard | } |
1642 | aa0aa4fa | bellard | |
1643 | aa0aa4fa | bellard | if (info->flags & INSN_HAS_RELOC)
|
1644 | aa0aa4fa | bellard | /* If the instruction has a reloc associated with it, then
|
1645 | aa0aa4fa | bellard | the offset field in the instruction will actually be the
|
1646 | aa0aa4fa | bellard | addend for the reloc. (We are using REL type relocs).
|
1647 | aa0aa4fa | bellard | In such cases, we can ignore the pc when computing
|
1648 | aa0aa4fa | bellard | addresses, since the addend is not currently pc-relative. */
|
1649 | aa0aa4fa | bellard | pc = 0;
|
1650 | aa0aa4fa | bellard | if (is_thumb)
|
1651 | aa0aa4fa | bellard | status = print_insn_thumb (pc, info, given); |
1652 | aa0aa4fa | bellard | else
|
1653 | aa0aa4fa | bellard | status = print_insn_arm1 (pc, info, given); |
1654 | aa0aa4fa | bellard | |
1655 | aa0aa4fa | bellard | return status;
|
1656 | aa0aa4fa | bellard | } |
1657 | aa0aa4fa | bellard | |
1658 | aa0aa4fa | bellard | void
|
1659 | aa0aa4fa | bellard | print_arm_disassembler_options (FILE * stream) |
1660 | aa0aa4fa | bellard | { |
1661 | aa0aa4fa | bellard | int i;
|
1662 | aa0aa4fa | bellard | |
1663 | aa0aa4fa | bellard | fprintf (stream, _("\n\
|
1664 | aa0aa4fa | bellard | The following ARM specific disassembler options are supported for use with\n\
|
1665 | aa0aa4fa | bellard | the -M switch:\n"));
|
1666 | aa0aa4fa | bellard | |
1667 | aa0aa4fa | bellard | for (i = NUM_ARM_REGNAMES; i--;)
|
1668 | aa0aa4fa | bellard | fprintf (stream, " reg-names-%s %*c%s\n",
|
1669 | aa0aa4fa | bellard | regnames[i].name, |
1670 | aa0aa4fa | bellard | (int)(14 - strlen (regnames[i].name)), ' ', |
1671 | aa0aa4fa | bellard | regnames[i].description); |
1672 | aa0aa4fa | bellard | |
1673 | aa0aa4fa | bellard | fprintf (stream, " force-thumb Assume all insns are Thumb insns\n");
|
1674 | aa0aa4fa | bellard | fprintf (stream, " no-force-thumb Examine preceeding label to determine an insn's type\n\n");
|
1675 | aa0aa4fa | bellard | } |