root / hw / a9mpcore.c @ 8294a64d
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1 | f7c70325 | Paul Brook | /*
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2 | f7c70325 | Paul Brook | * Cortex-A9MPCore internal peripheral emulation.
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3 | f7c70325 | Paul Brook | *
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4 | f7c70325 | Paul Brook | * Copyright (c) 2009 CodeSourcery.
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5 | b12080cd | Peter Maydell | * Copyright (c) 2011 Linaro Limited.
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6 | b12080cd | Peter Maydell | * Written by Paul Brook, Peter Maydell.
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7 | f7c70325 | Paul Brook | *
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8 | 8e31bf38 | Matthew Fernandez | * This code is licensed under the GPL.
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9 | f7c70325 | Paul Brook | */
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10 | f7c70325 | Paul Brook | |
11 | b12080cd | Peter Maydell | #include "sysbus.h" |
12 | b12080cd | Peter Maydell | |
13 | b12080cd | Peter Maydell | /* A9MP private memory region. */
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14 | b12080cd | Peter Maydell | |
15 | b12080cd | Peter Maydell | typedef struct a9mp_priv_state { |
16 | ddd76165 | Peter Maydell | SysBusDevice busdev; |
17 | b12080cd | Peter Maydell | uint32_t scu_control; |
18 | 78aca8a7 | Rob Herring | uint32_t scu_status; |
19 | b12080cd | Peter Maydell | uint32_t old_timer_status[8];
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20 | b12080cd | Peter Maydell | uint32_t num_cpu; |
21 | b12080cd | Peter Maydell | MemoryRegion scu_iomem; |
22 | b12080cd | Peter Maydell | MemoryRegion ptimer_iomem; |
23 | b12080cd | Peter Maydell | MemoryRegion container; |
24 | b12080cd | Peter Maydell | DeviceState *mptimer; |
25 | ddd76165 | Peter Maydell | DeviceState *gic; |
26 | a32134aa | Mark Langsdorf | uint32_t num_irq; |
27 | b12080cd | Peter Maydell | } a9mp_priv_state; |
28 | b12080cd | Peter Maydell | |
29 | b12080cd | Peter Maydell | static uint64_t a9_scu_read(void *opaque, target_phys_addr_t offset, |
30 | b12080cd | Peter Maydell | unsigned size)
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31 | b12080cd | Peter Maydell | { |
32 | b12080cd | Peter Maydell | a9mp_priv_state *s = (a9mp_priv_state *)opaque; |
33 | b12080cd | Peter Maydell | switch (offset) {
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34 | b12080cd | Peter Maydell | case 0x00: /* Control */ |
35 | b12080cd | Peter Maydell | return s->scu_control;
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36 | b12080cd | Peter Maydell | case 0x04: /* Configuration */ |
37 | b12080cd | Peter Maydell | return (((1 << s->num_cpu) - 1) << 4) | (s->num_cpu - 1); |
38 | b12080cd | Peter Maydell | case 0x08: /* CPU Power Status */ |
39 | 78aca8a7 | Rob Herring | return s->scu_status;
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40 | 78aca8a7 | Rob Herring | case 0x09: /* CPU status. */ |
41 | 78aca8a7 | Rob Herring | return s->scu_status >> 8; |
42 | 78aca8a7 | Rob Herring | case 0x0a: /* CPU status. */ |
43 | 78aca8a7 | Rob Herring | return s->scu_status >> 16; |
44 | 78aca8a7 | Rob Herring | case 0x0b: /* CPU status. */ |
45 | 78aca8a7 | Rob Herring | return s->scu_status >> 24; |
46 | b12080cd | Peter Maydell | case 0x0c: /* Invalidate All Registers In Secure State */ |
47 | b12080cd | Peter Maydell | return 0; |
48 | b12080cd | Peter Maydell | case 0x40: /* Filtering Start Address Register */ |
49 | b12080cd | Peter Maydell | case 0x44: /* Filtering End Address Register */ |
50 | b12080cd | Peter Maydell | /* RAZ/WI, like an implementation with only one AXI master */
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51 | b12080cd | Peter Maydell | return 0; |
52 | b12080cd | Peter Maydell | case 0x50: /* SCU Access Control Register */ |
53 | b12080cd | Peter Maydell | case 0x54: /* SCU Non-secure Access Control Register */ |
54 | b12080cd | Peter Maydell | /* unimplemented, fall through */
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55 | b12080cd | Peter Maydell | default:
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56 | b12080cd | Peter Maydell | return 0; |
57 | b12080cd | Peter Maydell | } |
58 | b12080cd | Peter Maydell | } |
59 | b12080cd | Peter Maydell | |
60 | b12080cd | Peter Maydell | static void a9_scu_write(void *opaque, target_phys_addr_t offset, |
61 | b12080cd | Peter Maydell | uint64_t value, unsigned size)
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62 | b12080cd | Peter Maydell | { |
63 | b12080cd | Peter Maydell | a9mp_priv_state *s = (a9mp_priv_state *)opaque; |
64 | 78aca8a7 | Rob Herring | uint32_t mask; |
65 | 78aca8a7 | Rob Herring | uint32_t shift; |
66 | 78aca8a7 | Rob Herring | switch (size) {
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67 | 78aca8a7 | Rob Herring | case 1: |
68 | 78aca8a7 | Rob Herring | mask = 0xff;
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69 | 78aca8a7 | Rob Herring | break;
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70 | 78aca8a7 | Rob Herring | case 2: |
71 | 78aca8a7 | Rob Herring | mask = 0xffff;
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72 | 78aca8a7 | Rob Herring | break;
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73 | 78aca8a7 | Rob Herring | case 4: |
74 | 78aca8a7 | Rob Herring | mask = 0xffffffff;
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75 | 78aca8a7 | Rob Herring | break;
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76 | 78aca8a7 | Rob Herring | default:
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77 | 78aca8a7 | Rob Herring | fprintf(stderr, "Invalid size %u in write to a9 scu register %x\n",
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78 | 78aca8a7 | Rob Herring | size, offset); |
79 | 78aca8a7 | Rob Herring | return;
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80 | 78aca8a7 | Rob Herring | } |
81 | 78aca8a7 | Rob Herring | |
82 | b12080cd | Peter Maydell | switch (offset) {
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83 | b12080cd | Peter Maydell | case 0x00: /* Control */ |
84 | b12080cd | Peter Maydell | s->scu_control = value & 1;
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85 | b12080cd | Peter Maydell | break;
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86 | b12080cd | Peter Maydell | case 0x4: /* Configuration: RO */ |
87 | b12080cd | Peter Maydell | break;
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88 | 78aca8a7 | Rob Herring | case 0x08: case 0x09: case 0x0A: case 0x0B: /* Power Control */ |
89 | 78aca8a7 | Rob Herring | shift = (offset - 0x8) * 8; |
90 | 78aca8a7 | Rob Herring | s->scu_status &= ~(mask << shift); |
91 | 78aca8a7 | Rob Herring | s->scu_status |= ((value & mask) << shift); |
92 | 78aca8a7 | Rob Herring | break;
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93 | b12080cd | Peter Maydell | case 0x0c: /* Invalidate All Registers In Secure State */ |
94 | b12080cd | Peter Maydell | /* no-op as we do not implement caches */
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95 | b12080cd | Peter Maydell | break;
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96 | b12080cd | Peter Maydell | case 0x40: /* Filtering Start Address Register */ |
97 | b12080cd | Peter Maydell | case 0x44: /* Filtering End Address Register */ |
98 | b12080cd | Peter Maydell | /* RAZ/WI, like an implementation with only one AXI master */
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99 | b12080cd | Peter Maydell | break;
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100 | b12080cd | Peter Maydell | case 0x50: /* SCU Access Control Register */ |
101 | b12080cd | Peter Maydell | case 0x54: /* SCU Non-secure Access Control Register */ |
102 | b12080cd | Peter Maydell | /* unimplemented, fall through */
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103 | b12080cd | Peter Maydell | default:
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104 | b12080cd | Peter Maydell | break;
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105 | b12080cd | Peter Maydell | } |
106 | b12080cd | Peter Maydell | } |
107 | b12080cd | Peter Maydell | |
108 | b12080cd | Peter Maydell | static const MemoryRegionOps a9_scu_ops = { |
109 | b12080cd | Peter Maydell | .read = a9_scu_read, |
110 | b12080cd | Peter Maydell | .write = a9_scu_write, |
111 | b12080cd | Peter Maydell | .endianness = DEVICE_NATIVE_ENDIAN, |
112 | b12080cd | Peter Maydell | }; |
113 | b12080cd | Peter Maydell | |
114 | b12080cd | Peter Maydell | static void a9mp_priv_reset(DeviceState *dev) |
115 | b12080cd | Peter Maydell | { |
116 | ddd76165 | Peter Maydell | a9mp_priv_state *s = FROM_SYSBUS(a9mp_priv_state, sysbus_from_qdev(dev)); |
117 | b12080cd | Peter Maydell | int i;
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118 | b12080cd | Peter Maydell | s->scu_control = 0;
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119 | b12080cd | Peter Maydell | for (i = 0; i < ARRAY_SIZE(s->old_timer_status); i++) { |
120 | b12080cd | Peter Maydell | s->old_timer_status[i] = 0;
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121 | b12080cd | Peter Maydell | } |
122 | b12080cd | Peter Maydell | } |
123 | b12080cd | Peter Maydell | |
124 | ddd76165 | Peter Maydell | static void a9mp_priv_set_irq(void *opaque, int irq, int level) |
125 | ddd76165 | Peter Maydell | { |
126 | ddd76165 | Peter Maydell | a9mp_priv_state *s = (a9mp_priv_state *)opaque; |
127 | ddd76165 | Peter Maydell | qemu_set_irq(qdev_get_gpio_in(s->gic, irq), level); |
128 | ddd76165 | Peter Maydell | } |
129 | ddd76165 | Peter Maydell | |
130 | b12080cd | Peter Maydell | static int a9mp_priv_init(SysBusDevice *dev) |
131 | b12080cd | Peter Maydell | { |
132 | ddd76165 | Peter Maydell | a9mp_priv_state *s = FROM_SYSBUS(a9mp_priv_state, dev); |
133 | ddd76165 | Peter Maydell | SysBusDevice *busdev, *gicbusdev; |
134 | b12080cd | Peter Maydell | int i;
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135 | b12080cd | Peter Maydell | |
136 | ddd76165 | Peter Maydell | s->gic = qdev_create(NULL, "arm_gic"); |
137 | ddd76165 | Peter Maydell | qdev_prop_set_uint32(s->gic, "num-cpu", s->num_cpu);
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138 | ddd76165 | Peter Maydell | qdev_prop_set_uint32(s->gic, "num-irq", s->num_irq);
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139 | ddd76165 | Peter Maydell | qdev_init_nofail(s->gic); |
140 | ddd76165 | Peter Maydell | gicbusdev = sysbus_from_qdev(s->gic); |
141 | ddd76165 | Peter Maydell | |
142 | ddd76165 | Peter Maydell | /* Pass through outbound IRQ lines from the GIC */
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143 | ddd76165 | Peter Maydell | sysbus_pass_irq(dev, gicbusdev); |
144 | ddd76165 | Peter Maydell | |
145 | ddd76165 | Peter Maydell | /* Pass through inbound GPIO lines to the GIC */
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146 | ddd76165 | Peter Maydell | qdev_init_gpio_in(&s->busdev.qdev, a9mp_priv_set_irq, s->num_irq - 32);
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147 | b12080cd | Peter Maydell | |
148 | b12080cd | Peter Maydell | s->mptimer = qdev_create(NULL, "arm_mptimer"); |
149 | b12080cd | Peter Maydell | qdev_prop_set_uint32(s->mptimer, "num-cpu", s->num_cpu);
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150 | b12080cd | Peter Maydell | qdev_init_nofail(s->mptimer); |
151 | b12080cd | Peter Maydell | busdev = sysbus_from_qdev(s->mptimer); |
152 | b12080cd | Peter Maydell | |
153 | b12080cd | Peter Maydell | /* Memory map (addresses are offsets from PERIPHBASE):
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154 | b12080cd | Peter Maydell | * 0x0000-0x00ff -- Snoop Control Unit
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155 | b12080cd | Peter Maydell | * 0x0100-0x01ff -- GIC CPU interface
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156 | b12080cd | Peter Maydell | * 0x0200-0x02ff -- Global Timer
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157 | b12080cd | Peter Maydell | * 0x0300-0x05ff -- nothing
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158 | b12080cd | Peter Maydell | * 0x0600-0x06ff -- private timers and watchdogs
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159 | b12080cd | Peter Maydell | * 0x0700-0x0fff -- nothing
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160 | b12080cd | Peter Maydell | * 0x1000-0x1fff -- GIC Distributor
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161 | b12080cd | Peter Maydell | *
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162 | b12080cd | Peter Maydell | * We should implement the global timer but don't currently do so.
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163 | b12080cd | Peter Maydell | */
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164 | b12080cd | Peter Maydell | memory_region_init(&s->container, "a9mp-priv-container", 0x2000); |
165 | b12080cd | Peter Maydell | memory_region_init_io(&s->scu_iomem, &a9_scu_ops, s, "a9mp-scu", 0x100); |
166 | b12080cd | Peter Maydell | memory_region_add_subregion(&s->container, 0, &s->scu_iomem);
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167 | b12080cd | Peter Maydell | /* GIC CPU interface */
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168 | ddd76165 | Peter Maydell | memory_region_add_subregion(&s->container, 0x100,
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169 | ddd76165 | Peter Maydell | sysbus_mmio_get_region(gicbusdev, 1));
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170 | b12080cd | Peter Maydell | /* Note that the A9 exposes only the "timer/watchdog for this core"
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171 | b12080cd | Peter Maydell | * memory region, not the "timer/watchdog for core X" ones 11MPcore has.
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172 | b12080cd | Peter Maydell | */
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173 | b12080cd | Peter Maydell | memory_region_add_subregion(&s->container, 0x600,
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174 | b12080cd | Peter Maydell | sysbus_mmio_get_region(busdev, 0));
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175 | b12080cd | Peter Maydell | memory_region_add_subregion(&s->container, 0x620,
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176 | b12080cd | Peter Maydell | sysbus_mmio_get_region(busdev, 1));
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177 | ddd76165 | Peter Maydell | memory_region_add_subregion(&s->container, 0x1000,
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178 | ddd76165 | Peter Maydell | sysbus_mmio_get_region(gicbusdev, 0));
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179 | b12080cd | Peter Maydell | |
180 | b12080cd | Peter Maydell | sysbus_init_mmio(dev, &s->container); |
181 | b12080cd | Peter Maydell | |
182 | ddd76165 | Peter Maydell | /* Wire up the interrupt from each watchdog and timer.
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183 | ddd76165 | Peter Maydell | * For each core the timer is PPI 29 and the watchdog PPI 30.
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184 | ddd76165 | Peter Maydell | */
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185 | ddd76165 | Peter Maydell | for (i = 0; i < s->num_cpu; i++) { |
186 | ddd76165 | Peter Maydell | int ppibase = (s->num_irq - 32) + i * 32; |
187 | ddd76165 | Peter Maydell | sysbus_connect_irq(busdev, i * 2,
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188 | ddd76165 | Peter Maydell | qdev_get_gpio_in(s->gic, ppibase + 29));
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189 | ddd76165 | Peter Maydell | sysbus_connect_irq(busdev, i * 2 + 1, |
190 | ddd76165 | Peter Maydell | qdev_get_gpio_in(s->gic, ppibase + 30));
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191 | b12080cd | Peter Maydell | } |
192 | b12080cd | Peter Maydell | return 0; |
193 | b12080cd | Peter Maydell | } |
194 | b12080cd | Peter Maydell | |
195 | b12080cd | Peter Maydell | static const VMStateDescription vmstate_a9mp_priv = { |
196 | b12080cd | Peter Maydell | .name = "a9mpcore_priv",
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197 | 78aca8a7 | Rob Herring | .version_id = 2,
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198 | b12080cd | Peter Maydell | .minimum_version_id = 1,
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199 | b12080cd | Peter Maydell | .fields = (VMStateField[]) { |
200 | b12080cd | Peter Maydell | VMSTATE_UINT32(scu_control, a9mp_priv_state), |
201 | b12080cd | Peter Maydell | VMSTATE_UINT32_ARRAY(old_timer_status, a9mp_priv_state, 8),
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202 | 78aca8a7 | Rob Herring | VMSTATE_UINT32_V(scu_status, a9mp_priv_state, 2),
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203 | b12080cd | Peter Maydell | VMSTATE_END_OF_LIST() |
204 | b12080cd | Peter Maydell | } |
205 | b12080cd | Peter Maydell | }; |
206 | f7c70325 | Paul Brook | |
207 | 39bffca2 | Anthony Liguori | static Property a9mp_priv_properties[] = {
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208 | 39bffca2 | Anthony Liguori | DEFINE_PROP_UINT32("num-cpu", a9mp_priv_state, num_cpu, 1), |
209 | 39bffca2 | Anthony Liguori | /* The Cortex-A9MP may have anything from 0 to 224 external interrupt
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210 | 39bffca2 | Anthony Liguori | * IRQ lines (with another 32 internal). We default to 64+32, which
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211 | 39bffca2 | Anthony Liguori | * is the number provided by the Cortex-A9MP test chip in the
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212 | 39bffca2 | Anthony Liguori | * Realview PBX-A9 and Versatile Express A9 development boards.
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213 | 39bffca2 | Anthony Liguori | * Other boards may differ and should set this property appropriately.
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214 | 39bffca2 | Anthony Liguori | */
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215 | 39bffca2 | Anthony Liguori | DEFINE_PROP_UINT32("num-irq", a9mp_priv_state, num_irq, 96), |
216 | 39bffca2 | Anthony Liguori | DEFINE_PROP_END_OF_LIST(), |
217 | 39bffca2 | Anthony Liguori | }; |
218 | 39bffca2 | Anthony Liguori | |
219 | 999e12bb | Anthony Liguori | static void a9mp_priv_class_init(ObjectClass *klass, void *data) |
220 | 999e12bb | Anthony Liguori | { |
221 | 39bffca2 | Anthony Liguori | DeviceClass *dc = DEVICE_CLASS(klass); |
222 | 999e12bb | Anthony Liguori | SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); |
223 | 999e12bb | Anthony Liguori | |
224 | 999e12bb | Anthony Liguori | k->init = a9mp_priv_init; |
225 | 39bffca2 | Anthony Liguori | dc->props = a9mp_priv_properties; |
226 | 39bffca2 | Anthony Liguori | dc->vmsd = &vmstate_a9mp_priv; |
227 | 39bffca2 | Anthony Liguori | dc->reset = a9mp_priv_reset; |
228 | 999e12bb | Anthony Liguori | } |
229 | 999e12bb | Anthony Liguori | |
230 | 39bffca2 | Anthony Liguori | static TypeInfo a9mp_priv_info = {
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231 | 39bffca2 | Anthony Liguori | .name = "a9mpcore_priv",
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232 | 39bffca2 | Anthony Liguori | .parent = TYPE_SYS_BUS_DEVICE, |
233 | 39bffca2 | Anthony Liguori | .instance_size = sizeof(a9mp_priv_state),
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234 | 39bffca2 | Anthony Liguori | .class_init = a9mp_priv_class_init, |
235 | f7c70325 | Paul Brook | }; |
236 | f7c70325 | Paul Brook | |
237 | 83f7d43a | Andreas Färber | static void a9mp_register_types(void) |
238 | f7c70325 | Paul Brook | { |
239 | 39bffca2 | Anthony Liguori | type_register_static(&a9mp_priv_info); |
240 | f7c70325 | Paul Brook | } |
241 | f7c70325 | Paul Brook | |
242 | 83f7d43a | Andreas Färber | type_init(a9mp_register_types) |