root / hw / arm_mptimer.c @ 8294a64d
History | View | Annotate | Download (9.8 kB)
1 | b9dc07d4 | Peter Maydell | /*
|
---|---|---|---|
2 | b9dc07d4 | Peter Maydell | * Private peripheral timer/watchdog blocks for ARM 11MPCore and A9MP
|
3 | b9dc07d4 | Peter Maydell | *
|
4 | b9dc07d4 | Peter Maydell | * Copyright (c) 2006-2007 CodeSourcery.
|
5 | b9dc07d4 | Peter Maydell | * Copyright (c) 2011 Linaro Limited
|
6 | b9dc07d4 | Peter Maydell | * Written by Paul Brook, Peter Maydell
|
7 | b9dc07d4 | Peter Maydell | *
|
8 | b9dc07d4 | Peter Maydell | * This program is free software; you can redistribute it and/or
|
9 | b9dc07d4 | Peter Maydell | * modify it under the terms of the GNU General Public License
|
10 | b9dc07d4 | Peter Maydell | * as published by the Free Software Foundation; either version
|
11 | b9dc07d4 | Peter Maydell | * 2 of the License, or (at your option) any later version.
|
12 | b9dc07d4 | Peter Maydell | *
|
13 | b9dc07d4 | Peter Maydell | * This program is distributed in the hope that it will be useful,
|
14 | b9dc07d4 | Peter Maydell | * but WITHOUT ANY WARRANTY; without even the implied warranty of
|
15 | b9dc07d4 | Peter Maydell | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
16 | b9dc07d4 | Peter Maydell | * GNU General Public License for more details.
|
17 | b9dc07d4 | Peter Maydell | *
|
18 | b9dc07d4 | Peter Maydell | * You should have received a copy of the GNU General Public License along
|
19 | b9dc07d4 | Peter Maydell | * with this program; if not, see <http://www.gnu.org/licenses/>.
|
20 | b9dc07d4 | Peter Maydell | */
|
21 | b9dc07d4 | Peter Maydell | |
22 | b9dc07d4 | Peter Maydell | #include "sysbus.h" |
23 | b9dc07d4 | Peter Maydell | #include "qemu-timer.h" |
24 | b9dc07d4 | Peter Maydell | |
25 | b9dc07d4 | Peter Maydell | /* This device implements the per-cpu private timer and watchdog block
|
26 | b9dc07d4 | Peter Maydell | * which is used in both the ARM11MPCore and Cortex-A9MP.
|
27 | b9dc07d4 | Peter Maydell | */
|
28 | b9dc07d4 | Peter Maydell | |
29 | b9dc07d4 | Peter Maydell | #define MAX_CPUS 4 |
30 | b9dc07d4 | Peter Maydell | |
31 | b9dc07d4 | Peter Maydell | /* State of a single timer or watchdog block */
|
32 | b9dc07d4 | Peter Maydell | typedef struct { |
33 | b9dc07d4 | Peter Maydell | uint32_t count; |
34 | b9dc07d4 | Peter Maydell | uint32_t load; |
35 | b9dc07d4 | Peter Maydell | uint32_t control; |
36 | b9dc07d4 | Peter Maydell | uint32_t status; |
37 | b9dc07d4 | Peter Maydell | int64_t tick; |
38 | b9dc07d4 | Peter Maydell | QEMUTimer *timer; |
39 | b9dc07d4 | Peter Maydell | qemu_irq irq; |
40 | b9dc07d4 | Peter Maydell | MemoryRegion iomem; |
41 | b9dc07d4 | Peter Maydell | } timerblock; |
42 | b9dc07d4 | Peter Maydell | |
43 | b9dc07d4 | Peter Maydell | typedef struct { |
44 | b9dc07d4 | Peter Maydell | SysBusDevice busdev; |
45 | b9dc07d4 | Peter Maydell | uint32_t num_cpu; |
46 | b9dc07d4 | Peter Maydell | timerblock timerblock[MAX_CPUS * 2];
|
47 | b9dc07d4 | Peter Maydell | MemoryRegion iomem[2];
|
48 | b9dc07d4 | Peter Maydell | } arm_mptimer_state; |
49 | b9dc07d4 | Peter Maydell | |
50 | b9dc07d4 | Peter Maydell | static inline int get_current_cpu(arm_mptimer_state *s) |
51 | b9dc07d4 | Peter Maydell | { |
52 | b9dc07d4 | Peter Maydell | if (cpu_single_env->cpu_index >= s->num_cpu) {
|
53 | b9dc07d4 | Peter Maydell | hw_error("arm_mptimer: num-cpu %d but this cpu is %d!\n",
|
54 | b9dc07d4 | Peter Maydell | s->num_cpu, cpu_single_env->cpu_index); |
55 | b9dc07d4 | Peter Maydell | } |
56 | b9dc07d4 | Peter Maydell | return cpu_single_env->cpu_index;
|
57 | b9dc07d4 | Peter Maydell | } |
58 | b9dc07d4 | Peter Maydell | |
59 | b9dc07d4 | Peter Maydell | static inline void timerblock_update_irq(timerblock *tb) |
60 | b9dc07d4 | Peter Maydell | { |
61 | b9dc07d4 | Peter Maydell | qemu_set_irq(tb->irq, tb->status); |
62 | b9dc07d4 | Peter Maydell | } |
63 | b9dc07d4 | Peter Maydell | |
64 | b9dc07d4 | Peter Maydell | /* Return conversion factor from mpcore timer ticks to qemu timer ticks. */
|
65 | b9dc07d4 | Peter Maydell | static inline uint32_t timerblock_scale(timerblock *tb) |
66 | b9dc07d4 | Peter Maydell | { |
67 | b9dc07d4 | Peter Maydell | return (((tb->control >> 8) & 0xff) + 1) * 10; |
68 | b9dc07d4 | Peter Maydell | } |
69 | b9dc07d4 | Peter Maydell | |
70 | b9dc07d4 | Peter Maydell | static void timerblock_reload(timerblock *tb, int restart) |
71 | b9dc07d4 | Peter Maydell | { |
72 | b9dc07d4 | Peter Maydell | if (tb->count == 0) { |
73 | b9dc07d4 | Peter Maydell | return;
|
74 | b9dc07d4 | Peter Maydell | } |
75 | b9dc07d4 | Peter Maydell | if (restart) {
|
76 | b9dc07d4 | Peter Maydell | tb->tick = qemu_get_clock_ns(vm_clock); |
77 | b9dc07d4 | Peter Maydell | } |
78 | b9dc07d4 | Peter Maydell | tb->tick += (int64_t)tb->count * timerblock_scale(tb); |
79 | b9dc07d4 | Peter Maydell | qemu_mod_timer(tb->timer, tb->tick); |
80 | b9dc07d4 | Peter Maydell | } |
81 | b9dc07d4 | Peter Maydell | |
82 | b9dc07d4 | Peter Maydell | static void timerblock_tick(void *opaque) |
83 | b9dc07d4 | Peter Maydell | { |
84 | b9dc07d4 | Peter Maydell | timerblock *tb = (timerblock *)opaque; |
85 | b9dc07d4 | Peter Maydell | tb->status = 1;
|
86 | b9dc07d4 | Peter Maydell | if (tb->control & 2) { |
87 | b9dc07d4 | Peter Maydell | tb->count = tb->load; |
88 | b9dc07d4 | Peter Maydell | timerblock_reload(tb, 0);
|
89 | b9dc07d4 | Peter Maydell | } else {
|
90 | b9dc07d4 | Peter Maydell | tb->count = 0;
|
91 | b9dc07d4 | Peter Maydell | } |
92 | b9dc07d4 | Peter Maydell | timerblock_update_irq(tb); |
93 | b9dc07d4 | Peter Maydell | } |
94 | b9dc07d4 | Peter Maydell | |
95 | b9dc07d4 | Peter Maydell | static uint64_t timerblock_read(void *opaque, target_phys_addr_t addr, |
96 | b9dc07d4 | Peter Maydell | unsigned size)
|
97 | b9dc07d4 | Peter Maydell | { |
98 | b9dc07d4 | Peter Maydell | timerblock *tb = (timerblock *)opaque; |
99 | b9dc07d4 | Peter Maydell | int64_t val; |
100 | b9dc07d4 | Peter Maydell | switch (addr) {
|
101 | b9dc07d4 | Peter Maydell | case 0: /* Load */ |
102 | b9dc07d4 | Peter Maydell | return tb->load;
|
103 | b9dc07d4 | Peter Maydell | case 4: /* Counter. */ |
104 | b9dc07d4 | Peter Maydell | if (((tb->control & 1) == 0) || (tb->count == 0)) { |
105 | b9dc07d4 | Peter Maydell | return 0; |
106 | b9dc07d4 | Peter Maydell | } |
107 | b9dc07d4 | Peter Maydell | /* Slow and ugly, but hopefully won't happen too often. */
|
108 | b9dc07d4 | Peter Maydell | val = tb->tick - qemu_get_clock_ns(vm_clock); |
109 | b9dc07d4 | Peter Maydell | val /= timerblock_scale(tb); |
110 | b9dc07d4 | Peter Maydell | if (val < 0) { |
111 | b9dc07d4 | Peter Maydell | val = 0;
|
112 | b9dc07d4 | Peter Maydell | } |
113 | b9dc07d4 | Peter Maydell | return val;
|
114 | b9dc07d4 | Peter Maydell | case 8: /* Control. */ |
115 | b9dc07d4 | Peter Maydell | return tb->control;
|
116 | b9dc07d4 | Peter Maydell | case 12: /* Interrupt status. */ |
117 | b9dc07d4 | Peter Maydell | return tb->status;
|
118 | b9dc07d4 | Peter Maydell | default:
|
119 | b9dc07d4 | Peter Maydell | return 0; |
120 | b9dc07d4 | Peter Maydell | } |
121 | b9dc07d4 | Peter Maydell | } |
122 | b9dc07d4 | Peter Maydell | |
123 | b9dc07d4 | Peter Maydell | static void timerblock_write(void *opaque, target_phys_addr_t addr, |
124 | b9dc07d4 | Peter Maydell | uint64_t value, unsigned size)
|
125 | b9dc07d4 | Peter Maydell | { |
126 | b9dc07d4 | Peter Maydell | timerblock *tb = (timerblock *)opaque; |
127 | b9dc07d4 | Peter Maydell | int64_t old; |
128 | b9dc07d4 | Peter Maydell | switch (addr) {
|
129 | b9dc07d4 | Peter Maydell | case 0: /* Load */ |
130 | b9dc07d4 | Peter Maydell | tb->load = value; |
131 | b9dc07d4 | Peter Maydell | /* Fall through. */
|
132 | b9dc07d4 | Peter Maydell | case 4: /* Counter. */ |
133 | b9dc07d4 | Peter Maydell | if ((tb->control & 1) && tb->count) { |
134 | b9dc07d4 | Peter Maydell | /* Cancel the previous timer. */
|
135 | b9dc07d4 | Peter Maydell | qemu_del_timer(tb->timer); |
136 | b9dc07d4 | Peter Maydell | } |
137 | b9dc07d4 | Peter Maydell | tb->count = value; |
138 | b9dc07d4 | Peter Maydell | if (tb->control & 1) { |
139 | b9dc07d4 | Peter Maydell | timerblock_reload(tb, 1);
|
140 | b9dc07d4 | Peter Maydell | } |
141 | b9dc07d4 | Peter Maydell | break;
|
142 | b9dc07d4 | Peter Maydell | case 8: /* Control. */ |
143 | b9dc07d4 | Peter Maydell | old = tb->control; |
144 | b9dc07d4 | Peter Maydell | tb->control = value; |
145 | b9dc07d4 | Peter Maydell | if (((old & 1) == 0) && (value & 1)) { |
146 | b9dc07d4 | Peter Maydell | if (tb->count == 0 && (tb->control & 2)) { |
147 | b9dc07d4 | Peter Maydell | tb->count = tb->load; |
148 | b9dc07d4 | Peter Maydell | } |
149 | b9dc07d4 | Peter Maydell | timerblock_reload(tb, 1);
|
150 | b9dc07d4 | Peter Maydell | } |
151 | b9dc07d4 | Peter Maydell | break;
|
152 | b9dc07d4 | Peter Maydell | case 12: /* Interrupt status. */ |
153 | b9dc07d4 | Peter Maydell | tb->status &= ~value; |
154 | b9dc07d4 | Peter Maydell | timerblock_update_irq(tb); |
155 | b9dc07d4 | Peter Maydell | break;
|
156 | b9dc07d4 | Peter Maydell | } |
157 | b9dc07d4 | Peter Maydell | } |
158 | b9dc07d4 | Peter Maydell | |
159 | b9dc07d4 | Peter Maydell | /* Wrapper functions to implement the "read timer/watchdog for
|
160 | b9dc07d4 | Peter Maydell | * the current CPU" memory regions.
|
161 | b9dc07d4 | Peter Maydell | */
|
162 | b9dc07d4 | Peter Maydell | static uint64_t arm_thistimer_read(void *opaque, target_phys_addr_t addr, |
163 | b9dc07d4 | Peter Maydell | unsigned size)
|
164 | b9dc07d4 | Peter Maydell | { |
165 | b9dc07d4 | Peter Maydell | arm_mptimer_state *s = (arm_mptimer_state *)opaque; |
166 | b9dc07d4 | Peter Maydell | int id = get_current_cpu(s);
|
167 | b9dc07d4 | Peter Maydell | return timerblock_read(&s->timerblock[id * 2], addr, size); |
168 | b9dc07d4 | Peter Maydell | } |
169 | b9dc07d4 | Peter Maydell | |
170 | b9dc07d4 | Peter Maydell | static void arm_thistimer_write(void *opaque, target_phys_addr_t addr, |
171 | b9dc07d4 | Peter Maydell | uint64_t value, unsigned size)
|
172 | b9dc07d4 | Peter Maydell | { |
173 | b9dc07d4 | Peter Maydell | arm_mptimer_state *s = (arm_mptimer_state *)opaque; |
174 | b9dc07d4 | Peter Maydell | int id = get_current_cpu(s);
|
175 | b9dc07d4 | Peter Maydell | timerblock_write(&s->timerblock[id * 2], addr, value, size);
|
176 | b9dc07d4 | Peter Maydell | } |
177 | b9dc07d4 | Peter Maydell | |
178 | b9dc07d4 | Peter Maydell | static uint64_t arm_thiswdog_read(void *opaque, target_phys_addr_t addr, |
179 | b9dc07d4 | Peter Maydell | unsigned size)
|
180 | b9dc07d4 | Peter Maydell | { |
181 | b9dc07d4 | Peter Maydell | arm_mptimer_state *s = (arm_mptimer_state *)opaque; |
182 | b9dc07d4 | Peter Maydell | int id = get_current_cpu(s);
|
183 | b9dc07d4 | Peter Maydell | return timerblock_read(&s->timerblock[id * 2 + 1], addr, size); |
184 | b9dc07d4 | Peter Maydell | } |
185 | b9dc07d4 | Peter Maydell | |
186 | b9dc07d4 | Peter Maydell | static void arm_thiswdog_write(void *opaque, target_phys_addr_t addr, |
187 | b9dc07d4 | Peter Maydell | uint64_t value, unsigned size)
|
188 | b9dc07d4 | Peter Maydell | { |
189 | b9dc07d4 | Peter Maydell | arm_mptimer_state *s = (arm_mptimer_state *)opaque; |
190 | b9dc07d4 | Peter Maydell | int id = get_current_cpu(s);
|
191 | b9dc07d4 | Peter Maydell | timerblock_write(&s->timerblock[id * 2 + 1], addr, value, size); |
192 | b9dc07d4 | Peter Maydell | } |
193 | b9dc07d4 | Peter Maydell | |
194 | b9dc07d4 | Peter Maydell | static const MemoryRegionOps arm_thistimer_ops = { |
195 | b9dc07d4 | Peter Maydell | .read = arm_thistimer_read, |
196 | b9dc07d4 | Peter Maydell | .write = arm_thistimer_write, |
197 | b9dc07d4 | Peter Maydell | .valid = { |
198 | b9dc07d4 | Peter Maydell | .min_access_size = 4,
|
199 | b9dc07d4 | Peter Maydell | .max_access_size = 4,
|
200 | b9dc07d4 | Peter Maydell | }, |
201 | b9dc07d4 | Peter Maydell | .endianness = DEVICE_NATIVE_ENDIAN, |
202 | b9dc07d4 | Peter Maydell | }; |
203 | b9dc07d4 | Peter Maydell | |
204 | b9dc07d4 | Peter Maydell | static const MemoryRegionOps arm_thiswdog_ops = { |
205 | b9dc07d4 | Peter Maydell | .read = arm_thiswdog_read, |
206 | b9dc07d4 | Peter Maydell | .write = arm_thiswdog_write, |
207 | b9dc07d4 | Peter Maydell | .valid = { |
208 | b9dc07d4 | Peter Maydell | .min_access_size = 4,
|
209 | b9dc07d4 | Peter Maydell | .max_access_size = 4,
|
210 | b9dc07d4 | Peter Maydell | }, |
211 | b9dc07d4 | Peter Maydell | .endianness = DEVICE_NATIVE_ENDIAN, |
212 | b9dc07d4 | Peter Maydell | }; |
213 | b9dc07d4 | Peter Maydell | |
214 | b9dc07d4 | Peter Maydell | static const MemoryRegionOps timerblock_ops = { |
215 | b9dc07d4 | Peter Maydell | .read = timerblock_read, |
216 | b9dc07d4 | Peter Maydell | .write = timerblock_write, |
217 | b9dc07d4 | Peter Maydell | .valid = { |
218 | b9dc07d4 | Peter Maydell | .min_access_size = 4,
|
219 | b9dc07d4 | Peter Maydell | .max_access_size = 4,
|
220 | b9dc07d4 | Peter Maydell | }, |
221 | b9dc07d4 | Peter Maydell | .endianness = DEVICE_NATIVE_ENDIAN, |
222 | b9dc07d4 | Peter Maydell | }; |
223 | b9dc07d4 | Peter Maydell | |
224 | b9dc07d4 | Peter Maydell | static void timerblock_reset(timerblock *tb) |
225 | b9dc07d4 | Peter Maydell | { |
226 | b9dc07d4 | Peter Maydell | tb->count = 0;
|
227 | b9dc07d4 | Peter Maydell | tb->load = 0;
|
228 | b9dc07d4 | Peter Maydell | tb->control = 0;
|
229 | b9dc07d4 | Peter Maydell | tb->status = 0;
|
230 | b9dc07d4 | Peter Maydell | tb->tick = 0;
|
231 | bdac1c1e | Peter Maydell | if (tb->timer) {
|
232 | bdac1c1e | Peter Maydell | qemu_del_timer(tb->timer); |
233 | bdac1c1e | Peter Maydell | } |
234 | b9dc07d4 | Peter Maydell | } |
235 | b9dc07d4 | Peter Maydell | |
236 | b9dc07d4 | Peter Maydell | static void arm_mptimer_reset(DeviceState *dev) |
237 | b9dc07d4 | Peter Maydell | { |
238 | b9dc07d4 | Peter Maydell | arm_mptimer_state *s = |
239 | b9dc07d4 | Peter Maydell | FROM_SYSBUS(arm_mptimer_state, sysbus_from_qdev(dev)); |
240 | b9dc07d4 | Peter Maydell | int i;
|
241 | b9dc07d4 | Peter Maydell | /* We reset every timer in the array, not just the ones we're using,
|
242 | b9dc07d4 | Peter Maydell | * because vmsave will look at every array element.
|
243 | b9dc07d4 | Peter Maydell | */
|
244 | b9dc07d4 | Peter Maydell | for (i = 0; i < ARRAY_SIZE(s->timerblock); i++) { |
245 | b9dc07d4 | Peter Maydell | timerblock_reset(&s->timerblock[i]); |
246 | b9dc07d4 | Peter Maydell | } |
247 | b9dc07d4 | Peter Maydell | } |
248 | b9dc07d4 | Peter Maydell | |
249 | b9dc07d4 | Peter Maydell | static int arm_mptimer_init(SysBusDevice *dev) |
250 | b9dc07d4 | Peter Maydell | { |
251 | b9dc07d4 | Peter Maydell | arm_mptimer_state *s = FROM_SYSBUS(arm_mptimer_state, dev); |
252 | b9dc07d4 | Peter Maydell | int i;
|
253 | b9dc07d4 | Peter Maydell | if (s->num_cpu < 1 || s->num_cpu > MAX_CPUS) { |
254 | b9dc07d4 | Peter Maydell | hw_error("%s: num-cpu must be between 1 and %d\n", __func__, MAX_CPUS);
|
255 | b9dc07d4 | Peter Maydell | } |
256 | b9dc07d4 | Peter Maydell | /* We implement one timer and one watchdog block per CPU, and
|
257 | b9dc07d4 | Peter Maydell | * expose multiple MMIO regions:
|
258 | b9dc07d4 | Peter Maydell | * * region 0 is "timer for this core"
|
259 | b9dc07d4 | Peter Maydell | * * region 1 is "watchdog for this core"
|
260 | b9dc07d4 | Peter Maydell | * * region 2 is "timer for core 0"
|
261 | b9dc07d4 | Peter Maydell | * * region 3 is "watchdog for core 0"
|
262 | b9dc07d4 | Peter Maydell | * * region 4 is "timer for core 1"
|
263 | b9dc07d4 | Peter Maydell | * * region 5 is "watchdog for core 1"
|
264 | b9dc07d4 | Peter Maydell | * and so on.
|
265 | b9dc07d4 | Peter Maydell | * The outgoing interrupt lines are
|
266 | b9dc07d4 | Peter Maydell | * * timer for core 0
|
267 | b9dc07d4 | Peter Maydell | * * watchdog for core 0
|
268 | b9dc07d4 | Peter Maydell | * * timer for core 1
|
269 | b9dc07d4 | Peter Maydell | * * watchdog for core 1
|
270 | b9dc07d4 | Peter Maydell | * and so on.
|
271 | b9dc07d4 | Peter Maydell | */
|
272 | b9dc07d4 | Peter Maydell | memory_region_init_io(&s->iomem[0], &arm_thistimer_ops, s,
|
273 | b9dc07d4 | Peter Maydell | "arm_mptimer_timer", 0x20); |
274 | b9dc07d4 | Peter Maydell | sysbus_init_mmio(dev, &s->iomem[0]);
|
275 | b9dc07d4 | Peter Maydell | memory_region_init_io(&s->iomem[1], &arm_thiswdog_ops, s,
|
276 | b9dc07d4 | Peter Maydell | "arm_mptimer_wdog", 0x20); |
277 | b9dc07d4 | Peter Maydell | sysbus_init_mmio(dev, &s->iomem[1]);
|
278 | b9dc07d4 | Peter Maydell | for (i = 0; i < (s->num_cpu * 2); i++) { |
279 | b9dc07d4 | Peter Maydell | timerblock *tb = &s->timerblock[i]; |
280 | b9dc07d4 | Peter Maydell | tb->timer = qemu_new_timer_ns(vm_clock, timerblock_tick, tb); |
281 | b9dc07d4 | Peter Maydell | sysbus_init_irq(dev, &tb->irq); |
282 | b9dc07d4 | Peter Maydell | memory_region_init_io(&tb->iomem, &timerblock_ops, tb, |
283 | b9dc07d4 | Peter Maydell | "arm_mptimer_timerblock", 0x20); |
284 | b9dc07d4 | Peter Maydell | sysbus_init_mmio(dev, &tb->iomem); |
285 | b9dc07d4 | Peter Maydell | } |
286 | b9dc07d4 | Peter Maydell | |
287 | b9dc07d4 | Peter Maydell | return 0; |
288 | b9dc07d4 | Peter Maydell | } |
289 | b9dc07d4 | Peter Maydell | |
290 | b9dc07d4 | Peter Maydell | static const VMStateDescription vmstate_timerblock = { |
291 | b9dc07d4 | Peter Maydell | .name = "arm_mptimer_timerblock",
|
292 | b9dc07d4 | Peter Maydell | .version_id = 1,
|
293 | b9dc07d4 | Peter Maydell | .minimum_version_id = 1,
|
294 | b9dc07d4 | Peter Maydell | .fields = (VMStateField[]) { |
295 | b9dc07d4 | Peter Maydell | VMSTATE_UINT32(count, timerblock), |
296 | b9dc07d4 | Peter Maydell | VMSTATE_UINT32(load, timerblock), |
297 | b9dc07d4 | Peter Maydell | VMSTATE_UINT32(control, timerblock), |
298 | b9dc07d4 | Peter Maydell | VMSTATE_UINT32(status, timerblock), |
299 | b9dc07d4 | Peter Maydell | VMSTATE_INT64(tick, timerblock), |
300 | b9dc07d4 | Peter Maydell | VMSTATE_END_OF_LIST() |
301 | b9dc07d4 | Peter Maydell | } |
302 | b9dc07d4 | Peter Maydell | }; |
303 | b9dc07d4 | Peter Maydell | |
304 | b9dc07d4 | Peter Maydell | static const VMStateDescription vmstate_arm_mptimer = { |
305 | b9dc07d4 | Peter Maydell | .name = "arm_mptimer",
|
306 | b9dc07d4 | Peter Maydell | .version_id = 1,
|
307 | b9dc07d4 | Peter Maydell | .minimum_version_id = 1,
|
308 | b9dc07d4 | Peter Maydell | .fields = (VMStateField[]) { |
309 | b9dc07d4 | Peter Maydell | VMSTATE_STRUCT_ARRAY(timerblock, arm_mptimer_state, (MAX_CPUS * 2),
|
310 | b9dc07d4 | Peter Maydell | 1, vmstate_timerblock, timerblock),
|
311 | b9dc07d4 | Peter Maydell | VMSTATE_END_OF_LIST() |
312 | b9dc07d4 | Peter Maydell | } |
313 | b9dc07d4 | Peter Maydell | }; |
314 | b9dc07d4 | Peter Maydell | |
315 | 39bffca2 | Anthony Liguori | static Property arm_mptimer_properties[] = {
|
316 | 39bffca2 | Anthony Liguori | DEFINE_PROP_UINT32("num-cpu", arm_mptimer_state, num_cpu, 0), |
317 | 39bffca2 | Anthony Liguori | DEFINE_PROP_END_OF_LIST() |
318 | 39bffca2 | Anthony Liguori | }; |
319 | 39bffca2 | Anthony Liguori | |
320 | 999e12bb | Anthony Liguori | static void arm_mptimer_class_init(ObjectClass *klass, void *data) |
321 | 999e12bb | Anthony Liguori | { |
322 | 39bffca2 | Anthony Liguori | DeviceClass *dc = DEVICE_CLASS(klass); |
323 | 999e12bb | Anthony Liguori | SysBusDeviceClass *sbc = SYS_BUS_DEVICE_CLASS(klass); |
324 | 999e12bb | Anthony Liguori | |
325 | 999e12bb | Anthony Liguori | sbc->init = arm_mptimer_init; |
326 | 39bffca2 | Anthony Liguori | dc->vmsd = &vmstate_arm_mptimer; |
327 | 39bffca2 | Anthony Liguori | dc->reset = arm_mptimer_reset; |
328 | 39bffca2 | Anthony Liguori | dc->no_user = 1;
|
329 | 39bffca2 | Anthony Liguori | dc->props = arm_mptimer_properties; |
330 | 999e12bb | Anthony Liguori | } |
331 | 999e12bb | Anthony Liguori | |
332 | 39bffca2 | Anthony Liguori | static TypeInfo arm_mptimer_info = {
|
333 | 39bffca2 | Anthony Liguori | .name = "arm_mptimer",
|
334 | 39bffca2 | Anthony Liguori | .parent = TYPE_SYS_BUS_DEVICE, |
335 | 39bffca2 | Anthony Liguori | .instance_size = sizeof(arm_mptimer_state),
|
336 | 39bffca2 | Anthony Liguori | .class_init = arm_mptimer_class_init, |
337 | b9dc07d4 | Peter Maydell | }; |
338 | b9dc07d4 | Peter Maydell | |
339 | 83f7d43a | Andreas Färber | static void arm_mptimer_register_types(void) |
340 | b9dc07d4 | Peter Maydell | { |
341 | 39bffca2 | Anthony Liguori | type_register_static(&arm_mptimer_info); |
342 | b9dc07d4 | Peter Maydell | } |
343 | b9dc07d4 | Peter Maydell | |
344 | 83f7d43a | Andreas Färber | type_init(arm_mptimer_register_types) |