root / hw / rtl8139.c @ 8294a64d
History | View | Annotate | Download (101 kB)
1 | a41b2ff2 | pbrook | /**
|
---|---|---|---|
2 | a41b2ff2 | pbrook | * QEMU RTL8139 emulation
|
3 | 5fafdf24 | ths | *
|
4 | a41b2ff2 | pbrook | * Copyright (c) 2006 Igor Kovalenko
|
5 | 5fafdf24 | ths | *
|
6 | a41b2ff2 | pbrook | * Permission is hereby granted, free of charge, to any person obtaining a copy
|
7 | a41b2ff2 | pbrook | * of this software and associated documentation files (the "Software"), to deal
|
8 | a41b2ff2 | pbrook | * in the Software without restriction, including without limitation the rights
|
9 | a41b2ff2 | pbrook | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
10 | a41b2ff2 | pbrook | * copies of the Software, and to permit persons to whom the Software is
|
11 | a41b2ff2 | pbrook | * furnished to do so, subject to the following conditions:
|
12 | a41b2ff2 | pbrook | *
|
13 | a41b2ff2 | pbrook | * The above copyright notice and this permission notice shall be included in
|
14 | a41b2ff2 | pbrook | * all copies or substantial portions of the Software.
|
15 | a41b2ff2 | pbrook | *
|
16 | a41b2ff2 | pbrook | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
17 | a41b2ff2 | pbrook | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
18 | a41b2ff2 | pbrook | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
19 | a41b2ff2 | pbrook | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
20 | a41b2ff2 | pbrook | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
21 | a41b2ff2 | pbrook | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
22 | a41b2ff2 | pbrook | * THE SOFTWARE.
|
23 | 5fafdf24 | ths | |
24 | a41b2ff2 | pbrook | * Modifications:
|
25 | a41b2ff2 | pbrook | * 2006-Jan-28 Mark Malakanov : TSAD and CSCR implementation (for Windows driver)
|
26 | 5fafdf24 | ths | *
|
27 | 6cadb320 | bellard | * 2006-Apr-28 Juergen Lock : EEPROM emulation changes for FreeBSD driver
|
28 | 6cadb320 | bellard | * HW revision ID changes for FreeBSD driver
|
29 | 5fafdf24 | ths | *
|
30 | 6cadb320 | bellard | * 2006-Jul-01 Igor Kovalenko : Implemented loopback mode for FreeBSD driver
|
31 | 6cadb320 | bellard | * Corrected packet transfer reassembly routine for 8139C+ mode
|
32 | 6cadb320 | bellard | * Rearranged debugging print statements
|
33 | 6cadb320 | bellard | * Implemented PCI timer interrupt (disabled by default)
|
34 | 6cadb320 | bellard | * Implemented Tally Counters, increased VM load/save version
|
35 | 6cadb320 | bellard | * Implemented IP/TCP/UDP checksum task offloading
|
36 | 718da2b9 | bellard | *
|
37 | 718da2b9 | bellard | * 2006-Jul-04 Igor Kovalenko : Implemented TCP segmentation offloading
|
38 | 718da2b9 | bellard | * Fixed MTU=1500 for produced ethernet frames
|
39 | 718da2b9 | bellard | *
|
40 | 718da2b9 | bellard | * 2006-Jul-09 Igor Kovalenko : Fixed TCP header length calculation while processing
|
41 | 718da2b9 | bellard | * segmentation offloading
|
42 | 718da2b9 | bellard | * Removed slirp.h dependency
|
43 | 718da2b9 | bellard | * Added rx/tx buffer reset when enabling rx/tx operation
|
44 | 05447803 | Frediano Ziglio | *
|
45 | 05447803 | Frediano Ziglio | * 2010-Feb-04 Frediano Ziglio: Rewrote timer support using QEMU timer only
|
46 | 05447803 | Frediano Ziglio | * when strictly needed (required for for
|
47 | 05447803 | Frediano Ziglio | * Darwin)
|
48 | bf6b87a8 | Benjamin Poirier | * 2011-Mar-22 Benjamin Poirier: Implemented VLAN offloading
|
49 | a41b2ff2 | pbrook | */
|
50 | a41b2ff2 | pbrook | |
51 | 2c406b8f | Benjamin Poirier | /* For crc32 */
|
52 | 2c406b8f | Benjamin Poirier | #include <zlib.h> |
53 | 2c406b8f | Benjamin Poirier | |
54 | 87ecb68b | pbrook | #include "hw.h" |
55 | 87ecb68b | pbrook | #include "pci.h" |
56 | 3ada003a | Eduard - Gabriel Munteanu | #include "dma.h" |
57 | 87ecb68b | pbrook | #include "qemu-timer.h" |
58 | 87ecb68b | pbrook | #include "net.h" |
59 | 254111ec | Gerd Hoffmann | #include "loader.h" |
60 | 1ca4d09a | Gleb Natapov | #include "sysemu.h" |
61 | bf6b87a8 | Benjamin Poirier | #include "iov.h" |
62 | a41b2ff2 | pbrook | |
63 | a41b2ff2 | pbrook | /* debug RTL8139 card */
|
64 | a41b2ff2 | pbrook | //#define DEBUG_RTL8139 1
|
65 | a41b2ff2 | pbrook | |
66 | 6cadb320 | bellard | #define PCI_FREQUENCY 33000000L |
67 | 6cadb320 | bellard | |
68 | a41b2ff2 | pbrook | #define SET_MASKED(input, mask, curr) \
|
69 | a41b2ff2 | pbrook | ( ( (input) & ~(mask) ) | ( (curr) & (mask) ) ) |
70 | a41b2ff2 | pbrook | |
71 | a41b2ff2 | pbrook | /* arg % size for size which is a power of 2 */
|
72 | a41b2ff2 | pbrook | #define MOD2(input, size) \
|
73 | a41b2ff2 | pbrook | ( ( input ) & ( size - 1 ) )
|
74 | a41b2ff2 | pbrook | |
75 | 18dabfd1 | Benjamin Poirier | #define ETHER_ADDR_LEN 6 |
76 | 18dabfd1 | Benjamin Poirier | #define ETHER_TYPE_LEN 2 |
77 | 18dabfd1 | Benjamin Poirier | #define ETH_HLEN (ETHER_ADDR_LEN * 2 + ETHER_TYPE_LEN) |
78 | 18dabfd1 | Benjamin Poirier | #define ETH_P_IP 0x0800 /* Internet Protocol packet */ |
79 | 18dabfd1 | Benjamin Poirier | #define ETH_P_8021Q 0x8100 /* 802.1Q VLAN Extended Header */ |
80 | 18dabfd1 | Benjamin Poirier | #define ETH_MTU 1500 |
81 | 18dabfd1 | Benjamin Poirier | |
82 | 18dabfd1 | Benjamin Poirier | #define VLAN_TCI_LEN 2 |
83 | 18dabfd1 | Benjamin Poirier | #define VLAN_HLEN (ETHER_TYPE_LEN + VLAN_TCI_LEN)
|
84 | 18dabfd1 | Benjamin Poirier | |
85 | 6cadb320 | bellard | #if defined (DEBUG_RTL8139)
|
86 | 7cdeb319 | Benjamin Poirier | # define DPRINTF(fmt, ...) \
|
87 | 7cdeb319 | Benjamin Poirier | do { fprintf(stderr, "RTL8139: " fmt, ## __VA_ARGS__); } while (0) |
88 | 6cadb320 | bellard | #else
|
89 | c6a0487b | Stefan Weil | static inline GCC_FMT_ATTR(1, 2) int DPRINTF(const char *fmt, ...) |
90 | ec48c774 | Benjamin Poirier | { |
91 | ec48c774 | Benjamin Poirier | return 0; |
92 | ec48c774 | Benjamin Poirier | } |
93 | 6cadb320 | bellard | #endif
|
94 | 6cadb320 | bellard | |
95 | a41b2ff2 | pbrook | /* Symbolic offsets to registers. */
|
96 | a41b2ff2 | pbrook | enum RTL8139_registers {
|
97 | a41b2ff2 | pbrook | MAC0 = 0, /* Ethernet hardware address. */ |
98 | a41b2ff2 | pbrook | MAR0 = 8, /* Multicast filter. */ |
99 | 6cadb320 | bellard | TxStatus0 = 0x10,/* Transmit status (Four 32bit registers). C mode only */ |
100 | 6cadb320 | bellard | /* Dump Tally Conter control register(64bit). C+ mode only */
|
101 | 6cadb320 | bellard | TxAddr0 = 0x20, /* Tx descriptors (also four 32bit). */ |
102 | a41b2ff2 | pbrook | RxBuf = 0x30,
|
103 | a41b2ff2 | pbrook | ChipCmd = 0x37,
|
104 | a41b2ff2 | pbrook | RxBufPtr = 0x38,
|
105 | a41b2ff2 | pbrook | RxBufAddr = 0x3A,
|
106 | a41b2ff2 | pbrook | IntrMask = 0x3C,
|
107 | a41b2ff2 | pbrook | IntrStatus = 0x3E,
|
108 | a41b2ff2 | pbrook | TxConfig = 0x40,
|
109 | a41b2ff2 | pbrook | RxConfig = 0x44,
|
110 | a41b2ff2 | pbrook | Timer = 0x48, /* A general-purpose counter. */ |
111 | a41b2ff2 | pbrook | RxMissed = 0x4C, /* 24 bits valid, write clears. */ |
112 | a41b2ff2 | pbrook | Cfg9346 = 0x50,
|
113 | a41b2ff2 | pbrook | Config0 = 0x51,
|
114 | a41b2ff2 | pbrook | Config1 = 0x52,
|
115 | a41b2ff2 | pbrook | FlashReg = 0x54,
|
116 | a41b2ff2 | pbrook | MediaStatus = 0x58,
|
117 | a41b2ff2 | pbrook | Config3 = 0x59,
|
118 | a41b2ff2 | pbrook | Config4 = 0x5A, /* absent on RTL-8139A */ |
119 | a41b2ff2 | pbrook | HltClk = 0x5B,
|
120 | a41b2ff2 | pbrook | MultiIntr = 0x5C,
|
121 | a41b2ff2 | pbrook | PCIRevisionID = 0x5E,
|
122 | a41b2ff2 | pbrook | TxSummary = 0x60, /* TSAD register. Transmit Status of All Descriptors*/ |
123 | a41b2ff2 | pbrook | BasicModeCtrl = 0x62,
|
124 | a41b2ff2 | pbrook | BasicModeStatus = 0x64,
|
125 | a41b2ff2 | pbrook | NWayAdvert = 0x66,
|
126 | a41b2ff2 | pbrook | NWayLPAR = 0x68,
|
127 | a41b2ff2 | pbrook | NWayExpansion = 0x6A,
|
128 | a41b2ff2 | pbrook | /* Undocumented registers, but required for proper operation. */
|
129 | a41b2ff2 | pbrook | FIFOTMS = 0x70, /* FIFO Control and test. */ |
130 | a41b2ff2 | pbrook | CSCR = 0x74, /* Chip Status and Configuration Register. */ |
131 | a41b2ff2 | pbrook | PARA78 = 0x78,
|
132 | a41b2ff2 | pbrook | PARA7c = 0x7c, /* Magic transceiver parameter register. */ |
133 | a41b2ff2 | pbrook | Config5 = 0xD8, /* absent on RTL-8139A */ |
134 | a41b2ff2 | pbrook | /* C+ mode */
|
135 | a41b2ff2 | pbrook | TxPoll = 0xD9, /* Tell chip to check Tx descriptors for work */ |
136 | a41b2ff2 | pbrook | RxMaxSize = 0xDA, /* Max size of an Rx packet (8169 only) */ |
137 | a41b2ff2 | pbrook | CpCmd = 0xE0, /* C+ Command register (C+ mode only) */ |
138 | a41b2ff2 | pbrook | IntrMitigate = 0xE2, /* rx/tx interrupt mitigation control */ |
139 | a41b2ff2 | pbrook | RxRingAddrLO = 0xE4, /* 64-bit start addr of Rx ring */ |
140 | a41b2ff2 | pbrook | RxRingAddrHI = 0xE8, /* 64-bit start addr of Rx ring */ |
141 | a41b2ff2 | pbrook | TxThresh = 0xEC, /* Early Tx threshold */ |
142 | a41b2ff2 | pbrook | }; |
143 | a41b2ff2 | pbrook | |
144 | a41b2ff2 | pbrook | enum ClearBitMasks {
|
145 | a41b2ff2 | pbrook | MultiIntrClear = 0xF000,
|
146 | a41b2ff2 | pbrook | ChipCmdClear = 0xE2,
|
147 | a41b2ff2 | pbrook | Config1Clear = (1<<7)|(1<<6)|(1<<3)|(1<<2)|(1<<1), |
148 | a41b2ff2 | pbrook | }; |
149 | a41b2ff2 | pbrook | |
150 | a41b2ff2 | pbrook | enum ChipCmdBits {
|
151 | a41b2ff2 | pbrook | CmdReset = 0x10,
|
152 | a41b2ff2 | pbrook | CmdRxEnb = 0x08,
|
153 | a41b2ff2 | pbrook | CmdTxEnb = 0x04,
|
154 | a41b2ff2 | pbrook | RxBufEmpty = 0x01,
|
155 | a41b2ff2 | pbrook | }; |
156 | a41b2ff2 | pbrook | |
157 | a41b2ff2 | pbrook | /* C+ mode */
|
158 | a41b2ff2 | pbrook | enum CplusCmdBits {
|
159 | 6cadb320 | bellard | CPlusRxVLAN = 0x0040, /* enable receive VLAN detagging */ |
160 | 6cadb320 | bellard | CPlusRxChkSum = 0x0020, /* enable receive checksum offloading */ |
161 | 6cadb320 | bellard | CPlusRxEnb = 0x0002,
|
162 | 6cadb320 | bellard | CPlusTxEnb = 0x0001,
|
163 | a41b2ff2 | pbrook | }; |
164 | a41b2ff2 | pbrook | |
165 | a41b2ff2 | pbrook | /* Interrupt register bits, using my own meaningful names. */
|
166 | a41b2ff2 | pbrook | enum IntrStatusBits {
|
167 | a41b2ff2 | pbrook | PCIErr = 0x8000,
|
168 | a41b2ff2 | pbrook | PCSTimeout = 0x4000,
|
169 | a41b2ff2 | pbrook | RxFIFOOver = 0x40,
|
170 | a41b2ff2 | pbrook | RxUnderrun = 0x20,
|
171 | a41b2ff2 | pbrook | RxOverflow = 0x10,
|
172 | a41b2ff2 | pbrook | TxErr = 0x08,
|
173 | a41b2ff2 | pbrook | TxOK = 0x04,
|
174 | a41b2ff2 | pbrook | RxErr = 0x02,
|
175 | a41b2ff2 | pbrook | RxOK = 0x01,
|
176 | a41b2ff2 | pbrook | |
177 | a41b2ff2 | pbrook | RxAckBits = RxFIFOOver | RxOverflow | RxOK, |
178 | a41b2ff2 | pbrook | }; |
179 | a41b2ff2 | pbrook | |
180 | a41b2ff2 | pbrook | enum TxStatusBits {
|
181 | a41b2ff2 | pbrook | TxHostOwns = 0x2000,
|
182 | a41b2ff2 | pbrook | TxUnderrun = 0x4000,
|
183 | a41b2ff2 | pbrook | TxStatOK = 0x8000,
|
184 | a41b2ff2 | pbrook | TxOutOfWindow = 0x20000000,
|
185 | a41b2ff2 | pbrook | TxAborted = 0x40000000,
|
186 | a41b2ff2 | pbrook | TxCarrierLost = 0x80000000,
|
187 | a41b2ff2 | pbrook | }; |
188 | a41b2ff2 | pbrook | enum RxStatusBits {
|
189 | a41b2ff2 | pbrook | RxMulticast = 0x8000,
|
190 | a41b2ff2 | pbrook | RxPhysical = 0x4000,
|
191 | a41b2ff2 | pbrook | RxBroadcast = 0x2000,
|
192 | a41b2ff2 | pbrook | RxBadSymbol = 0x0020,
|
193 | a41b2ff2 | pbrook | RxRunt = 0x0010,
|
194 | a41b2ff2 | pbrook | RxTooLong = 0x0008,
|
195 | a41b2ff2 | pbrook | RxCRCErr = 0x0004,
|
196 | a41b2ff2 | pbrook | RxBadAlign = 0x0002,
|
197 | a41b2ff2 | pbrook | RxStatusOK = 0x0001,
|
198 | a41b2ff2 | pbrook | }; |
199 | a41b2ff2 | pbrook | |
200 | a41b2ff2 | pbrook | /* Bits in RxConfig. */
|
201 | a41b2ff2 | pbrook | enum rx_mode_bits {
|
202 | a41b2ff2 | pbrook | AcceptErr = 0x20,
|
203 | a41b2ff2 | pbrook | AcceptRunt = 0x10,
|
204 | a41b2ff2 | pbrook | AcceptBroadcast = 0x08,
|
205 | a41b2ff2 | pbrook | AcceptMulticast = 0x04,
|
206 | a41b2ff2 | pbrook | AcceptMyPhys = 0x02,
|
207 | a41b2ff2 | pbrook | AcceptAllPhys = 0x01,
|
208 | a41b2ff2 | pbrook | }; |
209 | a41b2ff2 | pbrook | |
210 | a41b2ff2 | pbrook | /* Bits in TxConfig. */
|
211 | a41b2ff2 | pbrook | enum tx_config_bits {
|
212 | a41b2ff2 | pbrook | |
213 | a41b2ff2 | pbrook | /* Interframe Gap Time. Only TxIFG96 doesn't violate IEEE 802.3 */
|
214 | a41b2ff2 | pbrook | TxIFGShift = 24,
|
215 | a41b2ff2 | pbrook | TxIFG84 = (0 << TxIFGShift), /* 8.4us / 840ns (10 / 100Mbps) */ |
216 | a41b2ff2 | pbrook | TxIFG88 = (1 << TxIFGShift), /* 8.8us / 880ns (10 / 100Mbps) */ |
217 | a41b2ff2 | pbrook | TxIFG92 = (2 << TxIFGShift), /* 9.2us / 920ns (10 / 100Mbps) */ |
218 | a41b2ff2 | pbrook | TxIFG96 = (3 << TxIFGShift), /* 9.6us / 960ns (10 / 100Mbps) */ |
219 | a41b2ff2 | pbrook | |
220 | a41b2ff2 | pbrook | TxLoopBack = (1 << 18) | (1 << 17), /* enable loopback test mode */ |
221 | a41b2ff2 | pbrook | TxCRC = (1 << 16), /* DISABLE appending CRC to end of Tx packets */ |
222 | a41b2ff2 | pbrook | TxClearAbt = (1 << 0), /* Clear abort (WO) */ |
223 | a41b2ff2 | pbrook | TxDMAShift = 8, /* DMA burst value (0-7) is shifted this many bits */ |
224 | a41b2ff2 | pbrook | TxRetryShift = 4, /* TXRR value (0-15) is shifted this many bits */ |
225 | a41b2ff2 | pbrook | |
226 | a41b2ff2 | pbrook | TxVersionMask = 0x7C800000, /* mask out version bits 30-26, 23 */ |
227 | a41b2ff2 | pbrook | }; |
228 | a41b2ff2 | pbrook | |
229 | a41b2ff2 | pbrook | |
230 | a41b2ff2 | pbrook | /* Transmit Status of All Descriptors (TSAD) Register */
|
231 | a41b2ff2 | pbrook | enum TSAD_bits {
|
232 | a41b2ff2 | pbrook | TSAD_TOK3 = 1<<15, // TOK bit of Descriptor 3 |
233 | a41b2ff2 | pbrook | TSAD_TOK2 = 1<<14, // TOK bit of Descriptor 2 |
234 | a41b2ff2 | pbrook | TSAD_TOK1 = 1<<13, // TOK bit of Descriptor 1 |
235 | a41b2ff2 | pbrook | TSAD_TOK0 = 1<<12, // TOK bit of Descriptor 0 |
236 | a41b2ff2 | pbrook | TSAD_TUN3 = 1<<11, // TUN bit of Descriptor 3 |
237 | a41b2ff2 | pbrook | TSAD_TUN2 = 1<<10, // TUN bit of Descriptor 2 |
238 | a41b2ff2 | pbrook | TSAD_TUN1 = 1<<9, // TUN bit of Descriptor 1 |
239 | a41b2ff2 | pbrook | TSAD_TUN0 = 1<<8, // TUN bit of Descriptor 0 |
240 | a41b2ff2 | pbrook | TSAD_TABT3 = 1<<07, // TABT bit of Descriptor 3 |
241 | a41b2ff2 | pbrook | TSAD_TABT2 = 1<<06, // TABT bit of Descriptor 2 |
242 | a41b2ff2 | pbrook | TSAD_TABT1 = 1<<05, // TABT bit of Descriptor 1 |
243 | a41b2ff2 | pbrook | TSAD_TABT0 = 1<<04, // TABT bit of Descriptor 0 |
244 | a41b2ff2 | pbrook | TSAD_OWN3 = 1<<03, // OWN bit of Descriptor 3 |
245 | a41b2ff2 | pbrook | TSAD_OWN2 = 1<<02, // OWN bit of Descriptor 2 |
246 | a41b2ff2 | pbrook | TSAD_OWN1 = 1<<01, // OWN bit of Descriptor 1 |
247 | a41b2ff2 | pbrook | TSAD_OWN0 = 1<<00, // OWN bit of Descriptor 0 |
248 | a41b2ff2 | pbrook | }; |
249 | a41b2ff2 | pbrook | |
250 | a41b2ff2 | pbrook | |
251 | a41b2ff2 | pbrook | /* Bits in Config1 */
|
252 | a41b2ff2 | pbrook | enum Config1Bits {
|
253 | a41b2ff2 | pbrook | Cfg1_PM_Enable = 0x01,
|
254 | a41b2ff2 | pbrook | Cfg1_VPD_Enable = 0x02,
|
255 | a41b2ff2 | pbrook | Cfg1_PIO = 0x04,
|
256 | a41b2ff2 | pbrook | Cfg1_MMIO = 0x08,
|
257 | a41b2ff2 | pbrook | LWAKE = 0x10, /* not on 8139, 8139A */ |
258 | a41b2ff2 | pbrook | Cfg1_Driver_Load = 0x20,
|
259 | a41b2ff2 | pbrook | Cfg1_LED0 = 0x40,
|
260 | a41b2ff2 | pbrook | Cfg1_LED1 = 0x80,
|
261 | a41b2ff2 | pbrook | SLEEP = (1 << 1), /* only on 8139, 8139A */ |
262 | a41b2ff2 | pbrook | PWRDN = (1 << 0), /* only on 8139, 8139A */ |
263 | a41b2ff2 | pbrook | }; |
264 | a41b2ff2 | pbrook | |
265 | a41b2ff2 | pbrook | /* Bits in Config3 */
|
266 | a41b2ff2 | pbrook | enum Config3Bits {
|
267 | a41b2ff2 | pbrook | Cfg3_FBtBEn = (1 << 0), /* 1 = Fast Back to Back */ |
268 | a41b2ff2 | pbrook | Cfg3_FuncRegEn = (1 << 1), /* 1 = enable CardBus Function registers */ |
269 | a41b2ff2 | pbrook | Cfg3_CLKRUN_En = (1 << 2), /* 1 = enable CLKRUN */ |
270 | a41b2ff2 | pbrook | Cfg3_CardB_En = (1 << 3), /* 1 = enable CardBus registers */ |
271 | a41b2ff2 | pbrook | Cfg3_LinkUp = (1 << 4), /* 1 = wake up on link up */ |
272 | a41b2ff2 | pbrook | Cfg3_Magic = (1 << 5), /* 1 = wake up on Magic Packet (tm) */ |
273 | a41b2ff2 | pbrook | Cfg3_PARM_En = (1 << 6), /* 0 = software can set twister parameters */ |
274 | a41b2ff2 | pbrook | Cfg3_GNTSel = (1 << 7), /* 1 = delay 1 clock from PCI GNT signal */ |
275 | a41b2ff2 | pbrook | }; |
276 | a41b2ff2 | pbrook | |
277 | a41b2ff2 | pbrook | /* Bits in Config4 */
|
278 | a41b2ff2 | pbrook | enum Config4Bits {
|
279 | a41b2ff2 | pbrook | LWPTN = (1 << 2), /* not on 8139, 8139A */ |
280 | a41b2ff2 | pbrook | }; |
281 | a41b2ff2 | pbrook | |
282 | a41b2ff2 | pbrook | /* Bits in Config5 */
|
283 | a41b2ff2 | pbrook | enum Config5Bits {
|
284 | a41b2ff2 | pbrook | Cfg5_PME_STS = (1 << 0), /* 1 = PCI reset resets PME_Status */ |
285 | a41b2ff2 | pbrook | Cfg5_LANWake = (1 << 1), /* 1 = enable LANWake signal */ |
286 | a41b2ff2 | pbrook | Cfg5_LDPS = (1 << 2), /* 0 = save power when link is down */ |
287 | a41b2ff2 | pbrook | Cfg5_FIFOAddrPtr = (1 << 3), /* Realtek internal SRAM testing */ |
288 | a41b2ff2 | pbrook | Cfg5_UWF = (1 << 4), /* 1 = accept unicast wakeup frame */ |
289 | a41b2ff2 | pbrook | Cfg5_MWF = (1 << 5), /* 1 = accept multicast wakeup frame */ |
290 | a41b2ff2 | pbrook | Cfg5_BWF = (1 << 6), /* 1 = accept broadcast wakeup frame */ |
291 | a41b2ff2 | pbrook | }; |
292 | a41b2ff2 | pbrook | |
293 | a41b2ff2 | pbrook | enum RxConfigBits {
|
294 | a41b2ff2 | pbrook | /* rx fifo threshold */
|
295 | a41b2ff2 | pbrook | RxCfgFIFOShift = 13,
|
296 | a41b2ff2 | pbrook | RxCfgFIFONone = (7 << RxCfgFIFOShift),
|
297 | a41b2ff2 | pbrook | |
298 | a41b2ff2 | pbrook | /* Max DMA burst */
|
299 | a41b2ff2 | pbrook | RxCfgDMAShift = 8,
|
300 | a41b2ff2 | pbrook | RxCfgDMAUnlimited = (7 << RxCfgDMAShift),
|
301 | a41b2ff2 | pbrook | |
302 | a41b2ff2 | pbrook | /* rx ring buffer length */
|
303 | a41b2ff2 | pbrook | RxCfgRcv8K = 0,
|
304 | a41b2ff2 | pbrook | RxCfgRcv16K = (1 << 11), |
305 | a41b2ff2 | pbrook | RxCfgRcv32K = (1 << 12), |
306 | a41b2ff2 | pbrook | RxCfgRcv64K = (1 << 11) | (1 << 12), |
307 | a41b2ff2 | pbrook | |
308 | a41b2ff2 | pbrook | /* Disable packet wrap at end of Rx buffer. (not possible with 64k) */
|
309 | a41b2ff2 | pbrook | RxNoWrap = (1 << 7), |
310 | a41b2ff2 | pbrook | }; |
311 | a41b2ff2 | pbrook | |
312 | a41b2ff2 | pbrook | /* Twister tuning parameters from RealTek.
|
313 | a41b2ff2 | pbrook | Completely undocumented, but required to tune bad links on some boards. */
|
314 | a41b2ff2 | pbrook | /*
|
315 | a41b2ff2 | pbrook | enum CSCRBits {
|
316 | a41b2ff2 | pbrook | CSCR_LinkOKBit = 0x0400,
|
317 | a41b2ff2 | pbrook | CSCR_LinkChangeBit = 0x0800,
|
318 | a41b2ff2 | pbrook | CSCR_LinkStatusBits = 0x0f000,
|
319 | a41b2ff2 | pbrook | CSCR_LinkDownOffCmd = 0x003c0,
|
320 | a41b2ff2 | pbrook | CSCR_LinkDownCmd = 0x0f3c0,
|
321 | a41b2ff2 | pbrook | */
|
322 | a41b2ff2 | pbrook | enum CSCRBits {
|
323 | 5fafdf24 | ths | CSCR_Testfun = 1<<15, /* 1 = Auto-neg speeds up internal timer, WO, def 0 */ |
324 | a41b2ff2 | pbrook | CSCR_LD = 1<<9, /* Active low TPI link disable signal. When low, TPI still transmits link pulses and TPI stays in good link state. def 1*/ |
325 | a41b2ff2 | pbrook | CSCR_HEART_BIT = 1<<8, /* 1 = HEART BEAT enable, 0 = HEART BEAT disable. HEART BEAT function is only valid in 10Mbps mode. def 1*/ |
326 | a41b2ff2 | pbrook | CSCR_JBEN = 1<<7, /* 1 = enable jabber function. 0 = disable jabber function, def 1*/ |
327 | 5fafdf24 | ths | CSCR_F_LINK_100 = 1<<6, /* Used to login force good link in 100Mbps for diagnostic purposes. 1 = DISABLE, 0 = ENABLE. def 1*/ |
328 | a41b2ff2 | pbrook | CSCR_F_Connect = 1<<5, /* Assertion of this bit forces the disconnect function to be bypassed. def 0*/ |
329 | a41b2ff2 | pbrook | CSCR_Con_status = 1<<3, /* This bit indicates the status of the connection. 1 = valid connected link detected; 0 = disconnected link detected. RO def 0*/ |
330 | a41b2ff2 | pbrook | CSCR_Con_status_En = 1<<2, /* Assertion of this bit configures LED1 pin to indicate connection status. def 0*/ |
331 | a41b2ff2 | pbrook | CSCR_PASS_SCR = 1<<0, /* Bypass Scramble, def 0*/ |
332 | a41b2ff2 | pbrook | }; |
333 | a41b2ff2 | pbrook | |
334 | a41b2ff2 | pbrook | enum Cfg9346Bits {
|
335 | eb46c5ed | Jason Wang | Cfg9346_Normal = 0x00,
|
336 | eb46c5ed | Jason Wang | Cfg9346_Autoload = 0x40,
|
337 | eb46c5ed | Jason Wang | Cfg9346_Programming = 0x80,
|
338 | eb46c5ed | Jason Wang | Cfg9346_ConfigWrite = 0xC0,
|
339 | a41b2ff2 | pbrook | }; |
340 | a41b2ff2 | pbrook | |
341 | a41b2ff2 | pbrook | typedef enum { |
342 | a41b2ff2 | pbrook | CH_8139 = 0,
|
343 | a41b2ff2 | pbrook | CH_8139_K, |
344 | a41b2ff2 | pbrook | CH_8139A, |
345 | a41b2ff2 | pbrook | CH_8139A_G, |
346 | a41b2ff2 | pbrook | CH_8139B, |
347 | a41b2ff2 | pbrook | CH_8130, |
348 | a41b2ff2 | pbrook | CH_8139C, |
349 | a41b2ff2 | pbrook | CH_8100, |
350 | a41b2ff2 | pbrook | CH_8100B_8139D, |
351 | a41b2ff2 | pbrook | CH_8101, |
352 | c227f099 | Anthony Liguori | } chip_t; |
353 | a41b2ff2 | pbrook | |
354 | a41b2ff2 | pbrook | enum chip_flags {
|
355 | a41b2ff2 | pbrook | HasHltClk = (1 << 0), |
356 | a41b2ff2 | pbrook | HasLWake = (1 << 1), |
357 | a41b2ff2 | pbrook | }; |
358 | a41b2ff2 | pbrook | |
359 | a41b2ff2 | pbrook | #define HW_REVID(b30, b29, b28, b27, b26, b23, b22) \
|
360 | a41b2ff2 | pbrook | (b30<<30 | b29<<29 | b28<<28 | b27<<27 | b26<<26 | b23<<23 | b22<<22) |
361 | a41b2ff2 | pbrook | #define HW_REVID_MASK HW_REVID(1, 1, 1, 1, 1, 1, 1) |
362 | a41b2ff2 | pbrook | |
363 | 6cadb320 | bellard | #define RTL8139_PCI_REVID_8139 0x10 |
364 | 6cadb320 | bellard | #define RTL8139_PCI_REVID_8139CPLUS 0x20 |
365 | 6cadb320 | bellard | |
366 | 6cadb320 | bellard | #define RTL8139_PCI_REVID RTL8139_PCI_REVID_8139CPLUS
|
367 | 6cadb320 | bellard | |
368 | a41b2ff2 | pbrook | /* Size is 64 * 16bit words */
|
369 | a41b2ff2 | pbrook | #define EEPROM_9346_ADDR_BITS 6 |
370 | a41b2ff2 | pbrook | #define EEPROM_9346_SIZE (1 << EEPROM_9346_ADDR_BITS) |
371 | a41b2ff2 | pbrook | #define EEPROM_9346_ADDR_MASK (EEPROM_9346_SIZE - 1) |
372 | a41b2ff2 | pbrook | |
373 | a41b2ff2 | pbrook | enum Chip9346Operation
|
374 | a41b2ff2 | pbrook | { |
375 | a41b2ff2 | pbrook | Chip9346_op_mask = 0xc0, /* 10 zzzzzz */ |
376 | a41b2ff2 | pbrook | Chip9346_op_read = 0x80, /* 10 AAAAAA */ |
377 | a41b2ff2 | pbrook | Chip9346_op_write = 0x40, /* 01 AAAAAA D(15)..D(0) */ |
378 | a41b2ff2 | pbrook | Chip9346_op_ext_mask = 0xf0, /* 11 zzzzzz */ |
379 | a41b2ff2 | pbrook | Chip9346_op_write_enable = 0x30, /* 00 11zzzz */ |
380 | a41b2ff2 | pbrook | Chip9346_op_write_all = 0x10, /* 00 01zzzz */ |
381 | a41b2ff2 | pbrook | Chip9346_op_write_disable = 0x00, /* 00 00zzzz */ |
382 | a41b2ff2 | pbrook | }; |
383 | a41b2ff2 | pbrook | |
384 | a41b2ff2 | pbrook | enum Chip9346Mode
|
385 | a41b2ff2 | pbrook | { |
386 | a41b2ff2 | pbrook | Chip9346_none = 0,
|
387 | a41b2ff2 | pbrook | Chip9346_enter_command_mode, |
388 | a41b2ff2 | pbrook | Chip9346_read_command, |
389 | a41b2ff2 | pbrook | Chip9346_data_read, /* from output register */
|
390 | a41b2ff2 | pbrook | Chip9346_data_write, /* to input register, then to contents at specified address */
|
391 | a41b2ff2 | pbrook | Chip9346_data_write_all, /* to input register, then filling contents */
|
392 | a41b2ff2 | pbrook | }; |
393 | a41b2ff2 | pbrook | |
394 | a41b2ff2 | pbrook | typedef struct EEprom9346 |
395 | a41b2ff2 | pbrook | { |
396 | a41b2ff2 | pbrook | uint16_t contents[EEPROM_9346_SIZE]; |
397 | a41b2ff2 | pbrook | int mode;
|
398 | a41b2ff2 | pbrook | uint32_t tick; |
399 | a41b2ff2 | pbrook | uint8_t address; |
400 | a41b2ff2 | pbrook | uint16_t input; |
401 | a41b2ff2 | pbrook | uint16_t output; |
402 | a41b2ff2 | pbrook | |
403 | a41b2ff2 | pbrook | uint8_t eecs; |
404 | a41b2ff2 | pbrook | uint8_t eesk; |
405 | a41b2ff2 | pbrook | uint8_t eedi; |
406 | a41b2ff2 | pbrook | uint8_t eedo; |
407 | a41b2ff2 | pbrook | } EEprom9346; |
408 | a41b2ff2 | pbrook | |
409 | 6cadb320 | bellard | typedef struct RTL8139TallyCounters |
410 | 6cadb320 | bellard | { |
411 | 6cadb320 | bellard | /* Tally counters */
|
412 | 6cadb320 | bellard | uint64_t TxOk; |
413 | 6cadb320 | bellard | uint64_t RxOk; |
414 | 6cadb320 | bellard | uint64_t TxERR; |
415 | 6cadb320 | bellard | uint32_t RxERR; |
416 | 6cadb320 | bellard | uint16_t MissPkt; |
417 | 6cadb320 | bellard | uint16_t FAE; |
418 | 6cadb320 | bellard | uint32_t Tx1Col; |
419 | 6cadb320 | bellard | uint32_t TxMCol; |
420 | 6cadb320 | bellard | uint64_t RxOkPhy; |
421 | 6cadb320 | bellard | uint64_t RxOkBrd; |
422 | 6cadb320 | bellard | uint32_t RxOkMul; |
423 | 6cadb320 | bellard | uint16_t TxAbt; |
424 | 6cadb320 | bellard | uint16_t TxUndrn; |
425 | 6cadb320 | bellard | } RTL8139TallyCounters; |
426 | 6cadb320 | bellard | |
427 | 6cadb320 | bellard | /* Clears all tally counters */
|
428 | 6cadb320 | bellard | static void RTL8139TallyCounters_clear(RTL8139TallyCounters* counters); |
429 | 6cadb320 | bellard | |
430 | a41b2ff2 | pbrook | typedef struct RTL8139State { |
431 | efd6dd45 | Juan Quintela | PCIDevice dev; |
432 | a41b2ff2 | pbrook | uint8_t phys[8]; /* mac address */ |
433 | a41b2ff2 | pbrook | uint8_t mult[8]; /* multicast mask array */ |
434 | a41b2ff2 | pbrook | |
435 | 6cadb320 | bellard | uint32_t TxStatus[4]; /* TxStatus0 in C mode*/ /* also DTCCR[0] and DTCCR[1] in C+ mode */ |
436 | a41b2ff2 | pbrook | uint32_t TxAddr[4]; /* TxAddr0 */ |
437 | a41b2ff2 | pbrook | uint32_t RxBuf; /* Receive buffer */
|
438 | a41b2ff2 | pbrook | uint32_t RxBufferSize;/* internal variable, receive ring buffer size in C mode */
|
439 | a41b2ff2 | pbrook | uint32_t RxBufPtr; |
440 | a41b2ff2 | pbrook | uint32_t RxBufAddr; |
441 | a41b2ff2 | pbrook | |
442 | a41b2ff2 | pbrook | uint16_t IntrStatus; |
443 | a41b2ff2 | pbrook | uint16_t IntrMask; |
444 | a41b2ff2 | pbrook | |
445 | a41b2ff2 | pbrook | uint32_t TxConfig; |
446 | a41b2ff2 | pbrook | uint32_t RxConfig; |
447 | a41b2ff2 | pbrook | uint32_t RxMissed; |
448 | a41b2ff2 | pbrook | |
449 | a41b2ff2 | pbrook | uint16_t CSCR; |
450 | a41b2ff2 | pbrook | |
451 | a41b2ff2 | pbrook | uint8_t Cfg9346; |
452 | a41b2ff2 | pbrook | uint8_t Config0; |
453 | a41b2ff2 | pbrook | uint8_t Config1; |
454 | a41b2ff2 | pbrook | uint8_t Config3; |
455 | a41b2ff2 | pbrook | uint8_t Config4; |
456 | a41b2ff2 | pbrook | uint8_t Config5; |
457 | a41b2ff2 | pbrook | |
458 | a41b2ff2 | pbrook | uint8_t clock_enabled; |
459 | a41b2ff2 | pbrook | uint8_t bChipCmdState; |
460 | a41b2ff2 | pbrook | |
461 | a41b2ff2 | pbrook | uint16_t MultiIntr; |
462 | a41b2ff2 | pbrook | |
463 | a41b2ff2 | pbrook | uint16_t BasicModeCtrl; |
464 | a41b2ff2 | pbrook | uint16_t BasicModeStatus; |
465 | a41b2ff2 | pbrook | uint16_t NWayAdvert; |
466 | a41b2ff2 | pbrook | uint16_t NWayLPAR; |
467 | a41b2ff2 | pbrook | uint16_t NWayExpansion; |
468 | a41b2ff2 | pbrook | |
469 | a41b2ff2 | pbrook | uint16_t CpCmd; |
470 | a41b2ff2 | pbrook | uint8_t TxThresh; |
471 | a41b2ff2 | pbrook | |
472 | 1673ad51 | Mark McLoughlin | NICState *nic; |
473 | 254111ec | Gerd Hoffmann | NICConf conf; |
474 | a41b2ff2 | pbrook | |
475 | a41b2ff2 | pbrook | /* C ring mode */
|
476 | a41b2ff2 | pbrook | uint32_t currTxDesc; |
477 | a41b2ff2 | pbrook | |
478 | a41b2ff2 | pbrook | /* C+ mode */
|
479 | 2c3891ab | aliguori | uint32_t cplus_enabled; |
480 | 2c3891ab | aliguori | |
481 | a41b2ff2 | pbrook | uint32_t currCPlusRxDesc; |
482 | a41b2ff2 | pbrook | uint32_t currCPlusTxDesc; |
483 | a41b2ff2 | pbrook | |
484 | a41b2ff2 | pbrook | uint32_t RxRingAddrLO; |
485 | a41b2ff2 | pbrook | uint32_t RxRingAddrHI; |
486 | a41b2ff2 | pbrook | |
487 | a41b2ff2 | pbrook | EEprom9346 eeprom; |
488 | 6cadb320 | bellard | |
489 | 6cadb320 | bellard | uint32_t TCTR; |
490 | 6cadb320 | bellard | uint32_t TimerInt; |
491 | 6cadb320 | bellard | int64_t TCTR_base; |
492 | 6cadb320 | bellard | |
493 | 6cadb320 | bellard | /* Tally counters */
|
494 | 6cadb320 | bellard | RTL8139TallyCounters tally_counters; |
495 | 6cadb320 | bellard | |
496 | 6cadb320 | bellard | /* Non-persistent data */
|
497 | 6cadb320 | bellard | uint8_t *cplus_txbuffer; |
498 | 6cadb320 | bellard | int cplus_txbuffer_len;
|
499 | 6cadb320 | bellard | int cplus_txbuffer_offset;
|
500 | 6cadb320 | bellard | |
501 | 6cadb320 | bellard | /* PCI interrupt timer */
|
502 | 6cadb320 | bellard | QEMUTimer *timer; |
503 | 05447803 | Frediano Ziglio | int64_t TimerExpire; |
504 | 6cadb320 | bellard | |
505 | bd80f3fc | Avi Kivity | MemoryRegion bar_io; |
506 | bd80f3fc | Avi Kivity | MemoryRegion bar_mem; |
507 | bd80f3fc | Avi Kivity | |
508 | c574ba5a | Alex Williamson | /* Support migration to/from old versions */
|
509 | c574ba5a | Alex Williamson | int rtl8139_mmio_io_addr_dummy;
|
510 | a41b2ff2 | pbrook | } RTL8139State; |
511 | a41b2ff2 | pbrook | |
512 | 3ada003a | Eduard - Gabriel Munteanu | /* Writes tally counters to memory via DMA */
|
513 | 3ada003a | Eduard - Gabriel Munteanu | static void RTL8139TallyCounters_dma_write(RTL8139State *s, dma_addr_t tc_addr); |
514 | 3ada003a | Eduard - Gabriel Munteanu | |
515 | 05447803 | Frediano Ziglio | static void rtl8139_set_next_tctr_time(RTL8139State *s, int64_t current_time); |
516 | 05447803 | Frediano Ziglio | |
517 | 9596ebb7 | pbrook | static void prom9346_decode_command(EEprom9346 *eeprom, uint8_t command) |
518 | a41b2ff2 | pbrook | { |
519 | 7cdeb319 | Benjamin Poirier | DPRINTF("eeprom command 0x%02x\n", command);
|
520 | a41b2ff2 | pbrook | |
521 | a41b2ff2 | pbrook | switch (command & Chip9346_op_mask)
|
522 | a41b2ff2 | pbrook | { |
523 | a41b2ff2 | pbrook | case Chip9346_op_read:
|
524 | a41b2ff2 | pbrook | { |
525 | a41b2ff2 | pbrook | eeprom->address = command & EEPROM_9346_ADDR_MASK; |
526 | a41b2ff2 | pbrook | eeprom->output = eeprom->contents[eeprom->address]; |
527 | a41b2ff2 | pbrook | eeprom->eedo = 0;
|
528 | a41b2ff2 | pbrook | eeprom->tick = 0;
|
529 | a41b2ff2 | pbrook | eeprom->mode = Chip9346_data_read; |
530 | 7cdeb319 | Benjamin Poirier | DPRINTF("eeprom read from address 0x%02x data=0x%04x\n",
|
531 | 7cdeb319 | Benjamin Poirier | eeprom->address, eeprom->output); |
532 | a41b2ff2 | pbrook | } |
533 | a41b2ff2 | pbrook | break;
|
534 | a41b2ff2 | pbrook | |
535 | a41b2ff2 | pbrook | case Chip9346_op_write:
|
536 | a41b2ff2 | pbrook | { |
537 | a41b2ff2 | pbrook | eeprom->address = command & EEPROM_9346_ADDR_MASK; |
538 | a41b2ff2 | pbrook | eeprom->input = 0;
|
539 | a41b2ff2 | pbrook | eeprom->tick = 0;
|
540 | a41b2ff2 | pbrook | eeprom->mode = Chip9346_none; /* Chip9346_data_write */
|
541 | 7cdeb319 | Benjamin Poirier | DPRINTF("eeprom begin write to address 0x%02x\n",
|
542 | 7cdeb319 | Benjamin Poirier | eeprom->address); |
543 | a41b2ff2 | pbrook | } |
544 | a41b2ff2 | pbrook | break;
|
545 | a41b2ff2 | pbrook | default:
|
546 | a41b2ff2 | pbrook | eeprom->mode = Chip9346_none; |
547 | a41b2ff2 | pbrook | switch (command & Chip9346_op_ext_mask)
|
548 | a41b2ff2 | pbrook | { |
549 | a41b2ff2 | pbrook | case Chip9346_op_write_enable:
|
550 | 7cdeb319 | Benjamin Poirier | DPRINTF("eeprom write enabled\n");
|
551 | a41b2ff2 | pbrook | break;
|
552 | a41b2ff2 | pbrook | case Chip9346_op_write_all:
|
553 | 7cdeb319 | Benjamin Poirier | DPRINTF("eeprom begin write all\n");
|
554 | a41b2ff2 | pbrook | break;
|
555 | a41b2ff2 | pbrook | case Chip9346_op_write_disable:
|
556 | 7cdeb319 | Benjamin Poirier | DPRINTF("eeprom write disabled\n");
|
557 | a41b2ff2 | pbrook | break;
|
558 | a41b2ff2 | pbrook | } |
559 | a41b2ff2 | pbrook | break;
|
560 | a41b2ff2 | pbrook | } |
561 | a41b2ff2 | pbrook | } |
562 | a41b2ff2 | pbrook | |
563 | 9596ebb7 | pbrook | static void prom9346_shift_clock(EEprom9346 *eeprom) |
564 | a41b2ff2 | pbrook | { |
565 | a41b2ff2 | pbrook | int bit = eeprom->eedi?1:0; |
566 | a41b2ff2 | pbrook | |
567 | a41b2ff2 | pbrook | ++ eeprom->tick; |
568 | a41b2ff2 | pbrook | |
569 | 7cdeb319 | Benjamin Poirier | DPRINTF("eeprom: tick %d eedi=%d eedo=%d\n", eeprom->tick, eeprom->eedi,
|
570 | 7cdeb319 | Benjamin Poirier | eeprom->eedo); |
571 | a41b2ff2 | pbrook | |
572 | a41b2ff2 | pbrook | switch (eeprom->mode)
|
573 | a41b2ff2 | pbrook | { |
574 | a41b2ff2 | pbrook | case Chip9346_enter_command_mode:
|
575 | a41b2ff2 | pbrook | if (bit)
|
576 | a41b2ff2 | pbrook | { |
577 | a41b2ff2 | pbrook | eeprom->mode = Chip9346_read_command; |
578 | a41b2ff2 | pbrook | eeprom->tick = 0;
|
579 | a41b2ff2 | pbrook | eeprom->input = 0;
|
580 | 7cdeb319 | Benjamin Poirier | DPRINTF("eeprom: +++ synchronized, begin command read\n");
|
581 | a41b2ff2 | pbrook | } |
582 | a41b2ff2 | pbrook | break;
|
583 | a41b2ff2 | pbrook | |
584 | a41b2ff2 | pbrook | case Chip9346_read_command:
|
585 | a41b2ff2 | pbrook | eeprom->input = (eeprom->input << 1) | (bit & 1); |
586 | a41b2ff2 | pbrook | if (eeprom->tick == 8) |
587 | a41b2ff2 | pbrook | { |
588 | a41b2ff2 | pbrook | prom9346_decode_command(eeprom, eeprom->input & 0xff);
|
589 | a41b2ff2 | pbrook | } |
590 | a41b2ff2 | pbrook | break;
|
591 | a41b2ff2 | pbrook | |
592 | a41b2ff2 | pbrook | case Chip9346_data_read:
|
593 | a41b2ff2 | pbrook | eeprom->eedo = (eeprom->output & 0x8000)?1:0; |
594 | a41b2ff2 | pbrook | eeprom->output <<= 1;
|
595 | a41b2ff2 | pbrook | if (eeprom->tick == 16) |
596 | a41b2ff2 | pbrook | { |
597 | 6cadb320 | bellard | #if 1 |
598 | 6cadb320 | bellard | // the FreeBSD drivers (rl and re) don't explicitly toggle
|
599 | 6cadb320 | bellard | // CS between reads (or does setting Cfg9346 to 0 count too?),
|
600 | 6cadb320 | bellard | // so we need to enter wait-for-command state here
|
601 | 6cadb320 | bellard | eeprom->mode = Chip9346_enter_command_mode; |
602 | 6cadb320 | bellard | eeprom->input = 0;
|
603 | 6cadb320 | bellard | eeprom->tick = 0;
|
604 | 6cadb320 | bellard | |
605 | 7cdeb319 | Benjamin Poirier | DPRINTF("eeprom: +++ end of read, awaiting next command\n");
|
606 | 6cadb320 | bellard | #else
|
607 | 6cadb320 | bellard | // original behaviour
|
608 | a41b2ff2 | pbrook | ++eeprom->address; |
609 | a41b2ff2 | pbrook | eeprom->address &= EEPROM_9346_ADDR_MASK; |
610 | a41b2ff2 | pbrook | eeprom->output = eeprom->contents[eeprom->address]; |
611 | a41b2ff2 | pbrook | eeprom->tick = 0;
|
612 | a41b2ff2 | pbrook | |
613 | 7cdeb319 | Benjamin Poirier | DPRINTF("eeprom: +++ read next address 0x%02x data=0x%04x\n",
|
614 | 7cdeb319 | Benjamin Poirier | eeprom->address, eeprom->output); |
615 | a41b2ff2 | pbrook | #endif
|
616 | a41b2ff2 | pbrook | } |
617 | a41b2ff2 | pbrook | break;
|
618 | a41b2ff2 | pbrook | |
619 | a41b2ff2 | pbrook | case Chip9346_data_write:
|
620 | a41b2ff2 | pbrook | eeprom->input = (eeprom->input << 1) | (bit & 1); |
621 | a41b2ff2 | pbrook | if (eeprom->tick == 16) |
622 | a41b2ff2 | pbrook | { |
623 | 7cdeb319 | Benjamin Poirier | DPRINTF("eeprom write to address 0x%02x data=0x%04x\n",
|
624 | 7cdeb319 | Benjamin Poirier | eeprom->address, eeprom->input); |
625 | 6cadb320 | bellard | |
626 | a41b2ff2 | pbrook | eeprom->contents[eeprom->address] = eeprom->input; |
627 | a41b2ff2 | pbrook | eeprom->mode = Chip9346_none; /* waiting for next command after CS cycle */
|
628 | a41b2ff2 | pbrook | eeprom->tick = 0;
|
629 | a41b2ff2 | pbrook | eeprom->input = 0;
|
630 | a41b2ff2 | pbrook | } |
631 | a41b2ff2 | pbrook | break;
|
632 | a41b2ff2 | pbrook | |
633 | a41b2ff2 | pbrook | case Chip9346_data_write_all:
|
634 | a41b2ff2 | pbrook | eeprom->input = (eeprom->input << 1) | (bit & 1); |
635 | a41b2ff2 | pbrook | if (eeprom->tick == 16) |
636 | a41b2ff2 | pbrook | { |
637 | a41b2ff2 | pbrook | int i;
|
638 | a41b2ff2 | pbrook | for (i = 0; i < EEPROM_9346_SIZE; i++) |
639 | a41b2ff2 | pbrook | { |
640 | a41b2ff2 | pbrook | eeprom->contents[i] = eeprom->input; |
641 | a41b2ff2 | pbrook | } |
642 | 7cdeb319 | Benjamin Poirier | DPRINTF("eeprom filled with data=0x%04x\n", eeprom->input);
|
643 | 6cadb320 | bellard | |
644 | a41b2ff2 | pbrook | eeprom->mode = Chip9346_enter_command_mode; |
645 | a41b2ff2 | pbrook | eeprom->tick = 0;
|
646 | a41b2ff2 | pbrook | eeprom->input = 0;
|
647 | a41b2ff2 | pbrook | } |
648 | a41b2ff2 | pbrook | break;
|
649 | a41b2ff2 | pbrook | |
650 | a41b2ff2 | pbrook | default:
|
651 | a41b2ff2 | pbrook | break;
|
652 | a41b2ff2 | pbrook | } |
653 | a41b2ff2 | pbrook | } |
654 | a41b2ff2 | pbrook | |
655 | 9596ebb7 | pbrook | static int prom9346_get_wire(RTL8139State *s) |
656 | a41b2ff2 | pbrook | { |
657 | a41b2ff2 | pbrook | EEprom9346 *eeprom = &s->eeprom; |
658 | a41b2ff2 | pbrook | if (!eeprom->eecs)
|
659 | a41b2ff2 | pbrook | return 0; |
660 | a41b2ff2 | pbrook | |
661 | a41b2ff2 | pbrook | return eeprom->eedo;
|
662 | a41b2ff2 | pbrook | } |
663 | a41b2ff2 | pbrook | |
664 | 9596ebb7 | pbrook | /* FIXME: This should be merged into/replaced by eeprom93xx.c. */
|
665 | 9596ebb7 | pbrook | static void prom9346_set_wire(RTL8139State *s, int eecs, int eesk, int eedi) |
666 | a41b2ff2 | pbrook | { |
667 | a41b2ff2 | pbrook | EEprom9346 *eeprom = &s->eeprom; |
668 | a41b2ff2 | pbrook | uint8_t old_eecs = eeprom->eecs; |
669 | a41b2ff2 | pbrook | uint8_t old_eesk = eeprom->eesk; |
670 | a41b2ff2 | pbrook | |
671 | a41b2ff2 | pbrook | eeprom->eecs = eecs; |
672 | a41b2ff2 | pbrook | eeprom->eesk = eesk; |
673 | a41b2ff2 | pbrook | eeprom->eedi = eedi; |
674 | a41b2ff2 | pbrook | |
675 | 7cdeb319 | Benjamin Poirier | DPRINTF("eeprom: +++ wires CS=%d SK=%d DI=%d DO=%d\n", eeprom->eecs,
|
676 | 7cdeb319 | Benjamin Poirier | eeprom->eesk, eeprom->eedi, eeprom->eedo); |
677 | a41b2ff2 | pbrook | |
678 | a41b2ff2 | pbrook | if (!old_eecs && eecs)
|
679 | a41b2ff2 | pbrook | { |
680 | a41b2ff2 | pbrook | /* Synchronize start */
|
681 | a41b2ff2 | pbrook | eeprom->tick = 0;
|
682 | a41b2ff2 | pbrook | eeprom->input = 0;
|
683 | a41b2ff2 | pbrook | eeprom->output = 0;
|
684 | a41b2ff2 | pbrook | eeprom->mode = Chip9346_enter_command_mode; |
685 | a41b2ff2 | pbrook | |
686 | 7cdeb319 | Benjamin Poirier | DPRINTF("=== eeprom: begin access, enter command mode\n");
|
687 | a41b2ff2 | pbrook | } |
688 | a41b2ff2 | pbrook | |
689 | a41b2ff2 | pbrook | if (!eecs)
|
690 | a41b2ff2 | pbrook | { |
691 | 7cdeb319 | Benjamin Poirier | DPRINTF("=== eeprom: end access\n");
|
692 | a41b2ff2 | pbrook | return;
|
693 | a41b2ff2 | pbrook | } |
694 | a41b2ff2 | pbrook | |
695 | a41b2ff2 | pbrook | if (!old_eesk && eesk)
|
696 | a41b2ff2 | pbrook | { |
697 | a41b2ff2 | pbrook | /* SK front rules */
|
698 | a41b2ff2 | pbrook | prom9346_shift_clock(eeprom); |
699 | a41b2ff2 | pbrook | } |
700 | a41b2ff2 | pbrook | } |
701 | a41b2ff2 | pbrook | |
702 | a41b2ff2 | pbrook | static void rtl8139_update_irq(RTL8139State *s) |
703 | a41b2ff2 | pbrook | { |
704 | a41b2ff2 | pbrook | int isr;
|
705 | a41b2ff2 | pbrook | isr = (s->IntrStatus & s->IntrMask) & 0xffff;
|
706 | 6cadb320 | bellard | |
707 | 7cdeb319 | Benjamin Poirier | DPRINTF("Set IRQ to %d (%04x %04x)\n", isr ? 1 : 0, s->IntrStatus, |
708 | 7cdeb319 | Benjamin Poirier | s->IntrMask); |
709 | 6cadb320 | bellard | |
710 | efd6dd45 | Juan Quintela | qemu_set_irq(s->dev.irq[0], (isr != 0)); |
711 | a41b2ff2 | pbrook | } |
712 | a41b2ff2 | pbrook | |
713 | a41b2ff2 | pbrook | static int rtl8139_RxWrap(RTL8139State *s) |
714 | a41b2ff2 | pbrook | { |
715 | a41b2ff2 | pbrook | /* wrapping enabled; assume 1.5k more buffer space if size < 65536 */
|
716 | a41b2ff2 | pbrook | return (s->RxConfig & (1 << 7)); |
717 | a41b2ff2 | pbrook | } |
718 | a41b2ff2 | pbrook | |
719 | a41b2ff2 | pbrook | static int rtl8139_receiver_enabled(RTL8139State *s) |
720 | a41b2ff2 | pbrook | { |
721 | a41b2ff2 | pbrook | return s->bChipCmdState & CmdRxEnb;
|
722 | a41b2ff2 | pbrook | } |
723 | a41b2ff2 | pbrook | |
724 | a41b2ff2 | pbrook | static int rtl8139_transmitter_enabled(RTL8139State *s) |
725 | a41b2ff2 | pbrook | { |
726 | a41b2ff2 | pbrook | return s->bChipCmdState & CmdTxEnb;
|
727 | a41b2ff2 | pbrook | } |
728 | a41b2ff2 | pbrook | |
729 | a41b2ff2 | pbrook | static int rtl8139_cp_receiver_enabled(RTL8139State *s) |
730 | a41b2ff2 | pbrook | { |
731 | a41b2ff2 | pbrook | return s->CpCmd & CPlusRxEnb;
|
732 | a41b2ff2 | pbrook | } |
733 | a41b2ff2 | pbrook | |
734 | a41b2ff2 | pbrook | static int rtl8139_cp_transmitter_enabled(RTL8139State *s) |
735 | a41b2ff2 | pbrook | { |
736 | a41b2ff2 | pbrook | return s->CpCmd & CPlusTxEnb;
|
737 | a41b2ff2 | pbrook | } |
738 | a41b2ff2 | pbrook | |
739 | a41b2ff2 | pbrook | static void rtl8139_write_buffer(RTL8139State *s, const void *buf, int size) |
740 | a41b2ff2 | pbrook | { |
741 | a41b2ff2 | pbrook | if (s->RxBufAddr + size > s->RxBufferSize)
|
742 | a41b2ff2 | pbrook | { |
743 | a41b2ff2 | pbrook | int wrapped = MOD2(s->RxBufAddr + size, s->RxBufferSize);
|
744 | a41b2ff2 | pbrook | |
745 | a41b2ff2 | pbrook | /* write packet data */
|
746 | ccf1d14a | ths | if (wrapped && !(s->RxBufferSize < 65536 && rtl8139_RxWrap(s))) |
747 | a41b2ff2 | pbrook | { |
748 | 7cdeb319 | Benjamin Poirier | DPRINTF(">>> rx packet wrapped in buffer at %d\n", size - wrapped);
|
749 | a41b2ff2 | pbrook | |
750 | a41b2ff2 | pbrook | if (size > wrapped)
|
751 | a41b2ff2 | pbrook | { |
752 | 3ada003a | Eduard - Gabriel Munteanu | pci_dma_write(&s->dev, s->RxBuf + s->RxBufAddr, |
753 | 3ada003a | Eduard - Gabriel Munteanu | buf, size-wrapped); |
754 | a41b2ff2 | pbrook | } |
755 | a41b2ff2 | pbrook | |
756 | a41b2ff2 | pbrook | /* reset buffer pointer */
|
757 | a41b2ff2 | pbrook | s->RxBufAddr = 0;
|
758 | a41b2ff2 | pbrook | |
759 | 3ada003a | Eduard - Gabriel Munteanu | pci_dma_write(&s->dev, s->RxBuf + s->RxBufAddr, |
760 | 3ada003a | Eduard - Gabriel Munteanu | buf + (size-wrapped), wrapped); |
761 | a41b2ff2 | pbrook | |
762 | a41b2ff2 | pbrook | s->RxBufAddr = wrapped; |
763 | a41b2ff2 | pbrook | |
764 | a41b2ff2 | pbrook | return;
|
765 | a41b2ff2 | pbrook | } |
766 | a41b2ff2 | pbrook | } |
767 | a41b2ff2 | pbrook | |
768 | a41b2ff2 | pbrook | /* non-wrapping path or overwrapping enabled */
|
769 | 3ada003a | Eduard - Gabriel Munteanu | pci_dma_write(&s->dev, s->RxBuf + s->RxBufAddr, buf, size); |
770 | a41b2ff2 | pbrook | |
771 | a41b2ff2 | pbrook | s->RxBufAddr += size; |
772 | a41b2ff2 | pbrook | } |
773 | a41b2ff2 | pbrook | |
774 | a41b2ff2 | pbrook | #define MIN_BUF_SIZE 60 |
775 | 3ada003a | Eduard - Gabriel Munteanu | static inline dma_addr_t rtl8139_addr64(uint32_t low, uint32_t high) |
776 | a41b2ff2 | pbrook | { |
777 | a41b2ff2 | pbrook | #if TARGET_PHYS_ADDR_BITS > 32 |
778 | c227f099 | Anthony Liguori | return low | ((target_phys_addr_t)high << 32); |
779 | a41b2ff2 | pbrook | #else
|
780 | a41b2ff2 | pbrook | return low;
|
781 | a41b2ff2 | pbrook | #endif
|
782 | a41b2ff2 | pbrook | } |
783 | a41b2ff2 | pbrook | |
784 | 1673ad51 | Mark McLoughlin | static int rtl8139_can_receive(VLANClientState *nc) |
785 | a41b2ff2 | pbrook | { |
786 | 1673ad51 | Mark McLoughlin | RTL8139State *s = DO_UPCAST(NICState, nc, nc)->opaque; |
787 | a41b2ff2 | pbrook | int avail;
|
788 | a41b2ff2 | pbrook | |
789 | aa1f17c1 | ths | /* Receive (drop) packets if card is disabled. */
|
790 | a41b2ff2 | pbrook | if (!s->clock_enabled)
|
791 | a41b2ff2 | pbrook | return 1; |
792 | a41b2ff2 | pbrook | if (!rtl8139_receiver_enabled(s))
|
793 | a41b2ff2 | pbrook | return 1; |
794 | ff71f2e8 | Jason Wang | /* network/host communication happens only in normal mode */
|
795 | ff71f2e8 | Jason Wang | if ((s->Cfg9346 & Chip9346_op_mask) != Cfg9346_Normal)
|
796 | ff71f2e8 | Jason Wang | return 0; |
797 | a41b2ff2 | pbrook | |
798 | a41b2ff2 | pbrook | if (rtl8139_cp_receiver_enabled(s)) {
|
799 | a41b2ff2 | pbrook | /* ??? Flow control not implemented in c+ mode.
|
800 | a41b2ff2 | pbrook | This is a hack to work around slirp deficiencies anyway. */
|
801 | a41b2ff2 | pbrook | return 1; |
802 | a41b2ff2 | pbrook | } else {
|
803 | a41b2ff2 | pbrook | avail = MOD2(s->RxBufferSize + s->RxBufPtr - s->RxBufAddr, |
804 | a41b2ff2 | pbrook | s->RxBufferSize); |
805 | a41b2ff2 | pbrook | return (avail == 0 || avail >= 1514); |
806 | a41b2ff2 | pbrook | } |
807 | a41b2ff2 | pbrook | } |
808 | a41b2ff2 | pbrook | |
809 | 1673ad51 | Mark McLoughlin | static ssize_t rtl8139_do_receive(VLANClientState *nc, const uint8_t *buf, size_t size_, int do_interrupt) |
810 | a41b2ff2 | pbrook | { |
811 | 1673ad51 | Mark McLoughlin | RTL8139State *s = DO_UPCAST(NICState, nc, nc)->opaque; |
812 | 18dabfd1 | Benjamin Poirier | /* size is the length of the buffer passed to the driver */
|
813 | 4f1c942b | Mark McLoughlin | int size = size_;
|
814 | 18dabfd1 | Benjamin Poirier | const uint8_t *dot1q_buf = NULL; |
815 | a41b2ff2 | pbrook | |
816 | a41b2ff2 | pbrook | uint32_t packet_header = 0;
|
817 | a41b2ff2 | pbrook | |
818 | 18dabfd1 | Benjamin Poirier | uint8_t buf1[MIN_BUF_SIZE + VLAN_HLEN]; |
819 | 5fafdf24 | ths | static const uint8_t broadcast_macaddr[6] = |
820 | a41b2ff2 | pbrook | { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff }; |
821 | a41b2ff2 | pbrook | |
822 | 7cdeb319 | Benjamin Poirier | DPRINTF(">>> received len=%d\n", size);
|
823 | a41b2ff2 | pbrook | |
824 | a41b2ff2 | pbrook | /* test if board clock is stopped */
|
825 | a41b2ff2 | pbrook | if (!s->clock_enabled)
|
826 | a41b2ff2 | pbrook | { |
827 | 7cdeb319 | Benjamin Poirier | DPRINTF("stopped ==========================\n");
|
828 | 4f1c942b | Mark McLoughlin | return -1; |
829 | a41b2ff2 | pbrook | } |
830 | a41b2ff2 | pbrook | |
831 | a41b2ff2 | pbrook | /* first check if receiver is enabled */
|
832 | a41b2ff2 | pbrook | |
833 | a41b2ff2 | pbrook | if (!rtl8139_receiver_enabled(s))
|
834 | a41b2ff2 | pbrook | { |
835 | 7cdeb319 | Benjamin Poirier | DPRINTF("receiver disabled ================\n");
|
836 | 4f1c942b | Mark McLoughlin | return -1; |
837 | a41b2ff2 | pbrook | } |
838 | a41b2ff2 | pbrook | |
839 | ff71f2e8 | Jason Wang | /* check whether we are in normal mode */
|
840 | ff71f2e8 | Jason Wang | if ((s->Cfg9346 & Chip9346_op_mask) != Cfg9346_Normal) {
|
841 | ff71f2e8 | Jason Wang | DPRINTF("not in normal op mode\n");
|
842 | ff71f2e8 | Jason Wang | return -1; |
843 | ff71f2e8 | Jason Wang | } |
844 | ff71f2e8 | Jason Wang | |
845 | a41b2ff2 | pbrook | /* XXX: check this */
|
846 | a41b2ff2 | pbrook | if (s->RxConfig & AcceptAllPhys) {
|
847 | a41b2ff2 | pbrook | /* promiscuous: receive all */
|
848 | 7cdeb319 | Benjamin Poirier | DPRINTF(">>> packet received in promiscuous mode\n");
|
849 | a41b2ff2 | pbrook | |
850 | a41b2ff2 | pbrook | } else {
|
851 | a41b2ff2 | pbrook | if (!memcmp(buf, broadcast_macaddr, 6)) { |
852 | a41b2ff2 | pbrook | /* broadcast address */
|
853 | a41b2ff2 | pbrook | if (!(s->RxConfig & AcceptBroadcast))
|
854 | a41b2ff2 | pbrook | { |
855 | 7cdeb319 | Benjamin Poirier | DPRINTF(">>> broadcast packet rejected\n");
|
856 | 6cadb320 | bellard | |
857 | 6cadb320 | bellard | /* update tally counter */
|
858 | 6cadb320 | bellard | ++s->tally_counters.RxERR; |
859 | 6cadb320 | bellard | |
860 | 4f1c942b | Mark McLoughlin | return size;
|
861 | a41b2ff2 | pbrook | } |
862 | a41b2ff2 | pbrook | |
863 | a41b2ff2 | pbrook | packet_header |= RxBroadcast; |
864 | a41b2ff2 | pbrook | |
865 | 7cdeb319 | Benjamin Poirier | DPRINTF(">>> broadcast packet received\n");
|
866 | 6cadb320 | bellard | |
867 | 6cadb320 | bellard | /* update tally counter */
|
868 | 6cadb320 | bellard | ++s->tally_counters.RxOkBrd; |
869 | 6cadb320 | bellard | |
870 | a41b2ff2 | pbrook | } else if (buf[0] & 0x01) { |
871 | a41b2ff2 | pbrook | /* multicast */
|
872 | a41b2ff2 | pbrook | if (!(s->RxConfig & AcceptMulticast))
|
873 | a41b2ff2 | pbrook | { |
874 | 7cdeb319 | Benjamin Poirier | DPRINTF(">>> multicast packet rejected\n");
|
875 | 6cadb320 | bellard | |
876 | 6cadb320 | bellard | /* update tally counter */
|
877 | 6cadb320 | bellard | ++s->tally_counters.RxERR; |
878 | 6cadb320 | bellard | |
879 | 4f1c942b | Mark McLoughlin | return size;
|
880 | a41b2ff2 | pbrook | } |
881 | a41b2ff2 | pbrook | |
882 | a41b2ff2 | pbrook | int mcast_idx = compute_mcast_idx(buf);
|
883 | a41b2ff2 | pbrook | |
884 | a41b2ff2 | pbrook | if (!(s->mult[mcast_idx >> 3] & (1 << (mcast_idx & 7)))) |
885 | a41b2ff2 | pbrook | { |
886 | 7cdeb319 | Benjamin Poirier | DPRINTF(">>> multicast address mismatch\n");
|
887 | 6cadb320 | bellard | |
888 | 6cadb320 | bellard | /* update tally counter */
|
889 | 6cadb320 | bellard | ++s->tally_counters.RxERR; |
890 | 6cadb320 | bellard | |
891 | 4f1c942b | Mark McLoughlin | return size;
|
892 | a41b2ff2 | pbrook | } |
893 | a41b2ff2 | pbrook | |
894 | a41b2ff2 | pbrook | packet_header |= RxMulticast; |
895 | a41b2ff2 | pbrook | |
896 | 7cdeb319 | Benjamin Poirier | DPRINTF(">>> multicast packet received\n");
|
897 | 6cadb320 | bellard | |
898 | 6cadb320 | bellard | /* update tally counter */
|
899 | 6cadb320 | bellard | ++s->tally_counters.RxOkMul; |
900 | 6cadb320 | bellard | |
901 | a41b2ff2 | pbrook | } else if (s->phys[0] == buf[0] && |
902 | 3b46e624 | ths | s->phys[1] == buf[1] && |
903 | 3b46e624 | ths | s->phys[2] == buf[2] && |
904 | 3b46e624 | ths | s->phys[3] == buf[3] && |
905 | 3b46e624 | ths | s->phys[4] == buf[4] && |
906 | a41b2ff2 | pbrook | s->phys[5] == buf[5]) { |
907 | a41b2ff2 | pbrook | /* match */
|
908 | a41b2ff2 | pbrook | if (!(s->RxConfig & AcceptMyPhys))
|
909 | a41b2ff2 | pbrook | { |
910 | 7cdeb319 | Benjamin Poirier | DPRINTF(">>> rejecting physical address matching packet\n");
|
911 | 6cadb320 | bellard | |
912 | 6cadb320 | bellard | /* update tally counter */
|
913 | 6cadb320 | bellard | ++s->tally_counters.RxERR; |
914 | 6cadb320 | bellard | |
915 | 4f1c942b | Mark McLoughlin | return size;
|
916 | a41b2ff2 | pbrook | } |
917 | a41b2ff2 | pbrook | |
918 | a41b2ff2 | pbrook | packet_header |= RxPhysical; |
919 | a41b2ff2 | pbrook | |
920 | 7cdeb319 | Benjamin Poirier | DPRINTF(">>> physical address matching packet received\n");
|
921 | 6cadb320 | bellard | |
922 | 6cadb320 | bellard | /* update tally counter */
|
923 | 6cadb320 | bellard | ++s->tally_counters.RxOkPhy; |
924 | a41b2ff2 | pbrook | |
925 | a41b2ff2 | pbrook | } else {
|
926 | a41b2ff2 | pbrook | |
927 | 7cdeb319 | Benjamin Poirier | DPRINTF(">>> unknown packet\n");
|
928 | 6cadb320 | bellard | |
929 | 6cadb320 | bellard | /* update tally counter */
|
930 | 6cadb320 | bellard | ++s->tally_counters.RxERR; |
931 | 6cadb320 | bellard | |
932 | 4f1c942b | Mark McLoughlin | return size;
|
933 | a41b2ff2 | pbrook | } |
934 | a41b2ff2 | pbrook | } |
935 | a41b2ff2 | pbrook | |
936 | 18dabfd1 | Benjamin Poirier | /* if too small buffer, then expand it
|
937 | 18dabfd1 | Benjamin Poirier | * Include some tailroom in case a vlan tag is later removed. */
|
938 | 18dabfd1 | Benjamin Poirier | if (size < MIN_BUF_SIZE + VLAN_HLEN) {
|
939 | a41b2ff2 | pbrook | memcpy(buf1, buf, size); |
940 | 18dabfd1 | Benjamin Poirier | memset(buf1 + size, 0, MIN_BUF_SIZE + VLAN_HLEN - size);
|
941 | a41b2ff2 | pbrook | buf = buf1; |
942 | 18dabfd1 | Benjamin Poirier | if (size < MIN_BUF_SIZE) {
|
943 | 18dabfd1 | Benjamin Poirier | size = MIN_BUF_SIZE; |
944 | 18dabfd1 | Benjamin Poirier | } |
945 | a41b2ff2 | pbrook | } |
946 | a41b2ff2 | pbrook | |
947 | a41b2ff2 | pbrook | if (rtl8139_cp_receiver_enabled(s))
|
948 | a41b2ff2 | pbrook | { |
949 | 7cdeb319 | Benjamin Poirier | DPRINTF("in C+ Rx mode ================\n");
|
950 | a41b2ff2 | pbrook | |
951 | a41b2ff2 | pbrook | /* begin C+ receiver mode */
|
952 | a41b2ff2 | pbrook | |
953 | a41b2ff2 | pbrook | /* w0 ownership flag */
|
954 | a41b2ff2 | pbrook | #define CP_RX_OWN (1<<31) |
955 | a41b2ff2 | pbrook | /* w0 end of ring flag */
|
956 | a41b2ff2 | pbrook | #define CP_RX_EOR (1<<30) |
957 | a41b2ff2 | pbrook | /* w0 bits 0...12 : buffer size */
|
958 | a41b2ff2 | pbrook | #define CP_RX_BUFFER_SIZE_MASK ((1<<13) - 1) |
959 | a41b2ff2 | pbrook | /* w1 tag available flag */
|
960 | a41b2ff2 | pbrook | #define CP_RX_TAVA (1<<16) |
961 | a41b2ff2 | pbrook | /* w1 bits 0...15 : VLAN tag */
|
962 | a41b2ff2 | pbrook | #define CP_RX_VLAN_TAG_MASK ((1<<16) - 1) |
963 | a41b2ff2 | pbrook | /* w2 low 32bit of Rx buffer ptr */
|
964 | a41b2ff2 | pbrook | /* w3 high 32bit of Rx buffer ptr */
|
965 | a41b2ff2 | pbrook | |
966 | a41b2ff2 | pbrook | int descriptor = s->currCPlusRxDesc;
|
967 | 3ada003a | Eduard - Gabriel Munteanu | dma_addr_t cplus_rx_ring_desc; |
968 | a41b2ff2 | pbrook | |
969 | a41b2ff2 | pbrook | cplus_rx_ring_desc = rtl8139_addr64(s->RxRingAddrLO, s->RxRingAddrHI); |
970 | a41b2ff2 | pbrook | cplus_rx_ring_desc += 16 * descriptor;
|
971 | a41b2ff2 | pbrook | |
972 | 7cdeb319 | Benjamin Poirier | DPRINTF("+++ C+ mode reading RX descriptor %d from host memory at "
|
973 | 3ada003a | Eduard - Gabriel Munteanu | "%08x %08x = "DMA_ADDR_FMT"\n", descriptor, s->RxRingAddrHI, |
974 | 7cdeb319 | Benjamin Poirier | s->RxRingAddrLO, cplus_rx_ring_desc); |
975 | a41b2ff2 | pbrook | |
976 | a41b2ff2 | pbrook | uint32_t val, rxdw0,rxdw1,rxbufLO,rxbufHI; |
977 | a41b2ff2 | pbrook | |
978 | a6a29eea | David Gibson | pci_dma_read(&s->dev, cplus_rx_ring_desc, &val, 4);
|
979 | a41b2ff2 | pbrook | rxdw0 = le32_to_cpu(val); |
980 | a6a29eea | David Gibson | pci_dma_read(&s->dev, cplus_rx_ring_desc+4, &val, 4); |
981 | a41b2ff2 | pbrook | rxdw1 = le32_to_cpu(val); |
982 | a6a29eea | David Gibson | pci_dma_read(&s->dev, cplus_rx_ring_desc+8, &val, 4); |
983 | a41b2ff2 | pbrook | rxbufLO = le32_to_cpu(val); |
984 | a6a29eea | David Gibson | pci_dma_read(&s->dev, cplus_rx_ring_desc+12, &val, 4); |
985 | a41b2ff2 | pbrook | rxbufHI = le32_to_cpu(val); |
986 | a41b2ff2 | pbrook | |
987 | 7cdeb319 | Benjamin Poirier | DPRINTF("+++ C+ mode RX descriptor %d %08x %08x %08x %08x\n",
|
988 | 7cdeb319 | Benjamin Poirier | descriptor, rxdw0, rxdw1, rxbufLO, rxbufHI); |
989 | a41b2ff2 | pbrook | |
990 | a41b2ff2 | pbrook | if (!(rxdw0 & CP_RX_OWN))
|
991 | a41b2ff2 | pbrook | { |
992 | 7cdeb319 | Benjamin Poirier | DPRINTF("C+ Rx mode : descriptor %d is owned by host\n",
|
993 | 7cdeb319 | Benjamin Poirier | descriptor); |
994 | 6cadb320 | bellard | |
995 | a41b2ff2 | pbrook | s->IntrStatus |= RxOverflow; |
996 | a41b2ff2 | pbrook | ++s->RxMissed; |
997 | 6cadb320 | bellard | |
998 | 6cadb320 | bellard | /* update tally counter */
|
999 | 6cadb320 | bellard | ++s->tally_counters.RxERR; |
1000 | 6cadb320 | bellard | ++s->tally_counters.MissPkt; |
1001 | 6cadb320 | bellard | |
1002 | a41b2ff2 | pbrook | rtl8139_update_irq(s); |
1003 | 4f1c942b | Mark McLoughlin | return size_;
|
1004 | a41b2ff2 | pbrook | } |
1005 | a41b2ff2 | pbrook | |
1006 | a41b2ff2 | pbrook | uint32_t rx_space = rxdw0 & CP_RX_BUFFER_SIZE_MASK; |
1007 | a41b2ff2 | pbrook | |
1008 | 18dabfd1 | Benjamin Poirier | /* write VLAN info to descriptor variables. */
|
1009 | 18dabfd1 | Benjamin Poirier | if (s->CpCmd & CPlusRxVLAN && be16_to_cpup((uint16_t *)
|
1010 | 18dabfd1 | Benjamin Poirier | &buf[ETHER_ADDR_LEN * 2]) == ETH_P_8021Q) {
|
1011 | 18dabfd1 | Benjamin Poirier | dot1q_buf = &buf[ETHER_ADDR_LEN * 2];
|
1012 | 18dabfd1 | Benjamin Poirier | size -= VLAN_HLEN; |
1013 | 18dabfd1 | Benjamin Poirier | /* if too small buffer, use the tailroom added duing expansion */
|
1014 | 18dabfd1 | Benjamin Poirier | if (size < MIN_BUF_SIZE) {
|
1015 | 18dabfd1 | Benjamin Poirier | size = MIN_BUF_SIZE; |
1016 | 18dabfd1 | Benjamin Poirier | } |
1017 | 18dabfd1 | Benjamin Poirier | |
1018 | 18dabfd1 | Benjamin Poirier | rxdw1 &= ~CP_RX_VLAN_TAG_MASK; |
1019 | 18dabfd1 | Benjamin Poirier | /* BE + ~le_to_cpu()~ + cpu_to_le() = BE */
|
1020 | 18dabfd1 | Benjamin Poirier | rxdw1 |= CP_RX_TAVA | le16_to_cpup((uint16_t *) |
1021 | 18dabfd1 | Benjamin Poirier | &dot1q_buf[ETHER_TYPE_LEN]); |
1022 | 18dabfd1 | Benjamin Poirier | |
1023 | 7cdeb319 | Benjamin Poirier | DPRINTF("C+ Rx mode : extracted vlan tag with tci: ""%u\n", |
1024 | 7cdeb319 | Benjamin Poirier | be16_to_cpup((uint16_t *)&dot1q_buf[ETHER_TYPE_LEN])); |
1025 | 18dabfd1 | Benjamin Poirier | } else {
|
1026 | 18dabfd1 | Benjamin Poirier | /* reset VLAN tag flag */
|
1027 | 18dabfd1 | Benjamin Poirier | rxdw1 &= ~CP_RX_TAVA; |
1028 | 18dabfd1 | Benjamin Poirier | } |
1029 | 18dabfd1 | Benjamin Poirier | |
1030 | 6cadb320 | bellard | /* TODO: scatter the packet over available receive ring descriptors space */
|
1031 | 6cadb320 | bellard | |
1032 | a41b2ff2 | pbrook | if (size+4 > rx_space) |
1033 | a41b2ff2 | pbrook | { |
1034 | 7cdeb319 | Benjamin Poirier | DPRINTF("C+ Rx mode : descriptor %d size %d received %d + 4\n",
|
1035 | 7cdeb319 | Benjamin Poirier | descriptor, rx_space, size); |
1036 | 6cadb320 | bellard | |
1037 | a41b2ff2 | pbrook | s->IntrStatus |= RxOverflow; |
1038 | a41b2ff2 | pbrook | ++s->RxMissed; |
1039 | 6cadb320 | bellard | |
1040 | 6cadb320 | bellard | /* update tally counter */
|
1041 | 6cadb320 | bellard | ++s->tally_counters.RxERR; |
1042 | 6cadb320 | bellard | ++s->tally_counters.MissPkt; |
1043 | 6cadb320 | bellard | |
1044 | a41b2ff2 | pbrook | rtl8139_update_irq(s); |
1045 | 4f1c942b | Mark McLoughlin | return size_;
|
1046 | a41b2ff2 | pbrook | } |
1047 | a41b2ff2 | pbrook | |
1048 | 3ada003a | Eduard - Gabriel Munteanu | dma_addr_t rx_addr = rtl8139_addr64(rxbufLO, rxbufHI); |
1049 | a41b2ff2 | pbrook | |
1050 | a41b2ff2 | pbrook | /* receive/copy to target memory */
|
1051 | 18dabfd1 | Benjamin Poirier | if (dot1q_buf) {
|
1052 | 3ada003a | Eduard - Gabriel Munteanu | pci_dma_write(&s->dev, rx_addr, buf, 2 * ETHER_ADDR_LEN);
|
1053 | 3ada003a | Eduard - Gabriel Munteanu | pci_dma_write(&s->dev, rx_addr + 2 * ETHER_ADDR_LEN,
|
1054 | 3ada003a | Eduard - Gabriel Munteanu | buf + 2 * ETHER_ADDR_LEN + VLAN_HLEN,
|
1055 | 3ada003a | Eduard - Gabriel Munteanu | size - 2 * ETHER_ADDR_LEN);
|
1056 | 18dabfd1 | Benjamin Poirier | } else {
|
1057 | 3ada003a | Eduard - Gabriel Munteanu | pci_dma_write(&s->dev, rx_addr, buf, size); |
1058 | 18dabfd1 | Benjamin Poirier | } |
1059 | a41b2ff2 | pbrook | |
1060 | 6cadb320 | bellard | if (s->CpCmd & CPlusRxChkSum)
|
1061 | 6cadb320 | bellard | { |
1062 | 6cadb320 | bellard | /* do some packet checksumming */
|
1063 | 6cadb320 | bellard | } |
1064 | 6cadb320 | bellard | |
1065 | a41b2ff2 | pbrook | /* write checksum */
|
1066 | 18dabfd1 | Benjamin Poirier | val = cpu_to_le32(crc32(0, buf, size_));
|
1067 | 3ada003a | Eduard - Gabriel Munteanu | pci_dma_write(&s->dev, rx_addr+size, (uint8_t *)&val, 4);
|
1068 | a41b2ff2 | pbrook | |
1069 | a41b2ff2 | pbrook | /* first segment of received packet flag */
|
1070 | a41b2ff2 | pbrook | #define CP_RX_STATUS_FS (1<<29) |
1071 | a41b2ff2 | pbrook | /* last segment of received packet flag */
|
1072 | a41b2ff2 | pbrook | #define CP_RX_STATUS_LS (1<<28) |
1073 | a41b2ff2 | pbrook | /* multicast packet flag */
|
1074 | a41b2ff2 | pbrook | #define CP_RX_STATUS_MAR (1<<26) |
1075 | a41b2ff2 | pbrook | /* physical-matching packet flag */
|
1076 | a41b2ff2 | pbrook | #define CP_RX_STATUS_PAM (1<<25) |
1077 | a41b2ff2 | pbrook | /* broadcast packet flag */
|
1078 | a41b2ff2 | pbrook | #define CP_RX_STATUS_BAR (1<<24) |
1079 | a41b2ff2 | pbrook | /* runt packet flag */
|
1080 | a41b2ff2 | pbrook | #define CP_RX_STATUS_RUNT (1<<19) |
1081 | a41b2ff2 | pbrook | /* crc error flag */
|
1082 | a41b2ff2 | pbrook | #define CP_RX_STATUS_CRC (1<<18) |
1083 | a41b2ff2 | pbrook | /* IP checksum error flag */
|
1084 | a41b2ff2 | pbrook | #define CP_RX_STATUS_IPF (1<<15) |
1085 | a41b2ff2 | pbrook | /* UDP checksum error flag */
|
1086 | a41b2ff2 | pbrook | #define CP_RX_STATUS_UDPF (1<<14) |
1087 | a41b2ff2 | pbrook | /* TCP checksum error flag */
|
1088 | a41b2ff2 | pbrook | #define CP_RX_STATUS_TCPF (1<<13) |
1089 | a41b2ff2 | pbrook | |
1090 | a41b2ff2 | pbrook | /* transfer ownership to target */
|
1091 | a41b2ff2 | pbrook | rxdw0 &= ~CP_RX_OWN; |
1092 | a41b2ff2 | pbrook | |
1093 | a41b2ff2 | pbrook | /* set first segment bit */
|
1094 | a41b2ff2 | pbrook | rxdw0 |= CP_RX_STATUS_FS; |
1095 | a41b2ff2 | pbrook | |
1096 | a41b2ff2 | pbrook | /* set last segment bit */
|
1097 | a41b2ff2 | pbrook | rxdw0 |= CP_RX_STATUS_LS; |
1098 | a41b2ff2 | pbrook | |
1099 | a41b2ff2 | pbrook | /* set received packet type flags */
|
1100 | a41b2ff2 | pbrook | if (packet_header & RxBroadcast)
|
1101 | a41b2ff2 | pbrook | rxdw0 |= CP_RX_STATUS_BAR; |
1102 | a41b2ff2 | pbrook | if (packet_header & RxMulticast)
|
1103 | a41b2ff2 | pbrook | rxdw0 |= CP_RX_STATUS_MAR; |
1104 | a41b2ff2 | pbrook | if (packet_header & RxPhysical)
|
1105 | a41b2ff2 | pbrook | rxdw0 |= CP_RX_STATUS_PAM; |
1106 | a41b2ff2 | pbrook | |
1107 | a41b2ff2 | pbrook | /* set received size */
|
1108 | a41b2ff2 | pbrook | rxdw0 &= ~CP_RX_BUFFER_SIZE_MASK; |
1109 | a41b2ff2 | pbrook | rxdw0 |= (size+4);
|
1110 | a41b2ff2 | pbrook | |
1111 | a41b2ff2 | pbrook | /* update ring data */
|
1112 | a41b2ff2 | pbrook | val = cpu_to_le32(rxdw0); |
1113 | 3ada003a | Eduard - Gabriel Munteanu | pci_dma_write(&s->dev, cplus_rx_ring_desc, (uint8_t *)&val, 4);
|
1114 | a41b2ff2 | pbrook | val = cpu_to_le32(rxdw1); |
1115 | 3ada003a | Eduard - Gabriel Munteanu | pci_dma_write(&s->dev, cplus_rx_ring_desc+4, (uint8_t *)&val, 4); |
1116 | a41b2ff2 | pbrook | |
1117 | 6cadb320 | bellard | /* update tally counter */
|
1118 | 6cadb320 | bellard | ++s->tally_counters.RxOk; |
1119 | 6cadb320 | bellard | |
1120 | a41b2ff2 | pbrook | /* seek to next Rx descriptor */
|
1121 | a41b2ff2 | pbrook | if (rxdw0 & CP_RX_EOR)
|
1122 | a41b2ff2 | pbrook | { |
1123 | a41b2ff2 | pbrook | s->currCPlusRxDesc = 0;
|
1124 | a41b2ff2 | pbrook | } |
1125 | a41b2ff2 | pbrook | else
|
1126 | a41b2ff2 | pbrook | { |
1127 | a41b2ff2 | pbrook | ++s->currCPlusRxDesc; |
1128 | a41b2ff2 | pbrook | } |
1129 | a41b2ff2 | pbrook | |
1130 | 7cdeb319 | Benjamin Poirier | DPRINTF("done C+ Rx mode ----------------\n");
|
1131 | a41b2ff2 | pbrook | |
1132 | a41b2ff2 | pbrook | } |
1133 | a41b2ff2 | pbrook | else
|
1134 | a41b2ff2 | pbrook | { |
1135 | 7cdeb319 | Benjamin Poirier | DPRINTF("in ring Rx mode ================\n");
|
1136 | 6cadb320 | bellard | |
1137 | a41b2ff2 | pbrook | /* begin ring receiver mode */
|
1138 | a41b2ff2 | pbrook | int avail = MOD2(s->RxBufferSize + s->RxBufPtr - s->RxBufAddr, s->RxBufferSize);
|
1139 | a41b2ff2 | pbrook | |
1140 | a41b2ff2 | pbrook | /* if receiver buffer is empty then avail == 0 */
|
1141 | a41b2ff2 | pbrook | |
1142 | a41b2ff2 | pbrook | if (avail != 0 && size + 8 >= avail) |
1143 | a41b2ff2 | pbrook | { |
1144 | 7cdeb319 | Benjamin Poirier | DPRINTF("rx overflow: rx buffer length %d head 0x%04x "
|
1145 | 7cdeb319 | Benjamin Poirier | "read 0x%04x === available 0x%04x need 0x%04x\n",
|
1146 | 7cdeb319 | Benjamin Poirier | s->RxBufferSize, s->RxBufAddr, s->RxBufPtr, avail, size + 8);
|
1147 | 6cadb320 | bellard | |
1148 | a41b2ff2 | pbrook | s->IntrStatus |= RxOverflow; |
1149 | a41b2ff2 | pbrook | ++s->RxMissed; |
1150 | a41b2ff2 | pbrook | rtl8139_update_irq(s); |
1151 | 4f1c942b | Mark McLoughlin | return size_;
|
1152 | a41b2ff2 | pbrook | } |
1153 | a41b2ff2 | pbrook | |
1154 | a41b2ff2 | pbrook | packet_header |= RxStatusOK; |
1155 | a41b2ff2 | pbrook | |
1156 | a41b2ff2 | pbrook | packet_header |= (((size+4) << 16) & 0xffff0000); |
1157 | a41b2ff2 | pbrook | |
1158 | a41b2ff2 | pbrook | /* write header */
|
1159 | a41b2ff2 | pbrook | uint32_t val = cpu_to_le32(packet_header); |
1160 | a41b2ff2 | pbrook | |
1161 | a41b2ff2 | pbrook | rtl8139_write_buffer(s, (uint8_t *)&val, 4);
|
1162 | a41b2ff2 | pbrook | |
1163 | a41b2ff2 | pbrook | rtl8139_write_buffer(s, buf, size); |
1164 | a41b2ff2 | pbrook | |
1165 | a41b2ff2 | pbrook | /* write checksum */
|
1166 | ccf1d14a | ths | val = cpu_to_le32(crc32(0, buf, size));
|
1167 | a41b2ff2 | pbrook | rtl8139_write_buffer(s, (uint8_t *)&val, 4);
|
1168 | a41b2ff2 | pbrook | |
1169 | a41b2ff2 | pbrook | /* correct buffer write pointer */
|
1170 | a41b2ff2 | pbrook | s->RxBufAddr = MOD2((s->RxBufAddr + 3) & ~0x3, s->RxBufferSize); |
1171 | a41b2ff2 | pbrook | |
1172 | a41b2ff2 | pbrook | /* now we can signal we have received something */
|
1173 | a41b2ff2 | pbrook | |
1174 | 7cdeb319 | Benjamin Poirier | DPRINTF("received: rx buffer length %d head 0x%04x read 0x%04x\n",
|
1175 | 7cdeb319 | Benjamin Poirier | s->RxBufferSize, s->RxBufAddr, s->RxBufPtr); |
1176 | a41b2ff2 | pbrook | } |
1177 | a41b2ff2 | pbrook | |
1178 | a41b2ff2 | pbrook | s->IntrStatus |= RxOK; |
1179 | 6cadb320 | bellard | |
1180 | 6cadb320 | bellard | if (do_interrupt)
|
1181 | 6cadb320 | bellard | { |
1182 | 6cadb320 | bellard | rtl8139_update_irq(s); |
1183 | 6cadb320 | bellard | } |
1184 | 4f1c942b | Mark McLoughlin | |
1185 | 4f1c942b | Mark McLoughlin | return size_;
|
1186 | 6cadb320 | bellard | } |
1187 | 6cadb320 | bellard | |
1188 | 1673ad51 | Mark McLoughlin | static ssize_t rtl8139_receive(VLANClientState *nc, const uint8_t *buf, size_t size) |
1189 | 6cadb320 | bellard | { |
1190 | 1673ad51 | Mark McLoughlin | return rtl8139_do_receive(nc, buf, size, 1); |
1191 | a41b2ff2 | pbrook | } |
1192 | a41b2ff2 | pbrook | |
1193 | a41b2ff2 | pbrook | static void rtl8139_reset_rxring(RTL8139State *s, uint32_t bufferSize) |
1194 | a41b2ff2 | pbrook | { |
1195 | a41b2ff2 | pbrook | s->RxBufferSize = bufferSize; |
1196 | a41b2ff2 | pbrook | s->RxBufPtr = 0;
|
1197 | a41b2ff2 | pbrook | s->RxBufAddr = 0;
|
1198 | a41b2ff2 | pbrook | } |
1199 | a41b2ff2 | pbrook | |
1200 | 7f23f812 | Michael S. Tsirkin | static void rtl8139_reset(DeviceState *d) |
1201 | a41b2ff2 | pbrook | { |
1202 | 7f23f812 | Michael S. Tsirkin | RTL8139State *s = container_of(d, RTL8139State, dev.qdev); |
1203 | a41b2ff2 | pbrook | int i;
|
1204 | a41b2ff2 | pbrook | |
1205 | a41b2ff2 | pbrook | /* restore MAC address */
|
1206 | 254111ec | Gerd Hoffmann | memcpy(s->phys, s->conf.macaddr.a, 6);
|
1207 | a41b2ff2 | pbrook | |
1208 | a41b2ff2 | pbrook | /* reset interrupt mask */
|
1209 | a41b2ff2 | pbrook | s->IntrStatus = 0;
|
1210 | a41b2ff2 | pbrook | s->IntrMask = 0;
|
1211 | a41b2ff2 | pbrook | |
1212 | a41b2ff2 | pbrook | rtl8139_update_irq(s); |
1213 | a41b2ff2 | pbrook | |
1214 | a41b2ff2 | pbrook | /* mark all status registers as owned by host */
|
1215 | a41b2ff2 | pbrook | for (i = 0; i < 4; ++i) |
1216 | a41b2ff2 | pbrook | { |
1217 | a41b2ff2 | pbrook | s->TxStatus[i] = TxHostOwns; |
1218 | a41b2ff2 | pbrook | } |
1219 | a41b2ff2 | pbrook | |
1220 | a41b2ff2 | pbrook | s->currTxDesc = 0;
|
1221 | a41b2ff2 | pbrook | s->currCPlusRxDesc = 0;
|
1222 | a41b2ff2 | pbrook | s->currCPlusTxDesc = 0;
|
1223 | a41b2ff2 | pbrook | |
1224 | a41b2ff2 | pbrook | s->RxRingAddrLO = 0;
|
1225 | a41b2ff2 | pbrook | s->RxRingAddrHI = 0;
|
1226 | a41b2ff2 | pbrook | |
1227 | a41b2ff2 | pbrook | s->RxBuf = 0;
|
1228 | a41b2ff2 | pbrook | |
1229 | a41b2ff2 | pbrook | rtl8139_reset_rxring(s, 8192);
|
1230 | a41b2ff2 | pbrook | |
1231 | a41b2ff2 | pbrook | /* ACK the reset */
|
1232 | a41b2ff2 | pbrook | s->TxConfig = 0;
|
1233 | a41b2ff2 | pbrook | |
1234 | a41b2ff2 | pbrook | #if 0
|
1235 | a41b2ff2 | pbrook | // s->TxConfig |= HW_REVID(1, 0, 0, 0, 0, 0, 0); // RTL-8139 HasHltClk
|
1236 | a41b2ff2 | pbrook | s->clock_enabled = 0;
|
1237 | a41b2ff2 | pbrook | #else
|
1238 | 6cadb320 | bellard | s->TxConfig |= HW_REVID(1, 1, 1, 0, 1, 1, 0); // RTL-8139C+ HasLWake |
1239 | a41b2ff2 | pbrook | s->clock_enabled = 1;
|
1240 | a41b2ff2 | pbrook | #endif
|
1241 | a41b2ff2 | pbrook | |
1242 | a41b2ff2 | pbrook | s->bChipCmdState = CmdReset; /* RxBufEmpty bit is calculated on read from ChipCmd */;
|
1243 | a41b2ff2 | pbrook | |
1244 | a41b2ff2 | pbrook | /* set initial state data */
|
1245 | a41b2ff2 | pbrook | s->Config0 = 0x0; /* No boot ROM */ |
1246 | a41b2ff2 | pbrook | s->Config1 = 0xC; /* IO mapped and MEM mapped registers available */ |
1247 | a41b2ff2 | pbrook | s->Config3 = 0x1; /* fast back-to-back compatible */ |
1248 | a41b2ff2 | pbrook | s->Config5 = 0x0;
|
1249 | a41b2ff2 | pbrook | |
1250 | 5fafdf24 | ths | s->CSCR = CSCR_F_LINK_100 | CSCR_HEART_BIT | CSCR_LD; |
1251 | a41b2ff2 | pbrook | |
1252 | a41b2ff2 | pbrook | s->CpCmd = 0x0; /* reset C+ mode */ |
1253 | 2c3891ab | aliguori | s->cplus_enabled = 0;
|
1254 | 2c3891ab | aliguori | |
1255 | a41b2ff2 | pbrook | |
1256 | a41b2ff2 | pbrook | // s->BasicModeCtrl = 0x3100; // 100Mbps, full duplex, autonegotiation
|
1257 | a41b2ff2 | pbrook | // s->BasicModeCtrl = 0x2100; // 100Mbps, full duplex
|
1258 | a41b2ff2 | pbrook | s->BasicModeCtrl = 0x1000; // autonegotiation |
1259 | a41b2ff2 | pbrook | |
1260 | a41b2ff2 | pbrook | s->BasicModeStatus = 0x7809;
|
1261 | a41b2ff2 | pbrook | //s->BasicModeStatus |= 0x0040; /* UTP medium */
|
1262 | a41b2ff2 | pbrook | s->BasicModeStatus |= 0x0020; /* autonegotiation completed */ |
1263 | a41b2ff2 | pbrook | s->BasicModeStatus |= 0x0004; /* link is up */ |
1264 | a41b2ff2 | pbrook | |
1265 | a41b2ff2 | pbrook | s->NWayAdvert = 0x05e1; /* all modes, full duplex */ |
1266 | a41b2ff2 | pbrook | s->NWayLPAR = 0x05e1; /* all modes, full duplex */ |
1267 | a41b2ff2 | pbrook | s->NWayExpansion = 0x0001; /* autonegotiation supported */ |
1268 | 6cadb320 | bellard | |
1269 | 6cadb320 | bellard | /* also reset timer and disable timer interrupt */
|
1270 | 6cadb320 | bellard | s->TCTR = 0;
|
1271 | 6cadb320 | bellard | s->TimerInt = 0;
|
1272 | 6cadb320 | bellard | s->TCTR_base = 0;
|
1273 | 6cadb320 | bellard | |
1274 | 6cadb320 | bellard | /* reset tally counters */
|
1275 | 6cadb320 | bellard | RTL8139TallyCounters_clear(&s->tally_counters); |
1276 | 6cadb320 | bellard | } |
1277 | 6cadb320 | bellard | |
1278 | b1d8e52e | blueswir1 | static void RTL8139TallyCounters_clear(RTL8139TallyCounters* counters) |
1279 | 6cadb320 | bellard | { |
1280 | 6cadb320 | bellard | counters->TxOk = 0;
|
1281 | 6cadb320 | bellard | counters->RxOk = 0;
|
1282 | 6cadb320 | bellard | counters->TxERR = 0;
|
1283 | 6cadb320 | bellard | counters->RxERR = 0;
|
1284 | 6cadb320 | bellard | counters->MissPkt = 0;
|
1285 | 6cadb320 | bellard | counters->FAE = 0;
|
1286 | 6cadb320 | bellard | counters->Tx1Col = 0;
|
1287 | 6cadb320 | bellard | counters->TxMCol = 0;
|
1288 | 6cadb320 | bellard | counters->RxOkPhy = 0;
|
1289 | 6cadb320 | bellard | counters->RxOkBrd = 0;
|
1290 | 6cadb320 | bellard | counters->RxOkMul = 0;
|
1291 | 6cadb320 | bellard | counters->TxAbt = 0;
|
1292 | 6cadb320 | bellard | counters->TxUndrn = 0;
|
1293 | 6cadb320 | bellard | } |
1294 | 6cadb320 | bellard | |
1295 | 3ada003a | Eduard - Gabriel Munteanu | static void RTL8139TallyCounters_dma_write(RTL8139State *s, dma_addr_t tc_addr) |
1296 | 6cadb320 | bellard | { |
1297 | 3ada003a | Eduard - Gabriel Munteanu | RTL8139TallyCounters *tally_counters = &s->tally_counters; |
1298 | 6cadb320 | bellard | uint16_t val16; |
1299 | 6cadb320 | bellard | uint32_t val32; |
1300 | 6cadb320 | bellard | uint64_t val64; |
1301 | 6cadb320 | bellard | |
1302 | 6cadb320 | bellard | val64 = cpu_to_le64(tally_counters->TxOk); |
1303 | 3ada003a | Eduard - Gabriel Munteanu | pci_dma_write(&s->dev, tc_addr + 0, (uint8_t *)&val64, 8); |
1304 | 6cadb320 | bellard | |
1305 | 6cadb320 | bellard | val64 = cpu_to_le64(tally_counters->RxOk); |
1306 | 3ada003a | Eduard - Gabriel Munteanu | pci_dma_write(&s->dev, tc_addr + 8, (uint8_t *)&val64, 8); |
1307 | 6cadb320 | bellard | |
1308 | 6cadb320 | bellard | val64 = cpu_to_le64(tally_counters->TxERR); |
1309 | 3ada003a | Eduard - Gabriel Munteanu | pci_dma_write(&s->dev, tc_addr + 16, (uint8_t *)&val64, 8); |
1310 | 6cadb320 | bellard | |
1311 | 6cadb320 | bellard | val32 = cpu_to_le32(tally_counters->RxERR); |
1312 | 3ada003a | Eduard - Gabriel Munteanu | pci_dma_write(&s->dev, tc_addr + 24, (uint8_t *)&val32, 4); |
1313 | 6cadb320 | bellard | |
1314 | 6cadb320 | bellard | val16 = cpu_to_le16(tally_counters->MissPkt); |
1315 | 3ada003a | Eduard - Gabriel Munteanu | pci_dma_write(&s->dev, tc_addr + 28, (uint8_t *)&val16, 2); |
1316 | 6cadb320 | bellard | |
1317 | 6cadb320 | bellard | val16 = cpu_to_le16(tally_counters->FAE); |
1318 | 3ada003a | Eduard - Gabriel Munteanu | pci_dma_write(&s->dev, tc_addr + 30, (uint8_t *)&val16, 2); |
1319 | 6cadb320 | bellard | |
1320 | 6cadb320 | bellard | val32 = cpu_to_le32(tally_counters->Tx1Col); |
1321 | 3ada003a | Eduard - Gabriel Munteanu | pci_dma_write(&s->dev, tc_addr + 32, (uint8_t *)&val32, 4); |
1322 | 6cadb320 | bellard | |
1323 | 6cadb320 | bellard | val32 = cpu_to_le32(tally_counters->TxMCol); |
1324 | 3ada003a | Eduard - Gabriel Munteanu | pci_dma_write(&s->dev, tc_addr + 36, (uint8_t *)&val32, 4); |
1325 | 6cadb320 | bellard | |
1326 | 6cadb320 | bellard | val64 = cpu_to_le64(tally_counters->RxOkPhy); |
1327 | 3ada003a | Eduard - Gabriel Munteanu | pci_dma_write(&s->dev, tc_addr + 40, (uint8_t *)&val64, 8); |
1328 | 6cadb320 | bellard | |
1329 | 6cadb320 | bellard | val64 = cpu_to_le64(tally_counters->RxOkBrd); |
1330 | 3ada003a | Eduard - Gabriel Munteanu | pci_dma_write(&s->dev, tc_addr + 48, (uint8_t *)&val64, 8); |
1331 | 6cadb320 | bellard | |
1332 | 6cadb320 | bellard | val32 = cpu_to_le32(tally_counters->RxOkMul); |
1333 | 3ada003a | Eduard - Gabriel Munteanu | pci_dma_write(&s->dev, tc_addr + 56, (uint8_t *)&val32, 4); |
1334 | 6cadb320 | bellard | |
1335 | 6cadb320 | bellard | val16 = cpu_to_le16(tally_counters->TxAbt); |
1336 | 3ada003a | Eduard - Gabriel Munteanu | pci_dma_write(&s->dev, tc_addr + 60, (uint8_t *)&val16, 2); |
1337 | 6cadb320 | bellard | |
1338 | 6cadb320 | bellard | val16 = cpu_to_le16(tally_counters->TxUndrn); |
1339 | 3ada003a | Eduard - Gabriel Munteanu | pci_dma_write(&s->dev, tc_addr + 62, (uint8_t *)&val16, 2); |
1340 | 6cadb320 | bellard | } |
1341 | 6cadb320 | bellard | |
1342 | 6cadb320 | bellard | /* Loads values of tally counters from VM state file */
|
1343 | 9d29cdea | Juan Quintela | |
1344 | 9d29cdea | Juan Quintela | static const VMStateDescription vmstate_tally_counters = { |
1345 | 9d29cdea | Juan Quintela | .name = "tally_counters",
|
1346 | 9d29cdea | Juan Quintela | .version_id = 1,
|
1347 | 9d29cdea | Juan Quintela | .minimum_version_id = 1,
|
1348 | 9d29cdea | Juan Quintela | .minimum_version_id_old = 1,
|
1349 | 9d29cdea | Juan Quintela | .fields = (VMStateField []) { |
1350 | 9d29cdea | Juan Quintela | VMSTATE_UINT64(TxOk, RTL8139TallyCounters), |
1351 | 9d29cdea | Juan Quintela | VMSTATE_UINT64(RxOk, RTL8139TallyCounters), |
1352 | 9d29cdea | Juan Quintela | VMSTATE_UINT64(TxERR, RTL8139TallyCounters), |
1353 | 9d29cdea | Juan Quintela | VMSTATE_UINT32(RxERR, RTL8139TallyCounters), |
1354 | 9d29cdea | Juan Quintela | VMSTATE_UINT16(MissPkt, RTL8139TallyCounters), |
1355 | 9d29cdea | Juan Quintela | VMSTATE_UINT16(FAE, RTL8139TallyCounters), |
1356 | 9d29cdea | Juan Quintela | VMSTATE_UINT32(Tx1Col, RTL8139TallyCounters), |
1357 | 9d29cdea | Juan Quintela | VMSTATE_UINT32(TxMCol, RTL8139TallyCounters), |
1358 | 9d29cdea | Juan Quintela | VMSTATE_UINT64(RxOkPhy, RTL8139TallyCounters), |
1359 | 9d29cdea | Juan Quintela | VMSTATE_UINT64(RxOkBrd, RTL8139TallyCounters), |
1360 | 9d29cdea | Juan Quintela | VMSTATE_UINT16(TxAbt, RTL8139TallyCounters), |
1361 | 9d29cdea | Juan Quintela | VMSTATE_UINT16(TxUndrn, RTL8139TallyCounters), |
1362 | 9d29cdea | Juan Quintela | VMSTATE_END_OF_LIST() |
1363 | 9d29cdea | Juan Quintela | } |
1364 | 9d29cdea | Juan Quintela | }; |
1365 | a41b2ff2 | pbrook | |
1366 | a41b2ff2 | pbrook | static void rtl8139_ChipCmd_write(RTL8139State *s, uint32_t val) |
1367 | a41b2ff2 | pbrook | { |
1368 | a41b2ff2 | pbrook | val &= 0xff;
|
1369 | a41b2ff2 | pbrook | |
1370 | 7cdeb319 | Benjamin Poirier | DPRINTF("ChipCmd write val=0x%08x\n", val);
|
1371 | a41b2ff2 | pbrook | |
1372 | a41b2ff2 | pbrook | if (val & CmdReset)
|
1373 | a41b2ff2 | pbrook | { |
1374 | 7cdeb319 | Benjamin Poirier | DPRINTF("ChipCmd reset\n");
|
1375 | 7f23f812 | Michael S. Tsirkin | rtl8139_reset(&s->dev.qdev); |
1376 | a41b2ff2 | pbrook | } |
1377 | a41b2ff2 | pbrook | if (val & CmdRxEnb)
|
1378 | a41b2ff2 | pbrook | { |
1379 | 7cdeb319 | Benjamin Poirier | DPRINTF("ChipCmd enable receiver\n");
|
1380 | 718da2b9 | bellard | |
1381 | 718da2b9 | bellard | s->currCPlusRxDesc = 0;
|
1382 | a41b2ff2 | pbrook | } |
1383 | a41b2ff2 | pbrook | if (val & CmdTxEnb)
|
1384 | a41b2ff2 | pbrook | { |
1385 | 7cdeb319 | Benjamin Poirier | DPRINTF("ChipCmd enable transmitter\n");
|
1386 | 718da2b9 | bellard | |
1387 | 718da2b9 | bellard | s->currCPlusTxDesc = 0;
|
1388 | a41b2ff2 | pbrook | } |
1389 | a41b2ff2 | pbrook | |
1390 | ebabb67a | Stefan Weil | /* mask unwritable bits */
|
1391 | a41b2ff2 | pbrook | val = SET_MASKED(val, 0xe3, s->bChipCmdState);
|
1392 | a41b2ff2 | pbrook | |
1393 | a41b2ff2 | pbrook | /* Deassert reset pin before next read */
|
1394 | a41b2ff2 | pbrook | val &= ~CmdReset; |
1395 | a41b2ff2 | pbrook | |
1396 | a41b2ff2 | pbrook | s->bChipCmdState = val; |
1397 | a41b2ff2 | pbrook | } |
1398 | a41b2ff2 | pbrook | |
1399 | a41b2ff2 | pbrook | static int rtl8139_RxBufferEmpty(RTL8139State *s) |
1400 | a41b2ff2 | pbrook | { |
1401 | a41b2ff2 | pbrook | int unread = MOD2(s->RxBufferSize + s->RxBufAddr - s->RxBufPtr, s->RxBufferSize);
|
1402 | a41b2ff2 | pbrook | |
1403 | a41b2ff2 | pbrook | if (unread != 0) |
1404 | a41b2ff2 | pbrook | { |
1405 | 7cdeb319 | Benjamin Poirier | DPRINTF("receiver buffer data available 0x%04x\n", unread);
|
1406 | a41b2ff2 | pbrook | return 0; |
1407 | a41b2ff2 | pbrook | } |
1408 | a41b2ff2 | pbrook | |
1409 | 7cdeb319 | Benjamin Poirier | DPRINTF("receiver buffer is empty\n");
|
1410 | a41b2ff2 | pbrook | |
1411 | a41b2ff2 | pbrook | return 1; |
1412 | a41b2ff2 | pbrook | } |
1413 | a41b2ff2 | pbrook | |
1414 | a41b2ff2 | pbrook | static uint32_t rtl8139_ChipCmd_read(RTL8139State *s)
|
1415 | a41b2ff2 | pbrook | { |
1416 | a41b2ff2 | pbrook | uint32_t ret = s->bChipCmdState; |
1417 | a41b2ff2 | pbrook | |
1418 | a41b2ff2 | pbrook | if (rtl8139_RxBufferEmpty(s))
|
1419 | a41b2ff2 | pbrook | ret |= RxBufEmpty; |
1420 | a41b2ff2 | pbrook | |
1421 | 7cdeb319 | Benjamin Poirier | DPRINTF("ChipCmd read val=0x%04x\n", ret);
|
1422 | a41b2ff2 | pbrook | |
1423 | a41b2ff2 | pbrook | return ret;
|
1424 | a41b2ff2 | pbrook | } |
1425 | a41b2ff2 | pbrook | |
1426 | a41b2ff2 | pbrook | static void rtl8139_CpCmd_write(RTL8139State *s, uint32_t val) |
1427 | a41b2ff2 | pbrook | { |
1428 | a41b2ff2 | pbrook | val &= 0xffff;
|
1429 | a41b2ff2 | pbrook | |
1430 | 7cdeb319 | Benjamin Poirier | DPRINTF("C+ command register write(w) val=0x%04x\n", val);
|
1431 | a41b2ff2 | pbrook | |
1432 | 2c3891ab | aliguori | s->cplus_enabled = 1;
|
1433 | 2c3891ab | aliguori | |
1434 | ebabb67a | Stefan Weil | /* mask unwritable bits */
|
1435 | a41b2ff2 | pbrook | val = SET_MASKED(val, 0xff84, s->CpCmd);
|
1436 | a41b2ff2 | pbrook | |
1437 | a41b2ff2 | pbrook | s->CpCmd = val; |
1438 | a41b2ff2 | pbrook | } |
1439 | a41b2ff2 | pbrook | |
1440 | a41b2ff2 | pbrook | static uint32_t rtl8139_CpCmd_read(RTL8139State *s)
|
1441 | a41b2ff2 | pbrook | { |
1442 | a41b2ff2 | pbrook | uint32_t ret = s->CpCmd; |
1443 | a41b2ff2 | pbrook | |
1444 | 7cdeb319 | Benjamin Poirier | DPRINTF("C+ command register read(w) val=0x%04x\n", ret);
|
1445 | 6cadb320 | bellard | |
1446 | 6cadb320 | bellard | return ret;
|
1447 | 6cadb320 | bellard | } |
1448 | 6cadb320 | bellard | |
1449 | 6cadb320 | bellard | static void rtl8139_IntrMitigate_write(RTL8139State *s, uint32_t val) |
1450 | 6cadb320 | bellard | { |
1451 | 7cdeb319 | Benjamin Poirier | DPRINTF("C+ IntrMitigate register write(w) val=0x%04x\n", val);
|
1452 | 6cadb320 | bellard | } |
1453 | 6cadb320 | bellard | |
1454 | 6cadb320 | bellard | static uint32_t rtl8139_IntrMitigate_read(RTL8139State *s)
|
1455 | 6cadb320 | bellard | { |
1456 | 6cadb320 | bellard | uint32_t ret = 0;
|
1457 | 6cadb320 | bellard | |
1458 | 7cdeb319 | Benjamin Poirier | DPRINTF("C+ IntrMitigate register read(w) val=0x%04x\n", ret);
|
1459 | a41b2ff2 | pbrook | |
1460 | a41b2ff2 | pbrook | return ret;
|
1461 | a41b2ff2 | pbrook | } |
1462 | a41b2ff2 | pbrook | |
1463 | ebabb67a | Stefan Weil | static int rtl8139_config_writable(RTL8139State *s) |
1464 | a41b2ff2 | pbrook | { |
1465 | eb46c5ed | Jason Wang | if ((s->Cfg9346 & Chip9346_op_mask) == Cfg9346_ConfigWrite)
|
1466 | a41b2ff2 | pbrook | { |
1467 | a41b2ff2 | pbrook | return 1; |
1468 | a41b2ff2 | pbrook | } |
1469 | a41b2ff2 | pbrook | |
1470 | 7cdeb319 | Benjamin Poirier | DPRINTF("Configuration registers are write-protected\n");
|
1471 | a41b2ff2 | pbrook | |
1472 | a41b2ff2 | pbrook | return 0; |
1473 | a41b2ff2 | pbrook | } |
1474 | a41b2ff2 | pbrook | |
1475 | a41b2ff2 | pbrook | static void rtl8139_BasicModeCtrl_write(RTL8139State *s, uint32_t val) |
1476 | a41b2ff2 | pbrook | { |
1477 | a41b2ff2 | pbrook | val &= 0xffff;
|
1478 | a41b2ff2 | pbrook | |
1479 | 7cdeb319 | Benjamin Poirier | DPRINTF("BasicModeCtrl register write(w) val=0x%04x\n", val);
|
1480 | a41b2ff2 | pbrook | |
1481 | ebabb67a | Stefan Weil | /* mask unwritable bits */
|
1482 | e3d7e843 | ths | uint32_t mask = 0x4cff;
|
1483 | a41b2ff2 | pbrook | |
1484 | ebabb67a | Stefan Weil | if (1 || !rtl8139_config_writable(s)) |
1485 | a41b2ff2 | pbrook | { |
1486 | a41b2ff2 | pbrook | /* Speed setting and autonegotiation enable bits are read-only */
|
1487 | a41b2ff2 | pbrook | mask |= 0x3000;
|
1488 | a41b2ff2 | pbrook | /* Duplex mode setting is read-only */
|
1489 | a41b2ff2 | pbrook | mask |= 0x0100;
|
1490 | a41b2ff2 | pbrook | } |
1491 | a41b2ff2 | pbrook | |
1492 | a41b2ff2 | pbrook | val = SET_MASKED(val, mask, s->BasicModeCtrl); |
1493 | a41b2ff2 | pbrook | |
1494 | a41b2ff2 | pbrook | s->BasicModeCtrl = val; |
1495 | a41b2ff2 | pbrook | } |
1496 | a41b2ff2 | pbrook | |
1497 | a41b2ff2 | pbrook | static uint32_t rtl8139_BasicModeCtrl_read(RTL8139State *s)
|
1498 | a41b2ff2 | pbrook | { |
1499 | a41b2ff2 | pbrook | uint32_t ret = s->BasicModeCtrl; |
1500 | a41b2ff2 | pbrook | |
1501 | 7cdeb319 | Benjamin Poirier | DPRINTF("BasicModeCtrl register read(w) val=0x%04x\n", ret);
|
1502 | a41b2ff2 | pbrook | |
1503 | a41b2ff2 | pbrook | return ret;
|
1504 | a41b2ff2 | pbrook | } |
1505 | a41b2ff2 | pbrook | |
1506 | a41b2ff2 | pbrook | static void rtl8139_BasicModeStatus_write(RTL8139State *s, uint32_t val) |
1507 | a41b2ff2 | pbrook | { |
1508 | a41b2ff2 | pbrook | val &= 0xffff;
|
1509 | a41b2ff2 | pbrook | |
1510 | 7cdeb319 | Benjamin Poirier | DPRINTF("BasicModeStatus register write(w) val=0x%04x\n", val);
|
1511 | a41b2ff2 | pbrook | |
1512 | ebabb67a | Stefan Weil | /* mask unwritable bits */
|
1513 | a41b2ff2 | pbrook | val = SET_MASKED(val, 0xff3f, s->BasicModeStatus);
|
1514 | a41b2ff2 | pbrook | |
1515 | a41b2ff2 | pbrook | s->BasicModeStatus = val; |
1516 | a41b2ff2 | pbrook | } |
1517 | a41b2ff2 | pbrook | |
1518 | a41b2ff2 | pbrook | static uint32_t rtl8139_BasicModeStatus_read(RTL8139State *s)
|
1519 | a41b2ff2 | pbrook | { |
1520 | a41b2ff2 | pbrook | uint32_t ret = s->BasicModeStatus; |
1521 | a41b2ff2 | pbrook | |
1522 | 7cdeb319 | Benjamin Poirier | DPRINTF("BasicModeStatus register read(w) val=0x%04x\n", ret);
|
1523 | a41b2ff2 | pbrook | |
1524 | a41b2ff2 | pbrook | return ret;
|
1525 | a41b2ff2 | pbrook | } |
1526 | a41b2ff2 | pbrook | |
1527 | a41b2ff2 | pbrook | static void rtl8139_Cfg9346_write(RTL8139State *s, uint32_t val) |
1528 | a41b2ff2 | pbrook | { |
1529 | a41b2ff2 | pbrook | val &= 0xff;
|
1530 | a41b2ff2 | pbrook | |
1531 | 7cdeb319 | Benjamin Poirier | DPRINTF("Cfg9346 write val=0x%02x\n", val);
|
1532 | a41b2ff2 | pbrook | |
1533 | ebabb67a | Stefan Weil | /* mask unwritable bits */
|
1534 | a41b2ff2 | pbrook | val = SET_MASKED(val, 0x31, s->Cfg9346);
|
1535 | a41b2ff2 | pbrook | |
1536 | a41b2ff2 | pbrook | uint32_t opmode = val & 0xc0;
|
1537 | a41b2ff2 | pbrook | uint32_t eeprom_val = val & 0xf;
|
1538 | a41b2ff2 | pbrook | |
1539 | a41b2ff2 | pbrook | if (opmode == 0x80) { |
1540 | a41b2ff2 | pbrook | /* eeprom access */
|
1541 | a41b2ff2 | pbrook | int eecs = (eeprom_val & 0x08)?1:0; |
1542 | a41b2ff2 | pbrook | int eesk = (eeprom_val & 0x04)?1:0; |
1543 | a41b2ff2 | pbrook | int eedi = (eeprom_val & 0x02)?1:0; |
1544 | a41b2ff2 | pbrook | prom9346_set_wire(s, eecs, eesk, eedi); |
1545 | a41b2ff2 | pbrook | } else if (opmode == 0x40) { |
1546 | a41b2ff2 | pbrook | /* Reset. */
|
1547 | a41b2ff2 | pbrook | val = 0;
|
1548 | 7f23f812 | Michael S. Tsirkin | rtl8139_reset(&s->dev.qdev); |
1549 | a41b2ff2 | pbrook | } |
1550 | a41b2ff2 | pbrook | |
1551 | a41b2ff2 | pbrook | s->Cfg9346 = val; |
1552 | a41b2ff2 | pbrook | } |
1553 | a41b2ff2 | pbrook | |
1554 | a41b2ff2 | pbrook | static uint32_t rtl8139_Cfg9346_read(RTL8139State *s)
|
1555 | a41b2ff2 | pbrook | { |
1556 | a41b2ff2 | pbrook | uint32_t ret = s->Cfg9346; |
1557 | a41b2ff2 | pbrook | |
1558 | a41b2ff2 | pbrook | uint32_t opmode = ret & 0xc0;
|
1559 | a41b2ff2 | pbrook | |
1560 | a41b2ff2 | pbrook | if (opmode == 0x80) |
1561 | a41b2ff2 | pbrook | { |
1562 | a41b2ff2 | pbrook | /* eeprom access */
|
1563 | a41b2ff2 | pbrook | int eedo = prom9346_get_wire(s);
|
1564 | a41b2ff2 | pbrook | if (eedo)
|
1565 | a41b2ff2 | pbrook | { |
1566 | a41b2ff2 | pbrook | ret |= 0x01;
|
1567 | a41b2ff2 | pbrook | } |
1568 | a41b2ff2 | pbrook | else
|
1569 | a41b2ff2 | pbrook | { |
1570 | a41b2ff2 | pbrook | ret &= ~0x01;
|
1571 | a41b2ff2 | pbrook | } |
1572 | a41b2ff2 | pbrook | } |
1573 | a41b2ff2 | pbrook | |
1574 | 7cdeb319 | Benjamin Poirier | DPRINTF("Cfg9346 read val=0x%02x\n", ret);
|
1575 | a41b2ff2 | pbrook | |
1576 | a41b2ff2 | pbrook | return ret;
|
1577 | a41b2ff2 | pbrook | } |
1578 | a41b2ff2 | pbrook | |
1579 | a41b2ff2 | pbrook | static void rtl8139_Config0_write(RTL8139State *s, uint32_t val) |
1580 | a41b2ff2 | pbrook | { |
1581 | a41b2ff2 | pbrook | val &= 0xff;
|
1582 | a41b2ff2 | pbrook | |
1583 | 7cdeb319 | Benjamin Poirier | DPRINTF("Config0 write val=0x%02x\n", val);
|
1584 | a41b2ff2 | pbrook | |
1585 | ebabb67a | Stefan Weil | if (!rtl8139_config_writable(s)) {
|
1586 | a41b2ff2 | pbrook | return;
|
1587 | ebabb67a | Stefan Weil | } |
1588 | a41b2ff2 | pbrook | |
1589 | ebabb67a | Stefan Weil | /* mask unwritable bits */
|
1590 | a41b2ff2 | pbrook | val = SET_MASKED(val, 0xf8, s->Config0);
|
1591 | a41b2ff2 | pbrook | |
1592 | a41b2ff2 | pbrook | s->Config0 = val; |
1593 | a41b2ff2 | pbrook | } |
1594 | a41b2ff2 | pbrook | |
1595 | a41b2ff2 | pbrook | static uint32_t rtl8139_Config0_read(RTL8139State *s)
|
1596 | a41b2ff2 | pbrook | { |
1597 | a41b2ff2 | pbrook | uint32_t ret = s->Config0; |
1598 | a41b2ff2 | pbrook | |
1599 | 7cdeb319 | Benjamin Poirier | DPRINTF("Config0 read val=0x%02x\n", ret);
|
1600 | a41b2ff2 | pbrook | |
1601 | a41b2ff2 | pbrook | return ret;
|
1602 | a41b2ff2 | pbrook | } |
1603 | a41b2ff2 | pbrook | |
1604 | a41b2ff2 | pbrook | static void rtl8139_Config1_write(RTL8139State *s, uint32_t val) |
1605 | a41b2ff2 | pbrook | { |
1606 | a41b2ff2 | pbrook | val &= 0xff;
|
1607 | a41b2ff2 | pbrook | |
1608 | 7cdeb319 | Benjamin Poirier | DPRINTF("Config1 write val=0x%02x\n", val);
|
1609 | a41b2ff2 | pbrook | |
1610 | ebabb67a | Stefan Weil | if (!rtl8139_config_writable(s)) {
|
1611 | a41b2ff2 | pbrook | return;
|
1612 | ebabb67a | Stefan Weil | } |
1613 | a41b2ff2 | pbrook | |
1614 | ebabb67a | Stefan Weil | /* mask unwritable bits */
|
1615 | a41b2ff2 | pbrook | val = SET_MASKED(val, 0xC, s->Config1);
|
1616 | a41b2ff2 | pbrook | |
1617 | a41b2ff2 | pbrook | s->Config1 = val; |
1618 | a41b2ff2 | pbrook | } |
1619 | a41b2ff2 | pbrook | |
1620 | a41b2ff2 | pbrook | static uint32_t rtl8139_Config1_read(RTL8139State *s)
|
1621 | a41b2ff2 | pbrook | { |
1622 | a41b2ff2 | pbrook | uint32_t ret = s->Config1; |
1623 | a41b2ff2 | pbrook | |
1624 | 7cdeb319 | Benjamin Poirier | DPRINTF("Config1 read val=0x%02x\n", ret);
|
1625 | a41b2ff2 | pbrook | |
1626 | a41b2ff2 | pbrook | return ret;
|
1627 | a41b2ff2 | pbrook | } |
1628 | a41b2ff2 | pbrook | |
1629 | a41b2ff2 | pbrook | static void rtl8139_Config3_write(RTL8139State *s, uint32_t val) |
1630 | a41b2ff2 | pbrook | { |
1631 | a41b2ff2 | pbrook | val &= 0xff;
|
1632 | a41b2ff2 | pbrook | |
1633 | 7cdeb319 | Benjamin Poirier | DPRINTF("Config3 write val=0x%02x\n", val);
|
1634 | a41b2ff2 | pbrook | |
1635 | ebabb67a | Stefan Weil | if (!rtl8139_config_writable(s)) {
|
1636 | a41b2ff2 | pbrook | return;
|
1637 | ebabb67a | Stefan Weil | } |
1638 | a41b2ff2 | pbrook | |
1639 | ebabb67a | Stefan Weil | /* mask unwritable bits */
|
1640 | a41b2ff2 | pbrook | val = SET_MASKED(val, 0x8F, s->Config3);
|
1641 | a41b2ff2 | pbrook | |
1642 | a41b2ff2 | pbrook | s->Config3 = val; |
1643 | a41b2ff2 | pbrook | } |
1644 | a41b2ff2 | pbrook | |
1645 | a41b2ff2 | pbrook | static uint32_t rtl8139_Config3_read(RTL8139State *s)
|
1646 | a41b2ff2 | pbrook | { |
1647 | a41b2ff2 | pbrook | uint32_t ret = s->Config3; |
1648 | a41b2ff2 | pbrook | |
1649 | 7cdeb319 | Benjamin Poirier | DPRINTF("Config3 read val=0x%02x\n", ret);
|
1650 | a41b2ff2 | pbrook | |
1651 | a41b2ff2 | pbrook | return ret;
|
1652 | a41b2ff2 | pbrook | } |
1653 | a41b2ff2 | pbrook | |
1654 | a41b2ff2 | pbrook | static void rtl8139_Config4_write(RTL8139State *s, uint32_t val) |
1655 | a41b2ff2 | pbrook | { |
1656 | a41b2ff2 | pbrook | val &= 0xff;
|
1657 | a41b2ff2 | pbrook | |
1658 | 7cdeb319 | Benjamin Poirier | DPRINTF("Config4 write val=0x%02x\n", val);
|
1659 | a41b2ff2 | pbrook | |
1660 | ebabb67a | Stefan Weil | if (!rtl8139_config_writable(s)) {
|
1661 | a41b2ff2 | pbrook | return;
|
1662 | ebabb67a | Stefan Weil | } |
1663 | a41b2ff2 | pbrook | |
1664 | ebabb67a | Stefan Weil | /* mask unwritable bits */
|
1665 | a41b2ff2 | pbrook | val = SET_MASKED(val, 0x0a, s->Config4);
|
1666 | a41b2ff2 | pbrook | |
1667 | a41b2ff2 | pbrook | s->Config4 = val; |
1668 | a41b2ff2 | pbrook | } |
1669 | a41b2ff2 | pbrook | |
1670 | a41b2ff2 | pbrook | static uint32_t rtl8139_Config4_read(RTL8139State *s)
|
1671 | a41b2ff2 | pbrook | { |
1672 | a41b2ff2 | pbrook | uint32_t ret = s->Config4; |
1673 | a41b2ff2 | pbrook | |
1674 | 7cdeb319 | Benjamin Poirier | DPRINTF("Config4 read val=0x%02x\n", ret);
|
1675 | a41b2ff2 | pbrook | |
1676 | a41b2ff2 | pbrook | return ret;
|
1677 | a41b2ff2 | pbrook | } |
1678 | a41b2ff2 | pbrook | |
1679 | a41b2ff2 | pbrook | static void rtl8139_Config5_write(RTL8139State *s, uint32_t val) |
1680 | a41b2ff2 | pbrook | { |
1681 | a41b2ff2 | pbrook | val &= 0xff;
|
1682 | a41b2ff2 | pbrook | |
1683 | 7cdeb319 | Benjamin Poirier | DPRINTF("Config5 write val=0x%02x\n", val);
|
1684 | a41b2ff2 | pbrook | |
1685 | ebabb67a | Stefan Weil | /* mask unwritable bits */
|
1686 | a41b2ff2 | pbrook | val = SET_MASKED(val, 0x80, s->Config5);
|
1687 | a41b2ff2 | pbrook | |
1688 | a41b2ff2 | pbrook | s->Config5 = val; |
1689 | a41b2ff2 | pbrook | } |
1690 | a41b2ff2 | pbrook | |
1691 | a41b2ff2 | pbrook | static uint32_t rtl8139_Config5_read(RTL8139State *s)
|
1692 | a41b2ff2 | pbrook | { |
1693 | a41b2ff2 | pbrook | uint32_t ret = s->Config5; |
1694 | a41b2ff2 | pbrook | |
1695 | 7cdeb319 | Benjamin Poirier | DPRINTF("Config5 read val=0x%02x\n", ret);
|
1696 | a41b2ff2 | pbrook | |
1697 | a41b2ff2 | pbrook | return ret;
|
1698 | a41b2ff2 | pbrook | } |
1699 | a41b2ff2 | pbrook | |
1700 | a41b2ff2 | pbrook | static void rtl8139_TxConfig_write(RTL8139State *s, uint32_t val) |
1701 | a41b2ff2 | pbrook | { |
1702 | a41b2ff2 | pbrook | if (!rtl8139_transmitter_enabled(s))
|
1703 | a41b2ff2 | pbrook | { |
1704 | 7cdeb319 | Benjamin Poirier | DPRINTF("transmitter disabled; no TxConfig write val=0x%08x\n", val);
|
1705 | a41b2ff2 | pbrook | return;
|
1706 | a41b2ff2 | pbrook | } |
1707 | a41b2ff2 | pbrook | |
1708 | 7cdeb319 | Benjamin Poirier | DPRINTF("TxConfig write val=0x%08x\n", val);
|
1709 | a41b2ff2 | pbrook | |
1710 | a41b2ff2 | pbrook | val = SET_MASKED(val, TxVersionMask | 0x8070f80f, s->TxConfig);
|
1711 | a41b2ff2 | pbrook | |
1712 | a41b2ff2 | pbrook | s->TxConfig = val; |
1713 | a41b2ff2 | pbrook | } |
1714 | a41b2ff2 | pbrook | |
1715 | a41b2ff2 | pbrook | static void rtl8139_TxConfig_writeb(RTL8139State *s, uint32_t val) |
1716 | a41b2ff2 | pbrook | { |
1717 | 7cdeb319 | Benjamin Poirier | DPRINTF("RTL8139C TxConfig via write(b) val=0x%02x\n", val);
|
1718 | 6cadb320 | bellard | |
1719 | 6cadb320 | bellard | uint32_t tc = s->TxConfig; |
1720 | 6cadb320 | bellard | tc &= 0xFFFFFF00;
|
1721 | 6cadb320 | bellard | tc |= (val & 0x000000FF);
|
1722 | 6cadb320 | bellard | rtl8139_TxConfig_write(s, tc); |
1723 | a41b2ff2 | pbrook | } |
1724 | a41b2ff2 | pbrook | |
1725 | a41b2ff2 | pbrook | static uint32_t rtl8139_TxConfig_read(RTL8139State *s)
|
1726 | a41b2ff2 | pbrook | { |
1727 | a41b2ff2 | pbrook | uint32_t ret = s->TxConfig; |
1728 | a41b2ff2 | pbrook | |
1729 | 7cdeb319 | Benjamin Poirier | DPRINTF("TxConfig read val=0x%04x\n", ret);
|
1730 | a41b2ff2 | pbrook | |
1731 | a41b2ff2 | pbrook | return ret;
|
1732 | a41b2ff2 | pbrook | } |
1733 | a41b2ff2 | pbrook | |
1734 | a41b2ff2 | pbrook | static void rtl8139_RxConfig_write(RTL8139State *s, uint32_t val) |
1735 | a41b2ff2 | pbrook | { |
1736 | 7cdeb319 | Benjamin Poirier | DPRINTF("RxConfig write val=0x%08x\n", val);
|
1737 | a41b2ff2 | pbrook | |
1738 | ebabb67a | Stefan Weil | /* mask unwritable bits */
|
1739 | a41b2ff2 | pbrook | val = SET_MASKED(val, 0xf0fc0040, s->RxConfig);
|
1740 | a41b2ff2 | pbrook | |
1741 | a41b2ff2 | pbrook | s->RxConfig = val; |
1742 | a41b2ff2 | pbrook | |
1743 | a41b2ff2 | pbrook | /* reset buffer size and read/write pointers */
|
1744 | a41b2ff2 | pbrook | rtl8139_reset_rxring(s, 8192 << ((s->RxConfig >> 11) & 0x3)); |
1745 | a41b2ff2 | pbrook | |
1746 | 7cdeb319 | Benjamin Poirier | DPRINTF("RxConfig write reset buffer size to %d\n", s->RxBufferSize);
|
1747 | a41b2ff2 | pbrook | } |
1748 | a41b2ff2 | pbrook | |
1749 | a41b2ff2 | pbrook | static uint32_t rtl8139_RxConfig_read(RTL8139State *s)
|
1750 | a41b2ff2 | pbrook | { |
1751 | a41b2ff2 | pbrook | uint32_t ret = s->RxConfig; |
1752 | a41b2ff2 | pbrook | |
1753 | 7cdeb319 | Benjamin Poirier | DPRINTF("RxConfig read val=0x%08x\n", ret);
|
1754 | a41b2ff2 | pbrook | |
1755 | a41b2ff2 | pbrook | return ret;
|
1756 | a41b2ff2 | pbrook | } |
1757 | a41b2ff2 | pbrook | |
1758 | bf6b87a8 | Benjamin Poirier | static void rtl8139_transfer_frame(RTL8139State *s, uint8_t *buf, int size, |
1759 | bf6b87a8 | Benjamin Poirier | int do_interrupt, const uint8_t *dot1q_buf) |
1760 | 718da2b9 | bellard | { |
1761 | bf6b87a8 | Benjamin Poirier | struct iovec *iov = NULL; |
1762 | bf6b87a8 | Benjamin Poirier | |
1763 | 718da2b9 | bellard | if (!size)
|
1764 | 718da2b9 | bellard | { |
1765 | 7cdeb319 | Benjamin Poirier | DPRINTF("+++ empty ethernet frame\n");
|
1766 | 718da2b9 | bellard | return;
|
1767 | 718da2b9 | bellard | } |
1768 | 718da2b9 | bellard | |
1769 | bf6b87a8 | Benjamin Poirier | if (dot1q_buf && size >= ETHER_ADDR_LEN * 2) { |
1770 | bf6b87a8 | Benjamin Poirier | iov = (struct iovec[3]) { |
1771 | bf6b87a8 | Benjamin Poirier | { .iov_base = buf, .iov_len = ETHER_ADDR_LEN * 2 },
|
1772 | bf6b87a8 | Benjamin Poirier | { .iov_base = (void *) dot1q_buf, .iov_len = VLAN_HLEN },
|
1773 | bf6b87a8 | Benjamin Poirier | { .iov_base = buf + ETHER_ADDR_LEN * 2,
|
1774 | bf6b87a8 | Benjamin Poirier | .iov_len = size - ETHER_ADDR_LEN * 2 },
|
1775 | bf6b87a8 | Benjamin Poirier | }; |
1776 | bf6b87a8 | Benjamin Poirier | } |
1777 | bf6b87a8 | Benjamin Poirier | |
1778 | 718da2b9 | bellard | if (TxLoopBack == (s->TxConfig & TxLoopBack))
|
1779 | 718da2b9 | bellard | { |
1780 | bf6b87a8 | Benjamin Poirier | size_t buf2_size; |
1781 | bf6b87a8 | Benjamin Poirier | uint8_t *buf2; |
1782 | bf6b87a8 | Benjamin Poirier | |
1783 | bf6b87a8 | Benjamin Poirier | if (iov) {
|
1784 | bf6b87a8 | Benjamin Poirier | buf2_size = iov_size(iov, 3);
|
1785 | 7267c094 | Anthony Liguori | buf2 = g_malloc(buf2_size); |
1786 | bf6b87a8 | Benjamin Poirier | iov_to_buf(iov, 3, buf2, 0, buf2_size); |
1787 | bf6b87a8 | Benjamin Poirier | buf = buf2; |
1788 | bf6b87a8 | Benjamin Poirier | } |
1789 | bf6b87a8 | Benjamin Poirier | |
1790 | 7cdeb319 | Benjamin Poirier | DPRINTF("+++ transmit loopback mode\n");
|
1791 | 1673ad51 | Mark McLoughlin | rtl8139_do_receive(&s->nic->nc, buf, size, do_interrupt); |
1792 | bf6b87a8 | Benjamin Poirier | |
1793 | bf6b87a8 | Benjamin Poirier | if (iov) {
|
1794 | 7267c094 | Anthony Liguori | g_free(buf2); |
1795 | bf6b87a8 | Benjamin Poirier | } |
1796 | 718da2b9 | bellard | } |
1797 | 718da2b9 | bellard | else
|
1798 | 718da2b9 | bellard | { |
1799 | bf6b87a8 | Benjamin Poirier | if (iov) {
|
1800 | bf6b87a8 | Benjamin Poirier | qemu_sendv_packet(&s->nic->nc, iov, 3);
|
1801 | bf6b87a8 | Benjamin Poirier | } else {
|
1802 | bf6b87a8 | Benjamin Poirier | qemu_send_packet(&s->nic->nc, buf, size); |
1803 | bf6b87a8 | Benjamin Poirier | } |
1804 | 718da2b9 | bellard | } |
1805 | 718da2b9 | bellard | } |
1806 | 718da2b9 | bellard | |
1807 | a41b2ff2 | pbrook | static int rtl8139_transmit_one(RTL8139State *s, int descriptor) |
1808 | a41b2ff2 | pbrook | { |
1809 | a41b2ff2 | pbrook | if (!rtl8139_transmitter_enabled(s))
|
1810 | a41b2ff2 | pbrook | { |
1811 | 7cdeb319 | Benjamin Poirier | DPRINTF("+++ cannot transmit from descriptor %d: transmitter "
|
1812 | 7cdeb319 | Benjamin Poirier | "disabled\n", descriptor);
|
1813 | a41b2ff2 | pbrook | return 0; |
1814 | a41b2ff2 | pbrook | } |
1815 | a41b2ff2 | pbrook | |
1816 | a41b2ff2 | pbrook | if (s->TxStatus[descriptor] & TxHostOwns)
|
1817 | a41b2ff2 | pbrook | { |
1818 | 7cdeb319 | Benjamin Poirier | DPRINTF("+++ cannot transmit from descriptor %d: owned by host "
|
1819 | 7cdeb319 | Benjamin Poirier | "(%08x)\n", descriptor, s->TxStatus[descriptor]);
|
1820 | a41b2ff2 | pbrook | return 0; |
1821 | a41b2ff2 | pbrook | } |
1822 | a41b2ff2 | pbrook | |
1823 | 7cdeb319 | Benjamin Poirier | DPRINTF("+++ transmitting from descriptor %d\n", descriptor);
|
1824 | a41b2ff2 | pbrook | |
1825 | a41b2ff2 | pbrook | int txsize = s->TxStatus[descriptor] & 0x1fff; |
1826 | a41b2ff2 | pbrook | uint8_t txbuffer[0x2000];
|
1827 | a41b2ff2 | pbrook | |
1828 | 7cdeb319 | Benjamin Poirier | DPRINTF("+++ transmit reading %d bytes from host memory at 0x%08x\n",
|
1829 | 7cdeb319 | Benjamin Poirier | txsize, s->TxAddr[descriptor]); |
1830 | a41b2ff2 | pbrook | |
1831 | 3ada003a | Eduard - Gabriel Munteanu | pci_dma_read(&s->dev, s->TxAddr[descriptor], txbuffer, txsize); |
1832 | a41b2ff2 | pbrook | |
1833 | a41b2ff2 | pbrook | /* Mark descriptor as transferred */
|
1834 | a41b2ff2 | pbrook | s->TxStatus[descriptor] |= TxHostOwns; |
1835 | a41b2ff2 | pbrook | s->TxStatus[descriptor] |= TxStatOK; |
1836 | a41b2ff2 | pbrook | |
1837 | bf6b87a8 | Benjamin Poirier | rtl8139_transfer_frame(s, txbuffer, txsize, 0, NULL); |
1838 | 6cadb320 | bellard | |
1839 | 7cdeb319 | Benjamin Poirier | DPRINTF("+++ transmitted %d bytes from descriptor %d\n", txsize,
|
1840 | 7cdeb319 | Benjamin Poirier | descriptor); |
1841 | a41b2ff2 | pbrook | |
1842 | a41b2ff2 | pbrook | /* update interrupt */
|
1843 | a41b2ff2 | pbrook | s->IntrStatus |= TxOK; |
1844 | a41b2ff2 | pbrook | rtl8139_update_irq(s); |
1845 | a41b2ff2 | pbrook | |
1846 | a41b2ff2 | pbrook | return 1; |
1847 | a41b2ff2 | pbrook | } |
1848 | a41b2ff2 | pbrook | |
1849 | 718da2b9 | bellard | /* structures and macros for task offloading */
|
1850 | 718da2b9 | bellard | typedef struct ip_header |
1851 | 718da2b9 | bellard | { |
1852 | 718da2b9 | bellard | uint8_t ip_ver_len; /* version and header length */
|
1853 | 718da2b9 | bellard | uint8_t ip_tos; /* type of service */
|
1854 | 718da2b9 | bellard | uint16_t ip_len; /* total length */
|
1855 | 718da2b9 | bellard | uint16_t ip_id; /* identification */
|
1856 | 718da2b9 | bellard | uint16_t ip_off; /* fragment offset field */
|
1857 | 718da2b9 | bellard | uint8_t ip_ttl; /* time to live */
|
1858 | 718da2b9 | bellard | uint8_t ip_p; /* protocol */
|
1859 | 718da2b9 | bellard | uint16_t ip_sum; /* checksum */
|
1860 | 718da2b9 | bellard | uint32_t ip_src,ip_dst; /* source and dest address */
|
1861 | 718da2b9 | bellard | } ip_header; |
1862 | 718da2b9 | bellard | |
1863 | 718da2b9 | bellard | #define IP_HEADER_VERSION_4 4 |
1864 | 718da2b9 | bellard | #define IP_HEADER_VERSION(ip) ((ip->ip_ver_len >> 4)&0xf) |
1865 | 718da2b9 | bellard | #define IP_HEADER_LENGTH(ip) (((ip->ip_ver_len)&0xf) << 2) |
1866 | 718da2b9 | bellard | |
1867 | 718da2b9 | bellard | typedef struct tcp_header |
1868 | 718da2b9 | bellard | { |
1869 | 718da2b9 | bellard | uint16_t th_sport; /* source port */
|
1870 | 718da2b9 | bellard | uint16_t th_dport; /* destination port */
|
1871 | 718da2b9 | bellard | uint32_t th_seq; /* sequence number */
|
1872 | 718da2b9 | bellard | uint32_t th_ack; /* acknowledgement number */
|
1873 | 718da2b9 | bellard | uint16_t th_offset_flags; /* data offset, reserved 6 bits, TCP protocol flags */
|
1874 | 718da2b9 | bellard | uint16_t th_win; /* window */
|
1875 | 718da2b9 | bellard | uint16_t th_sum; /* checksum */
|
1876 | 718da2b9 | bellard | uint16_t th_urp; /* urgent pointer */
|
1877 | 718da2b9 | bellard | } tcp_header; |
1878 | 718da2b9 | bellard | |
1879 | 718da2b9 | bellard | typedef struct udp_header |
1880 | 718da2b9 | bellard | { |
1881 | 718da2b9 | bellard | uint16_t uh_sport; /* source port */
|
1882 | 718da2b9 | bellard | uint16_t uh_dport; /* destination port */
|
1883 | 718da2b9 | bellard | uint16_t uh_ulen; /* udp length */
|
1884 | 718da2b9 | bellard | uint16_t uh_sum; /* udp checksum */
|
1885 | 718da2b9 | bellard | } udp_header; |
1886 | 718da2b9 | bellard | |
1887 | 718da2b9 | bellard | typedef struct ip_pseudo_header |
1888 | 718da2b9 | bellard | { |
1889 | 718da2b9 | bellard | uint32_t ip_src; |
1890 | 718da2b9 | bellard | uint32_t ip_dst; |
1891 | 718da2b9 | bellard | uint8_t zeros; |
1892 | 718da2b9 | bellard | uint8_t ip_proto; |
1893 | 718da2b9 | bellard | uint16_t ip_payload; |
1894 | 718da2b9 | bellard | } ip_pseudo_header; |
1895 | 718da2b9 | bellard | |
1896 | 718da2b9 | bellard | #define IP_PROTO_TCP 6 |
1897 | 718da2b9 | bellard | #define IP_PROTO_UDP 17 |
1898 | 718da2b9 | bellard | |
1899 | 718da2b9 | bellard | #define TCP_HEADER_DATA_OFFSET(tcp) (((be16_to_cpu(tcp->th_offset_flags) >> 12)&0xf) << 2) |
1900 | 718da2b9 | bellard | #define TCP_FLAGS_ONLY(flags) ((flags)&0x3f) |
1901 | 718da2b9 | bellard | #define TCP_HEADER_FLAGS(tcp) TCP_FLAGS_ONLY(be16_to_cpu(tcp->th_offset_flags))
|
1902 | 718da2b9 | bellard | |
1903 | 718da2b9 | bellard | #define TCP_HEADER_CLEAR_FLAGS(tcp, off) ((tcp)->th_offset_flags &= cpu_to_be16(~TCP_FLAGS_ONLY(off)))
|
1904 | 718da2b9 | bellard | |
1905 | 718da2b9 | bellard | #define TCP_FLAG_FIN 0x01 |
1906 | 718da2b9 | bellard | #define TCP_FLAG_PUSH 0x08 |
1907 | 718da2b9 | bellard | |
1908 | 718da2b9 | bellard | /* produces ones' complement sum of data */
|
1909 | 718da2b9 | bellard | static uint16_t ones_complement_sum(uint8_t *data, size_t len)
|
1910 | 718da2b9 | bellard | { |
1911 | 718da2b9 | bellard | uint32_t result = 0;
|
1912 | 718da2b9 | bellard | |
1913 | 718da2b9 | bellard | for (; len > 1; data+=2, len-=2) |
1914 | 718da2b9 | bellard | { |
1915 | 718da2b9 | bellard | result += *(uint16_t*)data; |
1916 | 718da2b9 | bellard | } |
1917 | 718da2b9 | bellard | |
1918 | 718da2b9 | bellard | /* add the remainder byte */
|
1919 | 718da2b9 | bellard | if (len)
|
1920 | 718da2b9 | bellard | { |
1921 | 718da2b9 | bellard | uint8_t odd[2] = {*data, 0}; |
1922 | 718da2b9 | bellard | result += *(uint16_t*)odd; |
1923 | 718da2b9 | bellard | } |
1924 | 718da2b9 | bellard | |
1925 | 718da2b9 | bellard | while (result>>16) |
1926 | 718da2b9 | bellard | result = (result & 0xffff) + (result >> 16); |
1927 | 718da2b9 | bellard | |
1928 | 718da2b9 | bellard | return result;
|
1929 | 718da2b9 | bellard | } |
1930 | 718da2b9 | bellard | |
1931 | 718da2b9 | bellard | static uint16_t ip_checksum(void *data, size_t len) |
1932 | 718da2b9 | bellard | { |
1933 | 718da2b9 | bellard | return ~ones_complement_sum((uint8_t*)data, len);
|
1934 | 718da2b9 | bellard | } |
1935 | 718da2b9 | bellard | |
1936 | a41b2ff2 | pbrook | static int rtl8139_cplus_transmit_one(RTL8139State *s) |
1937 | a41b2ff2 | pbrook | { |
1938 | a41b2ff2 | pbrook | if (!rtl8139_transmitter_enabled(s))
|
1939 | a41b2ff2 | pbrook | { |
1940 | 7cdeb319 | Benjamin Poirier | DPRINTF("+++ C+ mode: transmitter disabled\n");
|
1941 | a41b2ff2 | pbrook | return 0; |
1942 | a41b2ff2 | pbrook | } |
1943 | a41b2ff2 | pbrook | |
1944 | a41b2ff2 | pbrook | if (!rtl8139_cp_transmitter_enabled(s))
|
1945 | a41b2ff2 | pbrook | { |
1946 | 7cdeb319 | Benjamin Poirier | DPRINTF("+++ C+ mode: C+ transmitter disabled\n");
|
1947 | a41b2ff2 | pbrook | return 0 ; |
1948 | a41b2ff2 | pbrook | } |
1949 | a41b2ff2 | pbrook | |
1950 | a41b2ff2 | pbrook | int descriptor = s->currCPlusTxDesc;
|
1951 | a41b2ff2 | pbrook | |
1952 | 3ada003a | Eduard - Gabriel Munteanu | dma_addr_t cplus_tx_ring_desc = rtl8139_addr64(s->TxAddr[0], s->TxAddr[1]); |
1953 | a41b2ff2 | pbrook | |
1954 | a41b2ff2 | pbrook | /* Normal priority ring */
|
1955 | a41b2ff2 | pbrook | cplus_tx_ring_desc += 16 * descriptor;
|
1956 | a41b2ff2 | pbrook | |
1957 | 7cdeb319 | Benjamin Poirier | DPRINTF("+++ C+ mode reading TX descriptor %d from host memory at "
|
1958 | 4abf12f4 | Julian Pidancet | "%08x %08x = 0x"DMA_ADDR_FMT"\n", descriptor, s->TxAddr[1], |
1959 | 7cdeb319 | Benjamin Poirier | s->TxAddr[0], cplus_tx_ring_desc);
|
1960 | a41b2ff2 | pbrook | |
1961 | a41b2ff2 | pbrook | uint32_t val, txdw0,txdw1,txbufLO,txbufHI; |
1962 | a41b2ff2 | pbrook | |
1963 | 3ada003a | Eduard - Gabriel Munteanu | pci_dma_read(&s->dev, cplus_tx_ring_desc, (uint8_t *)&val, 4);
|
1964 | a41b2ff2 | pbrook | txdw0 = le32_to_cpu(val); |
1965 | 3ada003a | Eduard - Gabriel Munteanu | pci_dma_read(&s->dev, cplus_tx_ring_desc+4, (uint8_t *)&val, 4); |
1966 | a41b2ff2 | pbrook | txdw1 = le32_to_cpu(val); |
1967 | 3ada003a | Eduard - Gabriel Munteanu | pci_dma_read(&s->dev, cplus_tx_ring_desc+8, (uint8_t *)&val, 4); |
1968 | a41b2ff2 | pbrook | txbufLO = le32_to_cpu(val); |
1969 | 3ada003a | Eduard - Gabriel Munteanu | pci_dma_read(&s->dev, cplus_tx_ring_desc+12, (uint8_t *)&val, 4); |
1970 | a41b2ff2 | pbrook | txbufHI = le32_to_cpu(val); |
1971 | a41b2ff2 | pbrook | |
1972 | 7cdeb319 | Benjamin Poirier | DPRINTF("+++ C+ mode TX descriptor %d %08x %08x %08x %08x\n", descriptor,
|
1973 | 7cdeb319 | Benjamin Poirier | txdw0, txdw1, txbufLO, txbufHI); |
1974 | a41b2ff2 | pbrook | |
1975 | a41b2ff2 | pbrook | /* w0 ownership flag */
|
1976 | a41b2ff2 | pbrook | #define CP_TX_OWN (1<<31) |
1977 | a41b2ff2 | pbrook | /* w0 end of ring flag */
|
1978 | a41b2ff2 | pbrook | #define CP_TX_EOR (1<<30) |
1979 | a41b2ff2 | pbrook | /* first segment of received packet flag */
|
1980 | a41b2ff2 | pbrook | #define CP_TX_FS (1<<29) |
1981 | a41b2ff2 | pbrook | /* last segment of received packet flag */
|
1982 | a41b2ff2 | pbrook | #define CP_TX_LS (1<<28) |
1983 | a41b2ff2 | pbrook | /* large send packet flag */
|
1984 | a41b2ff2 | pbrook | #define CP_TX_LGSEN (1<<27) |
1985 | 718da2b9 | bellard | /* large send MSS mask, bits 16...25 */
|
1986 | 718da2b9 | bellard | #define CP_TC_LGSEN_MSS_MASK ((1 << 12) - 1) |
1987 | 718da2b9 | bellard | |
1988 | a41b2ff2 | pbrook | /* IP checksum offload flag */
|
1989 | a41b2ff2 | pbrook | #define CP_TX_IPCS (1<<18) |
1990 | a41b2ff2 | pbrook | /* UDP checksum offload flag */
|
1991 | a41b2ff2 | pbrook | #define CP_TX_UDPCS (1<<17) |
1992 | a41b2ff2 | pbrook | /* TCP checksum offload flag */
|
1993 | a41b2ff2 | pbrook | #define CP_TX_TCPCS (1<<16) |
1994 | a41b2ff2 | pbrook | |
1995 | a41b2ff2 | pbrook | /* w0 bits 0...15 : buffer size */
|
1996 | a41b2ff2 | pbrook | #define CP_TX_BUFFER_SIZE (1<<16) |
1997 | a41b2ff2 | pbrook | #define CP_TX_BUFFER_SIZE_MASK (CP_TX_BUFFER_SIZE - 1) |
1998 | bf6b87a8 | Benjamin Poirier | /* w1 add tag flag */
|
1999 | bf6b87a8 | Benjamin Poirier | #define CP_TX_TAGC (1<<17) |
2000 | bf6b87a8 | Benjamin Poirier | /* w1 bits 0...15 : VLAN tag (big endian) */
|
2001 | a41b2ff2 | pbrook | #define CP_TX_VLAN_TAG_MASK ((1<<16) - 1) |
2002 | a41b2ff2 | pbrook | /* w2 low 32bit of Rx buffer ptr */
|
2003 | a41b2ff2 | pbrook | /* w3 high 32bit of Rx buffer ptr */
|
2004 | a41b2ff2 | pbrook | |
2005 | a41b2ff2 | pbrook | /* set after transmission */
|
2006 | a41b2ff2 | pbrook | /* FIFO underrun flag */
|
2007 | a41b2ff2 | pbrook | #define CP_TX_STATUS_UNF (1<<25) |
2008 | a41b2ff2 | pbrook | /* transmit error summary flag, valid if set any of three below */
|
2009 | a41b2ff2 | pbrook | #define CP_TX_STATUS_TES (1<<23) |
2010 | a41b2ff2 | pbrook | /* out-of-window collision flag */
|
2011 | a41b2ff2 | pbrook | #define CP_TX_STATUS_OWC (1<<22) |
2012 | a41b2ff2 | pbrook | /* link failure flag */
|
2013 | a41b2ff2 | pbrook | #define CP_TX_STATUS_LNKF (1<<21) |
2014 | a41b2ff2 | pbrook | /* excessive collisions flag */
|
2015 | a41b2ff2 | pbrook | #define CP_TX_STATUS_EXC (1<<20) |
2016 | a41b2ff2 | pbrook | |
2017 | a41b2ff2 | pbrook | if (!(txdw0 & CP_TX_OWN))
|
2018 | a41b2ff2 | pbrook | { |
2019 | 7cdeb319 | Benjamin Poirier | DPRINTF("C+ Tx mode : descriptor %d is owned by host\n", descriptor);
|
2020 | a41b2ff2 | pbrook | return 0 ; |
2021 | a41b2ff2 | pbrook | } |
2022 | a41b2ff2 | pbrook | |
2023 | 7cdeb319 | Benjamin Poirier | DPRINTF("+++ C+ Tx mode : transmitting from descriptor %d\n", descriptor);
|
2024 | 6cadb320 | bellard | |
2025 | 6cadb320 | bellard | if (txdw0 & CP_TX_FS)
|
2026 | 6cadb320 | bellard | { |
2027 | 7cdeb319 | Benjamin Poirier | DPRINTF("+++ C+ Tx mode : descriptor %d is first segment "
|
2028 | 7cdeb319 | Benjamin Poirier | "descriptor\n", descriptor);
|
2029 | 6cadb320 | bellard | |
2030 | 6cadb320 | bellard | /* reset internal buffer offset */
|
2031 | 6cadb320 | bellard | s->cplus_txbuffer_offset = 0;
|
2032 | 6cadb320 | bellard | } |
2033 | a41b2ff2 | pbrook | |
2034 | a41b2ff2 | pbrook | int txsize = txdw0 & CP_TX_BUFFER_SIZE_MASK;
|
2035 | 3ada003a | Eduard - Gabriel Munteanu | dma_addr_t tx_addr = rtl8139_addr64(txbufLO, txbufHI); |
2036 | a41b2ff2 | pbrook | |
2037 | 6cadb320 | bellard | /* make sure we have enough space to assemble the packet */
|
2038 | 6cadb320 | bellard | if (!s->cplus_txbuffer)
|
2039 | 6cadb320 | bellard | { |
2040 | 6cadb320 | bellard | s->cplus_txbuffer_len = CP_TX_BUFFER_SIZE; |
2041 | 7267c094 | Anthony Liguori | s->cplus_txbuffer = g_malloc(s->cplus_txbuffer_len); |
2042 | 6cadb320 | bellard | s->cplus_txbuffer_offset = 0;
|
2043 | 718da2b9 | bellard | |
2044 | 7cdeb319 | Benjamin Poirier | DPRINTF("+++ C+ mode transmission buffer allocated space %d\n",
|
2045 | 7cdeb319 | Benjamin Poirier | s->cplus_txbuffer_len); |
2046 | 6cadb320 | bellard | } |
2047 | 6cadb320 | bellard | |
2048 | cde31a0e | Jason Wang | if (s->cplus_txbuffer_offset + txsize >= s->cplus_txbuffer_len)
|
2049 | 6cadb320 | bellard | { |
2050 | cde31a0e | Jason Wang | /* The spec didn't tell the maximum size, stick to CP_TX_BUFFER_SIZE */
|
2051 | cde31a0e | Jason Wang | txsize = s->cplus_txbuffer_len - s->cplus_txbuffer_offset; |
2052 | cde31a0e | Jason Wang | DPRINTF("+++ C+ mode transmission buffer overrun, truncated descriptor"
|
2053 | cde31a0e | Jason Wang | "length to %d\n", txsize);
|
2054 | 6cadb320 | bellard | } |
2055 | 6cadb320 | bellard | |
2056 | 6cadb320 | bellard | if (!s->cplus_txbuffer)
|
2057 | 6cadb320 | bellard | { |
2058 | 6cadb320 | bellard | /* out of memory */
|
2059 | a41b2ff2 | pbrook | |
2060 | 7cdeb319 | Benjamin Poirier | DPRINTF("+++ C+ mode transmiter failed to reallocate %d bytes\n",
|
2061 | 7cdeb319 | Benjamin Poirier | s->cplus_txbuffer_len); |
2062 | 6cadb320 | bellard | |
2063 | 6cadb320 | bellard | /* update tally counter */
|
2064 | 6cadb320 | bellard | ++s->tally_counters.TxERR; |
2065 | 6cadb320 | bellard | ++s->tally_counters.TxAbt; |
2066 | 6cadb320 | bellard | |
2067 | 6cadb320 | bellard | return 0; |
2068 | 6cadb320 | bellard | } |
2069 | 6cadb320 | bellard | |
2070 | 6cadb320 | bellard | /* append more data to the packet */
|
2071 | 6cadb320 | bellard | |
2072 | 7cdeb319 | Benjamin Poirier | DPRINTF("+++ C+ mode transmit reading %d bytes from host memory at "
|
2073 | 3ada003a | Eduard - Gabriel Munteanu | DMA_ADDR_FMT" to offset %d\n", txsize, tx_addr,
|
2074 | 3ada003a | Eduard - Gabriel Munteanu | s->cplus_txbuffer_offset); |
2075 | 6cadb320 | bellard | |
2076 | 3ada003a | Eduard - Gabriel Munteanu | pci_dma_read(&s->dev, tx_addr, |
2077 | 3ada003a | Eduard - Gabriel Munteanu | s->cplus_txbuffer + s->cplus_txbuffer_offset, txsize); |
2078 | 6cadb320 | bellard | s->cplus_txbuffer_offset += txsize; |
2079 | 6cadb320 | bellard | |
2080 | 6cadb320 | bellard | /* seek to next Rx descriptor */
|
2081 | 6cadb320 | bellard | if (txdw0 & CP_TX_EOR)
|
2082 | 6cadb320 | bellard | { |
2083 | 6cadb320 | bellard | s->currCPlusTxDesc = 0;
|
2084 | 6cadb320 | bellard | } |
2085 | 6cadb320 | bellard | else
|
2086 | 6cadb320 | bellard | { |
2087 | 6cadb320 | bellard | ++s->currCPlusTxDesc; |
2088 | 6cadb320 | bellard | if (s->currCPlusTxDesc >= 64) |
2089 | 6cadb320 | bellard | s->currCPlusTxDesc = 0;
|
2090 | 6cadb320 | bellard | } |
2091 | a41b2ff2 | pbrook | |
2092 | a41b2ff2 | pbrook | /* transfer ownership to target */
|
2093 | a41b2ff2 | pbrook | txdw0 &= ~CP_RX_OWN; |
2094 | a41b2ff2 | pbrook | |
2095 | a41b2ff2 | pbrook | /* reset error indicator bits */
|
2096 | a41b2ff2 | pbrook | txdw0 &= ~CP_TX_STATUS_UNF; |
2097 | a41b2ff2 | pbrook | txdw0 &= ~CP_TX_STATUS_TES; |
2098 | a41b2ff2 | pbrook | txdw0 &= ~CP_TX_STATUS_OWC; |
2099 | a41b2ff2 | pbrook | txdw0 &= ~CP_TX_STATUS_LNKF; |
2100 | a41b2ff2 | pbrook | txdw0 &= ~CP_TX_STATUS_EXC; |
2101 | a41b2ff2 | pbrook | |
2102 | a41b2ff2 | pbrook | /* update ring data */
|
2103 | a41b2ff2 | pbrook | val = cpu_to_le32(txdw0); |
2104 | 3ada003a | Eduard - Gabriel Munteanu | pci_dma_write(&s->dev, cplus_tx_ring_desc, (uint8_t *)&val, 4);
|
2105 | a41b2ff2 | pbrook | |
2106 | 6cadb320 | bellard | /* Now decide if descriptor being processed is holding the last segment of packet */
|
2107 | 6cadb320 | bellard | if (txdw0 & CP_TX_LS)
|
2108 | a41b2ff2 | pbrook | { |
2109 | bf6b87a8 | Benjamin Poirier | uint8_t dot1q_buffer_space[VLAN_HLEN]; |
2110 | bf6b87a8 | Benjamin Poirier | uint16_t *dot1q_buffer; |
2111 | bf6b87a8 | Benjamin Poirier | |
2112 | 7cdeb319 | Benjamin Poirier | DPRINTF("+++ C+ Tx mode : descriptor %d is last segment descriptor\n",
|
2113 | 7cdeb319 | Benjamin Poirier | descriptor); |
2114 | 6cadb320 | bellard | |
2115 | 6cadb320 | bellard | /* can transfer fully assembled packet */
|
2116 | 6cadb320 | bellard | |
2117 | 6cadb320 | bellard | uint8_t *saved_buffer = s->cplus_txbuffer; |
2118 | 6cadb320 | bellard | int saved_size = s->cplus_txbuffer_offset;
|
2119 | 6cadb320 | bellard | int saved_buffer_len = s->cplus_txbuffer_len;
|
2120 | 6cadb320 | bellard | |
2121 | bf6b87a8 | Benjamin Poirier | /* create vlan tag */
|
2122 | bf6b87a8 | Benjamin Poirier | if (txdw1 & CP_TX_TAGC) {
|
2123 | bf6b87a8 | Benjamin Poirier | /* the vlan tag is in BE byte order in the descriptor
|
2124 | bf6b87a8 | Benjamin Poirier | * BE + le_to_cpu() + ~swap()~ = cpu */
|
2125 | 7cdeb319 | Benjamin Poirier | DPRINTF("+++ C+ Tx mode : inserting vlan tag with ""tci: %u\n", |
2126 | 7cdeb319 | Benjamin Poirier | bswap16(txdw1 & CP_TX_VLAN_TAG_MASK)); |
2127 | bf6b87a8 | Benjamin Poirier | |
2128 | bf6b87a8 | Benjamin Poirier | dot1q_buffer = (uint16_t *) dot1q_buffer_space; |
2129 | bf6b87a8 | Benjamin Poirier | dot1q_buffer[0] = cpu_to_be16(ETH_P_8021Q);
|
2130 | bf6b87a8 | Benjamin Poirier | /* BE + le_to_cpu() + ~cpu_to_le()~ = BE */
|
2131 | bf6b87a8 | Benjamin Poirier | dot1q_buffer[1] = cpu_to_le16(txdw1 & CP_TX_VLAN_TAG_MASK);
|
2132 | bf6b87a8 | Benjamin Poirier | } else {
|
2133 | bf6b87a8 | Benjamin Poirier | dot1q_buffer = NULL;
|
2134 | bf6b87a8 | Benjamin Poirier | } |
2135 | bf6b87a8 | Benjamin Poirier | |
2136 | 6cadb320 | bellard | /* reset the card space to protect from recursive call */
|
2137 | 6cadb320 | bellard | s->cplus_txbuffer = NULL;
|
2138 | 6cadb320 | bellard | s->cplus_txbuffer_offset = 0;
|
2139 | 6cadb320 | bellard | s->cplus_txbuffer_len = 0;
|
2140 | 6cadb320 | bellard | |
2141 | 718da2b9 | bellard | if (txdw0 & (CP_TX_IPCS | CP_TX_UDPCS | CP_TX_TCPCS | CP_TX_LGSEN))
|
2142 | 6cadb320 | bellard | { |
2143 | 7cdeb319 | Benjamin Poirier | DPRINTF("+++ C+ mode offloaded task checksum\n");
|
2144 | 6cadb320 | bellard | |
2145 | 6cadb320 | bellard | /* ip packet header */
|
2146 | 660f11be | Blue Swirl | ip_header *ip = NULL;
|
2147 | 6cadb320 | bellard | int hlen = 0; |
2148 | 718da2b9 | bellard | uint8_t ip_protocol = 0;
|
2149 | 718da2b9 | bellard | uint16_t ip_data_len = 0;
|
2150 | 6cadb320 | bellard | |
2151 | 660f11be | Blue Swirl | uint8_t *eth_payload_data = NULL;
|
2152 | 718da2b9 | bellard | size_t eth_payload_len = 0;
|
2153 | 6cadb320 | bellard | |
2154 | 718da2b9 | bellard | int proto = be16_to_cpu(*(uint16_t *)(saved_buffer + 12)); |
2155 | 6cadb320 | bellard | if (proto == ETH_P_IP)
|
2156 | 6cadb320 | bellard | { |
2157 | 7cdeb319 | Benjamin Poirier | DPRINTF("+++ C+ mode has IP packet\n");
|
2158 | 6cadb320 | bellard | |
2159 | 6cadb320 | bellard | /* not aligned */
|
2160 | 718da2b9 | bellard | eth_payload_data = saved_buffer + ETH_HLEN; |
2161 | 718da2b9 | bellard | eth_payload_len = saved_size - ETH_HLEN; |
2162 | 6cadb320 | bellard | |
2163 | 718da2b9 | bellard | ip = (ip_header*)eth_payload_data; |
2164 | 6cadb320 | bellard | |
2165 | 718da2b9 | bellard | if (IP_HEADER_VERSION(ip) != IP_HEADER_VERSION_4) {
|
2166 | 7cdeb319 | Benjamin Poirier | DPRINTF("+++ C+ mode packet has bad IP version %d "
|
2167 | 7cdeb319 | Benjamin Poirier | "expected %d\n", IP_HEADER_VERSION(ip),
|
2168 | 7cdeb319 | Benjamin Poirier | IP_HEADER_VERSION_4); |
2169 | 6cadb320 | bellard | ip = NULL;
|
2170 | 6cadb320 | bellard | } else {
|
2171 | 718da2b9 | bellard | hlen = IP_HEADER_LENGTH(ip); |
2172 | 718da2b9 | bellard | ip_protocol = ip->ip_p; |
2173 | 718da2b9 | bellard | ip_data_len = be16_to_cpu(ip->ip_len) - hlen; |
2174 | 6cadb320 | bellard | } |
2175 | 6cadb320 | bellard | } |
2176 | 6cadb320 | bellard | |
2177 | 6cadb320 | bellard | if (ip)
|
2178 | 6cadb320 | bellard | { |
2179 | 6cadb320 | bellard | if (txdw0 & CP_TX_IPCS)
|
2180 | 6cadb320 | bellard | { |
2181 | 7cdeb319 | Benjamin Poirier | DPRINTF("+++ C+ mode need IP checksum\n");
|
2182 | 6cadb320 | bellard | |
2183 | 718da2b9 | bellard | if (hlen<sizeof(ip_header) || hlen>eth_payload_len) {/* min header length */ |
2184 | 6cadb320 | bellard | /* bad packet header len */
|
2185 | 6cadb320 | bellard | /* or packet too short */
|
2186 | 6cadb320 | bellard | } |
2187 | 6cadb320 | bellard | else
|
2188 | 6cadb320 | bellard | { |
2189 | 6cadb320 | bellard | ip->ip_sum = 0;
|
2190 | 718da2b9 | bellard | ip->ip_sum = ip_checksum(ip, hlen); |
2191 | 7cdeb319 | Benjamin Poirier | DPRINTF("+++ C+ mode IP header len=%d checksum=%04x\n",
|
2192 | 7cdeb319 | Benjamin Poirier | hlen, ip->ip_sum); |
2193 | 6cadb320 | bellard | } |
2194 | 6cadb320 | bellard | } |
2195 | 6cadb320 | bellard | |
2196 | 718da2b9 | bellard | if ((txdw0 & CP_TX_LGSEN) && ip_protocol == IP_PROTO_TCP)
|
2197 | 6cadb320 | bellard | { |
2198 | 718da2b9 | bellard | int large_send_mss = (txdw0 >> 16) & CP_TC_LGSEN_MSS_MASK; |
2199 | ec48c774 | Benjamin Poirier | |
2200 | 7cdeb319 | Benjamin Poirier | DPRINTF("+++ C+ mode offloaded task TSO MTU=%d IP data %d "
|
2201 | 7cdeb319 | Benjamin Poirier | "frame data %d specified MSS=%d\n", ETH_MTU,
|
2202 | 7cdeb319 | Benjamin Poirier | ip_data_len, saved_size - ETH_HLEN, large_send_mss); |
2203 | 6cadb320 | bellard | |
2204 | 718da2b9 | bellard | int tcp_send_offset = 0; |
2205 | 718da2b9 | bellard | int send_count = 0; |
2206 | 6cadb320 | bellard | |
2207 | 6cadb320 | bellard | /* maximum IP header length is 60 bytes */
|
2208 | 6cadb320 | bellard | uint8_t saved_ip_header[60];
|
2209 | 6cadb320 | bellard | |
2210 | 718da2b9 | bellard | /* save IP header template; data area is used in tcp checksum calculation */
|
2211 | 718da2b9 | bellard | memcpy(saved_ip_header, eth_payload_data, hlen); |
2212 | 718da2b9 | bellard | |
2213 | 718da2b9 | bellard | /* a placeholder for checksum calculation routine in tcp case */
|
2214 | 718da2b9 | bellard | uint8_t *data_to_checksum = eth_payload_data + hlen - 12;
|
2215 | 718da2b9 | bellard | // size_t data_to_checksum_len = eth_payload_len - hlen + 12;
|
2216 | 718da2b9 | bellard | |
2217 | 718da2b9 | bellard | /* pointer to TCP header */
|
2218 | 718da2b9 | bellard | tcp_header *p_tcp_hdr = (tcp_header*)(eth_payload_data + hlen); |
2219 | 718da2b9 | bellard | |
2220 | 718da2b9 | bellard | int tcp_hlen = TCP_HEADER_DATA_OFFSET(p_tcp_hdr);
|
2221 | 718da2b9 | bellard | |
2222 | 718da2b9 | bellard | /* ETH_MTU = ip header len + tcp header len + payload */
|
2223 | 718da2b9 | bellard | int tcp_data_len = ip_data_len - tcp_hlen;
|
2224 | 718da2b9 | bellard | int tcp_chunk_size = ETH_MTU - hlen - tcp_hlen;
|
2225 | 718da2b9 | bellard | |
2226 | 7cdeb319 | Benjamin Poirier | DPRINTF("+++ C+ mode TSO IP data len %d TCP hlen %d TCP "
|
2227 | 7cdeb319 | Benjamin Poirier | "data len %d TCP chunk size %d\n", ip_data_len,
|
2228 | 7cdeb319 | Benjamin Poirier | tcp_hlen, tcp_data_len, tcp_chunk_size); |
2229 | 718da2b9 | bellard | |
2230 | 718da2b9 | bellard | /* note the cycle below overwrites IP header data,
|
2231 | 718da2b9 | bellard | but restores it from saved_ip_header before sending packet */
|
2232 | 718da2b9 | bellard | |
2233 | 718da2b9 | bellard | int is_last_frame = 0; |
2234 | 718da2b9 | bellard | |
2235 | 718da2b9 | bellard | for (tcp_send_offset = 0; tcp_send_offset < tcp_data_len; tcp_send_offset += tcp_chunk_size) |
2236 | 718da2b9 | bellard | { |
2237 | 718da2b9 | bellard | uint16_t chunk_size = tcp_chunk_size; |
2238 | 718da2b9 | bellard | |
2239 | 718da2b9 | bellard | /* check if this is the last frame */
|
2240 | 718da2b9 | bellard | if (tcp_send_offset + tcp_chunk_size >= tcp_data_len)
|
2241 | 718da2b9 | bellard | { |
2242 | 718da2b9 | bellard | is_last_frame = 1;
|
2243 | 718da2b9 | bellard | chunk_size = tcp_data_len - tcp_send_offset; |
2244 | 718da2b9 | bellard | } |
2245 | 718da2b9 | bellard | |
2246 | 7cdeb319 | Benjamin Poirier | DPRINTF("+++ C+ mode TSO TCP seqno %08x\n",
|
2247 | 7cdeb319 | Benjamin Poirier | be32_to_cpu(p_tcp_hdr->th_seq)); |
2248 | 718da2b9 | bellard | |
2249 | 718da2b9 | bellard | /* add 4 TCP pseudoheader fields */
|
2250 | 718da2b9 | bellard | /* copy IP source and destination fields */
|
2251 | 718da2b9 | bellard | memcpy(data_to_checksum, saved_ip_header + 12, 8); |
2252 | 718da2b9 | bellard | |
2253 | 7cdeb319 | Benjamin Poirier | DPRINTF("+++ C+ mode TSO calculating TCP checksum for "
|
2254 | 7cdeb319 | Benjamin Poirier | "packet with %d bytes data\n", tcp_hlen +
|
2255 | 7cdeb319 | Benjamin Poirier | chunk_size); |
2256 | 718da2b9 | bellard | |
2257 | 718da2b9 | bellard | if (tcp_send_offset)
|
2258 | 718da2b9 | bellard | { |
2259 | 718da2b9 | bellard | memcpy((uint8_t*)p_tcp_hdr + tcp_hlen, (uint8_t*)p_tcp_hdr + tcp_hlen + tcp_send_offset, chunk_size); |
2260 | 718da2b9 | bellard | } |
2261 | 718da2b9 | bellard | |
2262 | 718da2b9 | bellard | /* keep PUSH and FIN flags only for the last frame */
|
2263 | 718da2b9 | bellard | if (!is_last_frame)
|
2264 | 718da2b9 | bellard | { |
2265 | 718da2b9 | bellard | TCP_HEADER_CLEAR_FLAGS(p_tcp_hdr, TCP_FLAG_PUSH|TCP_FLAG_FIN); |
2266 | 718da2b9 | bellard | } |
2267 | 6cadb320 | bellard | |
2268 | 718da2b9 | bellard | /* recalculate TCP checksum */
|
2269 | 718da2b9 | bellard | ip_pseudo_header *p_tcpip_hdr = (ip_pseudo_header *)data_to_checksum; |
2270 | 718da2b9 | bellard | p_tcpip_hdr->zeros = 0;
|
2271 | 718da2b9 | bellard | p_tcpip_hdr->ip_proto = IP_PROTO_TCP; |
2272 | 718da2b9 | bellard | p_tcpip_hdr->ip_payload = cpu_to_be16(tcp_hlen + chunk_size); |
2273 | 718da2b9 | bellard | |
2274 | 718da2b9 | bellard | p_tcp_hdr->th_sum = 0;
|
2275 | 718da2b9 | bellard | |
2276 | 718da2b9 | bellard | int tcp_checksum = ip_checksum(data_to_checksum, tcp_hlen + chunk_size + 12); |
2277 | 7cdeb319 | Benjamin Poirier | DPRINTF("+++ C+ mode TSO TCP checksum %04x\n",
|
2278 | 7cdeb319 | Benjamin Poirier | tcp_checksum); |
2279 | 718da2b9 | bellard | |
2280 | 718da2b9 | bellard | p_tcp_hdr->th_sum = tcp_checksum; |
2281 | 718da2b9 | bellard | |
2282 | 718da2b9 | bellard | /* restore IP header */
|
2283 | 718da2b9 | bellard | memcpy(eth_payload_data, saved_ip_header, hlen); |
2284 | 718da2b9 | bellard | |
2285 | 718da2b9 | bellard | /* set IP data length and recalculate IP checksum */
|
2286 | 718da2b9 | bellard | ip->ip_len = cpu_to_be16(hlen + tcp_hlen + chunk_size); |
2287 | 718da2b9 | bellard | |
2288 | 718da2b9 | bellard | /* increment IP id for subsequent frames */
|
2289 | 718da2b9 | bellard | ip->ip_id = cpu_to_be16(tcp_send_offset/tcp_chunk_size + be16_to_cpu(ip->ip_id)); |
2290 | 718da2b9 | bellard | |
2291 | 718da2b9 | bellard | ip->ip_sum = 0;
|
2292 | 718da2b9 | bellard | ip->ip_sum = ip_checksum(eth_payload_data, hlen); |
2293 | 7cdeb319 | Benjamin Poirier | DPRINTF("+++ C+ mode TSO IP header len=%d "
|
2294 | 7cdeb319 | Benjamin Poirier | "checksum=%04x\n", hlen, ip->ip_sum);
|
2295 | 718da2b9 | bellard | |
2296 | 718da2b9 | bellard | int tso_send_size = ETH_HLEN + hlen + tcp_hlen + chunk_size;
|
2297 | 7cdeb319 | Benjamin Poirier | DPRINTF("+++ C+ mode TSO transferring packet size "
|
2298 | 7cdeb319 | Benjamin Poirier | "%d\n", tso_send_size);
|
2299 | bf6b87a8 | Benjamin Poirier | rtl8139_transfer_frame(s, saved_buffer, tso_send_size, |
2300 | bf6b87a8 | Benjamin Poirier | 0, (uint8_t *) dot1q_buffer);
|
2301 | 718da2b9 | bellard | |
2302 | 718da2b9 | bellard | /* add transferred count to TCP sequence number */
|
2303 | 718da2b9 | bellard | p_tcp_hdr->th_seq = cpu_to_be32(chunk_size + be32_to_cpu(p_tcp_hdr->th_seq)); |
2304 | 718da2b9 | bellard | ++send_count; |
2305 | 718da2b9 | bellard | } |
2306 | 718da2b9 | bellard | |
2307 | 718da2b9 | bellard | /* Stop sending this frame */
|
2308 | 718da2b9 | bellard | saved_size = 0;
|
2309 | 718da2b9 | bellard | } |
2310 | 718da2b9 | bellard | else if (txdw0 & (CP_TX_TCPCS|CP_TX_UDPCS)) |
2311 | 718da2b9 | bellard | { |
2312 | 7cdeb319 | Benjamin Poirier | DPRINTF("+++ C+ mode need TCP or UDP checksum\n");
|
2313 | 718da2b9 | bellard | |
2314 | 718da2b9 | bellard | /* maximum IP header length is 60 bytes */
|
2315 | 718da2b9 | bellard | uint8_t saved_ip_header[60];
|
2316 | 718da2b9 | bellard | memcpy(saved_ip_header, eth_payload_data, hlen); |
2317 | 718da2b9 | bellard | |
2318 | 718da2b9 | bellard | uint8_t *data_to_checksum = eth_payload_data + hlen - 12;
|
2319 | 718da2b9 | bellard | // size_t data_to_checksum_len = eth_payload_len - hlen + 12;
|
2320 | 6cadb320 | bellard | |
2321 | 6cadb320 | bellard | /* add 4 TCP pseudoheader fields */
|
2322 | 6cadb320 | bellard | /* copy IP source and destination fields */
|
2323 | 718da2b9 | bellard | memcpy(data_to_checksum, saved_ip_header + 12, 8); |
2324 | 6cadb320 | bellard | |
2325 | 718da2b9 | bellard | if ((txdw0 & CP_TX_TCPCS) && ip_protocol == IP_PROTO_TCP)
|
2326 | 6cadb320 | bellard | { |
2327 | 7cdeb319 | Benjamin Poirier | DPRINTF("+++ C+ mode calculating TCP checksum for "
|
2328 | 7cdeb319 | Benjamin Poirier | "packet with %d bytes data\n", ip_data_len);
|
2329 | 6cadb320 | bellard | |
2330 | 718da2b9 | bellard | ip_pseudo_header *p_tcpip_hdr = (ip_pseudo_header *)data_to_checksum; |
2331 | 718da2b9 | bellard | p_tcpip_hdr->zeros = 0;
|
2332 | 718da2b9 | bellard | p_tcpip_hdr->ip_proto = IP_PROTO_TCP; |
2333 | 718da2b9 | bellard | p_tcpip_hdr->ip_payload = cpu_to_be16(ip_data_len); |
2334 | 6cadb320 | bellard | |
2335 | 718da2b9 | bellard | tcp_header* p_tcp_hdr = (tcp_header *) (data_to_checksum+12);
|
2336 | 6cadb320 | bellard | |
2337 | 6cadb320 | bellard | p_tcp_hdr->th_sum = 0;
|
2338 | 6cadb320 | bellard | |
2339 | 718da2b9 | bellard | int tcp_checksum = ip_checksum(data_to_checksum, ip_data_len + 12); |
2340 | 7cdeb319 | Benjamin Poirier | DPRINTF("+++ C+ mode TCP checksum %04x\n",
|
2341 | 7cdeb319 | Benjamin Poirier | tcp_checksum); |
2342 | 6cadb320 | bellard | |
2343 | 6cadb320 | bellard | p_tcp_hdr->th_sum = tcp_checksum; |
2344 | 6cadb320 | bellard | } |
2345 | 718da2b9 | bellard | else if ((txdw0 & CP_TX_UDPCS) && ip_protocol == IP_PROTO_UDP) |
2346 | 6cadb320 | bellard | { |
2347 | 7cdeb319 | Benjamin Poirier | DPRINTF("+++ C+ mode calculating UDP checksum for "
|
2348 | 7cdeb319 | Benjamin Poirier | "packet with %d bytes data\n", ip_data_len);
|
2349 | 6cadb320 | bellard | |
2350 | 718da2b9 | bellard | ip_pseudo_header *p_udpip_hdr = (ip_pseudo_header *)data_to_checksum; |
2351 | 718da2b9 | bellard | p_udpip_hdr->zeros = 0;
|
2352 | 718da2b9 | bellard | p_udpip_hdr->ip_proto = IP_PROTO_UDP; |
2353 | 718da2b9 | bellard | p_udpip_hdr->ip_payload = cpu_to_be16(ip_data_len); |
2354 | 6cadb320 | bellard | |
2355 | 718da2b9 | bellard | udp_header *p_udp_hdr = (udp_header *) (data_to_checksum+12);
|
2356 | 6cadb320 | bellard | |
2357 | 6cadb320 | bellard | p_udp_hdr->uh_sum = 0;
|
2358 | 6cadb320 | bellard | |
2359 | 718da2b9 | bellard | int udp_checksum = ip_checksum(data_to_checksum, ip_data_len + 12); |
2360 | 7cdeb319 | Benjamin Poirier | DPRINTF("+++ C+ mode UDP checksum %04x\n",
|
2361 | 7cdeb319 | Benjamin Poirier | udp_checksum); |
2362 | 6cadb320 | bellard | |
2363 | 6cadb320 | bellard | p_udp_hdr->uh_sum = udp_checksum; |
2364 | 6cadb320 | bellard | } |
2365 | 6cadb320 | bellard | |
2366 | 6cadb320 | bellard | /* restore IP header */
|
2367 | 718da2b9 | bellard | memcpy(eth_payload_data, saved_ip_header, hlen); |
2368 | 6cadb320 | bellard | } |
2369 | 6cadb320 | bellard | } |
2370 | 6cadb320 | bellard | } |
2371 | 6cadb320 | bellard | |
2372 | 6cadb320 | bellard | /* update tally counter */
|
2373 | 6cadb320 | bellard | ++s->tally_counters.TxOk; |
2374 | 6cadb320 | bellard | |
2375 | 7cdeb319 | Benjamin Poirier | DPRINTF("+++ C+ mode transmitting %d bytes packet\n", saved_size);
|
2376 | 6cadb320 | bellard | |
2377 | bf6b87a8 | Benjamin Poirier | rtl8139_transfer_frame(s, saved_buffer, saved_size, 1,
|
2378 | bf6b87a8 | Benjamin Poirier | (uint8_t *) dot1q_buffer); |
2379 | 6cadb320 | bellard | |
2380 | 6cadb320 | bellard | /* restore card space if there was no recursion and reset offset */
|
2381 | 6cadb320 | bellard | if (!s->cplus_txbuffer)
|
2382 | 6cadb320 | bellard | { |
2383 | 6cadb320 | bellard | s->cplus_txbuffer = saved_buffer; |
2384 | 6cadb320 | bellard | s->cplus_txbuffer_len = saved_buffer_len; |
2385 | 6cadb320 | bellard | s->cplus_txbuffer_offset = 0;
|
2386 | 6cadb320 | bellard | } |
2387 | 6cadb320 | bellard | else
|
2388 | 6cadb320 | bellard | { |
2389 | 7267c094 | Anthony Liguori | g_free(saved_buffer); |
2390 | 6cadb320 | bellard | } |
2391 | a41b2ff2 | pbrook | } |
2392 | a41b2ff2 | pbrook | else
|
2393 | a41b2ff2 | pbrook | { |
2394 | 7cdeb319 | Benjamin Poirier | DPRINTF("+++ C+ mode transmission continue to next descriptor\n");
|
2395 | a41b2ff2 | pbrook | } |
2396 | a41b2ff2 | pbrook | |
2397 | a41b2ff2 | pbrook | return 1; |
2398 | a41b2ff2 | pbrook | } |
2399 | a41b2ff2 | pbrook | |
2400 | a41b2ff2 | pbrook | static void rtl8139_cplus_transmit(RTL8139State *s) |
2401 | a41b2ff2 | pbrook | { |
2402 | a41b2ff2 | pbrook | int txcount = 0; |
2403 | a41b2ff2 | pbrook | |
2404 | a41b2ff2 | pbrook | while (rtl8139_cplus_transmit_one(s))
|
2405 | a41b2ff2 | pbrook | { |
2406 | a41b2ff2 | pbrook | ++txcount; |
2407 | a41b2ff2 | pbrook | } |
2408 | a41b2ff2 | pbrook | |
2409 | a41b2ff2 | pbrook | /* Mark transfer completed */
|
2410 | a41b2ff2 | pbrook | if (!txcount)
|
2411 | a41b2ff2 | pbrook | { |
2412 | 7cdeb319 | Benjamin Poirier | DPRINTF("C+ mode : transmitter queue stalled, current TxDesc = %d\n",
|
2413 | 7cdeb319 | Benjamin Poirier | s->currCPlusTxDesc); |
2414 | a41b2ff2 | pbrook | } |
2415 | a41b2ff2 | pbrook | else
|
2416 | a41b2ff2 | pbrook | { |
2417 | a41b2ff2 | pbrook | /* update interrupt status */
|
2418 | a41b2ff2 | pbrook | s->IntrStatus |= TxOK; |
2419 | a41b2ff2 | pbrook | rtl8139_update_irq(s); |
2420 | a41b2ff2 | pbrook | } |
2421 | a41b2ff2 | pbrook | } |
2422 | a41b2ff2 | pbrook | |
2423 | a41b2ff2 | pbrook | static void rtl8139_transmit(RTL8139State *s) |
2424 | a41b2ff2 | pbrook | { |
2425 | a41b2ff2 | pbrook | int descriptor = s->currTxDesc, txcount = 0; |
2426 | a41b2ff2 | pbrook | |
2427 | a41b2ff2 | pbrook | /*while*/
|
2428 | a41b2ff2 | pbrook | if (rtl8139_transmit_one(s, descriptor))
|
2429 | a41b2ff2 | pbrook | { |
2430 | a41b2ff2 | pbrook | ++s->currTxDesc; |
2431 | a41b2ff2 | pbrook | s->currTxDesc %= 4;
|
2432 | a41b2ff2 | pbrook | ++txcount; |
2433 | a41b2ff2 | pbrook | } |
2434 | a41b2ff2 | pbrook | |
2435 | a41b2ff2 | pbrook | /* Mark transfer completed */
|
2436 | a41b2ff2 | pbrook | if (!txcount)
|
2437 | a41b2ff2 | pbrook | { |
2438 | 7cdeb319 | Benjamin Poirier | DPRINTF("transmitter queue stalled, current TxDesc = %d\n",
|
2439 | 7cdeb319 | Benjamin Poirier | s->currTxDesc); |
2440 | a41b2ff2 | pbrook | } |
2441 | a41b2ff2 | pbrook | } |
2442 | a41b2ff2 | pbrook | |
2443 | a41b2ff2 | pbrook | static void rtl8139_TxStatus_write(RTL8139State *s, uint32_t txRegOffset, uint32_t val) |
2444 | a41b2ff2 | pbrook | { |
2445 | a41b2ff2 | pbrook | |
2446 | a41b2ff2 | pbrook | int descriptor = txRegOffset/4; |
2447 | 6cadb320 | bellard | |
2448 | 6cadb320 | bellard | /* handle C+ transmit mode register configuration */
|
2449 | 6cadb320 | bellard | |
2450 | 2c3891ab | aliguori | if (s->cplus_enabled)
|
2451 | 6cadb320 | bellard | { |
2452 | 7cdeb319 | Benjamin Poirier | DPRINTF("RTL8139C+ DTCCR write offset=0x%x val=0x%08x "
|
2453 | 7cdeb319 | Benjamin Poirier | "descriptor=%d\n", txRegOffset, val, descriptor);
|
2454 | 6cadb320 | bellard | |
2455 | 6cadb320 | bellard | /* handle Dump Tally Counters command */
|
2456 | 6cadb320 | bellard | s->TxStatus[descriptor] = val; |
2457 | 6cadb320 | bellard | |
2458 | 6cadb320 | bellard | if (descriptor == 0 && (val & 0x8)) |
2459 | 6cadb320 | bellard | { |
2460 | c227f099 | Anthony Liguori | target_phys_addr_t tc_addr = rtl8139_addr64(s->TxStatus[0] & ~0x3f, s->TxStatus[1]); |
2461 | 6cadb320 | bellard | |
2462 | 6cadb320 | bellard | /* dump tally counters to specified memory location */
|
2463 | 3ada003a | Eduard - Gabriel Munteanu | RTL8139TallyCounters_dma_write(s, tc_addr); |
2464 | 6cadb320 | bellard | |
2465 | 6cadb320 | bellard | /* mark dump completed */
|
2466 | 6cadb320 | bellard | s->TxStatus[0] &= ~0x8; |
2467 | 6cadb320 | bellard | } |
2468 | 6cadb320 | bellard | |
2469 | 6cadb320 | bellard | return;
|
2470 | 6cadb320 | bellard | } |
2471 | 6cadb320 | bellard | |
2472 | 7cdeb319 | Benjamin Poirier | DPRINTF("TxStatus write offset=0x%x val=0x%08x descriptor=%d\n",
|
2473 | 7cdeb319 | Benjamin Poirier | txRegOffset, val, descriptor); |
2474 | a41b2ff2 | pbrook | |
2475 | a41b2ff2 | pbrook | /* mask only reserved bits */
|
2476 | a41b2ff2 | pbrook | val &= ~0xff00c000; /* these bits are reset on write */ |
2477 | a41b2ff2 | pbrook | val = SET_MASKED(val, 0x00c00000, s->TxStatus[descriptor]);
|
2478 | a41b2ff2 | pbrook | |
2479 | a41b2ff2 | pbrook | s->TxStatus[descriptor] = val; |
2480 | a41b2ff2 | pbrook | |
2481 | a41b2ff2 | pbrook | /* attempt to start transmission */
|
2482 | a41b2ff2 | pbrook | rtl8139_transmit(s); |
2483 | a41b2ff2 | pbrook | } |
2484 | a41b2ff2 | pbrook | |
2485 | 3e48dd4a | Stefan Hajnoczi | static uint32_t rtl8139_TxStatus_TxAddr_read(RTL8139State *s, uint32_t regs[],
|
2486 | 3e48dd4a | Stefan Hajnoczi | uint32_t base, uint8_t addr, |
2487 | 3e48dd4a | Stefan Hajnoczi | int size)
|
2488 | a41b2ff2 | pbrook | { |
2489 | 3e48dd4a | Stefan Hajnoczi | uint32_t reg = (addr - base) / 4;
|
2490 | afe0a595 | Jason Wang | uint32_t offset = addr & 0x3;
|
2491 | afe0a595 | Jason Wang | uint32_t ret = 0;
|
2492 | afe0a595 | Jason Wang | |
2493 | afe0a595 | Jason Wang | if (addr & (size - 1)) { |
2494 | 3e48dd4a | Stefan Hajnoczi | DPRINTF("not implemented read for TxStatus/TxAddr "
|
2495 | 3e48dd4a | Stefan Hajnoczi | "addr=0x%x size=0x%x\n", addr, size);
|
2496 | afe0a595 | Jason Wang | return ret;
|
2497 | afe0a595 | Jason Wang | } |
2498 | a41b2ff2 | pbrook | |
2499 | afe0a595 | Jason Wang | switch (size) {
|
2500 | afe0a595 | Jason Wang | case 1: /* fall through */ |
2501 | afe0a595 | Jason Wang | case 2: /* fall through */ |
2502 | afe0a595 | Jason Wang | case 4: |
2503 | bdc62e62 | Avi Kivity | ret = (regs[reg] >> offset * 8) & (((uint64_t)1 << (size * 8)) - 1); |
2504 | 3e48dd4a | Stefan Hajnoczi | DPRINTF("TxStatus/TxAddr[%d] read addr=0x%x size=0x%x val=0x%08x\n",
|
2505 | 3e48dd4a | Stefan Hajnoczi | reg, addr, size, ret); |
2506 | afe0a595 | Jason Wang | break;
|
2507 | afe0a595 | Jason Wang | default:
|
2508 | 3e48dd4a | Stefan Hajnoczi | DPRINTF("unsupported size 0x%x of TxStatus/TxAddr reading\n", size);
|
2509 | afe0a595 | Jason Wang | break;
|
2510 | afe0a595 | Jason Wang | } |
2511 | a41b2ff2 | pbrook | |
2512 | a41b2ff2 | pbrook | return ret;
|
2513 | a41b2ff2 | pbrook | } |
2514 | a41b2ff2 | pbrook | |
2515 | a41b2ff2 | pbrook | static uint16_t rtl8139_TSAD_read(RTL8139State *s)
|
2516 | a41b2ff2 | pbrook | { |
2517 | a41b2ff2 | pbrook | uint16_t ret = 0;
|
2518 | a41b2ff2 | pbrook | |
2519 | a41b2ff2 | pbrook | /* Simulate TSAD, it is read only anyway */
|
2520 | a41b2ff2 | pbrook | |
2521 | a41b2ff2 | pbrook | ret = ((s->TxStatus[3] & TxStatOK )?TSAD_TOK3:0) |
2522 | a41b2ff2 | pbrook | |((s->TxStatus[2] & TxStatOK )?TSAD_TOK2:0) |
2523 | a41b2ff2 | pbrook | |((s->TxStatus[1] & TxStatOK )?TSAD_TOK1:0) |
2524 | a41b2ff2 | pbrook | |((s->TxStatus[0] & TxStatOK )?TSAD_TOK0:0) |
2525 | a41b2ff2 | pbrook | |
2526 | a41b2ff2 | pbrook | |((s->TxStatus[3] & TxUnderrun)?TSAD_TUN3:0) |
2527 | a41b2ff2 | pbrook | |((s->TxStatus[2] & TxUnderrun)?TSAD_TUN2:0) |
2528 | a41b2ff2 | pbrook | |((s->TxStatus[1] & TxUnderrun)?TSAD_TUN1:0) |
2529 | a41b2ff2 | pbrook | |((s->TxStatus[0] & TxUnderrun)?TSAD_TUN0:0) |
2530 | 3b46e624 | ths | |
2531 | a41b2ff2 | pbrook | |((s->TxStatus[3] & TxAborted )?TSAD_TABT3:0) |
2532 | a41b2ff2 | pbrook | |((s->TxStatus[2] & TxAborted )?TSAD_TABT2:0) |
2533 | a41b2ff2 | pbrook | |((s->TxStatus[1] & TxAborted )?TSAD_TABT1:0) |
2534 | a41b2ff2 | pbrook | |((s->TxStatus[0] & TxAborted )?TSAD_TABT0:0) |
2535 | 3b46e624 | ths | |
2536 | a41b2ff2 | pbrook | |((s->TxStatus[3] & TxHostOwns )?TSAD_OWN3:0) |
2537 | a41b2ff2 | pbrook | |((s->TxStatus[2] & TxHostOwns )?TSAD_OWN2:0) |
2538 | a41b2ff2 | pbrook | |((s->TxStatus[1] & TxHostOwns )?TSAD_OWN1:0) |
2539 | a41b2ff2 | pbrook | |((s->TxStatus[0] & TxHostOwns )?TSAD_OWN0:0) ; |
2540 | 3b46e624 | ths | |
2541 | a41b2ff2 | pbrook | |
2542 | 7cdeb319 | Benjamin Poirier | DPRINTF("TSAD read val=0x%04x\n", ret);
|
2543 | a41b2ff2 | pbrook | |
2544 | a41b2ff2 | pbrook | return ret;
|
2545 | a41b2ff2 | pbrook | } |
2546 | a41b2ff2 | pbrook | |
2547 | a41b2ff2 | pbrook | static uint16_t rtl8139_CSCR_read(RTL8139State *s)
|
2548 | a41b2ff2 | pbrook | { |
2549 | a41b2ff2 | pbrook | uint16_t ret = s->CSCR; |
2550 | a41b2ff2 | pbrook | |
2551 | 7cdeb319 | Benjamin Poirier | DPRINTF("CSCR read val=0x%04x\n", ret);
|
2552 | a41b2ff2 | pbrook | |
2553 | a41b2ff2 | pbrook | return ret;
|
2554 | a41b2ff2 | pbrook | } |
2555 | a41b2ff2 | pbrook | |
2556 | a41b2ff2 | pbrook | static void rtl8139_TxAddr_write(RTL8139State *s, uint32_t txAddrOffset, uint32_t val) |
2557 | a41b2ff2 | pbrook | { |
2558 | 7cdeb319 | Benjamin Poirier | DPRINTF("TxAddr write offset=0x%x val=0x%08x\n", txAddrOffset, val);
|
2559 | a41b2ff2 | pbrook | |
2560 | 290a0933 | ths | s->TxAddr[txAddrOffset/4] = val;
|
2561 | a41b2ff2 | pbrook | } |
2562 | a41b2ff2 | pbrook | |
2563 | a41b2ff2 | pbrook | static uint32_t rtl8139_TxAddr_read(RTL8139State *s, uint32_t txAddrOffset)
|
2564 | a41b2ff2 | pbrook | { |
2565 | 290a0933 | ths | uint32_t ret = s->TxAddr[txAddrOffset/4];
|
2566 | a41b2ff2 | pbrook | |
2567 | 7cdeb319 | Benjamin Poirier | DPRINTF("TxAddr read offset=0x%x val=0x%08x\n", txAddrOffset, ret);
|
2568 | a41b2ff2 | pbrook | |
2569 | a41b2ff2 | pbrook | return ret;
|
2570 | a41b2ff2 | pbrook | } |
2571 | a41b2ff2 | pbrook | |
2572 | a41b2ff2 | pbrook | static void rtl8139_RxBufPtr_write(RTL8139State *s, uint32_t val) |
2573 | a41b2ff2 | pbrook | { |
2574 | 7cdeb319 | Benjamin Poirier | DPRINTF("RxBufPtr write val=0x%04x\n", val);
|
2575 | a41b2ff2 | pbrook | |
2576 | a41b2ff2 | pbrook | /* this value is off by 16 */
|
2577 | a41b2ff2 | pbrook | s->RxBufPtr = MOD2(val + 0x10, s->RxBufferSize);
|
2578 | a41b2ff2 | pbrook | |
2579 | 7cdeb319 | Benjamin Poirier | DPRINTF(" CAPR write: rx buffer length %d head 0x%04x read 0x%04x\n",
|
2580 | 7cdeb319 | Benjamin Poirier | s->RxBufferSize, s->RxBufAddr, s->RxBufPtr); |
2581 | a41b2ff2 | pbrook | } |
2582 | a41b2ff2 | pbrook | |
2583 | a41b2ff2 | pbrook | static uint32_t rtl8139_RxBufPtr_read(RTL8139State *s)
|
2584 | a41b2ff2 | pbrook | { |
2585 | a41b2ff2 | pbrook | /* this value is off by 16 */
|
2586 | a41b2ff2 | pbrook | uint32_t ret = s->RxBufPtr - 0x10;
|
2587 | a41b2ff2 | pbrook | |
2588 | 7cdeb319 | Benjamin Poirier | DPRINTF("RxBufPtr read val=0x%04x\n", ret);
|
2589 | 6cadb320 | bellard | |
2590 | 6cadb320 | bellard | return ret;
|
2591 | 6cadb320 | bellard | } |
2592 | 6cadb320 | bellard | |
2593 | 6cadb320 | bellard | static uint32_t rtl8139_RxBufAddr_read(RTL8139State *s)
|
2594 | 6cadb320 | bellard | { |
2595 | 6cadb320 | bellard | /* this value is NOT off by 16 */
|
2596 | 6cadb320 | bellard | uint32_t ret = s->RxBufAddr; |
2597 | 6cadb320 | bellard | |
2598 | 7cdeb319 | Benjamin Poirier | DPRINTF("RxBufAddr read val=0x%04x\n", ret);
|
2599 | a41b2ff2 | pbrook | |
2600 | a41b2ff2 | pbrook | return ret;
|
2601 | a41b2ff2 | pbrook | } |
2602 | a41b2ff2 | pbrook | |
2603 | a41b2ff2 | pbrook | static void rtl8139_RxBuf_write(RTL8139State *s, uint32_t val) |
2604 | a41b2ff2 | pbrook | { |
2605 | 7cdeb319 | Benjamin Poirier | DPRINTF("RxBuf write val=0x%08x\n", val);
|
2606 | a41b2ff2 | pbrook | |
2607 | a41b2ff2 | pbrook | s->RxBuf = val; |
2608 | a41b2ff2 | pbrook | |
2609 | a41b2ff2 | pbrook | /* may need to reset rxring here */
|
2610 | a41b2ff2 | pbrook | } |
2611 | a41b2ff2 | pbrook | |
2612 | a41b2ff2 | pbrook | static uint32_t rtl8139_RxBuf_read(RTL8139State *s)
|
2613 | a41b2ff2 | pbrook | { |
2614 | a41b2ff2 | pbrook | uint32_t ret = s->RxBuf; |
2615 | a41b2ff2 | pbrook | |
2616 | 7cdeb319 | Benjamin Poirier | DPRINTF("RxBuf read val=0x%08x\n", ret);
|
2617 | a41b2ff2 | pbrook | |
2618 | a41b2ff2 | pbrook | return ret;
|
2619 | a41b2ff2 | pbrook | } |
2620 | a41b2ff2 | pbrook | |
2621 | a41b2ff2 | pbrook | static void rtl8139_IntrMask_write(RTL8139State *s, uint32_t val) |
2622 | a41b2ff2 | pbrook | { |
2623 | 7cdeb319 | Benjamin Poirier | DPRINTF("IntrMask write(w) val=0x%04x\n", val);
|
2624 | a41b2ff2 | pbrook | |
2625 | ebabb67a | Stefan Weil | /* mask unwritable bits */
|
2626 | a41b2ff2 | pbrook | val = SET_MASKED(val, 0x1e00, s->IntrMask);
|
2627 | a41b2ff2 | pbrook | |
2628 | a41b2ff2 | pbrook | s->IntrMask = val; |
2629 | a41b2ff2 | pbrook | |
2630 | 74475455 | Paolo Bonzini | rtl8139_set_next_tctr_time(s, qemu_get_clock_ns(vm_clock)); |
2631 | a41b2ff2 | pbrook | rtl8139_update_irq(s); |
2632 | 05447803 | Frediano Ziglio | |
2633 | a41b2ff2 | pbrook | } |
2634 | a41b2ff2 | pbrook | |
2635 | a41b2ff2 | pbrook | static uint32_t rtl8139_IntrMask_read(RTL8139State *s)
|
2636 | a41b2ff2 | pbrook | { |
2637 | a41b2ff2 | pbrook | uint32_t ret = s->IntrMask; |
2638 | a41b2ff2 | pbrook | |
2639 | 7cdeb319 | Benjamin Poirier | DPRINTF("IntrMask read(w) val=0x%04x\n", ret);
|
2640 | a41b2ff2 | pbrook | |
2641 | a41b2ff2 | pbrook | return ret;
|
2642 | a41b2ff2 | pbrook | } |
2643 | a41b2ff2 | pbrook | |
2644 | a41b2ff2 | pbrook | static void rtl8139_IntrStatus_write(RTL8139State *s, uint32_t val) |
2645 | a41b2ff2 | pbrook | { |
2646 | 7cdeb319 | Benjamin Poirier | DPRINTF("IntrStatus write(w) val=0x%04x\n", val);
|
2647 | a41b2ff2 | pbrook | |
2648 | a41b2ff2 | pbrook | #if 0
|
2649 | a41b2ff2 | pbrook | |
2650 | a41b2ff2 | pbrook | /* writing to ISR has no effect */
|
2651 | a41b2ff2 | pbrook | |
2652 | a41b2ff2 | pbrook | return;
|
2653 | a41b2ff2 | pbrook | |
2654 | a41b2ff2 | pbrook | #else
|
2655 | a41b2ff2 | pbrook | uint16_t newStatus = s->IntrStatus & ~val; |
2656 | a41b2ff2 | pbrook | |
2657 | ebabb67a | Stefan Weil | /* mask unwritable bits */
|
2658 | a41b2ff2 | pbrook | newStatus = SET_MASKED(newStatus, 0x1e00, s->IntrStatus);
|
2659 | a41b2ff2 | pbrook | |
2660 | a41b2ff2 | pbrook | /* writing 1 to interrupt status register bit clears it */
|
2661 | a41b2ff2 | pbrook | s->IntrStatus = 0;
|
2662 | a41b2ff2 | pbrook | rtl8139_update_irq(s); |
2663 | a41b2ff2 | pbrook | |
2664 | a41b2ff2 | pbrook | s->IntrStatus = newStatus; |
2665 | 05447803 | Frediano Ziglio | /*
|
2666 | 05447803 | Frediano Ziglio | * Computing if we miss an interrupt here is not that correct but
|
2667 | 05447803 | Frediano Ziglio | * considered that we should have had already an interrupt
|
2668 | 05447803 | Frediano Ziglio | * and probably emulated is slower is better to assume this resetting was
|
2669 | 26404edc | Stefan Weil | * done before testing on previous rtl8139_update_irq lead to IRQ losing
|
2670 | 05447803 | Frediano Ziglio | */
|
2671 | 74475455 | Paolo Bonzini | rtl8139_set_next_tctr_time(s, qemu_get_clock_ns(vm_clock)); |
2672 | a41b2ff2 | pbrook | rtl8139_update_irq(s); |
2673 | 05447803 | Frediano Ziglio | |
2674 | a41b2ff2 | pbrook | #endif
|
2675 | a41b2ff2 | pbrook | } |
2676 | a41b2ff2 | pbrook | |
2677 | a41b2ff2 | pbrook | static uint32_t rtl8139_IntrStatus_read(RTL8139State *s)
|
2678 | a41b2ff2 | pbrook | { |
2679 | 74475455 | Paolo Bonzini | rtl8139_set_next_tctr_time(s, qemu_get_clock_ns(vm_clock)); |
2680 | 05447803 | Frediano Ziglio | |
2681 | a41b2ff2 | pbrook | uint32_t ret = s->IntrStatus; |
2682 | a41b2ff2 | pbrook | |
2683 | 7cdeb319 | Benjamin Poirier | DPRINTF("IntrStatus read(w) val=0x%04x\n", ret);
|
2684 | a41b2ff2 | pbrook | |
2685 | a41b2ff2 | pbrook | #if 0
|
2686 | a41b2ff2 | pbrook | |
2687 | a41b2ff2 | pbrook | /* reading ISR clears all interrupts */
|
2688 | a41b2ff2 | pbrook | s->IntrStatus = 0;
|
2689 | a41b2ff2 | pbrook | |
2690 | a41b2ff2 | pbrook | rtl8139_update_irq(s);
|
2691 | a41b2ff2 | pbrook | |
2692 | a41b2ff2 | pbrook | #endif
|
2693 | a41b2ff2 | pbrook | |
2694 | a41b2ff2 | pbrook | return ret;
|
2695 | a41b2ff2 | pbrook | } |
2696 | a41b2ff2 | pbrook | |
2697 | a41b2ff2 | pbrook | static void rtl8139_MultiIntr_write(RTL8139State *s, uint32_t val) |
2698 | a41b2ff2 | pbrook | { |
2699 | 7cdeb319 | Benjamin Poirier | DPRINTF("MultiIntr write(w) val=0x%04x\n", val);
|
2700 | a41b2ff2 | pbrook | |
2701 | ebabb67a | Stefan Weil | /* mask unwritable bits */
|
2702 | a41b2ff2 | pbrook | val = SET_MASKED(val, 0xf000, s->MultiIntr);
|
2703 | a41b2ff2 | pbrook | |
2704 | a41b2ff2 | pbrook | s->MultiIntr = val; |
2705 | a41b2ff2 | pbrook | } |
2706 | a41b2ff2 | pbrook | |
2707 | a41b2ff2 | pbrook | static uint32_t rtl8139_MultiIntr_read(RTL8139State *s)
|
2708 | a41b2ff2 | pbrook | { |
2709 | a41b2ff2 | pbrook | uint32_t ret = s->MultiIntr; |
2710 | a41b2ff2 | pbrook | |
2711 | 7cdeb319 | Benjamin Poirier | DPRINTF("MultiIntr read(w) val=0x%04x\n", ret);
|
2712 | a41b2ff2 | pbrook | |
2713 | a41b2ff2 | pbrook | return ret;
|
2714 | a41b2ff2 | pbrook | } |
2715 | a41b2ff2 | pbrook | |
2716 | a41b2ff2 | pbrook | static void rtl8139_io_writeb(void *opaque, uint8_t addr, uint32_t val) |
2717 | a41b2ff2 | pbrook | { |
2718 | a41b2ff2 | pbrook | RTL8139State *s = opaque; |
2719 | a41b2ff2 | pbrook | |
2720 | a41b2ff2 | pbrook | switch (addr)
|
2721 | a41b2ff2 | pbrook | { |
2722 | a41b2ff2 | pbrook | case MAC0 ... MAC0+5: |
2723 | a41b2ff2 | pbrook | s->phys[addr - MAC0] = val; |
2724 | a41b2ff2 | pbrook | break;
|
2725 | a41b2ff2 | pbrook | case MAC0+6 ... MAC0+7: |
2726 | a41b2ff2 | pbrook | /* reserved */
|
2727 | a41b2ff2 | pbrook | break;
|
2728 | a41b2ff2 | pbrook | case MAR0 ... MAR0+7: |
2729 | a41b2ff2 | pbrook | s->mult[addr - MAR0] = val; |
2730 | a41b2ff2 | pbrook | break;
|
2731 | a41b2ff2 | pbrook | case ChipCmd:
|
2732 | a41b2ff2 | pbrook | rtl8139_ChipCmd_write(s, val); |
2733 | a41b2ff2 | pbrook | break;
|
2734 | a41b2ff2 | pbrook | case Cfg9346:
|
2735 | a41b2ff2 | pbrook | rtl8139_Cfg9346_write(s, val); |
2736 | a41b2ff2 | pbrook | break;
|
2737 | a41b2ff2 | pbrook | case TxConfig: /* windows driver sometimes writes using byte-lenth call */ |
2738 | a41b2ff2 | pbrook | rtl8139_TxConfig_writeb(s, val); |
2739 | a41b2ff2 | pbrook | break;
|
2740 | a41b2ff2 | pbrook | case Config0:
|
2741 | a41b2ff2 | pbrook | rtl8139_Config0_write(s, val); |
2742 | a41b2ff2 | pbrook | break;
|
2743 | a41b2ff2 | pbrook | case Config1:
|
2744 | a41b2ff2 | pbrook | rtl8139_Config1_write(s, val); |
2745 | a41b2ff2 | pbrook | break;
|
2746 | a41b2ff2 | pbrook | case Config3:
|
2747 | a41b2ff2 | pbrook | rtl8139_Config3_write(s, val); |
2748 | a41b2ff2 | pbrook | break;
|
2749 | a41b2ff2 | pbrook | case Config4:
|
2750 | a41b2ff2 | pbrook | rtl8139_Config4_write(s, val); |
2751 | a41b2ff2 | pbrook | break;
|
2752 | a41b2ff2 | pbrook | case Config5:
|
2753 | a41b2ff2 | pbrook | rtl8139_Config5_write(s, val); |
2754 | a41b2ff2 | pbrook | break;
|
2755 | a41b2ff2 | pbrook | case MediaStatus:
|
2756 | a41b2ff2 | pbrook | /* ignore */
|
2757 | 7cdeb319 | Benjamin Poirier | DPRINTF("not implemented write(b) to MediaStatus val=0x%02x\n",
|
2758 | 7cdeb319 | Benjamin Poirier | val); |
2759 | a41b2ff2 | pbrook | break;
|
2760 | a41b2ff2 | pbrook | |
2761 | a41b2ff2 | pbrook | case HltClk:
|
2762 | 7cdeb319 | Benjamin Poirier | DPRINTF("HltClk write val=0x%08x\n", val);
|
2763 | a41b2ff2 | pbrook | if (val == 'R') |
2764 | a41b2ff2 | pbrook | { |
2765 | a41b2ff2 | pbrook | s->clock_enabled = 1;
|
2766 | a41b2ff2 | pbrook | } |
2767 | a41b2ff2 | pbrook | else if (val == 'H') |
2768 | a41b2ff2 | pbrook | { |
2769 | a41b2ff2 | pbrook | s->clock_enabled = 0;
|
2770 | a41b2ff2 | pbrook | } |
2771 | a41b2ff2 | pbrook | break;
|
2772 | a41b2ff2 | pbrook | |
2773 | a41b2ff2 | pbrook | case TxThresh:
|
2774 | 7cdeb319 | Benjamin Poirier | DPRINTF("C+ TxThresh write(b) val=0x%02x\n", val);
|
2775 | a41b2ff2 | pbrook | s->TxThresh = val; |
2776 | a41b2ff2 | pbrook | break;
|
2777 | a41b2ff2 | pbrook | |
2778 | a41b2ff2 | pbrook | case TxPoll:
|
2779 | 7cdeb319 | Benjamin Poirier | DPRINTF("C+ TxPoll write(b) val=0x%02x\n", val);
|
2780 | a41b2ff2 | pbrook | if (val & (1 << 7)) |
2781 | a41b2ff2 | pbrook | { |
2782 | 7cdeb319 | Benjamin Poirier | DPRINTF("C+ TxPoll high priority transmission (not "
|
2783 | 7cdeb319 | Benjamin Poirier | "implemented)\n");
|
2784 | a41b2ff2 | pbrook | //rtl8139_cplus_transmit(s);
|
2785 | a41b2ff2 | pbrook | } |
2786 | a41b2ff2 | pbrook | if (val & (1 << 6)) |
2787 | a41b2ff2 | pbrook | { |
2788 | 7cdeb319 | Benjamin Poirier | DPRINTF("C+ TxPoll normal priority transmission\n");
|
2789 | a41b2ff2 | pbrook | rtl8139_cplus_transmit(s); |
2790 | a41b2ff2 | pbrook | } |
2791 | a41b2ff2 | pbrook | |
2792 | a41b2ff2 | pbrook | break;
|
2793 | a41b2ff2 | pbrook | |
2794 | a41b2ff2 | pbrook | default:
|
2795 | 7cdeb319 | Benjamin Poirier | DPRINTF("not implemented write(b) addr=0x%x val=0x%02x\n", addr,
|
2796 | 7cdeb319 | Benjamin Poirier | val); |
2797 | a41b2ff2 | pbrook | break;
|
2798 | a41b2ff2 | pbrook | } |
2799 | a41b2ff2 | pbrook | } |
2800 | a41b2ff2 | pbrook | |
2801 | a41b2ff2 | pbrook | static void rtl8139_io_writew(void *opaque, uint8_t addr, uint32_t val) |
2802 | a41b2ff2 | pbrook | { |
2803 | a41b2ff2 | pbrook | RTL8139State *s = opaque; |
2804 | a41b2ff2 | pbrook | |
2805 | a41b2ff2 | pbrook | switch (addr)
|
2806 | a41b2ff2 | pbrook | { |
2807 | a41b2ff2 | pbrook | case IntrMask:
|
2808 | a41b2ff2 | pbrook | rtl8139_IntrMask_write(s, val); |
2809 | a41b2ff2 | pbrook | break;
|
2810 | a41b2ff2 | pbrook | |
2811 | a41b2ff2 | pbrook | case IntrStatus:
|
2812 | a41b2ff2 | pbrook | rtl8139_IntrStatus_write(s, val); |
2813 | a41b2ff2 | pbrook | break;
|
2814 | a41b2ff2 | pbrook | |
2815 | a41b2ff2 | pbrook | case MultiIntr:
|
2816 | a41b2ff2 | pbrook | rtl8139_MultiIntr_write(s, val); |
2817 | a41b2ff2 | pbrook | break;
|
2818 | a41b2ff2 | pbrook | |
2819 | a41b2ff2 | pbrook | case RxBufPtr:
|
2820 | a41b2ff2 | pbrook | rtl8139_RxBufPtr_write(s, val); |
2821 | a41b2ff2 | pbrook | break;
|
2822 | a41b2ff2 | pbrook | |
2823 | a41b2ff2 | pbrook | case BasicModeCtrl:
|
2824 | a41b2ff2 | pbrook | rtl8139_BasicModeCtrl_write(s, val); |
2825 | a41b2ff2 | pbrook | break;
|
2826 | a41b2ff2 | pbrook | case BasicModeStatus:
|
2827 | a41b2ff2 | pbrook | rtl8139_BasicModeStatus_write(s, val); |
2828 | a41b2ff2 | pbrook | break;
|
2829 | a41b2ff2 | pbrook | case NWayAdvert:
|
2830 | 7cdeb319 | Benjamin Poirier | DPRINTF("NWayAdvert write(w) val=0x%04x\n", val);
|
2831 | a41b2ff2 | pbrook | s->NWayAdvert = val; |
2832 | a41b2ff2 | pbrook | break;
|
2833 | a41b2ff2 | pbrook | case NWayLPAR:
|
2834 | 7cdeb319 | Benjamin Poirier | DPRINTF("forbidden NWayLPAR write(w) val=0x%04x\n", val);
|
2835 | a41b2ff2 | pbrook | break;
|
2836 | a41b2ff2 | pbrook | case NWayExpansion:
|
2837 | 7cdeb319 | Benjamin Poirier | DPRINTF("NWayExpansion write(w) val=0x%04x\n", val);
|
2838 | a41b2ff2 | pbrook | s->NWayExpansion = val; |
2839 | a41b2ff2 | pbrook | break;
|
2840 | a41b2ff2 | pbrook | |
2841 | a41b2ff2 | pbrook | case CpCmd:
|
2842 | a41b2ff2 | pbrook | rtl8139_CpCmd_write(s, val); |
2843 | a41b2ff2 | pbrook | break;
|
2844 | a41b2ff2 | pbrook | |
2845 | 6cadb320 | bellard | case IntrMitigate:
|
2846 | 6cadb320 | bellard | rtl8139_IntrMitigate_write(s, val); |
2847 | 6cadb320 | bellard | break;
|
2848 | 6cadb320 | bellard | |
2849 | a41b2ff2 | pbrook | default:
|
2850 | 7cdeb319 | Benjamin Poirier | DPRINTF("ioport write(w) addr=0x%x val=0x%04x via write(b)\n",
|
2851 | 7cdeb319 | Benjamin Poirier | addr, val); |
2852 | a41b2ff2 | pbrook | |
2853 | a41b2ff2 | pbrook | rtl8139_io_writeb(opaque, addr, val & 0xff);
|
2854 | a41b2ff2 | pbrook | rtl8139_io_writeb(opaque, addr + 1, (val >> 8) & 0xff); |
2855 | a41b2ff2 | pbrook | break;
|
2856 | a41b2ff2 | pbrook | } |
2857 | a41b2ff2 | pbrook | } |
2858 | a41b2ff2 | pbrook | |
2859 | 05447803 | Frediano Ziglio | static void rtl8139_set_next_tctr_time(RTL8139State *s, int64_t current_time) |
2860 | 05447803 | Frediano Ziglio | { |
2861 | 05447803 | Frediano Ziglio | int64_t pci_time, next_time; |
2862 | 05447803 | Frediano Ziglio | uint32_t low_pci; |
2863 | 05447803 | Frediano Ziglio | |
2864 | 7cdeb319 | Benjamin Poirier | DPRINTF("entered rtl8139_set_next_tctr_time\n");
|
2865 | 05447803 | Frediano Ziglio | |
2866 | 05447803 | Frediano Ziglio | if (s->TimerExpire && current_time >= s->TimerExpire) {
|
2867 | 05447803 | Frediano Ziglio | s->IntrStatus |= PCSTimeout; |
2868 | 05447803 | Frediano Ziglio | rtl8139_update_irq(s); |
2869 | 05447803 | Frediano Ziglio | } |
2870 | 05447803 | Frediano Ziglio | |
2871 | 05447803 | Frediano Ziglio | /* Set QEMU timer only if needed that is
|
2872 | 05447803 | Frediano Ziglio | * - TimerInt <> 0 (we have a timer)
|
2873 | 05447803 | Frediano Ziglio | * - mask = 1 (we want an interrupt timer)
|
2874 | 05447803 | Frediano Ziglio | * - irq = 0 (irq is not already active)
|
2875 | 05447803 | Frediano Ziglio | * If any of above change we need to compute timer again
|
2876 | 05447803 | Frediano Ziglio | * Also we must check if timer is passed without QEMU timer
|
2877 | 05447803 | Frediano Ziglio | */
|
2878 | 05447803 | Frediano Ziglio | s->TimerExpire = 0;
|
2879 | 05447803 | Frediano Ziglio | if (!s->TimerInt) {
|
2880 | 05447803 | Frediano Ziglio | return;
|
2881 | 05447803 | Frediano Ziglio | } |
2882 | 05447803 | Frediano Ziglio | |
2883 | 05447803 | Frediano Ziglio | pci_time = muldiv64(current_time - s->TCTR_base, PCI_FREQUENCY, |
2884 | 05447803 | Frediano Ziglio | get_ticks_per_sec()); |
2885 | 05447803 | Frediano Ziglio | low_pci = pci_time & 0xffffffff;
|
2886 | 05447803 | Frediano Ziglio | pci_time = pci_time - low_pci + s->TimerInt; |
2887 | 05447803 | Frediano Ziglio | if (low_pci >= s->TimerInt) {
|
2888 | 05447803 | Frediano Ziglio | pci_time += 0x100000000LL;
|
2889 | 05447803 | Frediano Ziglio | } |
2890 | 05447803 | Frediano Ziglio | next_time = s->TCTR_base + muldiv64(pci_time, get_ticks_per_sec(), |
2891 | 05447803 | Frediano Ziglio | PCI_FREQUENCY); |
2892 | 05447803 | Frediano Ziglio | s->TimerExpire = next_time; |
2893 | 05447803 | Frediano Ziglio | |
2894 | 05447803 | Frediano Ziglio | if ((s->IntrMask & PCSTimeout) != 0 && (s->IntrStatus & PCSTimeout) == 0) { |
2895 | 05447803 | Frediano Ziglio | qemu_mod_timer(s->timer, next_time); |
2896 | 05447803 | Frediano Ziglio | } |
2897 | 05447803 | Frediano Ziglio | } |
2898 | 05447803 | Frediano Ziglio | |
2899 | a41b2ff2 | pbrook | static void rtl8139_io_writel(void *opaque, uint8_t addr, uint32_t val) |
2900 | a41b2ff2 | pbrook | { |
2901 | a41b2ff2 | pbrook | RTL8139State *s = opaque; |
2902 | a41b2ff2 | pbrook | |
2903 | a41b2ff2 | pbrook | switch (addr)
|
2904 | a41b2ff2 | pbrook | { |
2905 | a41b2ff2 | pbrook | case RxMissed:
|
2906 | 7cdeb319 | Benjamin Poirier | DPRINTF("RxMissed clearing on write\n");
|
2907 | a41b2ff2 | pbrook | s->RxMissed = 0;
|
2908 | a41b2ff2 | pbrook | break;
|
2909 | a41b2ff2 | pbrook | |
2910 | a41b2ff2 | pbrook | case TxConfig:
|
2911 | a41b2ff2 | pbrook | rtl8139_TxConfig_write(s, val); |
2912 | a41b2ff2 | pbrook | break;
|
2913 | a41b2ff2 | pbrook | |
2914 | a41b2ff2 | pbrook | case RxConfig:
|
2915 | a41b2ff2 | pbrook | rtl8139_RxConfig_write(s, val); |
2916 | a41b2ff2 | pbrook | break;
|
2917 | a41b2ff2 | pbrook | |
2918 | a41b2ff2 | pbrook | case TxStatus0 ... TxStatus0+4*4-1: |
2919 | a41b2ff2 | pbrook | rtl8139_TxStatus_write(s, addr-TxStatus0, val); |
2920 | a41b2ff2 | pbrook | break;
|
2921 | a41b2ff2 | pbrook | |
2922 | a41b2ff2 | pbrook | case TxAddr0 ... TxAddr0+4*4-1: |
2923 | a41b2ff2 | pbrook | rtl8139_TxAddr_write(s, addr-TxAddr0, val); |
2924 | a41b2ff2 | pbrook | break;
|
2925 | a41b2ff2 | pbrook | |
2926 | a41b2ff2 | pbrook | case RxBuf:
|
2927 | a41b2ff2 | pbrook | rtl8139_RxBuf_write(s, val); |
2928 | a41b2ff2 | pbrook | break;
|
2929 | a41b2ff2 | pbrook | |
2930 | a41b2ff2 | pbrook | case RxRingAddrLO:
|
2931 | 7cdeb319 | Benjamin Poirier | DPRINTF("C+ RxRing low bits write val=0x%08x\n", val);
|
2932 | a41b2ff2 | pbrook | s->RxRingAddrLO = val; |
2933 | a41b2ff2 | pbrook | break;
|
2934 | a41b2ff2 | pbrook | |
2935 | a41b2ff2 | pbrook | case RxRingAddrHI:
|
2936 | 7cdeb319 | Benjamin Poirier | DPRINTF("C+ RxRing high bits write val=0x%08x\n", val);
|
2937 | a41b2ff2 | pbrook | s->RxRingAddrHI = val; |
2938 | a41b2ff2 | pbrook | break;
|
2939 | a41b2ff2 | pbrook | |
2940 | 6cadb320 | bellard | case Timer:
|
2941 | 7cdeb319 | Benjamin Poirier | DPRINTF("TCTR Timer reset on write\n");
|
2942 | 74475455 | Paolo Bonzini | s->TCTR_base = qemu_get_clock_ns(vm_clock); |
2943 | 05447803 | Frediano Ziglio | rtl8139_set_next_tctr_time(s, s->TCTR_base); |
2944 | 6cadb320 | bellard | break;
|
2945 | 6cadb320 | bellard | |
2946 | 6cadb320 | bellard | case FlashReg:
|
2947 | 7cdeb319 | Benjamin Poirier | DPRINTF("FlashReg TimerInt write val=0x%08x\n", val);
|
2948 | 05447803 | Frediano Ziglio | if (s->TimerInt != val) {
|
2949 | 05447803 | Frediano Ziglio | s->TimerInt = val; |
2950 | 74475455 | Paolo Bonzini | rtl8139_set_next_tctr_time(s, qemu_get_clock_ns(vm_clock)); |
2951 | 05447803 | Frediano Ziglio | } |
2952 | 6cadb320 | bellard | break;
|
2953 | 6cadb320 | bellard | |
2954 | a41b2ff2 | pbrook | default:
|
2955 | 7cdeb319 | Benjamin Poirier | DPRINTF("ioport write(l) addr=0x%x val=0x%08x via write(b)\n",
|
2956 | 7cdeb319 | Benjamin Poirier | addr, val); |
2957 | a41b2ff2 | pbrook | rtl8139_io_writeb(opaque, addr, val & 0xff);
|
2958 | a41b2ff2 | pbrook | rtl8139_io_writeb(opaque, addr + 1, (val >> 8) & 0xff); |
2959 | a41b2ff2 | pbrook | rtl8139_io_writeb(opaque, addr + 2, (val >> 16) & 0xff); |
2960 | a41b2ff2 | pbrook | rtl8139_io_writeb(opaque, addr + 3, (val >> 24) & 0xff); |
2961 | a41b2ff2 | pbrook | break;
|
2962 | a41b2ff2 | pbrook | } |
2963 | a41b2ff2 | pbrook | } |
2964 | a41b2ff2 | pbrook | |
2965 | a41b2ff2 | pbrook | static uint32_t rtl8139_io_readb(void *opaque, uint8_t addr) |
2966 | a41b2ff2 | pbrook | { |
2967 | a41b2ff2 | pbrook | RTL8139State *s = opaque; |
2968 | a41b2ff2 | pbrook | int ret;
|
2969 | a41b2ff2 | pbrook | |
2970 | a41b2ff2 | pbrook | switch (addr)
|
2971 | a41b2ff2 | pbrook | { |
2972 | a41b2ff2 | pbrook | case MAC0 ... MAC0+5: |
2973 | a41b2ff2 | pbrook | ret = s->phys[addr - MAC0]; |
2974 | a41b2ff2 | pbrook | break;
|
2975 | a41b2ff2 | pbrook | case MAC0+6 ... MAC0+7: |
2976 | a41b2ff2 | pbrook | ret = 0;
|
2977 | a41b2ff2 | pbrook | break;
|
2978 | a41b2ff2 | pbrook | case MAR0 ... MAR0+7: |
2979 | a41b2ff2 | pbrook | ret = s->mult[addr - MAR0]; |
2980 | a41b2ff2 | pbrook | break;
|
2981 | afe0a595 | Jason Wang | case TxStatus0 ... TxStatus0+4*4-1: |
2982 | 3e48dd4a | Stefan Hajnoczi | ret = rtl8139_TxStatus_TxAddr_read(s, s->TxStatus, TxStatus0, |
2983 | 3e48dd4a | Stefan Hajnoczi | addr, 1);
|
2984 | afe0a595 | Jason Wang | break;
|
2985 | a41b2ff2 | pbrook | case ChipCmd:
|
2986 | a41b2ff2 | pbrook | ret = rtl8139_ChipCmd_read(s); |
2987 | a41b2ff2 | pbrook | break;
|
2988 | a41b2ff2 | pbrook | case Cfg9346:
|
2989 | a41b2ff2 | pbrook | ret = rtl8139_Cfg9346_read(s); |
2990 | a41b2ff2 | pbrook | break;
|
2991 | a41b2ff2 | pbrook | case Config0:
|
2992 | a41b2ff2 | pbrook | ret = rtl8139_Config0_read(s); |
2993 | a41b2ff2 | pbrook | break;
|
2994 | a41b2ff2 | pbrook | case Config1:
|
2995 | a41b2ff2 | pbrook | ret = rtl8139_Config1_read(s); |
2996 | a41b2ff2 | pbrook | break;
|
2997 | a41b2ff2 | pbrook | case Config3:
|
2998 | a41b2ff2 | pbrook | ret = rtl8139_Config3_read(s); |
2999 | a41b2ff2 | pbrook | break;
|
3000 | a41b2ff2 | pbrook | case Config4:
|
3001 | a41b2ff2 | pbrook | ret = rtl8139_Config4_read(s); |
3002 | a41b2ff2 | pbrook | break;
|
3003 | a41b2ff2 | pbrook | case Config5:
|
3004 | a41b2ff2 | pbrook | ret = rtl8139_Config5_read(s); |
3005 | a41b2ff2 | pbrook | break;
|
3006 | a41b2ff2 | pbrook | |
3007 | a41b2ff2 | pbrook | case MediaStatus:
|
3008 | a41b2ff2 | pbrook | ret = 0xd0;
|
3009 | 7cdeb319 | Benjamin Poirier | DPRINTF("MediaStatus read 0x%x\n", ret);
|
3010 | a41b2ff2 | pbrook | break;
|
3011 | a41b2ff2 | pbrook | |
3012 | a41b2ff2 | pbrook | case HltClk:
|
3013 | a41b2ff2 | pbrook | ret = s->clock_enabled; |
3014 | 7cdeb319 | Benjamin Poirier | DPRINTF("HltClk read 0x%x\n", ret);
|
3015 | a41b2ff2 | pbrook | break;
|
3016 | a41b2ff2 | pbrook | |
3017 | a41b2ff2 | pbrook | case PCIRevisionID:
|
3018 | 6cadb320 | bellard | ret = RTL8139_PCI_REVID; |
3019 | 7cdeb319 | Benjamin Poirier | DPRINTF("PCI Revision ID read 0x%x\n", ret);
|
3020 | a41b2ff2 | pbrook | break;
|
3021 | a41b2ff2 | pbrook | |
3022 | a41b2ff2 | pbrook | case TxThresh:
|
3023 | a41b2ff2 | pbrook | ret = s->TxThresh; |
3024 | 7cdeb319 | Benjamin Poirier | DPRINTF("C+ TxThresh read(b) val=0x%02x\n", ret);
|
3025 | a41b2ff2 | pbrook | break;
|
3026 | a41b2ff2 | pbrook | |
3027 | a41b2ff2 | pbrook | case 0x43: /* Part of TxConfig register. Windows driver tries to read it */ |
3028 | a41b2ff2 | pbrook | ret = s->TxConfig >> 24;
|
3029 | 7cdeb319 | Benjamin Poirier | DPRINTF("RTL8139C TxConfig at 0x43 read(b) val=0x%02x\n", ret);
|
3030 | a41b2ff2 | pbrook | break;
|
3031 | a41b2ff2 | pbrook | |
3032 | a41b2ff2 | pbrook | default:
|
3033 | 7cdeb319 | Benjamin Poirier | DPRINTF("not implemented read(b) addr=0x%x\n", addr);
|
3034 | a41b2ff2 | pbrook | ret = 0;
|
3035 | a41b2ff2 | pbrook | break;
|
3036 | a41b2ff2 | pbrook | } |
3037 | a41b2ff2 | pbrook | |
3038 | a41b2ff2 | pbrook | return ret;
|
3039 | a41b2ff2 | pbrook | } |
3040 | a41b2ff2 | pbrook | |
3041 | a41b2ff2 | pbrook | static uint32_t rtl8139_io_readw(void *opaque, uint8_t addr) |
3042 | a41b2ff2 | pbrook | { |
3043 | a41b2ff2 | pbrook | RTL8139State *s = opaque; |
3044 | a41b2ff2 | pbrook | uint32_t ret; |
3045 | a41b2ff2 | pbrook | |
3046 | a41b2ff2 | pbrook | switch (addr)
|
3047 | a41b2ff2 | pbrook | { |
3048 | afe0a595 | Jason Wang | case TxAddr0 ... TxAddr0+4*4-1: |
3049 | 3e48dd4a | Stefan Hajnoczi | ret = rtl8139_TxStatus_TxAddr_read(s, s->TxAddr, TxAddr0, addr, 2);
|
3050 | afe0a595 | Jason Wang | break;
|
3051 | a41b2ff2 | pbrook | case IntrMask:
|
3052 | a41b2ff2 | pbrook | ret = rtl8139_IntrMask_read(s); |
3053 | a41b2ff2 | pbrook | break;
|
3054 | a41b2ff2 | pbrook | |
3055 | a41b2ff2 | pbrook | case IntrStatus:
|
3056 | a41b2ff2 | pbrook | ret = rtl8139_IntrStatus_read(s); |
3057 | a41b2ff2 | pbrook | break;
|
3058 | a41b2ff2 | pbrook | |
3059 | a41b2ff2 | pbrook | case MultiIntr:
|
3060 | a41b2ff2 | pbrook | ret = rtl8139_MultiIntr_read(s); |
3061 | a41b2ff2 | pbrook | break;
|
3062 | a41b2ff2 | pbrook | |
3063 | a41b2ff2 | pbrook | case RxBufPtr:
|
3064 | a41b2ff2 | pbrook | ret = rtl8139_RxBufPtr_read(s); |
3065 | a41b2ff2 | pbrook | break;
|
3066 | a41b2ff2 | pbrook | |
3067 | 6cadb320 | bellard | case RxBufAddr:
|
3068 | 6cadb320 | bellard | ret = rtl8139_RxBufAddr_read(s); |
3069 | 6cadb320 | bellard | break;
|
3070 | 6cadb320 | bellard | |
3071 | a41b2ff2 | pbrook | case BasicModeCtrl:
|
3072 | a41b2ff2 | pbrook | ret = rtl8139_BasicModeCtrl_read(s); |
3073 | a41b2ff2 | pbrook | break;
|
3074 | a41b2ff2 | pbrook | case BasicModeStatus:
|
3075 | a41b2ff2 | pbrook | ret = rtl8139_BasicModeStatus_read(s); |
3076 | a41b2ff2 | pbrook | break;
|
3077 | a41b2ff2 | pbrook | case NWayAdvert:
|
3078 | a41b2ff2 | pbrook | ret = s->NWayAdvert; |
3079 | 7cdeb319 | Benjamin Poirier | DPRINTF("NWayAdvert read(w) val=0x%04x\n", ret);
|
3080 | a41b2ff2 | pbrook | break;
|
3081 | a41b2ff2 | pbrook | case NWayLPAR:
|
3082 | a41b2ff2 | pbrook | ret = s->NWayLPAR; |
3083 | 7cdeb319 | Benjamin Poirier | DPRINTF("NWayLPAR read(w) val=0x%04x\n", ret);
|
3084 | a41b2ff2 | pbrook | break;
|
3085 | a41b2ff2 | pbrook | case NWayExpansion:
|
3086 | a41b2ff2 | pbrook | ret = s->NWayExpansion; |
3087 | 7cdeb319 | Benjamin Poirier | DPRINTF("NWayExpansion read(w) val=0x%04x\n", ret);
|
3088 | a41b2ff2 | pbrook | break;
|
3089 | a41b2ff2 | pbrook | |
3090 | a41b2ff2 | pbrook | case CpCmd:
|
3091 | a41b2ff2 | pbrook | ret = rtl8139_CpCmd_read(s); |
3092 | a41b2ff2 | pbrook | break;
|
3093 | a41b2ff2 | pbrook | |
3094 | 6cadb320 | bellard | case IntrMitigate:
|
3095 | 6cadb320 | bellard | ret = rtl8139_IntrMitigate_read(s); |
3096 | 6cadb320 | bellard | break;
|
3097 | 6cadb320 | bellard | |
3098 | a41b2ff2 | pbrook | case TxSummary:
|
3099 | a41b2ff2 | pbrook | ret = rtl8139_TSAD_read(s); |
3100 | a41b2ff2 | pbrook | break;
|
3101 | a41b2ff2 | pbrook | |
3102 | a41b2ff2 | pbrook | case CSCR:
|
3103 | a41b2ff2 | pbrook | ret = rtl8139_CSCR_read(s); |
3104 | a41b2ff2 | pbrook | break;
|
3105 | a41b2ff2 | pbrook | |
3106 | a41b2ff2 | pbrook | default:
|
3107 | 7cdeb319 | Benjamin Poirier | DPRINTF("ioport read(w) addr=0x%x via read(b)\n", addr);
|
3108 | a41b2ff2 | pbrook | |
3109 | a41b2ff2 | pbrook | ret = rtl8139_io_readb(opaque, addr); |
3110 | a41b2ff2 | pbrook | ret |= rtl8139_io_readb(opaque, addr + 1) << 8; |
3111 | a41b2ff2 | pbrook | |
3112 | 7cdeb319 | Benjamin Poirier | DPRINTF("ioport read(w) addr=0x%x val=0x%04x\n", addr, ret);
|
3113 | a41b2ff2 | pbrook | break;
|
3114 | a41b2ff2 | pbrook | } |
3115 | a41b2ff2 | pbrook | |
3116 | a41b2ff2 | pbrook | return ret;
|
3117 | a41b2ff2 | pbrook | } |
3118 | a41b2ff2 | pbrook | |
3119 | a41b2ff2 | pbrook | static uint32_t rtl8139_io_readl(void *opaque, uint8_t addr) |
3120 | a41b2ff2 | pbrook | { |
3121 | a41b2ff2 | pbrook | RTL8139State *s = opaque; |
3122 | a41b2ff2 | pbrook | uint32_t ret; |
3123 | a41b2ff2 | pbrook | |
3124 | a41b2ff2 | pbrook | switch (addr)
|
3125 | a41b2ff2 | pbrook | { |
3126 | a41b2ff2 | pbrook | case RxMissed:
|
3127 | a41b2ff2 | pbrook | ret = s->RxMissed; |
3128 | a41b2ff2 | pbrook | |
3129 | 7cdeb319 | Benjamin Poirier | DPRINTF("RxMissed read val=0x%08x\n", ret);
|
3130 | a41b2ff2 | pbrook | break;
|
3131 | a41b2ff2 | pbrook | |
3132 | a41b2ff2 | pbrook | case TxConfig:
|
3133 | a41b2ff2 | pbrook | ret = rtl8139_TxConfig_read(s); |
3134 | a41b2ff2 | pbrook | break;
|
3135 | a41b2ff2 | pbrook | |
3136 | a41b2ff2 | pbrook | case RxConfig:
|
3137 | a41b2ff2 | pbrook | ret = rtl8139_RxConfig_read(s); |
3138 | a41b2ff2 | pbrook | break;
|
3139 | a41b2ff2 | pbrook | |
3140 | a41b2ff2 | pbrook | case TxStatus0 ... TxStatus0+4*4-1: |
3141 | 3e48dd4a | Stefan Hajnoczi | ret = rtl8139_TxStatus_TxAddr_read(s, s->TxStatus, TxStatus0, |
3142 | 3e48dd4a | Stefan Hajnoczi | addr, 4);
|
3143 | a41b2ff2 | pbrook | break;
|
3144 | a41b2ff2 | pbrook | |
3145 | a41b2ff2 | pbrook | case TxAddr0 ... TxAddr0+4*4-1: |
3146 | a41b2ff2 | pbrook | ret = rtl8139_TxAddr_read(s, addr-TxAddr0); |
3147 | a41b2ff2 | pbrook | break;
|
3148 | a41b2ff2 | pbrook | |
3149 | a41b2ff2 | pbrook | case RxBuf:
|
3150 | a41b2ff2 | pbrook | ret = rtl8139_RxBuf_read(s); |
3151 | a41b2ff2 | pbrook | break;
|
3152 | a41b2ff2 | pbrook | |
3153 | a41b2ff2 | pbrook | case RxRingAddrLO:
|
3154 | a41b2ff2 | pbrook | ret = s->RxRingAddrLO; |
3155 | 7cdeb319 | Benjamin Poirier | DPRINTF("C+ RxRing low bits read val=0x%08x\n", ret);
|
3156 | a41b2ff2 | pbrook | break;
|
3157 | a41b2ff2 | pbrook | |
3158 | a41b2ff2 | pbrook | case RxRingAddrHI:
|
3159 | a41b2ff2 | pbrook | ret = s->RxRingAddrHI; |
3160 | 7cdeb319 | Benjamin Poirier | DPRINTF("C+ RxRing high bits read val=0x%08x\n", ret);
|
3161 | 6cadb320 | bellard | break;
|
3162 | 6cadb320 | bellard | |
3163 | 6cadb320 | bellard | case Timer:
|
3164 | 74475455 | Paolo Bonzini | ret = muldiv64(qemu_get_clock_ns(vm_clock) - s->TCTR_base, |
3165 | 05447803 | Frediano Ziglio | PCI_FREQUENCY, get_ticks_per_sec()); |
3166 | 7cdeb319 | Benjamin Poirier | DPRINTF("TCTR Timer read val=0x%08x\n", ret);
|
3167 | 6cadb320 | bellard | break;
|
3168 | 6cadb320 | bellard | |
3169 | 6cadb320 | bellard | case FlashReg:
|
3170 | 6cadb320 | bellard | ret = s->TimerInt; |
3171 | 7cdeb319 | Benjamin Poirier | DPRINTF("FlashReg TimerInt read val=0x%08x\n", ret);
|
3172 | a41b2ff2 | pbrook | break;
|
3173 | a41b2ff2 | pbrook | |
3174 | a41b2ff2 | pbrook | default:
|
3175 | 7cdeb319 | Benjamin Poirier | DPRINTF("ioport read(l) addr=0x%x via read(b)\n", addr);
|
3176 | a41b2ff2 | pbrook | |
3177 | a41b2ff2 | pbrook | ret = rtl8139_io_readb(opaque, addr); |
3178 | a41b2ff2 | pbrook | ret |= rtl8139_io_readb(opaque, addr + 1) << 8; |
3179 | a41b2ff2 | pbrook | ret |= rtl8139_io_readb(opaque, addr + 2) << 16; |
3180 | a41b2ff2 | pbrook | ret |= rtl8139_io_readb(opaque, addr + 3) << 24; |
3181 | a41b2ff2 | pbrook | |
3182 | 7cdeb319 | Benjamin Poirier | DPRINTF("read(l) addr=0x%x val=%08x\n", addr, ret);
|
3183 | a41b2ff2 | pbrook | break;
|
3184 | a41b2ff2 | pbrook | } |
3185 | a41b2ff2 | pbrook | |
3186 | a41b2ff2 | pbrook | return ret;
|
3187 | a41b2ff2 | pbrook | } |
3188 | a41b2ff2 | pbrook | |
3189 | a41b2ff2 | pbrook | /* */
|
3190 | a41b2ff2 | pbrook | |
3191 | a41b2ff2 | pbrook | static void rtl8139_ioport_writeb(void *opaque, uint32_t addr, uint32_t val) |
3192 | a41b2ff2 | pbrook | { |
3193 | a41b2ff2 | pbrook | rtl8139_io_writeb(opaque, addr & 0xFF, val);
|
3194 | a41b2ff2 | pbrook | } |
3195 | a41b2ff2 | pbrook | |
3196 | a41b2ff2 | pbrook | static void rtl8139_ioport_writew(void *opaque, uint32_t addr, uint32_t val) |
3197 | a41b2ff2 | pbrook | { |
3198 | a41b2ff2 | pbrook | rtl8139_io_writew(opaque, addr & 0xFF, val);
|
3199 | a41b2ff2 | pbrook | } |
3200 | a41b2ff2 | pbrook | |
3201 | a41b2ff2 | pbrook | static void rtl8139_ioport_writel(void *opaque, uint32_t addr, uint32_t val) |
3202 | a41b2ff2 | pbrook | { |
3203 | a41b2ff2 | pbrook | rtl8139_io_writel(opaque, addr & 0xFF, val);
|
3204 | a41b2ff2 | pbrook | } |
3205 | a41b2ff2 | pbrook | |
3206 | a41b2ff2 | pbrook | static uint32_t rtl8139_ioport_readb(void *opaque, uint32_t addr) |
3207 | a41b2ff2 | pbrook | { |
3208 | a41b2ff2 | pbrook | return rtl8139_io_readb(opaque, addr & 0xFF); |
3209 | a41b2ff2 | pbrook | } |
3210 | a41b2ff2 | pbrook | |
3211 | a41b2ff2 | pbrook | static uint32_t rtl8139_ioport_readw(void *opaque, uint32_t addr) |
3212 | a41b2ff2 | pbrook | { |
3213 | a41b2ff2 | pbrook | return rtl8139_io_readw(opaque, addr & 0xFF); |
3214 | a41b2ff2 | pbrook | } |
3215 | a41b2ff2 | pbrook | |
3216 | a41b2ff2 | pbrook | static uint32_t rtl8139_ioport_readl(void *opaque, uint32_t addr) |
3217 | a41b2ff2 | pbrook | { |
3218 | a41b2ff2 | pbrook | return rtl8139_io_readl(opaque, addr & 0xFF); |
3219 | a41b2ff2 | pbrook | } |
3220 | a41b2ff2 | pbrook | |
3221 | a41b2ff2 | pbrook | /* */
|
3222 | a41b2ff2 | pbrook | |
3223 | c227f099 | Anthony Liguori | static void rtl8139_mmio_writeb(void *opaque, target_phys_addr_t addr, uint32_t val) |
3224 | a41b2ff2 | pbrook | { |
3225 | a41b2ff2 | pbrook | rtl8139_io_writeb(opaque, addr & 0xFF, val);
|
3226 | a41b2ff2 | pbrook | } |
3227 | a41b2ff2 | pbrook | |
3228 | c227f099 | Anthony Liguori | static void rtl8139_mmio_writew(void *opaque, target_phys_addr_t addr, uint32_t val) |
3229 | a41b2ff2 | pbrook | { |
3230 | a41b2ff2 | pbrook | rtl8139_io_writew(opaque, addr & 0xFF, val);
|
3231 | a41b2ff2 | pbrook | } |
3232 | a41b2ff2 | pbrook | |
3233 | c227f099 | Anthony Liguori | static void rtl8139_mmio_writel(void *opaque, target_phys_addr_t addr, uint32_t val) |
3234 | a41b2ff2 | pbrook | { |
3235 | a41b2ff2 | pbrook | rtl8139_io_writel(opaque, addr & 0xFF, val);
|
3236 | a41b2ff2 | pbrook | } |
3237 | a41b2ff2 | pbrook | |
3238 | c227f099 | Anthony Liguori | static uint32_t rtl8139_mmio_readb(void *opaque, target_phys_addr_t addr) |
3239 | a41b2ff2 | pbrook | { |
3240 | a41b2ff2 | pbrook | return rtl8139_io_readb(opaque, addr & 0xFF); |
3241 | a41b2ff2 | pbrook | } |
3242 | a41b2ff2 | pbrook | |
3243 | c227f099 | Anthony Liguori | static uint32_t rtl8139_mmio_readw(void *opaque, target_phys_addr_t addr) |
3244 | a41b2ff2 | pbrook | { |
3245 | 5fedc612 | aurel32 | uint32_t val = rtl8139_io_readw(opaque, addr & 0xFF);
|
3246 | 5fedc612 | aurel32 | return val;
|
3247 | a41b2ff2 | pbrook | } |
3248 | a41b2ff2 | pbrook | |
3249 | c227f099 | Anthony Liguori | static uint32_t rtl8139_mmio_readl(void *opaque, target_phys_addr_t addr) |
3250 | a41b2ff2 | pbrook | { |
3251 | 5fedc612 | aurel32 | uint32_t val = rtl8139_io_readl(opaque, addr & 0xFF);
|
3252 | 5fedc612 | aurel32 | return val;
|
3253 | a41b2ff2 | pbrook | } |
3254 | a41b2ff2 | pbrook | |
3255 | 060110c3 | Juan Quintela | static int rtl8139_post_load(void *opaque, int version_id) |
3256 | a41b2ff2 | pbrook | { |
3257 | 6597ebbb | Juan Quintela | RTL8139State* s = opaque; |
3258 | 74475455 | Paolo Bonzini | rtl8139_set_next_tctr_time(s, qemu_get_clock_ns(vm_clock)); |
3259 | 060110c3 | Juan Quintela | if (version_id < 4) { |
3260 | 2c3891ab | aliguori | s->cplus_enabled = s->CpCmd != 0;
|
3261 | 2c3891ab | aliguori | } |
3262 | 2c3891ab | aliguori | |
3263 | a41b2ff2 | pbrook | return 0; |
3264 | a41b2ff2 | pbrook | } |
3265 | a41b2ff2 | pbrook | |
3266 | c574ba5a | Alex Williamson | static bool rtl8139_hotplug_ready_needed(void *opaque) |
3267 | c574ba5a | Alex Williamson | { |
3268 | c574ba5a | Alex Williamson | return qdev_machine_modified();
|
3269 | c574ba5a | Alex Williamson | } |
3270 | c574ba5a | Alex Williamson | |
3271 | c574ba5a | Alex Williamson | static const VMStateDescription vmstate_rtl8139_hotplug_ready ={ |
3272 | c574ba5a | Alex Williamson | .name = "rtl8139/hotplug_ready",
|
3273 | c574ba5a | Alex Williamson | .version_id = 1,
|
3274 | c574ba5a | Alex Williamson | .minimum_version_id = 1,
|
3275 | c574ba5a | Alex Williamson | .minimum_version_id_old = 1,
|
3276 | c574ba5a | Alex Williamson | .fields = (VMStateField []) { |
3277 | c574ba5a | Alex Williamson | VMSTATE_END_OF_LIST() |
3278 | c574ba5a | Alex Williamson | } |
3279 | c574ba5a | Alex Williamson | }; |
3280 | c574ba5a | Alex Williamson | |
3281 | 05447803 | Frediano Ziglio | static void rtl8139_pre_save(void *opaque) |
3282 | 05447803 | Frediano Ziglio | { |
3283 | 05447803 | Frediano Ziglio | RTL8139State* s = opaque; |
3284 | 74475455 | Paolo Bonzini | int64_t current_time = qemu_get_clock_ns(vm_clock); |
3285 | 05447803 | Frediano Ziglio | |
3286 | 05447803 | Frediano Ziglio | /* set IntrStatus correctly */
|
3287 | 05447803 | Frediano Ziglio | rtl8139_set_next_tctr_time(s, current_time); |
3288 | 05447803 | Frediano Ziglio | s->TCTR = muldiv64(current_time - s->TCTR_base, PCI_FREQUENCY, |
3289 | 05447803 | Frediano Ziglio | get_ticks_per_sec()); |
3290 | bd80f3fc | Avi Kivity | s->rtl8139_mmio_io_addr_dummy = 0;
|
3291 | 05447803 | Frediano Ziglio | } |
3292 | 05447803 | Frediano Ziglio | |
3293 | 060110c3 | Juan Quintela | static const VMStateDescription vmstate_rtl8139 = { |
3294 | 060110c3 | Juan Quintela | .name = "rtl8139",
|
3295 | 060110c3 | Juan Quintela | .version_id = 4,
|
3296 | 060110c3 | Juan Quintela | .minimum_version_id = 3,
|
3297 | 060110c3 | Juan Quintela | .minimum_version_id_old = 3,
|
3298 | 060110c3 | Juan Quintela | .post_load = rtl8139_post_load, |
3299 | 05447803 | Frediano Ziglio | .pre_save = rtl8139_pre_save, |
3300 | 060110c3 | Juan Quintela | .fields = (VMStateField []) { |
3301 | 060110c3 | Juan Quintela | VMSTATE_PCI_DEVICE(dev, RTL8139State), |
3302 | 060110c3 | Juan Quintela | VMSTATE_PARTIAL_BUFFER(phys, RTL8139State, 6),
|
3303 | 060110c3 | Juan Quintela | VMSTATE_BUFFER(mult, RTL8139State), |
3304 | 060110c3 | Juan Quintela | VMSTATE_UINT32_ARRAY(TxStatus, RTL8139State, 4),
|
3305 | 060110c3 | Juan Quintela | VMSTATE_UINT32_ARRAY(TxAddr, RTL8139State, 4),
|
3306 | 060110c3 | Juan Quintela | |
3307 | 060110c3 | Juan Quintela | VMSTATE_UINT32(RxBuf, RTL8139State), |
3308 | 060110c3 | Juan Quintela | VMSTATE_UINT32(RxBufferSize, RTL8139State), |
3309 | 060110c3 | Juan Quintela | VMSTATE_UINT32(RxBufPtr, RTL8139State), |
3310 | 060110c3 | Juan Quintela | VMSTATE_UINT32(RxBufAddr, RTL8139State), |
3311 | 060110c3 | Juan Quintela | |
3312 | 060110c3 | Juan Quintela | VMSTATE_UINT16(IntrStatus, RTL8139State), |
3313 | 060110c3 | Juan Quintela | VMSTATE_UINT16(IntrMask, RTL8139State), |
3314 | 060110c3 | Juan Quintela | |
3315 | 060110c3 | Juan Quintela | VMSTATE_UINT32(TxConfig, RTL8139State), |
3316 | 060110c3 | Juan Quintela | VMSTATE_UINT32(RxConfig, RTL8139State), |
3317 | 060110c3 | Juan Quintela | VMSTATE_UINT32(RxMissed, RTL8139State), |
3318 | 060110c3 | Juan Quintela | VMSTATE_UINT16(CSCR, RTL8139State), |
3319 | 060110c3 | Juan Quintela | |
3320 | 060110c3 | Juan Quintela | VMSTATE_UINT8(Cfg9346, RTL8139State), |
3321 | 060110c3 | Juan Quintela | VMSTATE_UINT8(Config0, RTL8139State), |
3322 | 060110c3 | Juan Quintela | VMSTATE_UINT8(Config1, RTL8139State), |
3323 | 060110c3 | Juan Quintela | VMSTATE_UINT8(Config3, RTL8139State), |
3324 | 060110c3 | Juan Quintela | VMSTATE_UINT8(Config4, RTL8139State), |
3325 | 060110c3 | Juan Quintela | VMSTATE_UINT8(Config5, RTL8139State), |
3326 | 060110c3 | Juan Quintela | |
3327 | 060110c3 | Juan Quintela | VMSTATE_UINT8(clock_enabled, RTL8139State), |
3328 | 060110c3 | Juan Quintela | VMSTATE_UINT8(bChipCmdState, RTL8139State), |
3329 | 060110c3 | Juan Quintela | |
3330 | 060110c3 | Juan Quintela | VMSTATE_UINT16(MultiIntr, RTL8139State), |
3331 | 060110c3 | Juan Quintela | |
3332 | 060110c3 | Juan Quintela | VMSTATE_UINT16(BasicModeCtrl, RTL8139State), |
3333 | 060110c3 | Juan Quintela | VMSTATE_UINT16(BasicModeStatus, RTL8139State), |
3334 | 060110c3 | Juan Quintela | VMSTATE_UINT16(NWayAdvert, RTL8139State), |
3335 | 060110c3 | Juan Quintela | VMSTATE_UINT16(NWayLPAR, RTL8139State), |
3336 | 060110c3 | Juan Quintela | VMSTATE_UINT16(NWayExpansion, RTL8139State), |
3337 | 060110c3 | Juan Quintela | |
3338 | 060110c3 | Juan Quintela | VMSTATE_UINT16(CpCmd, RTL8139State), |
3339 | 060110c3 | Juan Quintela | VMSTATE_UINT8(TxThresh, RTL8139State), |
3340 | 060110c3 | Juan Quintela | |
3341 | 060110c3 | Juan Quintela | VMSTATE_UNUSED(4),
|
3342 | 060110c3 | Juan Quintela | VMSTATE_MACADDR(conf.macaddr, RTL8139State), |
3343 | c574ba5a | Alex Williamson | VMSTATE_INT32(rtl8139_mmio_io_addr_dummy, RTL8139State), |
3344 | 060110c3 | Juan Quintela | |
3345 | 060110c3 | Juan Quintela | VMSTATE_UINT32(currTxDesc, RTL8139State), |
3346 | 060110c3 | Juan Quintela | VMSTATE_UINT32(currCPlusRxDesc, RTL8139State), |
3347 | 060110c3 | Juan Quintela | VMSTATE_UINT32(currCPlusTxDesc, RTL8139State), |
3348 | 060110c3 | Juan Quintela | VMSTATE_UINT32(RxRingAddrLO, RTL8139State), |
3349 | 060110c3 | Juan Quintela | VMSTATE_UINT32(RxRingAddrHI, RTL8139State), |
3350 | 060110c3 | Juan Quintela | |
3351 | 060110c3 | Juan Quintela | VMSTATE_UINT16_ARRAY(eeprom.contents, RTL8139State, EEPROM_9346_SIZE), |
3352 | 060110c3 | Juan Quintela | VMSTATE_INT32(eeprom.mode, RTL8139State), |
3353 | 060110c3 | Juan Quintela | VMSTATE_UINT32(eeprom.tick, RTL8139State), |
3354 | 060110c3 | Juan Quintela | VMSTATE_UINT8(eeprom.address, RTL8139State), |
3355 | 060110c3 | Juan Quintela | VMSTATE_UINT16(eeprom.input, RTL8139State), |
3356 | 060110c3 | Juan Quintela | VMSTATE_UINT16(eeprom.output, RTL8139State), |
3357 | 060110c3 | Juan Quintela | |
3358 | 060110c3 | Juan Quintela | VMSTATE_UINT8(eeprom.eecs, RTL8139State), |
3359 | 060110c3 | Juan Quintela | VMSTATE_UINT8(eeprom.eesk, RTL8139State), |
3360 | 060110c3 | Juan Quintela | VMSTATE_UINT8(eeprom.eedi, RTL8139State), |
3361 | 060110c3 | Juan Quintela | VMSTATE_UINT8(eeprom.eedo, RTL8139State), |
3362 | 060110c3 | Juan Quintela | |
3363 | 060110c3 | Juan Quintela | VMSTATE_UINT32(TCTR, RTL8139State), |
3364 | 060110c3 | Juan Quintela | VMSTATE_UINT32(TimerInt, RTL8139State), |
3365 | 060110c3 | Juan Quintela | VMSTATE_INT64(TCTR_base, RTL8139State), |
3366 | 060110c3 | Juan Quintela | |
3367 | 060110c3 | Juan Quintela | VMSTATE_STRUCT(tally_counters, RTL8139State, 0,
|
3368 | 060110c3 | Juan Quintela | vmstate_tally_counters, RTL8139TallyCounters), |
3369 | 060110c3 | Juan Quintela | |
3370 | 060110c3 | Juan Quintela | VMSTATE_UINT32_V(cplus_enabled, RTL8139State, 4),
|
3371 | 060110c3 | Juan Quintela | VMSTATE_END_OF_LIST() |
3372 | c574ba5a | Alex Williamson | }, |
3373 | c574ba5a | Alex Williamson | .subsections = (VMStateSubsection []) { |
3374 | c574ba5a | Alex Williamson | { |
3375 | c574ba5a | Alex Williamson | .vmsd = &vmstate_rtl8139_hotplug_ready, |
3376 | c574ba5a | Alex Williamson | .needed = rtl8139_hotplug_ready_needed, |
3377 | c574ba5a | Alex Williamson | }, { |
3378 | c574ba5a | Alex Williamson | /* empty */
|
3379 | c574ba5a | Alex Williamson | } |
3380 | 060110c3 | Juan Quintela | } |
3381 | 060110c3 | Juan Quintela | }; |
3382 | 060110c3 | Juan Quintela | |
3383 | a41b2ff2 | pbrook | /***********************************************************/
|
3384 | a41b2ff2 | pbrook | /* PCI RTL8139 definitions */
|
3385 | a41b2ff2 | pbrook | |
3386 | bd80f3fc | Avi Kivity | static const MemoryRegionPortio rtl8139_portio[] = { |
3387 | bd80f3fc | Avi Kivity | { 0, 0x100, 1, .read = rtl8139_ioport_readb, }, |
3388 | bd80f3fc | Avi Kivity | { 0, 0x100, 1, .write = rtl8139_ioport_writeb, }, |
3389 | bd80f3fc | Avi Kivity | { 0, 0x100, 2, .read = rtl8139_ioport_readw, }, |
3390 | bd80f3fc | Avi Kivity | { 0, 0x100, 2, .write = rtl8139_ioport_writew, }, |
3391 | bd80f3fc | Avi Kivity | { 0, 0x100, 4, .read = rtl8139_ioport_readl, }, |
3392 | bd80f3fc | Avi Kivity | { 0, 0x100, 4, .write = rtl8139_ioport_writel, }, |
3393 | bd80f3fc | Avi Kivity | PORTIO_END_OF_LIST() |
3394 | bd80f3fc | Avi Kivity | }; |
3395 | a41b2ff2 | pbrook | |
3396 | bd80f3fc | Avi Kivity | static const MemoryRegionOps rtl8139_io_ops = { |
3397 | bd80f3fc | Avi Kivity | .old_portio = rtl8139_portio, |
3398 | bd80f3fc | Avi Kivity | .endianness = DEVICE_LITTLE_ENDIAN, |
3399 | a41b2ff2 | pbrook | }; |
3400 | a41b2ff2 | pbrook | |
3401 | bd80f3fc | Avi Kivity | static const MemoryRegionOps rtl8139_mmio_ops = { |
3402 | bd80f3fc | Avi Kivity | .old_mmio = { |
3403 | bd80f3fc | Avi Kivity | .read = { |
3404 | bd80f3fc | Avi Kivity | rtl8139_mmio_readb, |
3405 | bd80f3fc | Avi Kivity | rtl8139_mmio_readw, |
3406 | bd80f3fc | Avi Kivity | rtl8139_mmio_readl, |
3407 | bd80f3fc | Avi Kivity | }, |
3408 | bd80f3fc | Avi Kivity | .write = { |
3409 | bd80f3fc | Avi Kivity | rtl8139_mmio_writeb, |
3410 | bd80f3fc | Avi Kivity | rtl8139_mmio_writew, |
3411 | bd80f3fc | Avi Kivity | rtl8139_mmio_writel, |
3412 | bd80f3fc | Avi Kivity | }, |
3413 | bd80f3fc | Avi Kivity | }, |
3414 | bd80f3fc | Avi Kivity | .endianness = DEVICE_LITTLE_ENDIAN, |
3415 | a41b2ff2 | pbrook | }; |
3416 | a41b2ff2 | pbrook | |
3417 | 6cadb320 | bellard | static void rtl8139_timer(void *opaque) |
3418 | 6cadb320 | bellard | { |
3419 | 6cadb320 | bellard | RTL8139State *s = opaque; |
3420 | 6cadb320 | bellard | |
3421 | 6cadb320 | bellard | if (!s->clock_enabled)
|
3422 | 6cadb320 | bellard | { |
3423 | 7cdeb319 | Benjamin Poirier | DPRINTF(">>> timer: clock is not running\n");
|
3424 | 6cadb320 | bellard | return;
|
3425 | 6cadb320 | bellard | } |
3426 | 6cadb320 | bellard | |
3427 | 05447803 | Frediano Ziglio | s->IntrStatus |= PCSTimeout; |
3428 | 05447803 | Frediano Ziglio | rtl8139_update_irq(s); |
3429 | 74475455 | Paolo Bonzini | rtl8139_set_next_tctr_time(s, qemu_get_clock_ns(vm_clock)); |
3430 | 6cadb320 | bellard | } |
3431 | 6cadb320 | bellard | |
3432 | 1673ad51 | Mark McLoughlin | static void rtl8139_cleanup(VLANClientState *nc) |
3433 | b946a153 | aliguori | { |
3434 | 1673ad51 | Mark McLoughlin | RTL8139State *s = DO_UPCAST(NICState, nc, nc)->opaque; |
3435 | b946a153 | aliguori | |
3436 | 1673ad51 | Mark McLoughlin | s->nic = NULL;
|
3437 | 254111ec | Gerd Hoffmann | } |
3438 | 254111ec | Gerd Hoffmann | |
3439 | 254111ec | Gerd Hoffmann | static int pci_rtl8139_uninit(PCIDevice *dev) |
3440 | 254111ec | Gerd Hoffmann | { |
3441 | 254111ec | Gerd Hoffmann | RTL8139State *s = DO_UPCAST(RTL8139State, dev, dev); |
3442 | 254111ec | Gerd Hoffmann | |
3443 | bd80f3fc | Avi Kivity | memory_region_destroy(&s->bar_io); |
3444 | bd80f3fc | Avi Kivity | memory_region_destroy(&s->bar_mem); |
3445 | b946a153 | aliguori | if (s->cplus_txbuffer) {
|
3446 | 7267c094 | Anthony Liguori | g_free(s->cplus_txbuffer); |
3447 | b946a153 | aliguori | s->cplus_txbuffer = NULL;
|
3448 | b946a153 | aliguori | } |
3449 | b946a153 | aliguori | qemu_del_timer(s->timer); |
3450 | b946a153 | aliguori | qemu_free_timer(s->timer); |
3451 | 1673ad51 | Mark McLoughlin | qemu_del_vlan_client(&s->nic->nc); |
3452 | b946a153 | aliguori | return 0; |
3453 | b946a153 | aliguori | } |
3454 | b946a153 | aliguori | |
3455 | 1673ad51 | Mark McLoughlin | static NetClientInfo net_rtl8139_info = {
|
3456 | 1673ad51 | Mark McLoughlin | .type = NET_CLIENT_TYPE_NIC, |
3457 | 1673ad51 | Mark McLoughlin | .size = sizeof(NICState),
|
3458 | 1673ad51 | Mark McLoughlin | .can_receive = rtl8139_can_receive, |
3459 | 1673ad51 | Mark McLoughlin | .receive = rtl8139_receive, |
3460 | 1673ad51 | Mark McLoughlin | .cleanup = rtl8139_cleanup, |
3461 | 1673ad51 | Mark McLoughlin | }; |
3462 | 1673ad51 | Mark McLoughlin | |
3463 | 81a322d4 | Gerd Hoffmann | static int pci_rtl8139_init(PCIDevice *dev) |
3464 | a41b2ff2 | pbrook | { |
3465 | efd6dd45 | Juan Quintela | RTL8139State * s = DO_UPCAST(RTL8139State, dev, dev); |
3466 | a41b2ff2 | pbrook | uint8_t *pci_conf; |
3467 | 3b46e624 | ths | |
3468 | efd6dd45 | Juan Quintela | pci_conf = s->dev.config; |
3469 | 817e0b6f | Michael S. Tsirkin | pci_conf[PCI_INTERRUPT_PIN] = 1; /* interrupt pin A */ |
3470 | 0b5b3547 | Michael S. Tsirkin | /* TODO: start of capability list, but no capability
|
3471 | 0b5b3547 | Michael S. Tsirkin | * list bit in status register, and offset 0xdc seems unused. */
|
3472 | 0b5b3547 | Michael S. Tsirkin | pci_conf[PCI_CAPABILITY_LIST] = 0xdc;
|
3473 | a41b2ff2 | pbrook | |
3474 | bd80f3fc | Avi Kivity | memory_region_init_io(&s->bar_io, &rtl8139_io_ops, s, "rtl8139", 0x100); |
3475 | bd80f3fc | Avi Kivity | memory_region_init_io(&s->bar_mem, &rtl8139_mmio_ops, s, "rtl8139", 0x100); |
3476 | e824b2cc | Avi Kivity | pci_register_bar(&s->dev, 0, PCI_BASE_ADDRESS_SPACE_IO, &s->bar_io);
|
3477 | e824b2cc | Avi Kivity | pci_register_bar(&s->dev, 1, PCI_BASE_ADDRESS_SPACE_MEMORY, &s->bar_mem);
|
3478 | a41b2ff2 | pbrook | |
3479 | 254111ec | Gerd Hoffmann | qemu_macaddr_default_if_unset(&s->conf.macaddr); |
3480 | c1699988 | Glauber Costa | |
3481 | 7165448a | William Dauchy | /* prepare eeprom */
|
3482 | 7165448a | William Dauchy | s->eeprom.contents[0] = 0x8129; |
3483 | 7165448a | William Dauchy | #if 1 |
3484 | 7165448a | William Dauchy | /* PCI vendor and device ID should be mirrored here */
|
3485 | 7165448a | William Dauchy | s->eeprom.contents[1] = PCI_VENDOR_ID_REALTEK;
|
3486 | 7165448a | William Dauchy | s->eeprom.contents[2] = PCI_DEVICE_ID_REALTEK_8139;
|
3487 | 7165448a | William Dauchy | #endif
|
3488 | 7165448a | William Dauchy | s->eeprom.contents[7] = s->conf.macaddr.a[0] | s->conf.macaddr.a[1] << 8; |
3489 | 7165448a | William Dauchy | s->eeprom.contents[8] = s->conf.macaddr.a[2] | s->conf.macaddr.a[3] << 8; |
3490 | 7165448a | William Dauchy | s->eeprom.contents[9] = s->conf.macaddr.a[4] | s->conf.macaddr.a[5] << 8; |
3491 | 7165448a | William Dauchy | |
3492 | 1673ad51 | Mark McLoughlin | s->nic = qemu_new_nic(&net_rtl8139_info, &s->conf, |
3493 | f79f2bfc | Anthony Liguori | object_get_typename(OBJECT(dev)), dev->qdev.id, s); |
3494 | 1673ad51 | Mark McLoughlin | qemu_format_nic_info_str(&s->nic->nc, s->conf.macaddr.a); |
3495 | 6cadb320 | bellard | |
3496 | 6cadb320 | bellard | s->cplus_txbuffer = NULL;
|
3497 | 6cadb320 | bellard | s->cplus_txbuffer_len = 0;
|
3498 | 6cadb320 | bellard | s->cplus_txbuffer_offset = 0;
|
3499 | 3b46e624 | ths | |
3500 | 05447803 | Frediano Ziglio | s->TimerExpire = 0;
|
3501 | 74475455 | Paolo Bonzini | s->timer = qemu_new_timer_ns(vm_clock, rtl8139_timer, s); |
3502 | 74475455 | Paolo Bonzini | rtl8139_set_next_tctr_time(s, qemu_get_clock_ns(vm_clock)); |
3503 | 1ca4d09a | Gleb Natapov | |
3504 | 1ca4d09a | Gleb Natapov | add_boot_device_path(s->conf.bootindex, &dev->qdev, "/ethernet-phy@0");
|
3505 | 1ca4d09a | Gleb Natapov | |
3506 | 81a322d4 | Gerd Hoffmann | return 0; |
3507 | a41b2ff2 | pbrook | } |
3508 | 9d07d757 | Paul Brook | |
3509 | 40021f08 | Anthony Liguori | static Property rtl8139_properties[] = {
|
3510 | 40021f08 | Anthony Liguori | DEFINE_NIC_PROPERTIES(RTL8139State, conf), |
3511 | 40021f08 | Anthony Liguori | DEFINE_PROP_END_OF_LIST(), |
3512 | 40021f08 | Anthony Liguori | }; |
3513 | 40021f08 | Anthony Liguori | |
3514 | 40021f08 | Anthony Liguori | static void rtl8139_class_init(ObjectClass *klass, void *data) |
3515 | 40021f08 | Anthony Liguori | { |
3516 | 39bffca2 | Anthony Liguori | DeviceClass *dc = DEVICE_CLASS(klass); |
3517 | 40021f08 | Anthony Liguori | PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); |
3518 | 40021f08 | Anthony Liguori | |
3519 | 40021f08 | Anthony Liguori | k->init = pci_rtl8139_init; |
3520 | 40021f08 | Anthony Liguori | k->exit = pci_rtl8139_uninit; |
3521 | 40021f08 | Anthony Liguori | k->romfile = "pxe-rtl8139.rom";
|
3522 | 40021f08 | Anthony Liguori | k->vendor_id = PCI_VENDOR_ID_REALTEK; |
3523 | 40021f08 | Anthony Liguori | k->device_id = PCI_DEVICE_ID_REALTEK_8139; |
3524 | 40021f08 | Anthony Liguori | k->revision = RTL8139_PCI_REVID; /* >=0x20 is for 8139C+ */
|
3525 | 40021f08 | Anthony Liguori | k->class_id = PCI_CLASS_NETWORK_ETHERNET; |
3526 | 39bffca2 | Anthony Liguori | dc->reset = rtl8139_reset; |
3527 | 39bffca2 | Anthony Liguori | dc->vmsd = &vmstate_rtl8139; |
3528 | 39bffca2 | Anthony Liguori | dc->props = rtl8139_properties; |
3529 | 40021f08 | Anthony Liguori | } |
3530 | 40021f08 | Anthony Liguori | |
3531 | 39bffca2 | Anthony Liguori | static TypeInfo rtl8139_info = {
|
3532 | 39bffca2 | Anthony Liguori | .name = "rtl8139",
|
3533 | 39bffca2 | Anthony Liguori | .parent = TYPE_PCI_DEVICE, |
3534 | 39bffca2 | Anthony Liguori | .instance_size = sizeof(RTL8139State),
|
3535 | 39bffca2 | Anthony Liguori | .class_init = rtl8139_class_init, |
3536 | 0aab0d3a | Gerd Hoffmann | }; |
3537 | 0aab0d3a | Gerd Hoffmann | |
3538 | 83f7d43a | Andreas Färber | static void rtl8139_register_types(void) |
3539 | 9d07d757 | Paul Brook | { |
3540 | 39bffca2 | Anthony Liguori | type_register_static(&rtl8139_info); |
3541 | 9d07d757 | Paul Brook | } |
3542 | 9d07d757 | Paul Brook | |
3543 | 83f7d43a | Andreas Färber | type_init(rtl8139_register_types) |