root / hw / spapr_pci.c @ 8294a64d
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1 | 3384f95c | David Gibson | /*
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2 | 3384f95c | David Gibson | * QEMU sPAPR PCI host originated from Uninorth PCI host
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3 | 3384f95c | David Gibson | *
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4 | 3384f95c | David Gibson | * Copyright (c) 2011 Alexey Kardashevskiy, IBM Corporation.
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5 | 3384f95c | David Gibson | * Copyright (C) 2011 David Gibson, IBM Corporation.
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6 | 3384f95c | David Gibson | *
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7 | 3384f95c | David Gibson | * Permission is hereby granted, free of charge, to any person obtaining a copy
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8 | 3384f95c | David Gibson | * of this software and associated documentation files (the "Software"), to deal
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9 | 3384f95c | David Gibson | * in the Software without restriction, including without limitation the rights
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10 | 3384f95c | David Gibson | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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11 | 3384f95c | David Gibson | * copies of the Software, and to permit persons to whom the Software is
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12 | 3384f95c | David Gibson | * furnished to do so, subject to the following conditions:
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13 | 3384f95c | David Gibson | *
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14 | 3384f95c | David Gibson | * The above copyright notice and this permission notice shall be included in
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15 | 3384f95c | David Gibson | * all copies or substantial portions of the Software.
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16 | 3384f95c | David Gibson | *
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17 | 3384f95c | David Gibson | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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18 | 3384f95c | David Gibson | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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19 | 3384f95c | David Gibson | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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20 | 3384f95c | David Gibson | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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21 | 3384f95c | David Gibson | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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22 | 3384f95c | David Gibson | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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23 | 3384f95c | David Gibson | * THE SOFTWARE.
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24 | 3384f95c | David Gibson | */
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25 | 3384f95c | David Gibson | #include "hw.h" |
26 | 3384f95c | David Gibson | #include "pci.h" |
27 | 3384f95c | David Gibson | #include "pci_host.h" |
28 | 3384f95c | David Gibson | #include "hw/spapr.h" |
29 | 3384f95c | David Gibson | #include "hw/spapr_pci.h" |
30 | 3384f95c | David Gibson | #include "exec-memory.h" |
31 | 3384f95c | David Gibson | #include <libfdt.h> |
32 | 3384f95c | David Gibson | |
33 | 3384f95c | David Gibson | #include "hw/pci_internals.h" |
34 | 3384f95c | David Gibson | |
35 | 3384f95c | David Gibson | static PCIDevice *find_dev(sPAPREnvironment *spapr,
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36 | 3384f95c | David Gibson | uint64_t buid, uint32_t config_addr) |
37 | 3384f95c | David Gibson | { |
38 | 3384f95c | David Gibson | DeviceState *qdev; |
39 | 3384f95c | David Gibson | int devfn = (config_addr >> 8) & 0xFF; |
40 | 3384f95c | David Gibson | sPAPRPHBState *phb; |
41 | 3384f95c | David Gibson | |
42 | 3384f95c | David Gibson | QLIST_FOREACH(phb, &spapr->phbs, list) { |
43 | 3384f95c | David Gibson | if (phb->buid != buid) {
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44 | 3384f95c | David Gibson | continue;
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45 | 3384f95c | David Gibson | } |
46 | 3384f95c | David Gibson | |
47 | 3a26360d | Anthony Liguori | QTAILQ_FOREACH(qdev, &phb->host_state.bus->qbus.children, sibling) { |
48 | 3384f95c | David Gibson | PCIDevice *dev = (PCIDevice *)qdev; |
49 | 3384f95c | David Gibson | if (dev->devfn == devfn) {
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50 | 3384f95c | David Gibson | return dev;
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51 | 3384f95c | David Gibson | } |
52 | 3384f95c | David Gibson | } |
53 | 3384f95c | David Gibson | } |
54 | 3384f95c | David Gibson | |
55 | 3384f95c | David Gibson | return NULL; |
56 | 3384f95c | David Gibson | } |
57 | 3384f95c | David Gibson | |
58 | 3f7565c9 | Benjamin Herrenschmidt | static uint32_t rtas_pci_cfgaddr(uint32_t arg)
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59 | 3f7565c9 | Benjamin Herrenschmidt | { |
60 | 92615a5a | David Gibson | /* This handles the encoding of extended config space addresses */
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61 | 3f7565c9 | Benjamin Herrenschmidt | return ((arg >> 20) & 0xf00) | (arg & 0xff); |
62 | 3f7565c9 | Benjamin Herrenschmidt | } |
63 | 3f7565c9 | Benjamin Herrenschmidt | |
64 | 92615a5a | David Gibson | static void finish_read_pci_config(sPAPREnvironment *spapr, uint64_t buid, |
65 | 92615a5a | David Gibson | uint32_t addr, uint32_t size, |
66 | 92615a5a | David Gibson | target_ulong rets) |
67 | 88045ac5 | Alexander Graf | { |
68 | 92615a5a | David Gibson | PCIDevice *pci_dev; |
69 | 92615a5a | David Gibson | uint32_t val; |
70 | 92615a5a | David Gibson | |
71 | 92615a5a | David Gibson | if ((size != 1) && (size != 2) && (size != 4)) { |
72 | 92615a5a | David Gibson | /* access must be 1, 2 or 4 bytes */
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73 | 92615a5a | David Gibson | rtas_st(rets, 0, -1); |
74 | 92615a5a | David Gibson | return;
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75 | 88045ac5 | Alexander Graf | } |
76 | 88045ac5 | Alexander Graf | |
77 | 92615a5a | David Gibson | pci_dev = find_dev(spapr, buid, addr); |
78 | 92615a5a | David Gibson | addr = rtas_pci_cfgaddr(addr); |
79 | 92615a5a | David Gibson | |
80 | 92615a5a | David Gibson | if (!pci_dev || (addr % size) || (addr >= pci_config_size(pci_dev))) {
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81 | 92615a5a | David Gibson | /* Access must be to a valid device, within bounds and
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82 | 92615a5a | David Gibson | * naturally aligned */
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83 | 92615a5a | David Gibson | rtas_st(rets, 0, -1); |
84 | 92615a5a | David Gibson | return;
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85 | 88045ac5 | Alexander Graf | } |
86 | 92615a5a | David Gibson | |
87 | 92615a5a | David Gibson | val = pci_host_config_read_common(pci_dev, addr, |
88 | 92615a5a | David Gibson | pci_config_size(pci_dev), size); |
89 | 92615a5a | David Gibson | |
90 | 92615a5a | David Gibson | rtas_st(rets, 0, 0); |
91 | 92615a5a | David Gibson | rtas_st(rets, 1, val);
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92 | 88045ac5 | Alexander Graf | } |
93 | 88045ac5 | Alexander Graf | |
94 | 3384f95c | David Gibson | static void rtas_ibm_read_pci_config(sPAPREnvironment *spapr, |
95 | 3384f95c | David Gibson | uint32_t token, uint32_t nargs, |
96 | 3384f95c | David Gibson | target_ulong args, |
97 | 3384f95c | David Gibson | uint32_t nret, target_ulong rets) |
98 | 3384f95c | David Gibson | { |
99 | 92615a5a | David Gibson | uint64_t buid; |
100 | 92615a5a | David Gibson | uint32_t size, addr; |
101 | 3384f95c | David Gibson | |
102 | 92615a5a | David Gibson | if ((nargs != 4) || (nret != 2)) { |
103 | 3384f95c | David Gibson | rtas_st(rets, 0, -1); |
104 | 3384f95c | David Gibson | return;
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105 | 3384f95c | David Gibson | } |
106 | 92615a5a | David Gibson | |
107 | 92615a5a | David Gibson | buid = ((uint64_t)rtas_ld(args, 1) << 32) | rtas_ld(args, 2); |
108 | 3384f95c | David Gibson | size = rtas_ld(args, 3);
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109 | 92615a5a | David Gibson | addr = rtas_ld(args, 0);
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110 | 92615a5a | David Gibson | |
111 | 92615a5a | David Gibson | finish_read_pci_config(spapr, buid, addr, size, rets); |
112 | 3384f95c | David Gibson | } |
113 | 3384f95c | David Gibson | |
114 | 3384f95c | David Gibson | static void rtas_read_pci_config(sPAPREnvironment *spapr, |
115 | 3384f95c | David Gibson | uint32_t token, uint32_t nargs, |
116 | 3384f95c | David Gibson | target_ulong args, |
117 | 3384f95c | David Gibson | uint32_t nret, target_ulong rets) |
118 | 3384f95c | David Gibson | { |
119 | 92615a5a | David Gibson | uint32_t size, addr; |
120 | 3384f95c | David Gibson | |
121 | 92615a5a | David Gibson | if ((nargs != 2) || (nret != 2)) { |
122 | 3384f95c | David Gibson | rtas_st(rets, 0, -1); |
123 | 3384f95c | David Gibson | return;
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124 | 3384f95c | David Gibson | } |
125 | 92615a5a | David Gibson | |
126 | 3384f95c | David Gibson | size = rtas_ld(args, 1);
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127 | 92615a5a | David Gibson | addr = rtas_ld(args, 0);
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128 | 92615a5a | David Gibson | |
129 | 92615a5a | David Gibson | finish_read_pci_config(spapr, 0, addr, size, rets);
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130 | 92615a5a | David Gibson | } |
131 | 92615a5a | David Gibson | |
132 | 92615a5a | David Gibson | static void finish_write_pci_config(sPAPREnvironment *spapr, uint64_t buid, |
133 | 92615a5a | David Gibson | uint32_t addr, uint32_t size, |
134 | 92615a5a | David Gibson | uint32_t val, target_ulong rets) |
135 | 92615a5a | David Gibson | { |
136 | 92615a5a | David Gibson | PCIDevice *pci_dev; |
137 | 92615a5a | David Gibson | |
138 | 92615a5a | David Gibson | if ((size != 1) && (size != 2) && (size != 4)) { |
139 | 92615a5a | David Gibson | /* access must be 1, 2 or 4 bytes */
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140 | 92615a5a | David Gibson | rtas_st(rets, 0, -1); |
141 | 92615a5a | David Gibson | return;
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142 | 92615a5a | David Gibson | } |
143 | 92615a5a | David Gibson | |
144 | 92615a5a | David Gibson | pci_dev = find_dev(spapr, buid, addr); |
145 | 92615a5a | David Gibson | addr = rtas_pci_cfgaddr(addr); |
146 | 92615a5a | David Gibson | |
147 | 92615a5a | David Gibson | if (!pci_dev || (addr % size) || (addr >= pci_config_size(pci_dev))) {
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148 | 92615a5a | David Gibson | /* Access must be to a valid device, within bounds and
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149 | 92615a5a | David Gibson | * naturally aligned */
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150 | 92615a5a | David Gibson | rtas_st(rets, 0, -1); |
151 | 92615a5a | David Gibson | return;
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152 | 92615a5a | David Gibson | } |
153 | 92615a5a | David Gibson | |
154 | 92615a5a | David Gibson | pci_host_config_write_common(pci_dev, addr, pci_config_size(pci_dev), |
155 | 92615a5a | David Gibson | val, size); |
156 | 92615a5a | David Gibson | |
157 | 3384f95c | David Gibson | rtas_st(rets, 0, 0); |
158 | 3384f95c | David Gibson | } |
159 | 3384f95c | David Gibson | |
160 | 3384f95c | David Gibson | static void rtas_ibm_write_pci_config(sPAPREnvironment *spapr, |
161 | 3384f95c | David Gibson | uint32_t token, uint32_t nargs, |
162 | 3384f95c | David Gibson | target_ulong args, |
163 | 3384f95c | David Gibson | uint32_t nret, target_ulong rets) |
164 | 3384f95c | David Gibson | { |
165 | 92615a5a | David Gibson | uint64_t buid; |
166 | 3384f95c | David Gibson | uint32_t val, size, addr; |
167 | 3384f95c | David Gibson | |
168 | 92615a5a | David Gibson | if ((nargs != 5) || (nret != 1)) { |
169 | 3384f95c | David Gibson | rtas_st(rets, 0, -1); |
170 | 3384f95c | David Gibson | return;
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171 | 3384f95c | David Gibson | } |
172 | 92615a5a | David Gibson | |
173 | 92615a5a | David Gibson | buid = ((uint64_t)rtas_ld(args, 1) << 32) | rtas_ld(args, 2); |
174 | 3384f95c | David Gibson | val = rtas_ld(args, 4);
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175 | 3384f95c | David Gibson | size = rtas_ld(args, 3);
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176 | 92615a5a | David Gibson | addr = rtas_ld(args, 0);
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177 | 92615a5a | David Gibson | |
178 | 92615a5a | David Gibson | finish_write_pci_config(spapr, buid, addr, size, val, rets); |
179 | 3384f95c | David Gibson | } |
180 | 3384f95c | David Gibson | |
181 | 3384f95c | David Gibson | static void rtas_write_pci_config(sPAPREnvironment *spapr, |
182 | 3384f95c | David Gibson | uint32_t token, uint32_t nargs, |
183 | 3384f95c | David Gibson | target_ulong args, |
184 | 3384f95c | David Gibson | uint32_t nret, target_ulong rets) |
185 | 3384f95c | David Gibson | { |
186 | 3384f95c | David Gibson | uint32_t val, size, addr; |
187 | 3384f95c | David Gibson | |
188 | 92615a5a | David Gibson | if ((nargs != 3) || (nret != 1)) { |
189 | 3384f95c | David Gibson | rtas_st(rets, 0, -1); |
190 | 3384f95c | David Gibson | return;
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191 | 3384f95c | David Gibson | } |
192 | 92615a5a | David Gibson | |
193 | 92615a5a | David Gibson | |
194 | 3384f95c | David Gibson | val = rtas_ld(args, 2);
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195 | 3384f95c | David Gibson | size = rtas_ld(args, 1);
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196 | 92615a5a | David Gibson | addr = rtas_ld(args, 0);
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197 | 92615a5a | David Gibson | |
198 | 92615a5a | David Gibson | finish_write_pci_config(spapr, 0, addr, size, val, rets);
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199 | 3384f95c | David Gibson | } |
200 | 3384f95c | David Gibson | |
201 | 7fb0bd34 | David Gibson | static int pci_spapr_swizzle(int slot, int pin) |
202 | 7fb0bd34 | David Gibson | { |
203 | 7fb0bd34 | David Gibson | return (slot + pin) % PCI_NUM_PINS;
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204 | 7fb0bd34 | David Gibson | } |
205 | 7fb0bd34 | David Gibson | |
206 | 3384f95c | David Gibson | static int pci_spapr_map_irq(PCIDevice *pci_dev, int irq_num) |
207 | 3384f95c | David Gibson | { |
208 | 3384f95c | David Gibson | /*
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209 | 3384f95c | David Gibson | * Here we need to convert pci_dev + irq_num to some unique value
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210 | 7fb0bd34 | David Gibson | * which is less than number of IRQs on the specific bus (4). We
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211 | 7fb0bd34 | David Gibson | * use standard PCI swizzling, that is (slot number + pin number)
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212 | 7fb0bd34 | David Gibson | * % 4.
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213 | 3384f95c | David Gibson | */
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214 | 7fb0bd34 | David Gibson | return pci_spapr_swizzle(PCI_SLOT(pci_dev->devfn), irq_num);
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215 | 3384f95c | David Gibson | } |
216 | 3384f95c | David Gibson | |
217 | 3384f95c | David Gibson | static void pci_spapr_set_irq(void *opaque, int irq_num, int level) |
218 | 3384f95c | David Gibson | { |
219 | 3384f95c | David Gibson | /*
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220 | 3384f95c | David Gibson | * Here we use the number returned by pci_spapr_map_irq to find a
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221 | 3384f95c | David Gibson | * corresponding qemu_irq.
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222 | 3384f95c | David Gibson | */
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223 | 3384f95c | David Gibson | sPAPRPHBState *phb = opaque; |
224 | 3384f95c | David Gibson | |
225 | 3384f95c | David Gibson | qemu_set_irq(phb->lsi_table[irq_num].qirq, level); |
226 | 3384f95c | David Gibson | } |
227 | 3384f95c | David Gibson | |
228 | 3384f95c | David Gibson | static uint64_t spapr_io_read(void *opaque, target_phys_addr_t addr, |
229 | 3384f95c | David Gibson | unsigned size)
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230 | 3384f95c | David Gibson | { |
231 | 3384f95c | David Gibson | switch (size) {
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232 | 3384f95c | David Gibson | case 1: |
233 | 3384f95c | David Gibson | return cpu_inb(addr);
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234 | 3384f95c | David Gibson | case 2: |
235 | 3384f95c | David Gibson | return cpu_inw(addr);
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236 | 3384f95c | David Gibson | case 4: |
237 | 3384f95c | David Gibson | return cpu_inl(addr);
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238 | 3384f95c | David Gibson | } |
239 | 3384f95c | David Gibson | assert(0);
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240 | 3384f95c | David Gibson | } |
241 | 3384f95c | David Gibson | |
242 | 3384f95c | David Gibson | static void spapr_io_write(void *opaque, target_phys_addr_t addr, |
243 | 3384f95c | David Gibson | uint64_t data, unsigned size)
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244 | 3384f95c | David Gibson | { |
245 | 3384f95c | David Gibson | switch (size) {
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246 | 3384f95c | David Gibson | case 1: |
247 | 3384f95c | David Gibson | cpu_outb(addr, data); |
248 | 3384f95c | David Gibson | return;
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249 | 3384f95c | David Gibson | case 2: |
250 | 3384f95c | David Gibson | cpu_outw(addr, data); |
251 | 3384f95c | David Gibson | return;
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252 | 3384f95c | David Gibson | case 4: |
253 | 3384f95c | David Gibson | cpu_outl(addr, data); |
254 | 3384f95c | David Gibson | return;
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255 | 3384f95c | David Gibson | } |
256 | 3384f95c | David Gibson | assert(0);
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257 | 3384f95c | David Gibson | } |
258 | 3384f95c | David Gibson | |
259 | a348f108 | Stefan Weil | static const MemoryRegionOps spapr_io_ops = { |
260 | 3384f95c | David Gibson | .endianness = DEVICE_LITTLE_ENDIAN, |
261 | 3384f95c | David Gibson | .read = spapr_io_read, |
262 | 3384f95c | David Gibson | .write = spapr_io_write |
263 | 3384f95c | David Gibson | }; |
264 | 3384f95c | David Gibson | |
265 | 298a9710 | David Gibson | /*
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266 | 298a9710 | David Gibson | * PHB PCI device
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267 | 298a9710 | David Gibson | */
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268 | 298a9710 | David Gibson | static int spapr_phb_init(SysBusDevice *s) |
269 | 3384f95c | David Gibson | { |
270 | 298a9710 | David Gibson | sPAPRPHBState *phb = FROM_SYSBUS(sPAPRPHBState, s); |
271 | 298a9710 | David Gibson | char *namebuf;
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272 | 298a9710 | David Gibson | int i;
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273 | 3384f95c | David Gibson | PCIBus *bus; |
274 | 3384f95c | David Gibson | |
275 | 298a9710 | David Gibson | phb->dtbusname = g_strdup_printf("pci@%" PRIx64, phb->buid);
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276 | 298a9710 | David Gibson | namebuf = alloca(strlen(phb->dtbusname) + 32);
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277 | 3384f95c | David Gibson | |
278 | 298a9710 | David Gibson | /* Initialize memory regions */
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279 | 298a9710 | David Gibson | sprintf(namebuf, "%s.mmio", phb->dtbusname);
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280 | 3384f95c | David Gibson | memory_region_init(&phb->memspace, namebuf, INT64_MAX); |
281 | 3384f95c | David Gibson | |
282 | 298a9710 | David Gibson | sprintf(namebuf, "%s.mmio-alias", phb->dtbusname);
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283 | 3384f95c | David Gibson | memory_region_init_alias(&phb->memwindow, namebuf, &phb->memspace, |
284 | 298a9710 | David Gibson | SPAPR_PCI_MEM_WIN_BUS_OFFSET, phb->mem_win_size); |
285 | 298a9710 | David Gibson | memory_region_add_subregion(get_system_memory(), phb->mem_win_addr, |
286 | 3384f95c | David Gibson | &phb->memwindow); |
287 | 3384f95c | David Gibson | |
288 | 3384f95c | David Gibson | /* On ppc, we only have MMIO no specific IO space from the CPU
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289 | 3384f95c | David Gibson | * perspective. In theory we ought to be able to embed the PCI IO
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290 | 3384f95c | David Gibson | * memory region direction in the system memory space. However,
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291 | 3384f95c | David Gibson | * if any of the IO BAR subregions use the old_portio mechanism,
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292 | 3384f95c | David Gibson | * that won't be processed properly unless accessed from the
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293 | 3384f95c | David Gibson | * system io address space. This hack to bounce things via
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294 | 3384f95c | David Gibson | * system_io works around the problem until all the users of
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295 | 3384f95c | David Gibson | * old_portion are updated */
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296 | 298a9710 | David Gibson | sprintf(namebuf, "%s.io", phb->dtbusname);
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297 | 3384f95c | David Gibson | memory_region_init(&phb->iospace, namebuf, SPAPR_PCI_IO_WIN_SIZE); |
298 | 3384f95c | David Gibson | /* FIXME: fix to support multiple PHBs */
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299 | 3384f95c | David Gibson | memory_region_add_subregion(get_system_io(), 0, &phb->iospace);
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300 | 3384f95c | David Gibson | |
301 | 298a9710 | David Gibson | sprintf(namebuf, "%s.io-alias", phb->dtbusname);
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302 | 3384f95c | David Gibson | memory_region_init_io(&phb->iowindow, &spapr_io_ops, phb, |
303 | 3384f95c | David Gibson | namebuf, SPAPR_PCI_IO_WIN_SIZE); |
304 | 298a9710 | David Gibson | memory_region_add_subregion(get_system_memory(), phb->io_win_addr, |
305 | 3384f95c | David Gibson | &phb->iowindow); |
306 | 3384f95c | David Gibson | |
307 | 298a9710 | David Gibson | bus = pci_register_bus(&phb->busdev.qdev, |
308 | 298a9710 | David Gibson | phb->busname ? phb->busname : phb->dtbusname, |
309 | 298a9710 | David Gibson | pci_spapr_set_irq, pci_spapr_map_irq, phb, |
310 | 298a9710 | David Gibson | &phb->memspace, &phb->iospace, |
311 | 7fb0bd34 | David Gibson | PCI_DEVFN(0, 0), PCI_NUM_PINS); |
312 | 298a9710 | David Gibson | phb->host_state.bus = bus; |
313 | 298a9710 | David Gibson | |
314 | 298a9710 | David Gibson | QLIST_INSERT_HEAD(&spapr->phbs, phb, list); |
315 | 298a9710 | David Gibson | |
316 | 298a9710 | David Gibson | /* Initialize the LSI table */
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317 | 7fb0bd34 | David Gibson | for (i = 0; i < PCI_NUM_PINS; i++) { |
318 | 298a9710 | David Gibson | qemu_irq qirq; |
319 | 298a9710 | David Gibson | uint32_t num; |
320 | 298a9710 | David Gibson | |
321 | 298a9710 | David Gibson | qirq = spapr_allocate_lsi(0, &num);
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322 | 298a9710 | David Gibson | if (!qirq) {
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323 | 298a9710 | David Gibson | return -1; |
324 | 298a9710 | David Gibson | } |
325 | 298a9710 | David Gibson | |
326 | 298a9710 | David Gibson | phb->lsi_table[i].dt_irq = num; |
327 | 298a9710 | David Gibson | phb->lsi_table[i].qirq = qirq; |
328 | 298a9710 | David Gibson | } |
329 | 298a9710 | David Gibson | |
330 | 298a9710 | David Gibson | return 0; |
331 | 298a9710 | David Gibson | } |
332 | 298a9710 | David Gibson | |
333 | 298a9710 | David Gibson | static Property spapr_phb_properties[] = {
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334 | 298a9710 | David Gibson | DEFINE_PROP_HEX64("buid", sPAPRPHBState, buid, 0), |
335 | 298a9710 | David Gibson | DEFINE_PROP_STRING("busname", sPAPRPHBState, busname),
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336 | 298a9710 | David Gibson | DEFINE_PROP_HEX64("mem_win_addr", sPAPRPHBState, mem_win_addr, 0), |
337 | 298a9710 | David Gibson | DEFINE_PROP_HEX64("mem_win_size", sPAPRPHBState, mem_win_size, 0x20000000), |
338 | 298a9710 | David Gibson | DEFINE_PROP_HEX64("io_win_addr", sPAPRPHBState, io_win_addr, 0), |
339 | 298a9710 | David Gibson | DEFINE_PROP_HEX64("io_win_size", sPAPRPHBState, io_win_size, 0x10000), |
340 | 298a9710 | David Gibson | DEFINE_PROP_END_OF_LIST(), |
341 | 298a9710 | David Gibson | }; |
342 | 298a9710 | David Gibson | |
343 | 298a9710 | David Gibson | static void spapr_phb_class_init(ObjectClass *klass, void *data) |
344 | 298a9710 | David Gibson | { |
345 | 298a9710 | David Gibson | SysBusDeviceClass *sdc = SYS_BUS_DEVICE_CLASS(klass); |
346 | 298a9710 | David Gibson | DeviceClass *dc = DEVICE_CLASS(klass); |
347 | 298a9710 | David Gibson | |
348 | 298a9710 | David Gibson | sdc->init = spapr_phb_init; |
349 | 298a9710 | David Gibson | dc->props = spapr_phb_properties; |
350 | 3384f95c | David Gibson | |
351 | 3384f95c | David Gibson | spapr_rtas_register("read-pci-config", rtas_read_pci_config);
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352 | 3384f95c | David Gibson | spapr_rtas_register("write-pci-config", rtas_write_pci_config);
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353 | 3384f95c | David Gibson | spapr_rtas_register("ibm,read-pci-config", rtas_ibm_read_pci_config);
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354 | 3384f95c | David Gibson | spapr_rtas_register("ibm,write-pci-config", rtas_ibm_write_pci_config);
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355 | 298a9710 | David Gibson | } |
356 | 3384f95c | David Gibson | |
357 | 298a9710 | David Gibson | static TypeInfo spapr_phb_info = {
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358 | 298a9710 | David Gibson | .name = "spapr-pci-host-bridge",
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359 | 298a9710 | David Gibson | .parent = TYPE_SYS_BUS_DEVICE, |
360 | 298a9710 | David Gibson | .instance_size = sizeof(sPAPRPHBState),
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361 | 298a9710 | David Gibson | .class_init = spapr_phb_class_init, |
362 | 298a9710 | David Gibson | }; |
363 | 298a9710 | David Gibson | |
364 | 298a9710 | David Gibson | void spapr_create_phb(sPAPREnvironment *spapr,
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365 | 298a9710 | David Gibson | const char *busname, uint64_t buid, |
366 | 298a9710 | David Gibson | uint64_t mem_win_addr, uint64_t mem_win_size, |
367 | 298a9710 | David Gibson | uint64_t io_win_addr) |
368 | 298a9710 | David Gibson | { |
369 | 298a9710 | David Gibson | DeviceState *dev; |
370 | 298a9710 | David Gibson | |
371 | 298a9710 | David Gibson | dev = qdev_create(NULL, spapr_phb_info.name);
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372 | 3384f95c | David Gibson | |
373 | 298a9710 | David Gibson | if (busname) {
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374 | 298a9710 | David Gibson | qdev_prop_set_string(dev, "busname", g_strdup(busname));
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375 | 298a9710 | David Gibson | } |
376 | 298a9710 | David Gibson | qdev_prop_set_uint64(dev, "buid", buid);
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377 | 298a9710 | David Gibson | qdev_prop_set_uint64(dev, "mem_win_addr", mem_win_addr);
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378 | 298a9710 | David Gibson | qdev_prop_set_uint64(dev, "mem_win_size", mem_win_size);
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379 | 298a9710 | David Gibson | qdev_prop_set_uint64(dev, "io_win_addr", io_win_addr);
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380 | 298a9710 | David Gibson | |
381 | 298a9710 | David Gibson | qdev_init_nofail(dev); |
382 | 3384f95c | David Gibson | } |
383 | 3384f95c | David Gibson | |
384 | 3384f95c | David Gibson | /* Macros to operate with address in OF binding to PCI */
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385 | 3384f95c | David Gibson | #define b_x(x, p, l) (((x) & ((1<<(l))-1)) << (p)) |
386 | 3384f95c | David Gibson | #define b_n(x) b_x((x), 31, 1) /* 0 if relocatable */ |
387 | 3384f95c | David Gibson | #define b_p(x) b_x((x), 30, 1) /* 1 if prefetchable */ |
388 | 3384f95c | David Gibson | #define b_t(x) b_x((x), 29, 1) /* 1 if the address is aliased */ |
389 | 3384f95c | David Gibson | #define b_ss(x) b_x((x), 24, 2) /* the space code */ |
390 | 3384f95c | David Gibson | #define b_bbbbbbbb(x) b_x((x), 16, 8) /* bus number */ |
391 | 3384f95c | David Gibson | #define b_ddddd(x) b_x((x), 11, 5) /* device number */ |
392 | 3384f95c | David Gibson | #define b_fff(x) b_x((x), 8, 3) /* function number */ |
393 | 3384f95c | David Gibson | #define b_rrrrrrrr(x) b_x((x), 0, 8) /* register number */ |
394 | 3384f95c | David Gibson | |
395 | 3384f95c | David Gibson | int spapr_populate_pci_devices(sPAPRPHBState *phb,
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396 | 3384f95c | David Gibson | uint32_t xics_phandle, |
397 | 3384f95c | David Gibson | void *fdt)
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398 | 3384f95c | David Gibson | { |
399 | 7fb0bd34 | David Gibson | int bus_off, i, j;
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400 | 3384f95c | David Gibson | char nodename[256]; |
401 | 3384f95c | David Gibson | uint32_t bus_range[] = { cpu_to_be32(0), cpu_to_be32(0xff) }; |
402 | 3384f95c | David Gibson | struct {
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403 | 3384f95c | David Gibson | uint32_t hi; |
404 | 3384f95c | David Gibson | uint64_t child; |
405 | 3384f95c | David Gibson | uint64_t parent; |
406 | 3384f95c | David Gibson | uint64_t size; |
407 | 3384f95c | David Gibson | } __attribute__((packed)) ranges[] = { |
408 | 3384f95c | David Gibson | { |
409 | 3384f95c | David Gibson | cpu_to_be32(b_ss(1)), cpu_to_be64(0), |
410 | 3384f95c | David Gibson | cpu_to_be64(phb->io_win_addr), |
411 | 3384f95c | David Gibson | cpu_to_be64(memory_region_size(&phb->iospace)), |
412 | 3384f95c | David Gibson | }, |
413 | 3384f95c | David Gibson | { |
414 | 3384f95c | David Gibson | cpu_to_be32(b_ss(2)), cpu_to_be64(SPAPR_PCI_MEM_WIN_BUS_OFFSET),
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415 | 3384f95c | David Gibson | cpu_to_be64(phb->mem_win_addr), |
416 | 3384f95c | David Gibson | cpu_to_be64(memory_region_size(&phb->memwindow)), |
417 | 3384f95c | David Gibson | }, |
418 | 3384f95c | David Gibson | }; |
419 | 3384f95c | David Gibson | uint64_t bus_reg[] = { cpu_to_be64(phb->buid), 0 };
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420 | 3384f95c | David Gibson | uint32_t interrupt_map_mask[] = { |
421 | 7fb0bd34 | David Gibson | cpu_to_be32(b_ddddd(-1)|b_fff(0)), 0x0, 0x0, cpu_to_be32(-1)}; |
422 | 7fb0bd34 | David Gibson | uint32_t interrupt_map[PCI_SLOT_MAX * PCI_NUM_PINS][7];
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423 | 3384f95c | David Gibson | |
424 | 3384f95c | David Gibson | /* Start populating the FDT */
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425 | 3384f95c | David Gibson | sprintf(nodename, "pci@%" PRIx64, phb->buid);
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426 | 3384f95c | David Gibson | bus_off = fdt_add_subnode(fdt, 0, nodename);
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427 | 3384f95c | David Gibson | if (bus_off < 0) { |
428 | 3384f95c | David Gibson | return bus_off;
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429 | 3384f95c | David Gibson | } |
430 | 3384f95c | David Gibson | |
431 | 3384f95c | David Gibson | #define _FDT(exp) \
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432 | 3384f95c | David Gibson | do { \
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433 | 3384f95c | David Gibson | int ret = (exp); \
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434 | 3384f95c | David Gibson | if (ret < 0) { \ |
435 | 3384f95c | David Gibson | return ret; \
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436 | 3384f95c | David Gibson | } \ |
437 | 3384f95c | David Gibson | } while (0) |
438 | 3384f95c | David Gibson | |
439 | 3384f95c | David Gibson | /* Write PHB properties */
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440 | 3384f95c | David Gibson | _FDT(fdt_setprop_string(fdt, bus_off, "device_type", "pci")); |
441 | 3384f95c | David Gibson | _FDT(fdt_setprop_string(fdt, bus_off, "compatible", "IBM,Logical_PHB")); |
442 | 3384f95c | David Gibson | _FDT(fdt_setprop_cell(fdt, bus_off, "#address-cells", 0x3)); |
443 | 3384f95c | David Gibson | _FDT(fdt_setprop_cell(fdt, bus_off, "#size-cells", 0x2)); |
444 | 3384f95c | David Gibson | _FDT(fdt_setprop_cell(fdt, bus_off, "#interrupt-cells", 0x1)); |
445 | 3384f95c | David Gibson | _FDT(fdt_setprop(fdt, bus_off, "used-by-rtas", NULL, 0)); |
446 | 3384f95c | David Gibson | _FDT(fdt_setprop(fdt, bus_off, "bus-range", &bus_range, sizeof(bus_range))); |
447 | 3384f95c | David Gibson | _FDT(fdt_setprop(fdt, bus_off, "ranges", &ranges, sizeof(ranges))); |
448 | 3384f95c | David Gibson | _FDT(fdt_setprop(fdt, bus_off, "reg", &bus_reg, sizeof(bus_reg))); |
449 | 3f7565c9 | Benjamin Herrenschmidt | _FDT(fdt_setprop_cell(fdt, bus_off, "ibm,pci-config-space-type", 0x1)); |
450 | 3384f95c | David Gibson | |
451 | 4d8d5467 | Benjamin Herrenschmidt | /* Build the interrupt-map, this must matches what is done
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452 | 4d8d5467 | Benjamin Herrenschmidt | * in pci_spapr_map_irq
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453 | 4d8d5467 | Benjamin Herrenschmidt | */
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454 | 4d8d5467 | Benjamin Herrenschmidt | _FDT(fdt_setprop(fdt, bus_off, "interrupt-map-mask",
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455 | 4d8d5467 | Benjamin Herrenschmidt | &interrupt_map_mask, sizeof(interrupt_map_mask)));
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456 | 7fb0bd34 | David Gibson | for (i = 0; i < PCI_SLOT_MAX; i++) { |
457 | 7fb0bd34 | David Gibson | for (j = 0; j < PCI_NUM_PINS; j++) { |
458 | 7fb0bd34 | David Gibson | uint32_t *irqmap = interrupt_map[i*PCI_NUM_PINS + j]; |
459 | 7fb0bd34 | David Gibson | int lsi_num = pci_spapr_swizzle(i, j);
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460 | 7fb0bd34 | David Gibson | |
461 | 7fb0bd34 | David Gibson | irqmap[0] = cpu_to_be32(b_ddddd(i)|b_fff(0)); |
462 | 7fb0bd34 | David Gibson | irqmap[1] = 0; |
463 | 7fb0bd34 | David Gibson | irqmap[2] = 0; |
464 | 7fb0bd34 | David Gibson | irqmap[3] = cpu_to_be32(j+1); |
465 | 7fb0bd34 | David Gibson | irqmap[4] = cpu_to_be32(xics_phandle);
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466 | 7fb0bd34 | David Gibson | irqmap[5] = cpu_to_be32(phb->lsi_table[lsi_num].dt_irq);
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467 | 7fb0bd34 | David Gibson | irqmap[6] = cpu_to_be32(0x8); |
468 | 7fb0bd34 | David Gibson | } |
469 | 3384f95c | David Gibson | } |
470 | 3384f95c | David Gibson | /* Write interrupt map */
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471 | 3384f95c | David Gibson | _FDT(fdt_setprop(fdt, bus_off, "interrupt-map", &interrupt_map,
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472 | 7fb0bd34 | David Gibson | sizeof(interrupt_map)));
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473 | 3384f95c | David Gibson | |
474 | 3384f95c | David Gibson | return 0; |
475 | 3384f95c | David Gibson | } |
476 | 298a9710 | David Gibson | |
477 | 298a9710 | David Gibson | static void register_types(void) |
478 | 298a9710 | David Gibson | { |
479 | 298a9710 | David Gibson | type_register_static(&spapr_phb_info); |
480 | 298a9710 | David Gibson | } |
481 | 298a9710 | David Gibson | type_init(register_types) |