root / hw / xio3130_upstream.c @ 8294a64d
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1 | faf1e708 | Isaku Yamahata | /*
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2 | faf1e708 | Isaku Yamahata | * xio3130_upstream.c
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3 | faf1e708 | Isaku Yamahata | * TI X3130 pci express upstream port switch
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4 | faf1e708 | Isaku Yamahata | *
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5 | faf1e708 | Isaku Yamahata | * Copyright (c) 2010 Isaku Yamahata <yamahata at valinux co jp>
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6 | faf1e708 | Isaku Yamahata | * VA Linux Systems Japan K.K.
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7 | faf1e708 | Isaku Yamahata | *
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8 | faf1e708 | Isaku Yamahata | * This program is free software; you can redistribute it and/or modify
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9 | faf1e708 | Isaku Yamahata | * it under the terms of the GNU General Public License as published by
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10 | faf1e708 | Isaku Yamahata | * the Free Software Foundation; either version 2 of the License, or
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11 | faf1e708 | Isaku Yamahata | * (at your option) any later version.
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12 | faf1e708 | Isaku Yamahata | *
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13 | faf1e708 | Isaku Yamahata | * This program is distributed in the hope that it will be useful,
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14 | faf1e708 | Isaku Yamahata | * but WITHOUT ANY WARRANTY; without even the implied warranty of
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15 | faf1e708 | Isaku Yamahata | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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16 | faf1e708 | Isaku Yamahata | * GNU General Public License for more details.
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17 | faf1e708 | Isaku Yamahata | *
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18 | faf1e708 | Isaku Yamahata | * You should have received a copy of the GNU General Public License along
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19 | faf1e708 | Isaku Yamahata | * with this program; if not, see <http://www.gnu.org/licenses/>.
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20 | faf1e708 | Isaku Yamahata | */
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21 | faf1e708 | Isaku Yamahata | |
22 | faf1e708 | Isaku Yamahata | #include "pci_ids.h" |
23 | faf1e708 | Isaku Yamahata | #include "msi.h" |
24 | faf1e708 | Isaku Yamahata | #include "pcie.h" |
25 | faf1e708 | Isaku Yamahata | #include "xio3130_upstream.h" |
26 | faf1e708 | Isaku Yamahata | |
27 | faf1e708 | Isaku Yamahata | #define PCI_DEVICE_ID_TI_XIO3130U 0x8232 /* upstream port */ |
28 | faf1e708 | Isaku Yamahata | #define XIO3130_REVISION 0x2 |
29 | faf1e708 | Isaku Yamahata | #define XIO3130_MSI_OFFSET 0x70 |
30 | faf1e708 | Isaku Yamahata | #define XIO3130_MSI_SUPPORTED_FLAGS PCI_MSI_FLAGS_64BIT
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31 | faf1e708 | Isaku Yamahata | #define XIO3130_MSI_NR_VECTOR 1 |
32 | faf1e708 | Isaku Yamahata | #define XIO3130_SSVID_OFFSET 0x80 |
33 | faf1e708 | Isaku Yamahata | #define XIO3130_SSVID_SVID 0 |
34 | faf1e708 | Isaku Yamahata | #define XIO3130_SSVID_SSID 0 |
35 | faf1e708 | Isaku Yamahata | #define XIO3130_EXP_OFFSET 0x90 |
36 | faf1e708 | Isaku Yamahata | #define XIO3130_AER_OFFSET 0x100 |
37 | faf1e708 | Isaku Yamahata | |
38 | faf1e708 | Isaku Yamahata | static void xio3130_upstream_write_config(PCIDevice *d, uint32_t address, |
39 | faf1e708 | Isaku Yamahata | uint32_t val, int len)
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40 | faf1e708 | Isaku Yamahata | { |
41 | faf1e708 | Isaku Yamahata | pci_bridge_write_config(d, address, val, len); |
42 | faf1e708 | Isaku Yamahata | pcie_cap_flr_write_config(d, address, val, len); |
43 | faf1e708 | Isaku Yamahata | msi_write_config(d, address, val, len); |
44 | a158f92f | Isaku Yamahata | pcie_aer_write_config(d, address, val, len); |
45 | faf1e708 | Isaku Yamahata | } |
46 | faf1e708 | Isaku Yamahata | |
47 | faf1e708 | Isaku Yamahata | static void xio3130_upstream_reset(DeviceState *qdev) |
48 | faf1e708 | Isaku Yamahata | { |
49 | 40021f08 | Anthony Liguori | PCIDevice *d = PCI_DEVICE(qdev); |
50 | faf1e708 | Isaku Yamahata | msi_reset(d); |
51 | faf1e708 | Isaku Yamahata | pci_bridge_reset(qdev); |
52 | faf1e708 | Isaku Yamahata | pcie_cap_deverr_reset(d); |
53 | faf1e708 | Isaku Yamahata | } |
54 | faf1e708 | Isaku Yamahata | |
55 | faf1e708 | Isaku Yamahata | static int xio3130_upstream_initfn(PCIDevice *d) |
56 | faf1e708 | Isaku Yamahata | { |
57 | faf1e708 | Isaku Yamahata | PCIBridge* br = DO_UPCAST(PCIBridge, dev, d); |
58 | faf1e708 | Isaku Yamahata | PCIEPort *p = DO_UPCAST(PCIEPort, br, br); |
59 | faf1e708 | Isaku Yamahata | int rc;
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60 | a158f92f | Isaku Yamahata | int tmp;
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61 | faf1e708 | Isaku Yamahata | |
62 | faf1e708 | Isaku Yamahata | rc = pci_bridge_initfn(d); |
63 | faf1e708 | Isaku Yamahata | if (rc < 0) { |
64 | faf1e708 | Isaku Yamahata | return rc;
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65 | faf1e708 | Isaku Yamahata | } |
66 | faf1e708 | Isaku Yamahata | |
67 | faf1e708 | Isaku Yamahata | pcie_port_init_reg(d); |
68 | faf1e708 | Isaku Yamahata | |
69 | faf1e708 | Isaku Yamahata | rc = msi_init(d, XIO3130_MSI_OFFSET, XIO3130_MSI_NR_VECTOR, |
70 | faf1e708 | Isaku Yamahata | XIO3130_MSI_SUPPORTED_FLAGS & PCI_MSI_FLAGS_64BIT, |
71 | faf1e708 | Isaku Yamahata | XIO3130_MSI_SUPPORTED_FLAGS & PCI_MSI_FLAGS_MASKBIT); |
72 | faf1e708 | Isaku Yamahata | if (rc < 0) { |
73 | a158f92f | Isaku Yamahata | goto err_bridge;
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74 | faf1e708 | Isaku Yamahata | } |
75 | faf1e708 | Isaku Yamahata | rc = pci_bridge_ssvid_init(d, XIO3130_SSVID_OFFSET, |
76 | faf1e708 | Isaku Yamahata | XIO3130_SSVID_SVID, XIO3130_SSVID_SSID); |
77 | faf1e708 | Isaku Yamahata | if (rc < 0) { |
78 | a158f92f | Isaku Yamahata | goto err_bridge;
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79 | faf1e708 | Isaku Yamahata | } |
80 | faf1e708 | Isaku Yamahata | rc = pcie_cap_init(d, XIO3130_EXP_OFFSET, PCI_EXP_TYPE_UPSTREAM, |
81 | faf1e708 | Isaku Yamahata | p->port); |
82 | faf1e708 | Isaku Yamahata | if (rc < 0) { |
83 | a158f92f | Isaku Yamahata | goto err_msi;
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84 | faf1e708 | Isaku Yamahata | } |
85 | faf1e708 | Isaku Yamahata | pcie_cap_flr_init(d); |
86 | faf1e708 | Isaku Yamahata | pcie_cap_deverr_init(d); |
87 | a158f92f | Isaku Yamahata | rc = pcie_aer_init(d, XIO3130_AER_OFFSET); |
88 | a158f92f | Isaku Yamahata | if (rc < 0) { |
89 | a158f92f | Isaku Yamahata | goto err;
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90 | a158f92f | Isaku Yamahata | } |
91 | faf1e708 | Isaku Yamahata | |
92 | faf1e708 | Isaku Yamahata | return 0; |
93 | a158f92f | Isaku Yamahata | |
94 | a158f92f | Isaku Yamahata | err:
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95 | a158f92f | Isaku Yamahata | pcie_cap_exit(d); |
96 | a158f92f | Isaku Yamahata | err_msi:
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97 | a158f92f | Isaku Yamahata | msi_uninit(d); |
98 | a158f92f | Isaku Yamahata | err_bridge:
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99 | a158f92f | Isaku Yamahata | tmp = pci_bridge_exitfn(d); |
100 | a158f92f | Isaku Yamahata | assert(!tmp); |
101 | a158f92f | Isaku Yamahata | return rc;
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102 | faf1e708 | Isaku Yamahata | } |
103 | faf1e708 | Isaku Yamahata | |
104 | faf1e708 | Isaku Yamahata | static int xio3130_upstream_exitfn(PCIDevice *d) |
105 | faf1e708 | Isaku Yamahata | { |
106 | a158f92f | Isaku Yamahata | pcie_aer_exit(d); |
107 | faf1e708 | Isaku Yamahata | pcie_cap_exit(d); |
108 | a158f92f | Isaku Yamahata | msi_uninit(d); |
109 | faf1e708 | Isaku Yamahata | return pci_bridge_exitfn(d);
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110 | faf1e708 | Isaku Yamahata | } |
111 | faf1e708 | Isaku Yamahata | |
112 | faf1e708 | Isaku Yamahata | PCIEPort *xio3130_upstream_init(PCIBus *bus, int devfn, bool multifunction, |
113 | faf1e708 | Isaku Yamahata | const char *bus_name, pci_map_irq_fn map_irq, |
114 | faf1e708 | Isaku Yamahata | uint8_t port) |
115 | faf1e708 | Isaku Yamahata | { |
116 | faf1e708 | Isaku Yamahata | PCIDevice *d; |
117 | faf1e708 | Isaku Yamahata | PCIBridge *br; |
118 | faf1e708 | Isaku Yamahata | DeviceState *qdev; |
119 | faf1e708 | Isaku Yamahata | |
120 | faf1e708 | Isaku Yamahata | d = pci_create_multifunction(bus, devfn, multifunction, "x3130-upstream");
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121 | faf1e708 | Isaku Yamahata | if (!d) {
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122 | faf1e708 | Isaku Yamahata | return NULL; |
123 | faf1e708 | Isaku Yamahata | } |
124 | faf1e708 | Isaku Yamahata | br = DO_UPCAST(PCIBridge, dev, d); |
125 | faf1e708 | Isaku Yamahata | |
126 | faf1e708 | Isaku Yamahata | qdev = &br->dev.qdev; |
127 | faf1e708 | Isaku Yamahata | pci_bridge_map_irq(br, bus_name, map_irq); |
128 | faf1e708 | Isaku Yamahata | qdev_prop_set_uint8(qdev, "port", port);
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129 | faf1e708 | Isaku Yamahata | qdev_init_nofail(qdev); |
130 | faf1e708 | Isaku Yamahata | |
131 | faf1e708 | Isaku Yamahata | return DO_UPCAST(PCIEPort, br, br);
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132 | faf1e708 | Isaku Yamahata | } |
133 | faf1e708 | Isaku Yamahata | |
134 | faf1e708 | Isaku Yamahata | static const VMStateDescription vmstate_xio3130_upstream = { |
135 | faf1e708 | Isaku Yamahata | .name = "xio3130-express-upstream-port",
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136 | faf1e708 | Isaku Yamahata | .version_id = 1,
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137 | faf1e708 | Isaku Yamahata | .minimum_version_id = 1,
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138 | faf1e708 | Isaku Yamahata | .minimum_version_id_old = 1,
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139 | faf1e708 | Isaku Yamahata | .fields = (VMStateField[]) { |
140 | faf1e708 | Isaku Yamahata | VMSTATE_PCIE_DEVICE(br.dev, PCIEPort), |
141 | a158f92f | Isaku Yamahata | VMSTATE_STRUCT(br.dev.exp.aer_log, PCIEPort, 0, vmstate_pcie_aer_log,
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142 | a158f92f | Isaku Yamahata | PCIEAERLog), |
143 | faf1e708 | Isaku Yamahata | VMSTATE_END_OF_LIST() |
144 | faf1e708 | Isaku Yamahata | } |
145 | faf1e708 | Isaku Yamahata | }; |
146 | faf1e708 | Isaku Yamahata | |
147 | 40021f08 | Anthony Liguori | static Property xio3130_upstream_properties[] = {
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148 | 40021f08 | Anthony Liguori | DEFINE_PROP_UINT8("port", PCIEPort, port, 0), |
149 | 40021f08 | Anthony Liguori | DEFINE_PROP_UINT16("aer_log_max", PCIEPort, br.dev.exp.aer_log.log_max,
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150 | 40021f08 | Anthony Liguori | PCIE_AER_LOG_MAX_DEFAULT), |
151 | 40021f08 | Anthony Liguori | DEFINE_PROP_END_OF_LIST(), |
152 | 40021f08 | Anthony Liguori | }; |
153 | 40021f08 | Anthony Liguori | |
154 | 40021f08 | Anthony Liguori | static void xio3130_upstream_class_init(ObjectClass *klass, void *data) |
155 | 40021f08 | Anthony Liguori | { |
156 | 39bffca2 | Anthony Liguori | DeviceClass *dc = DEVICE_CLASS(klass); |
157 | 40021f08 | Anthony Liguori | PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); |
158 | 40021f08 | Anthony Liguori | |
159 | 40021f08 | Anthony Liguori | k->is_express = 1;
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160 | 40021f08 | Anthony Liguori | k->is_bridge = 1;
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161 | 40021f08 | Anthony Liguori | k->config_write = xio3130_upstream_write_config; |
162 | 40021f08 | Anthony Liguori | k->init = xio3130_upstream_initfn; |
163 | 40021f08 | Anthony Liguori | k->exit = xio3130_upstream_exitfn; |
164 | 40021f08 | Anthony Liguori | k->vendor_id = PCI_VENDOR_ID_TI; |
165 | 40021f08 | Anthony Liguori | k->device_id = PCI_DEVICE_ID_TI_XIO3130U; |
166 | 40021f08 | Anthony Liguori | k->revision = XIO3130_REVISION; |
167 | 39bffca2 | Anthony Liguori | dc->desc = "TI X3130 Upstream Port of PCI Express Switch";
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168 | 39bffca2 | Anthony Liguori | dc->reset = xio3130_upstream_reset; |
169 | 39bffca2 | Anthony Liguori | dc->vmsd = &vmstate_xio3130_upstream; |
170 | 39bffca2 | Anthony Liguori | dc->props = xio3130_upstream_properties; |
171 | 40021f08 | Anthony Liguori | } |
172 | 40021f08 | Anthony Liguori | |
173 | 39bffca2 | Anthony Liguori | static TypeInfo xio3130_upstream_info = {
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174 | 39bffca2 | Anthony Liguori | .name = "x3130-upstream",
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175 | 39bffca2 | Anthony Liguori | .parent = TYPE_PCI_DEVICE, |
176 | 39bffca2 | Anthony Liguori | .instance_size = sizeof(PCIEPort),
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177 | 39bffca2 | Anthony Liguori | .class_init = xio3130_upstream_class_init, |
178 | faf1e708 | Isaku Yamahata | }; |
179 | faf1e708 | Isaku Yamahata | |
180 | 83f7d43a | Andreas Färber | static void xio3130_upstream_register_types(void) |
181 | faf1e708 | Isaku Yamahata | { |
182 | 39bffca2 | Anthony Liguori | type_register_static(&xio3130_upstream_info); |
183 | faf1e708 | Isaku Yamahata | } |
184 | faf1e708 | Isaku Yamahata | |
185 | 83f7d43a | Andreas Färber | type_init(xio3130_upstream_register_types) |
186 | faf1e708 | Isaku Yamahata | |
187 | faf1e708 | Isaku Yamahata | |
188 | faf1e708 | Isaku Yamahata | /*
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189 | faf1e708 | Isaku Yamahata | * Local variables:
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190 | faf1e708 | Isaku Yamahata | * c-indent-level: 4
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191 | faf1e708 | Isaku Yamahata | * c-basic-offset: 4
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192 | faf1e708 | Isaku Yamahata | * tab-width: 8
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193 | faf1e708 | Isaku Yamahata | * indent-tab-mode: nil
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194 | faf1e708 | Isaku Yamahata | * End:
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195 | faf1e708 | Isaku Yamahata | */ |