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/*
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* CBUS three-pin bus and the Retu / Betty / Tahvo / Vilma / Avilma /
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* Hinku / Vinku / Ahne / Pihi chips used in various Nokia platforms.
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* Based on reverse-engineering of a linux driver.
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*
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* Copyright (C) 2008 Nokia Corporation
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* Written by Andrzej Zaborowski <andrew@openedhand.com>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 or
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* (at your option) version 3 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "qemu-common.h" |
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#include "irq.h" |
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#include "devices.h" |
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#include "sysemu.h" |
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//#define DEBUG
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typedef struct { |
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void *opaque;
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void (*io)(void *opaque, int rw, int reg, uint16_t *val); |
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int addr;
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} CBusSlave; |
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typedef struct { |
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CBus cbus; |
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int sel;
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int dat;
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int clk;
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int bit;
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int dir;
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uint16_t val; |
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qemu_irq dat_out; |
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int addr;
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int reg;
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int rw;
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enum {
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cbus_address, |
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cbus_value, |
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} cycle; |
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CBusSlave *slave[8];
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} CBusPriv; |
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static void cbus_io(CBusPriv *s) |
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{ |
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if (s->slave[s->addr])
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s->slave[s->addr]->io(s->slave[s->addr]->opaque, |
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s->rw, s->reg, &s->val); |
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else
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hw_error("%s: bad slave address %i\n", __FUNCTION__, s->addr);
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} |
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static void cbus_cycle(CBusPriv *s) |
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{ |
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switch (s->cycle) {
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case cbus_address:
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s->addr = (s->val >> 6) & 7; |
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s->rw = (s->val >> 5) & 1; |
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s->reg = (s->val >> 0) & 0x1f; |
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s->cycle = cbus_value; |
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s->bit = 15;
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s->dir = !s->rw; |
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s->val = 0;
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if (s->rw)
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cbus_io(s); |
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break;
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case cbus_value:
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if (!s->rw)
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cbus_io(s); |
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s->cycle = cbus_address; |
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s->bit = 8;
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s->dir = 1;
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s->val = 0;
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break;
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} |
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} |
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static void cbus_clk(void *opaque, int line, int level) |
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{ |
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CBusPriv *s = (CBusPriv *) opaque; |
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if (!s->sel && level && !s->clk) {
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if (s->dir)
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s->val |= s->dat << (s->bit --); |
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else
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qemu_set_irq(s->dat_out, (s->val >> (s->bit --)) & 1);
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if (s->bit < 0) |
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cbus_cycle(s); |
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} |
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s->clk = level; |
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} |
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static void cbus_dat(void *opaque, int line, int level) |
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{ |
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CBusPriv *s = (CBusPriv *) opaque; |
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s->dat = level; |
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} |
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static void cbus_sel(void *opaque, int line, int level) |
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{ |
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CBusPriv *s = (CBusPriv *) opaque; |
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if (!level) {
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s->dir = 1;
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s->bit = 8;
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s->val = 0;
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} |
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s->sel = level; |
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} |
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CBus *cbus_init(qemu_irq dat) |
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{ |
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CBusPriv *s = (CBusPriv *) g_malloc0(sizeof(*s));
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s->dat_out = dat; |
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s->cbus.clk = qemu_allocate_irqs(cbus_clk, s, 1)[0]; |
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s->cbus.dat = qemu_allocate_irqs(cbus_dat, s, 1)[0]; |
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s->cbus.sel = qemu_allocate_irqs(cbus_sel, s, 1)[0]; |
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s->sel = 1;
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s->clk = 0;
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s->dat = 0;
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return &s->cbus;
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} |
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void cbus_attach(CBus *bus, void *slave_opaque) |
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{ |
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CBusSlave *slave = (CBusSlave *) slave_opaque; |
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CBusPriv *s = (CBusPriv *) bus; |
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s->slave[slave->addr] = slave; |
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} |
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/* Retu/Vilma */
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typedef struct { |
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uint16_t irqst; |
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uint16_t irqen; |
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uint16_t cc[2];
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int channel;
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uint16_t result[16];
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uint16_t sample; |
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uint16_t status; |
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struct {
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uint16_t cal; |
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} rtc; |
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int is_vilma;
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qemu_irq irq; |
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CBusSlave cbus; |
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} CBusRetu; |
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static void retu_interrupt_update(CBusRetu *s) |
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{ |
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qemu_set_irq(s->irq, s->irqst & ~s->irqen); |
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} |
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#define RETU_REG_ASICR 0x00 /* (RO) ASIC ID & revision */ |
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#define RETU_REG_IDR 0x01 /* (T) Interrupt ID */ |
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#define RETU_REG_IMR 0x02 /* (RW) Interrupt mask */ |
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#define RETU_REG_RTCDSR 0x03 /* (RW) RTC seconds register */ |
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#define RETU_REG_RTCHMR 0x04 /* (RO) RTC hours and minutes reg */ |
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#define RETU_REG_RTCHMAR 0x05 /* (RW) RTC hours and minutes set reg */ |
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#define RETU_REG_RTCCALR 0x06 /* (RW) RTC calibration register */ |
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#define RETU_REG_ADCR 0x08 /* (RW) ADC result register */ |
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#define RETU_REG_ADCSCR 0x09 /* (RW) ADC sample control register */ |
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#define RETU_REG_AFCR 0x0a /* (RW) AFC register */ |
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#define RETU_REG_ANTIFR 0x0b /* (RW) AntiF register */ |
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#define RETU_REG_CALIBR 0x0c /* (RW) CalibR register*/ |
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#define RETU_REG_CCR1 0x0d /* (RW) Common control register 1 */ |
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#define RETU_REG_CCR2 0x0e /* (RW) Common control register 2 */ |
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#define RETU_REG_RCTRL_CLR 0x0f /* (T) Regulator clear register */ |
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#define RETU_REG_RCTRL_SET 0x10 /* (T) Regulator set register */ |
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#define RETU_REG_TXCR 0x11 /* (RW) TxC register */ |
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#define RETU_REG_STATUS 0x16 /* (RO) Status register */ |
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#define RETU_REG_WATCHDOG 0x17 /* (RW) Watchdog register */ |
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#define RETU_REG_AUDTXR 0x18 /* (RW) Audio Codec Tx register */ |
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#define RETU_REG_AUDPAR 0x19 /* (RW) AudioPA register */ |
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#define RETU_REG_AUDRXR1 0x1a /* (RW) Audio receive register 1 */ |
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#define RETU_REG_AUDRXR2 0x1b /* (RW) Audio receive register 2 */ |
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#define RETU_REG_SGR1 0x1c /* (RW) */ |
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#define RETU_REG_SCR1 0x1d /* (RW) */ |
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#define RETU_REG_SGR2 0x1e /* (RW) */ |
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#define RETU_REG_SCR2 0x1f /* (RW) */ |
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/* Retu Interrupt sources */
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enum {
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retu_int_pwr = 0, /* Power button */ |
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retu_int_char = 1, /* Charger */ |
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retu_int_rtcs = 2, /* Seconds */ |
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retu_int_rtcm = 3, /* Minutes */ |
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retu_int_rtcd = 4, /* Days */ |
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retu_int_rtca = 5, /* Alarm */ |
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retu_int_hook = 6, /* Hook */ |
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retu_int_head = 7, /* Headset */ |
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retu_int_adcs = 8, /* ADC sample */ |
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}; |
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/* Retu ADC channel wiring */
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enum {
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retu_adc_bsi = 1, /* BSI */ |
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retu_adc_batt_temp = 2, /* Battery temperature */ |
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retu_adc_chg_volt = 3, /* Charger voltage */ |
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retu_adc_head_det = 4, /* Headset detection */ |
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retu_adc_hook_det = 5, /* Hook detection */ |
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retu_adc_rf_gp = 6, /* RF GP */ |
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retu_adc_tx_det = 7, /* Wideband Tx detection */ |
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retu_adc_batt_volt = 8, /* Battery voltage */ |
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retu_adc_sens = 10, /* Light sensor */ |
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retu_adc_sens_temp = 11, /* Light sensor temperature */ |
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retu_adc_bbatt_volt = 12, /* Backup battery voltage */ |
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retu_adc_self_temp = 13, /* RETU temperature */ |
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}; |
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static inline uint16_t retu_read(CBusRetu *s, int reg) |
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{ |
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#ifdef DEBUG
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printf("RETU read at %02x\n", reg);
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#endif
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switch (reg) {
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case RETU_REG_ASICR:
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return 0x0215 | (s->is_vilma << 7); |
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case RETU_REG_IDR: /* TODO: Or is this ffs(s->irqst)? */ |
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return s->irqst;
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case RETU_REG_IMR:
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return s->irqen;
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case RETU_REG_RTCDSR:
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case RETU_REG_RTCHMR:
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case RETU_REG_RTCHMAR:
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/* TODO */
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return 0x0000; |
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case RETU_REG_RTCCALR:
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return s->rtc.cal;
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case RETU_REG_ADCR:
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return (s->channel << 10) | s->result[s->channel]; |
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case RETU_REG_ADCSCR:
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return s->sample;
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case RETU_REG_AFCR:
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case RETU_REG_ANTIFR:
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case RETU_REG_CALIBR:
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/* TODO */
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return 0x0000; |
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case RETU_REG_CCR1:
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return s->cc[0]; |
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case RETU_REG_CCR2:
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return s->cc[1]; |
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case RETU_REG_RCTRL_CLR:
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case RETU_REG_RCTRL_SET:
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case RETU_REG_TXCR:
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/* TODO */
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return 0x0000; |
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case RETU_REG_STATUS:
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return s->status;
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case RETU_REG_WATCHDOG:
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case RETU_REG_AUDTXR:
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case RETU_REG_AUDPAR:
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case RETU_REG_AUDRXR1:
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case RETU_REG_AUDRXR2:
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case RETU_REG_SGR1:
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case RETU_REG_SCR1:
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case RETU_REG_SGR2:
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case RETU_REG_SCR2:
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/* TODO */
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return 0x0000; |
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default:
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hw_error("%s: bad register %02x\n", __FUNCTION__, reg);
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} |
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} |
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static inline void retu_write(CBusRetu *s, int reg, uint16_t val) |
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{ |
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#ifdef DEBUG
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printf("RETU write of %04x at %02x\n", val, reg);
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#endif
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switch (reg) {
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case RETU_REG_IDR:
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s->irqst ^= val; |
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retu_interrupt_update(s); |
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break;
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case RETU_REG_IMR:
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s->irqen = val; |
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retu_interrupt_update(s); |
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break;
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case RETU_REG_RTCDSR:
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case RETU_REG_RTCHMAR:
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/* TODO */
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break;
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case RETU_REG_RTCCALR:
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s->rtc.cal = val; |
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break;
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case RETU_REG_ADCR:
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s->channel = (val >> 10) & 0xf; |
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s->irqst |= 1 << retu_int_adcs;
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retu_interrupt_update(s); |
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break;
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case RETU_REG_ADCSCR:
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s->sample &= ~val; |
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break;
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case RETU_REG_AFCR:
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case RETU_REG_ANTIFR:
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case RETU_REG_CALIBR:
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case RETU_REG_CCR1:
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s->cc[0] = val;
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break;
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case RETU_REG_CCR2:
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s->cc[1] = val;
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break;
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case RETU_REG_RCTRL_CLR:
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case RETU_REG_RCTRL_SET:
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/* TODO */
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break;
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case RETU_REG_WATCHDOG:
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if (val == 0 && (s->cc[0] & 2)) |
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qemu_system_shutdown_request(); |
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break;
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|
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case RETU_REG_TXCR:
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case RETU_REG_AUDTXR:
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case RETU_REG_AUDPAR:
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case RETU_REG_AUDRXR1:
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case RETU_REG_AUDRXR2:
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case RETU_REG_SGR1:
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case RETU_REG_SCR1:
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case RETU_REG_SGR2:
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case RETU_REG_SCR2:
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/* TODO */
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break;
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default:
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hw_error("%s: bad register %02x\n", __FUNCTION__, reg);
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} |
376 |
} |
377 |
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static void retu_io(void *opaque, int rw, int reg, uint16_t *val) |
379 |
{ |
380 |
CBusRetu *s = (CBusRetu *) opaque; |
381 |
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if (rw)
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*val = retu_read(s, reg); |
384 |
else
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retu_write(s, reg, *val); |
386 |
} |
387 |
|
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void *retu_init(qemu_irq irq, int vilma) |
389 |
{ |
390 |
CBusRetu *s = (CBusRetu *) g_malloc0(sizeof(*s));
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391 |
|
392 |
s->irq = irq; |
393 |
s->irqen = 0xffff;
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s->irqst = 0x0000;
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s->status = 0x0020;
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s->is_vilma = !!vilma; |
397 |
s->rtc.cal = 0x01;
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398 |
s->result[retu_adc_bsi] = 0x3c2;
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399 |
s->result[retu_adc_batt_temp] = 0x0fc;
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s->result[retu_adc_chg_volt] = 0x165;
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s->result[retu_adc_head_det] = 123;
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s->result[retu_adc_hook_det] = 1023;
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s->result[retu_adc_rf_gp] = 0x11;
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s->result[retu_adc_tx_det] = 0x11;
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s->result[retu_adc_batt_volt] = 0x250;
|
406 |
s->result[retu_adc_sens] = 2;
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407 |
s->result[retu_adc_sens_temp] = 0x11;
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408 |
s->result[retu_adc_bbatt_volt] = 0x3d0;
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409 |
s->result[retu_adc_self_temp] = 0x330;
|
410 |
|
411 |
s->cbus.opaque = s; |
412 |
s->cbus.io = retu_io; |
413 |
s->cbus.addr = 1;
|
414 |
|
415 |
return &s->cbus;
|
416 |
} |
417 |
|
418 |
void retu_key_event(void *retu, int state) |
419 |
{ |
420 |
CBusSlave *slave = (CBusSlave *) retu; |
421 |
CBusRetu *s = (CBusRetu *) slave->opaque; |
422 |
|
423 |
s->irqst |= 1 << retu_int_pwr;
|
424 |
retu_interrupt_update(s); |
425 |
|
426 |
if (state)
|
427 |
s->status &= ~(1 << 5); |
428 |
else
|
429 |
s->status |= 1 << 5; |
430 |
} |
431 |
|
432 |
#if 0
|
433 |
static void retu_head_event(void *retu, int state)
|
434 |
{
|
435 |
CBusSlave *slave = (CBusSlave *) retu;
|
436 |
CBusRetu *s = (CBusRetu *) slave->opaque;
|
437 |
|
438 |
if ((s->cc[0] & 0x500) == 0x500) { /* TODO: Which bits? */
|
439 |
/* TODO: reissue the interrupt every 100ms or so. */
|
440 |
s->irqst |= 1 << retu_int_head;
|
441 |
retu_interrupt_update(s);
|
442 |
}
|
443 |
|
444 |
if (state)
|
445 |
s->result[retu_adc_head_det] = 50;
|
446 |
else
|
447 |
s->result[retu_adc_head_det] = 123;
|
448 |
}
|
449 |
|
450 |
static void retu_hook_event(void *retu, int state)
|
451 |
{
|
452 |
CBusSlave *slave = (CBusSlave *) retu;
|
453 |
CBusRetu *s = (CBusRetu *) slave->opaque;
|
454 |
|
455 |
if ((s->cc[0] & 0x500) == 0x500) {
|
456 |
/* TODO: reissue the interrupt every 100ms or so. */
|
457 |
s->irqst |= 1 << retu_int_hook;
|
458 |
retu_interrupt_update(s);
|
459 |
}
|
460 |
|
461 |
if (state)
|
462 |
s->result[retu_adc_hook_det] = 50;
|
463 |
else
|
464 |
s->result[retu_adc_hook_det] = 123;
|
465 |
}
|
466 |
#endif
|
467 |
|
468 |
/* Tahvo/Betty */
|
469 |
typedef struct { |
470 |
uint16_t irqst; |
471 |
uint16_t irqen; |
472 |
uint8_t charger; |
473 |
uint8_t backlight; |
474 |
uint16_t usbr; |
475 |
uint16_t power; |
476 |
|
477 |
int is_betty;
|
478 |
qemu_irq irq; |
479 |
CBusSlave cbus; |
480 |
} CBusTahvo; |
481 |
|
482 |
static void tahvo_interrupt_update(CBusTahvo *s) |
483 |
{ |
484 |
qemu_set_irq(s->irq, s->irqst & ~s->irqen); |
485 |
} |
486 |
|
487 |
#define TAHVO_REG_ASICR 0x00 /* (RO) ASIC ID & revision */ |
488 |
#define TAHVO_REG_IDR 0x01 /* (T) Interrupt ID */ |
489 |
#define TAHVO_REG_IDSR 0x02 /* (RO) Interrupt status */ |
490 |
#define TAHVO_REG_IMR 0x03 /* (RW) Interrupt mask */ |
491 |
#define TAHVO_REG_CHAPWMR 0x04 /* (RW) Charger PWM */ |
492 |
#define TAHVO_REG_LEDPWMR 0x05 /* (RW) LED PWM */ |
493 |
#define TAHVO_REG_USBR 0x06 /* (RW) USB control */ |
494 |
#define TAHVO_REG_RCR 0x07 /* (RW) Some kind of power management */ |
495 |
#define TAHVO_REG_CCR1 0x08 /* (RW) Common control register 1 */ |
496 |
#define TAHVO_REG_CCR2 0x09 /* (RW) Common control register 2 */ |
497 |
#define TAHVO_REG_TESTR1 0x0a /* (RW) Test register 1 */ |
498 |
#define TAHVO_REG_TESTR2 0x0b /* (RW) Test register 2 */ |
499 |
#define TAHVO_REG_NOPR 0x0c /* (RW) Number of periods */ |
500 |
#define TAHVO_REG_FRR 0x0d /* (RO) FR */ |
501 |
|
502 |
static inline uint16_t tahvo_read(CBusTahvo *s, int reg) |
503 |
{ |
504 |
#ifdef DEBUG
|
505 |
printf("TAHVO read at %02x\n", reg);
|
506 |
#endif
|
507 |
|
508 |
switch (reg) {
|
509 |
case TAHVO_REG_ASICR:
|
510 |
return 0x0021 | (s->is_betty ? 0x0b00 : 0x0300); /* 22 in N810 */ |
511 |
|
512 |
case TAHVO_REG_IDR:
|
513 |
case TAHVO_REG_IDSR: /* XXX: what does this do? */ |
514 |
return s->irqst;
|
515 |
|
516 |
case TAHVO_REG_IMR:
|
517 |
return s->irqen;
|
518 |
|
519 |
case TAHVO_REG_CHAPWMR:
|
520 |
return s->charger;
|
521 |
|
522 |
case TAHVO_REG_LEDPWMR:
|
523 |
return s->backlight;
|
524 |
|
525 |
case TAHVO_REG_USBR:
|
526 |
return s->usbr;
|
527 |
|
528 |
case TAHVO_REG_RCR:
|
529 |
return s->power;
|
530 |
|
531 |
case TAHVO_REG_CCR1:
|
532 |
case TAHVO_REG_CCR2:
|
533 |
case TAHVO_REG_TESTR1:
|
534 |
case TAHVO_REG_TESTR2:
|
535 |
case TAHVO_REG_NOPR:
|
536 |
case TAHVO_REG_FRR:
|
537 |
return 0x0000; |
538 |
|
539 |
default:
|
540 |
hw_error("%s: bad register %02x\n", __FUNCTION__, reg);
|
541 |
} |
542 |
} |
543 |
|
544 |
static inline void tahvo_write(CBusTahvo *s, int reg, uint16_t val) |
545 |
{ |
546 |
#ifdef DEBUG
|
547 |
printf("TAHVO write of %04x at %02x\n", val, reg);
|
548 |
#endif
|
549 |
|
550 |
switch (reg) {
|
551 |
case TAHVO_REG_IDR:
|
552 |
s->irqst ^= val; |
553 |
tahvo_interrupt_update(s); |
554 |
break;
|
555 |
|
556 |
case TAHVO_REG_IMR:
|
557 |
s->irqen = val; |
558 |
tahvo_interrupt_update(s); |
559 |
break;
|
560 |
|
561 |
case TAHVO_REG_CHAPWMR:
|
562 |
s->charger = val; |
563 |
break;
|
564 |
|
565 |
case TAHVO_REG_LEDPWMR:
|
566 |
if (s->backlight != (val & 0x7f)) { |
567 |
s->backlight = val & 0x7f;
|
568 |
printf("%s: LCD backlight now at %i / 127\n",
|
569 |
__FUNCTION__, s->backlight); |
570 |
} |
571 |
break;
|
572 |
|
573 |
case TAHVO_REG_USBR:
|
574 |
s->usbr = val; |
575 |
break;
|
576 |
|
577 |
case TAHVO_REG_RCR:
|
578 |
s->power = val; |
579 |
break;
|
580 |
|
581 |
case TAHVO_REG_CCR1:
|
582 |
case TAHVO_REG_CCR2:
|
583 |
case TAHVO_REG_TESTR1:
|
584 |
case TAHVO_REG_TESTR2:
|
585 |
case TAHVO_REG_NOPR:
|
586 |
case TAHVO_REG_FRR:
|
587 |
break;
|
588 |
|
589 |
default:
|
590 |
hw_error("%s: bad register %02x\n", __FUNCTION__, reg);
|
591 |
} |
592 |
} |
593 |
|
594 |
static void tahvo_io(void *opaque, int rw, int reg, uint16_t *val) |
595 |
{ |
596 |
CBusTahvo *s = (CBusTahvo *) opaque; |
597 |
|
598 |
if (rw)
|
599 |
*val = tahvo_read(s, reg); |
600 |
else
|
601 |
tahvo_write(s, reg, *val); |
602 |
} |
603 |
|
604 |
void *tahvo_init(qemu_irq irq, int betty) |
605 |
{ |
606 |
CBusTahvo *s = (CBusTahvo *) g_malloc0(sizeof(*s));
|
607 |
|
608 |
s->irq = irq; |
609 |
s->irqen = 0xffff;
|
610 |
s->irqst = 0x0000;
|
611 |
s->is_betty = !!betty; |
612 |
|
613 |
s->cbus.opaque = s; |
614 |
s->cbus.io = tahvo_io; |
615 |
s->cbus.addr = 2;
|
616 |
|
617 |
return &s->cbus;
|
618 |
} |