pseries: Convert sPAPR TCEs to use generic IOMMU infrastructure
The pseries platform already contains an IOMMU implementation, since it isessential for the platform's paravirtualized VIO devices. This IOMMUsupport is currently built into the implementation of the VIO "bus" and...
target-ppc: Fix build with --enable-debug
The order of the arguments was wrong (copy+paste error).
Signed-off-by: Stefan Weil <sw@weilnetz.de>Signed-off-by: Alexander Graf <agraf@suse.de>
target-ppc: Fix 2nd parameter for tcg_gen_shri_tl
This fixes a compiler error when QEMU was configured with --enable-debug.
PPC: BookE: Implement EPR SPR
On the e500 series, accessing SPR_EPR magically turns into an access atthat CPU's IACK register on the MPIC. Implement that logic to get kernelsthat make use of that feature work.
Signed-off-by: Alexander Graf <agraf@suse.de>
PPC: BookE: Make ivpr selectable by CPU type
IVPR can either hold 32 or 64 bit addresses, depending on the CPU type. Letthe CPU initialization function pass in its mask itself, so we can easilyextend it.
PPC: Add e5500 CPU target
This patch adds e5500's CPU initialization to the TCG CPU initializationcode.
PPC: Extract SPR dump generation into its own function
This patch moves the debug #ifdef'ed SPR trace generation into itsown function, so we can call it from multiple places.
PPC: BookE: Support 32 and 64 bit wide MAS2
The MAS registers on BookE are all 32 bit wide, except for MAS2, whichcan hold up to 64 bit on 64 bit capable CPUs. Reflect this in the SPRsetting code, so that the guest can never write invalid values in them....
PPC: BookE206: Bump MAS2 to 64bit
On 64bit capable systems, MAS2 can actually hold a 64bit virtual pageaddress. So increase the mask for its EPN.
PPC: Add some booke SPR defines
The number of SPRs avaiable in different PowerPC chip is still increasing. Adddefinitions for the MAS7_MAS3 SPR and all currently known bits in EPCR.
PPC: Add support for MSR_CM
The BookE variant of MSR_SF is MSR_CM. Implement everything it takes in TCG tosupport running 64bit code with MSR_CM set.
booke_206_tlbwe: Discard invalid bits in MAS2
The size of EPN field in MAS2 depends on page size. This patch adds amask to discard invalid bits in EPN field.
Definition of EPN field from e500v2 RM:EPN Effective page number: Depending on page size, only the bits...
ppc64: Rudimentary Support for extra page sizes on server CPUs
More recent Power server chips (i.e. based on the 64 bit hash MMU)support more than just the traditional 4k and 16M page sizes. Thiscan get quite complicated, because which page sizes are supported,...
ppc: Avoid AREG0 for timebase helpers
Add an explicit CPUPPCState parameter instead of relying on AREG0.
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>Signed-off-by: Alexander Graf <agraf@suse.de>Signed-off-by: Andreas Färber <afaerber@suse.de>Signed-off-by: Alexander Graf <agraf@suse.de>
ppc: Split off misc helpers
Move misc helpers from op_helper.c to misc_helpers.c.
ppc: Avoid AREG0 for misc helpers
ppc: Move misc helpers from helper.c to misc_helper.c
Move more misc helpers from helper.c to misc_helper.c.
ppc: Move load and store helpers, switch to AREG0 free mode
Add an explicit CPUPPCState parameter instead of relying on AREG0and rename op_helper.c (which only contains load and store helpers)to mem_helper.c. Remove AREG0 swapping intlb_fill().
Switch to AREG0 free mode. Use cpu_ld{l,uw}_code in translation...
ppc: Add missing break
Add obviously missing 'break' statement.
ppc: Make hbrev table const
Lookup table 'hbrev' is never written to, so add a 'const' qualifier.
ppc: Avoid AREG0 for MMU etc. helpers
ppc: Avoid a warning with the next patch
When the code is moved together by the next patch, compilerdetects a possible uninitialized variable use. Avoid the warningby initializing the variables.
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>Signed-off-by: Alexander Graf <agraf@suse.de>...
ppc: Move MMU helpers from helper.c to mmu_helper.c
Move more MMU helpers from helper.c to mmu_helper.c.
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>Signed-off-by: Alexander Graf <agraf@suse.de>Signed-off-by: Andreas Färber <afaerber@suse.de>[update to current helper.c state]...
ppc: Cleanup MMU merge
Remove useless wrappers. In some cases 'int' parameters arechanged to uint32_t.
Make internal functions static.
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>[agraf: fix kvm compilation]Signed-off-by: Alexander Graf <agraf@suse.de>...
ppc: Split off timebase helpers
Move decrementer and timebase helpers to a dedicated file.
ppc: Move exception helpers from helper.c to excp_helper.c
Move exception helpers from helper.c to excp_helper.c andmake cpu_dump_rfi() static.
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>Signed-off-by: Alexander Graf <agraf@suse.de>Signed-off-by: Andreas Färber <afaerber@suse.de>...
ppc: Split FPU and SPE ops
Move FPU and SPE helpers from op_helper.c to fpu_helper.c.
ppc: Avoid AREG0 for FPU and SPE helpers
ppc: Split integer and vector ops
Move integer and vector ops to int_helper.c.
ppc: Avoid AREG0 for integer and vector helpers
ppc: Split MMU etc. helpers from op_helper.c
Move MMU, TLB, SLB and BAT ops to mmu_helper.c.
ppc: Fix coding style in op_helper.c
op_helper.c will be split by the next patches, fixstyle issues before that.
ppc: Split exception helpers
Move exception helpers from op_helper.c to excp_helper.c.
ppc: Avoid AREG0 for exception helpers
ppc: Fix coding style in helper.c
helper.c will be spilt by the next patches, fixstyle issues before that.
qemu-log: use LOG_UNIMP for some target CPU cases
Use LOG_UNIMP for some target CPU cases.
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>Acked-by: Alexander Graf <agraf@suse.de>
target-ppc: Unbreak kvm_ppc.c build
The file is located in target-ppc/, not hw/.
Signed-off-by: Andreas Färber <andreas.faerber@web.de>Cc: Paolo Bonzini <pbonzini@redhat.com>Cc: Anthony Liguori <anthony@codemonkey.ws>Cc: Blue Swirl <blauwirbel@gmail.com>...
build: move other target-*/ objects to nested Makefile.objs
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
build: move libobj-y variable to nested Makefile.objs
build: move obj-TARGET-y variables to nested Makefile.objs
Also drop duplicate occurrence of device-hotplug.o.
Kill off cpu_state_reset()
In commit 1bba0dc932e8826a7d030df3767daf0bc339f9a2 cpu_reset()was renamed to cpu_state_reset(), to allow introducing a new cpu_reset()that would operate on QOM objects.
All callers have been updated except for one in target-mips, so drop all...
target-ppc: Let cpu_ppc_init() return PowerPCCPU
Adapt e500 mpc8544ds machine accordingly.
Turn cpu_init() into a static inline function returning CPUPPCState forbackwards compatibility.
Signed-off-by: Andreas Färber <afaerber@suse.de>Acked-by: Alexander Graf <agraf@suse.de>
target-ppc: Some support for dumping TLB_EMB TLBs
Add mmubooke_dump_mmu().
TODO: Add printing of individual flags.
Signed-off-by: François Revol <revol@free.fr>[agraf: fix coding style]Signed-off-by: Alexander Graf <agraf@suse.de>
PPC: Fix up e500 cache size setting
When initializing the e500 code, we need to expose itscache line size for user and system mode, while the mmudetails are only interesting for system emulation.
Split the 2 switch statements apart, allowing us to #ifdef...
target-ppc/machine.c: Drop unnecessary ifdefs
machine.c is only compiled for softmmu targets, so checks for!defined(CONFIG_USER_ONLY) are unnecessary and can be dropped.
Signed-off-by: Juan Quintela <quintela@redhat.com>[AF: Use more verbose commit message suggested by PMM]...
target-ppc: Init dcache and icache size for e500 user mode
commit f7aa558396dd0f6b7a2b22c05cb503c655854102 pulled the dcache and icacheline size initialization inside of a '#if !defined(CONFIG_USER_ONLY)' block.This is not correct because instructions like 'dcbz' need the dcache size...
target-ppc: Fix type casts for w64 (uintptr_t)
This changes nothing for other hosts.
Signed-off-by: Stefan Weil <sw@weilnetz.de>Signed-off-by: Andreas Färber <afaerber@suse.de>
target-ppc: QOM'ify CPU reset
Move code from cpu_state_reset() into ppc_cpu_reset().Reorder #include of helper_regs.h to use it in translate_init.c.
Adjust whitespace and add braces.
Signed-off-by: Andreas Färber <afaerber@suse.de>Acked-by: David Gibson <david@gibson.dropbear.id.au>
target-ppc: Start QOM'ifying CPU init
Move code not dependent on ppc_def_t from cpu_ppc_init() into an initfn.
target-ppc: QOM'ify CPU
Embed CPUPPCState as first member of PowerPCCPU.Distinguish between "powerpc-cpu", "powerpc64-cpu" and"embedded-powerpc-cpu".
Let CPUClass::reset() call cpu_state_reset() for now.
Signed-off-by: Andreas Färber <afaerber@suse.de>...
target-ppc: Add hooks for handling tcg and kvm limitations
On target-ppc, our table of CPU types and features encodes the features asfound on the hardware, regardless of whether these features are actuallyusable under TCG or KVM. We already have cases where the information from...
PPC: Fix TLB invalidation bug within the PPC interrupt handler.
Commit 41557447d30eeb944e42069513df13585f5e6c7f also introduced a subtle TLBflush bug. By applying a mask to the interrupt MSR which cleared the IR/DRbits at the start of the interrupt handler, the logic towards the end of the...
target-ppc: Drop cpu_ppc_close()
It is unused, so avoid QOM'ifying it unneededly.
Use uintptr_t for various op related functions
Use uintptr_t instead of void * or unsigned long inseveral op related functions, env->mem_io_pc andGETPC macro.
Reviewed-by: Stefan Weil <sw@weilnetz.de>Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
Replace Qemu by QEMU in comments
The official spelling is QEMU.
Signed-off-by: Stefan Weil <sw@weilnetz.de>Reviewed-by: Andreas Färber <afaerber@suse.de>[blauwirbel@gmail.com: fixed comment style in hw/sun4m.c]Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
PPC: Fix large page support in TCG
Fix large page support in TCG. The old code would overwrite the large pagetable entry with the fake 4 KB one generated here whenever the ref/change bitswere updated, causing it to point to the wrong area of memory.
Signed-off-by: Nathan Whitehorn <nwhitehorn@freebsd.org>...
ppc: Correctly define POWERPC_INSNS2_DEFAULT
'POWERPC_INSNS2_DEFAULT' was defined incorrectly which was causing theopcode table creation code to erroneously register 'eieio' and 'mbar'for the "default" processor:
PPC: KVM: Synchronize regs on CPU dump
When we dump the CPU registers, there's a certain chance they haven't beensynchronized with KVM yet, so we have to manually trigger that.
This aligns the code with x86 and fixes a bug where the register state wasbogus on invalid/unknown kvm exit reasons....
pseries: Don't try to munmap() a malloc()ed TCE table
For the pseries machine, TCE (IOMMU) tables can either be directlymalloc()ed in qemu or, when running on a KVM which supports it, mmap()edfrom a KVM ioctl. The latter option is used when available, because it...
PPC64: Add support for ldbrx and stdbrx instructions
These instructions for loading and storing byte-swapped 64-bit values havebeen introduced in PowerISA 2.06.
Signed-off-by: Thomas Huth <thuth@linux.vnet.ibm.com>Signed-off-by: David Gibson <david@gibson.dropbear.id.au>...
PPC: Add PIR register to POWER7 CPU
The POWER7 emulation is missing the Processor Identification Register,mandatory in recent POWER CPUs, that is required for SMP on at leastsome operating systems (e.g. FreeBSD) to function properly. This patchcopies the existing PIR code from the other CPUs that implement it....
Rename CPUState -> CPUArchState
Scripted conversion: for file in .[hc] hw/.[hc] hw/kvm/*.[hc] linux-user/*.[hc] linux-user/m68k/*.[hc] bsd-user/*.[hc] darwin-user/*.[hc] tcg/*/*.[hc] target-*/cpu.h; do sed -i "s/CPUState/CPUArchState/g" $file done...
target-ppc: Don't overuse CPUState
Scripted conversion: sed -i "s/CPUState/CPUPPCState/g" target-ppc/*.[hc] sed -i "s/#define CPUPPCState/#define CPUState/" target-ppc/cpu.h
Signed-off-by: Andreas Färber <afaerber@suse.de>Acked-by: Anthony Liguori <aliguori@us.ibm.com>
PPC: 405: Use proper CPU reset
On ppc405ep there is a register that allows for software to reset thecore, but not the whole system. Implement this reset using a resetinterrupt.
This gets rid of a bunch of #if 0'ed code.
Reported-by: Andreas Färber <afaerber@suse.de>...
Rename cpu_reset() to cpu_state_reset()
Frees the identifier cpu_reset for QOM CPUs (manual rename).
Don't hide the parameter type behind explicit casts, use staticfunctions with strongly typed argument to indirect.
target-ppc: Clean includes
Remove some include statements which are not needed.
Acked-by: Alexander Graf <agraf@suse.de>Signed-off-by: Stefan Weil <sw@weilnetz.de>
ppc: remove unused variables
Fix this error:/src/qemu/target-ppc/helper.c: In function 'booke206_tlb_to_page_size':/src/qemu/target-ppc/helper.c:1296:14: error: variable 'tlbncfg' set but not used [-Werror=unused-but-set-variable]
Tested-by: Andreas Färber <afaerber@suse.de>...
PPC: E500: Populate L1CFG0 SPR
When running Linux on e500 with powersave-nap enabled, Linux tries toread out the L1CFG0 register and calculates some things from it. Passing0 there ends up in a division by 0, resulting in -1, resulting in badness.
So let's populate the L1CFG0 register with reasonable defaults. That way...
PPC: E500: Add doorbell defines
We're going to introduce doorbell instructions (called processorcontrol in the spec) soon. Add some defines for easier patchreadability later.
PPC: Add CPU feature for processor control
We're soon going to implement processor control features. Add thefeature flag, so we're well prepared.
PPC: Enable doorbell excp handlers
We already had all the code available to have doorbell exceptionsbe handled properly. It was just disabled.
Enable it, so we can rely on it.
PPC: E500: Implement msgclr
This patch implements the msgclr instruction. It is part of theEmbedded.Processor Control specification and clears pending doorbellinterrupts on the current CPU.
PPC: E500: Implement msgsnd
This patch implements the msgsnd instruction. It is part of theEmbedded.Processor Control specification and allows one CPU toIPI another CPU without going through an interrupt controller.
PPC: e500mc: Enable processor control
The e500mc implements Embedded.Processor Control, so enable it andthus enable guests to IPI each other. This makes -smp work with -cpue500mc.
PPC: booke: add tlbnps handling
When using MAV 2.0 TLB registers, we have another range of TLB registersavailable to read the supported page sizes from.
Add SPR definitions for those and add a helper function that we can useto receive such a bitmap even when using MAV 1.0....
PPC: booke206: Check for min/max TLB entry size
When setting a TLB entry, we need to check if the TLB we're putting it inactually supports the given size. According to the 2.06 PowerPC ISA, avalue that's out of range can either be redefined to something implementation...
PPC: booke206: Implement tlbilx
The PowerPC 2.06 BookE ISA defines an opcode called "tlbilx" which is usedto flush TLB entries. It's the recommended way of flushing in virtualizedenvironments.
So far we got away without implementing it, but Linux for e500mc uses this...
PPC: booke206: Check for TLB overrun
Our internal helpers to fetch TLB entries were not able to tell usthat an entry doesn't even exist. Pass an error out if we hit sucha case to not accidently pass beyond the TLB array.
PPC: booke206: move avail check to tlbwe
We can have TLBs that only support a single page size. This is definedby the absence of the AVAIL flag in TLBnCFG. If this is the case, wecurrently write invalid size info into the TLB, but override it oninternal fault....
PPC: E500: Add some more excp vectors
Our EXCP list is getting outdated. By now, 3 new exception vectors havebeen introduced. Update the list so we have everything at one place.
PPC: KVM: Update HIOR code to new interface
Unfortunately the HIOR setting code slipped into upstream QEMUbefore it was pulled into upstream KVM. And since Murphy is alwaysright, comments on the patches only emerged on the pull requestleading to changes in the interface....
PPC: Add IVOR 38-42
Our code only knows IVORs up to 37. Add the new ones defined in ISA 2.06from 38 - 42.
Signed-off-by: Alexander Graf <agraf@suse.de>Reviewed-by: Andreas Färber <afaerber@suse.de>
PPC: e500mc: add missing IVORs to bitmap
E500mc supports IVORs 36-41. Add them to the support mask. Drop SPEsupport too.
PPC: e500: msync is 440 only, e500 has real sync
The e500 CPUs don't use 440's msync which falls on the same opcode IDs,but instead use the real powerpc sync instruction. This is important,since the invalid mask differs between the two.
PPC: rename msync to msync_4xx
The msync instruction as defined today is only valid on 4xx cores, noton e500 which also supports msync, but treats it the same way as sync.
Rename it to reflect that it's 4xx only.
PPC: booke206: allow NULL raddr in ppcmas_tlb_check
We might want to call the tlb check function without actually caring aboutthe real address resolution. Check if we really should write the valueback.
PPC: Enable 440EP CPU target
Now that we have 440 TLB emulation, we can also support running the 440EPCPU target in system emulation mode.
kvm: fix build error in ppc kvm due to memory_region_init_ram_ptr() change
Commit c5705a772 ("vmstate, memory: decouple vmstate from memory API") changedthe signature of memory_region_init_ram_ptr() but did not update a caller inthe ppc kvm module. Fix....
PPC: Add description for the Freescale e500mc core.
This core is found on chips such as p4080, p3041, p2040, and p5020.
More needs to be done to make this viable for TCG (such as missing SPRsand instructions), but this suffices to get KVM running with appropriate...
kvm-ppc: halt secondary cpus when guest reset
When guest reset, we need to halt secondary cpus until guest kick them.This already works for tcg. The patch add the support for kvm.
Signed-off-by: Liu Yu <yu.liu@freescale.com>Signed-off-by: Alexander Graf <agraf@suse.de>...
PPC: monitor: add ability to dump SLB entries
When run with a PPC Book3S (server) CPU Currently 'info tlb' in theqemu monitor reports "dump_mmu: unimplemented". However, duringbringup work, it can be quite handy to have the SLB entries, which areavailable in the CPUPPCState. This patch adds an implementation of...
fix spelling in target sub directory
Cc: Richard Henderson <rth@twiddle.net>Cc: Edgar E. Iglesias <edgar.iglesias@gmail.com>Cc: Aurelien Jarno <aurelien@aurel32.net>Cc: Alexander Graf <agraf@suse.de>Cc: Aurelien Jarno <aurelien@aurel32.net>Cc: Blue Swirl <blauwirbel@gmail.com>...
PPC: Fix for the gdb single step problem on an rfi instruction
When using gdb to single step a ppc interrupt routine, the executionflow passes the rfi instruction without actually returning from theinterrupt.
The patch fixes this by avoiding to update the nip when the debug...
ppc: Alter CPU state to mask out TCG unimplemented instructions as appropriate
The CPU state contains two bitmaps, initialized from the CPU specwhich describes which instructions are implemented on the CPU. Acouple of bits are defined which cover instructions (VSX and DFP)...
ppc: Fix up usermode only builds
The recent usage of MemoryRegion in kvm_ppc.h breaks builds withCONFIG_USER_ONLY=y. This patch fixes it.
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>Signed-off-by: Alexander Graf <agraf@suse.de>
KVM: PPC: Override host vmx/vsx/dfp only when information known
The -cpu host feature tries to find out the host capabilities basedon device tree information. However, we don't always have that availablebecause it's an optional property in dt.
So instead of force unsetting values depending on an unreliable source...
pseries: Allow writes to KVM accelerated TCE table
Sufficiently recent kernels include a KVM call to accelerate use ofPAPR TCE tables (IOMMU), which are used by PAPR virtual IO devices.This involves qemu mapping the TCE table in from a kernel obtained fd,...
PPC: Disable non-440 CPUs for ppcemb target
The sole reason we have the ppcemb target is to support MMUs that haveless than the usual 4k possible page size. There are very few of thesechips and I don't want to add additional QA and testing burden to everyone...
pseries: Correct vmx/dfp handling in both KVM and TCG cases
Currently, when KVM is enabled, the pseries machine checks if the hostCPU supports VMX, VSX and/or DFP instructions and advertisesaccordingly in the guest device tree. It does this regardless of what...
PPC: Bump qemu-system-ppc to 64-bit physical address space
Some 32-bit PPC CPUs can use up to 36 bit of physical address space.Treat them accordingly in the qemu-system-ppc binary type.