Revision 838335ec
| b/hw/axis_dev88.c | ||
|---|---|---|
| 39 | 39 |
struct nand_state_t |
| 40 | 40 |
{
|
| 41 | 41 |
DeviceState *nand; |
| 42 |
MemoryRegion iomem; |
|
| 42 | 43 |
unsigned int rdy:1; |
| 43 | 44 |
unsigned int ale:1; |
| 44 | 45 |
unsigned int cle:1; |
| ... | ... | |
| 46 | 47 |
}; |
| 47 | 48 |
|
| 48 | 49 |
static struct nand_state_t nand_state; |
| 49 |
static uint32_t nand_readl (void *opaque, target_phys_addr_t addr)
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|
| 50 |
static uint64_t nand_read(void *opaque, target_phys_addr_t addr, unsigned size)
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|
| 50 | 51 |
{
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| 51 | 52 |
struct nand_state_t *s = opaque; |
| 52 | 53 |
uint32_t r; |
| ... | ... | |
| 61 | 62 |
} |
| 62 | 63 |
|
| 63 | 64 |
static void |
| 64 |
nand_writel (void *opaque, target_phys_addr_t addr, uint32_t value) |
|
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nand_write(void *opaque, target_phys_addr_t addr, uint64_t value, |
|
| 66 |
unsigned size) |
|
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{
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struct nand_state_t *s = opaque; |
| 67 | 69 |
int rdy; |
| 68 | 70 |
|
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DNAND(printf("%s addr=%x v=%x\n", __func__, addr, value));
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DNAND(printf("%s addr=%x v=%x\n", __func__, addr, (unsigned)value));
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| 70 | 72 |
nand_setpins(s->nand, s->cle, s->ale, s->ce, 1, 0); |
| 71 | 73 |
nand_setio(s->nand, value); |
| 72 | 74 |
nand_getpins(s->nand, &rdy); |
| 73 | 75 |
s->rdy = rdy; |
| 74 | 76 |
} |
| 75 | 77 |
|
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static CPUReadMemoryFunc * const nand_read[] = {
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&nand_readl,
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&nand_readl,
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&nand_readl,
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static const MemoryRegionOps nand_ops = {
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.read = nand_read,
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.write = nand_write,
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| 81 |
.endianness = DEVICE_NATIVE_ENDIAN,
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| 80 | 82 |
}; |
| 81 | 83 |
|
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static CPUWriteMemoryFunc * const nand_write[] = {
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&nand_writel, |
|
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&nand_writel, |
|
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&nand_writel, |
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}; |
|
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|
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| 88 |
|
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| 89 | 84 |
struct tempsensor_t |
| 90 | 85 |
{
|
| 91 | 86 |
unsigned int shiftreg; |
| ... | ... | |
| 165 | 160 |
|
| 166 | 161 |
static struct gpio_state_t |
| 167 | 162 |
{
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MemoryRegion iomem; |
|
| 168 | 164 |
struct nand_state_t *nand; |
| 169 | 165 |
struct tempsensor_t tempsensor; |
| 170 | 166 |
uint32_t regs[0x5c / 4]; |
| 171 | 167 |
} gpio_state; |
| 172 | 168 |
|
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static uint32_t gpio_readl (void *opaque, target_phys_addr_t addr)
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static uint64_t gpio_read(void *opaque, target_phys_addr_t addr, unsigned size)
|
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| 174 | 170 |
{
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| 175 | 171 |
struct gpio_state_t *s = opaque; |
| 176 | 172 |
uint32_t r = 0; |
| ... | ... | |
| 199 | 195 |
D(printf("%s %x=%x\n", __func__, addr, r));
|
| 200 | 196 |
} |
| 201 | 197 |
|
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static void gpio_writel (void *opaque, target_phys_addr_t addr, uint32_t value) |
|
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static void gpio_write(void *opaque, target_phys_addr_t addr, uint64_t value, |
|
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unsigned size) |
|
| 203 | 200 |
{
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struct gpio_state_t *s = opaque; |
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D(printf("%s %x=%x\n", __func__, addr, value));
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D(printf("%s %x=%x\n", __func__, addr, (unsigned)value));
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| 206 | 203 |
|
| 207 | 204 |
addr >>= 2; |
| 208 | 205 |
switch (addr) |
| ... | ... | |
| 230 | 227 |
} |
| 231 | 228 |
} |
| 232 | 229 |
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static CPUReadMemoryFunc * const gpio_read[] = {
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NULL, NULL,
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&gpio_readl,
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};
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|
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static CPUWriteMemoryFunc * const gpio_write[] = {
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NULL, NULL,
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&gpio_writel,
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static const MemoryRegionOps gpio_ops = {
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.read = gpio_read,
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.write = gpio_write,
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.endianness = DEVICE_NATIVE_ENDIAN,
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.valid = {
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.min_access_size = 4,
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.max_access_size = 4,
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| 237 |
},
|
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| 241 | 238 |
}; |
| 242 | 239 |
|
| 243 | 240 |
#define INTMEM_SIZE (128 * 1024) |
| ... | ... | |
| 258 | 255 |
void *etraxfs_dmac; |
| 259 | 256 |
struct etraxfs_dma_client *dma_eth; |
| 260 | 257 |
int i; |
| 261 |
int nand_regs; |
|
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int gpio_regs; |
|
| 263 | 258 |
MemoryRegion *address_space_mem = get_system_memory(); |
| 264 | 259 |
MemoryRegion *phys_ram = g_new(MemoryRegion, 1); |
| 265 | 260 |
MemoryRegion *phys_intmem = g_new(MemoryRegion, 1); |
| ... | ... | |
| 283 | 278 |
nand = drive_get(IF_MTD, 0, 0); |
| 284 | 279 |
nand_state.nand = nand_init(nand ? nand->bdrv : NULL, |
| 285 | 280 |
NAND_MFR_STMICRO, 0x39); |
| 286 |
nand_regs = cpu_register_io_memory(nand_read, nand_write, &nand_state, |
|
| 287 |
DEVICE_NATIVE_ENDIAN); |
|
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cpu_register_physical_memory(0x10000000, 0x05000000, nand_regs); |
|
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memory_region_init_io(&nand_state.iomem, &nand_ops, &nand_state, |
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"nand", 0x05000000); |
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memory_region_add_subregion(address_space_mem, 0x10000000, |
|
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&nand_state.iomem); |
|
| 289 | 285 |
|
| 290 | 286 |
gpio_state.nand = &nand_state; |
| 291 |
gpio_regs = cpu_register_io_memory(gpio_read, gpio_write, &gpio_state, |
|
| 292 |
DEVICE_NATIVE_ENDIAN); |
|
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cpu_register_physical_memory(0x3001a000, 0x5c, gpio_regs); |
|
| 287 |
memory_region_init_io(&gpio_state.iomem, &gpio_ops, &gpio_state, |
|
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"gpio", 0x5c); |
|
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memory_region_add_subregion(address_space_mem, 0x3001a000, |
|
| 290 |
&gpio_state.iomem); |
|
| 294 | 291 |
|
| 295 | 292 |
|
| 296 | 293 |
cpu_irq = cris_pic_init_cpu(env); |
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