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1 | 83fa1010 | ths | /*
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2 | 83fa1010 | ths | * QEMU ETRAX System Emulator
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3 | 83fa1010 | ths | *
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4 | 83fa1010 | ths | * Copyright (c) 2007 Edgar E. Iglesias, Axis Communications AB.
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5 | 83fa1010 | ths | *
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6 | 83fa1010 | ths | * Permission is hereby granted, free of charge, to any person obtaining a copy
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7 | 83fa1010 | ths | * of this software and associated documentation files (the "Software"), to deal
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8 | 83fa1010 | ths | * in the Software without restriction, including without limitation the rights
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9 | 83fa1010 | ths | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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10 | 83fa1010 | ths | * copies of the Software, and to permit persons to whom the Software is
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11 | 83fa1010 | ths | * furnished to do so, subject to the following conditions:
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12 | 83fa1010 | ths | *
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13 | 83fa1010 | ths | * The above copyright notice and this permission notice shall be included in
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14 | 83fa1010 | ths | * all copies or substantial portions of the Software.
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15 | 83fa1010 | ths | *
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16 | 83fa1010 | ths | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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17 | 83fa1010 | ths | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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18 | 83fa1010 | ths | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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19 | 83fa1010 | ths | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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20 | 83fa1010 | ths | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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21 | 83fa1010 | ths | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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22 | 83fa1010 | ths | * THE SOFTWARE.
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23 | 83fa1010 | ths | */
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24 | 83fa1010 | ths | #include <time.h> |
25 | 83fa1010 | ths | #include <sys/time.h> |
26 | 83fa1010 | ths | #include "vl.h" |
27 | 83fa1010 | ths | |
28 | 83fa1010 | ths | extern FILE *logfile;
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29 | 83fa1010 | ths | |
30 | 83fa1010 | ths | static void main_cpu_reset(void *opaque) |
31 | 83fa1010 | ths | { |
32 | 83fa1010 | ths | CPUState *env = opaque; |
33 | 83fa1010 | ths | cpu_reset(env); |
34 | 83fa1010 | ths | } |
35 | 83fa1010 | ths | |
36 | 83fa1010 | ths | static uint32_t fs_mmio_readb (void *opaque, target_phys_addr_t addr) |
37 | 83fa1010 | ths | { |
38 | 83fa1010 | ths | CPUState *env = opaque; |
39 | 83fa1010 | ths | uint32_t r = 0;
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40 | 83fa1010 | ths | printf ("%s %x pc=%x\n", __func__, addr, env->pc);
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41 | 83fa1010 | ths | return r;
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42 | 83fa1010 | ths | } |
43 | 83fa1010 | ths | static uint32_t fs_mmio_readw (void *opaque, target_phys_addr_t addr) |
44 | 83fa1010 | ths | { |
45 | 83fa1010 | ths | CPUState *env = opaque; |
46 | 83fa1010 | ths | uint32_t r = 0;
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47 | 83fa1010 | ths | printf ("%s %x pc=%x\n", __func__, addr, env->pc);
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48 | 83fa1010 | ths | return r;
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49 | 83fa1010 | ths | } |
50 | 83fa1010 | ths | |
51 | 83fa1010 | ths | static uint32_t fs_mmio_readl (void *opaque, target_phys_addr_t addr) |
52 | 83fa1010 | ths | { |
53 | 83fa1010 | ths | CPUState *env = opaque; |
54 | 83fa1010 | ths | uint32_t r = 0;
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55 | 83fa1010 | ths | printf ("%s %x p=%x\n", __func__, addr, env->pc);
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56 | 83fa1010 | ths | return r;
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57 | 83fa1010 | ths | } |
58 | 83fa1010 | ths | |
59 | 83fa1010 | ths | static void |
60 | 83fa1010 | ths | fs_mmio_writeb (void *opaque, target_phys_addr_t addr, uint32_t value)
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61 | 83fa1010 | ths | { |
62 | 83fa1010 | ths | CPUState *env = opaque; |
63 | 83fa1010 | ths | printf ("%s %x %x pc=%x\n", __func__, addr, value, env->pc);
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64 | 83fa1010 | ths | } |
65 | 83fa1010 | ths | static void |
66 | 83fa1010 | ths | fs_mmio_writew (void *opaque, target_phys_addr_t addr, uint32_t value)
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67 | 83fa1010 | ths | { |
68 | 83fa1010 | ths | CPUState *env = opaque; |
69 | 83fa1010 | ths | printf ("%s %x %x pc=%x\n", __func__, addr, value, env->pc);
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70 | 83fa1010 | ths | } |
71 | 83fa1010 | ths | static void |
72 | 83fa1010 | ths | fs_mmio_writel (void *opaque, target_phys_addr_t addr, uint32_t value)
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73 | 83fa1010 | ths | { |
74 | 83fa1010 | ths | CPUState *env = opaque; |
75 | 83fa1010 | ths | printf ("%s %x %x pc=%x\n", __func__, addr, value, env->pc);
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76 | 83fa1010 | ths | } |
77 | 83fa1010 | ths | |
78 | 83fa1010 | ths | static CPUReadMemoryFunc *fs_mmio_read[] = {
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79 | 83fa1010 | ths | &fs_mmio_readb, |
80 | 83fa1010 | ths | &fs_mmio_readw, |
81 | 83fa1010 | ths | &fs_mmio_readl, |
82 | 83fa1010 | ths | }; |
83 | 83fa1010 | ths | |
84 | 83fa1010 | ths | static CPUWriteMemoryFunc *fs_mmio_write[] = {
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85 | 83fa1010 | ths | &fs_mmio_writeb, |
86 | 83fa1010 | ths | &fs_mmio_writew, |
87 | 83fa1010 | ths | &fs_mmio_writel, |
88 | 83fa1010 | ths | }; |
89 | 83fa1010 | ths | |
90 | 83fa1010 | ths | |
91 | 83fa1010 | ths | /* Init functions for different blocks. */
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92 | 83fa1010 | ths | extern void etraxfs_timer_init(CPUState *env, qemu_irq *irqs); |
93 | 83fa1010 | ths | extern void etraxfs_ser_init(CPUState *env, qemu_irq *irqs); |
94 | 83fa1010 | ths | |
95 | 83fa1010 | ths | void etrax_ack_irq(CPUState *env, uint32_t mask)
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96 | 83fa1010 | ths | { |
97 | 83fa1010 | ths | env->pending_interrupts &= ~mask; |
98 | 83fa1010 | ths | } |
99 | 83fa1010 | ths | |
100 | 83fa1010 | ths | static void dummy_cpu_set_irq(void *opaque, int irq, int level) |
101 | 83fa1010 | ths | { |
102 | 83fa1010 | ths | CPUState *env = opaque; |
103 | 83fa1010 | ths | |
104 | 83fa1010 | ths | /* Hmm, should this really be done here? */
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105 | 83fa1010 | ths | env->pending_interrupts |= 1 << irq;
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106 | 83fa1010 | ths | cpu_interrupt(env, CPU_INTERRUPT_HARD); |
107 | 83fa1010 | ths | } |
108 | 83fa1010 | ths | |
109 | 83fa1010 | ths | static
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110 | 83fa1010 | ths | void bareetraxfs_init (int ram_size, int vga_ram_size, int boot_device, |
111 | 83fa1010 | ths | DisplayState *ds, const char **fd_filename, int snapshot, |
112 | 83fa1010 | ths | const char *kernel_filename, const char *kernel_cmdline, |
113 | 83fa1010 | ths | const char *initrd_filename, const char *cpu_model) |
114 | 83fa1010 | ths | { |
115 | 83fa1010 | ths | CPUState *env; |
116 | 83fa1010 | ths | qemu_irq *irqs; |
117 | 83fa1010 | ths | int kernel_size;
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118 | 83fa1010 | ths | int internal_regs;
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119 | 83fa1010 | ths | |
120 | 83fa1010 | ths | /* init CPUs */
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121 | 83fa1010 | ths | if (cpu_model == NULL) { |
122 | 83fa1010 | ths | cpu_model = "crisv32";
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123 | 83fa1010 | ths | } |
124 | 83fa1010 | ths | env = cpu_init(); |
125 | 83fa1010 | ths | /* register_savevm("cpu", 0, 3, cpu_save, cpu_load, env); */
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126 | 83fa1010 | ths | qemu_register_reset(main_cpu_reset, env); |
127 | 83fa1010 | ths | irqs = qemu_allocate_irqs(dummy_cpu_set_irq, env, 32);
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128 | 83fa1010 | ths | |
129 | 83fa1010 | ths | internal_regs = cpu_register_io_memory(0,
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130 | 83fa1010 | ths | fs_mmio_read, fs_mmio_write, env); |
131 | 83fa1010 | ths | /* 0xb0050000 is the last reg. */
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132 | 83fa1010 | ths | cpu_register_physical_memory (0xac000000, 0x4010000, internal_regs); |
133 | 83fa1010 | ths | /* allocate RAM */
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134 | 83fa1010 | ths | cpu_register_physical_memory(0x40000000, ram_size, IO_MEM_RAM);
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135 | 83fa1010 | ths | |
136 | 83fa1010 | ths | etraxfs_timer_init(env, irqs); |
137 | 83fa1010 | ths | etraxfs_ser_init(env, irqs); |
138 | 83fa1010 | ths | |
139 | 83fa1010 | ths | kernel_size = load_image(kernel_filename, phys_ram_base + 0x4000);
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140 | 83fa1010 | ths | /* magic for boot. */
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141 | 83fa1010 | ths | env->regs[8] = 0x56902387; |
142 | 83fa1010 | ths | env->regs[9] = 0x40004000 + kernel_size; |
143 | 83fa1010 | ths | env->pc = 0x40004000;
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144 | 83fa1010 | ths | |
145 | 83fa1010 | ths | { |
146 | 83fa1010 | ths | unsigned char *ptr = phys_ram_base + 0x4000; |
147 | 83fa1010 | ths | int i;
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148 | 83fa1010 | ths | for (i = 0; i < 8; i++) |
149 | 83fa1010 | ths | { |
150 | 83fa1010 | ths | printf ("%2.2x ", ptr[i]);
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151 | 83fa1010 | ths | } |
152 | 83fa1010 | ths | printf("\n");
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153 | 83fa1010 | ths | } |
154 | 83fa1010 | ths | |
155 | 83fa1010 | ths | printf ("pc =%x\n", env->pc);
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156 | 83fa1010 | ths | printf ("ram size =%d\n", ram_size);
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157 | 83fa1010 | ths | printf ("kernel name =%s\n", kernel_filename);
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158 | 83fa1010 | ths | printf ("kernel size =%d\n", kernel_size);
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159 | 83fa1010 | ths | printf ("cpu haltd =%d\n", env->halted);
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160 | 83fa1010 | ths | } |
161 | 83fa1010 | ths | |
162 | 83fa1010 | ths | void DMA_run(void) |
163 | 83fa1010 | ths | { |
164 | 83fa1010 | ths | } |
165 | 83fa1010 | ths | |
166 | 83fa1010 | ths | void pic_info()
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167 | 83fa1010 | ths | { |
168 | 83fa1010 | ths | } |
169 | 83fa1010 | ths | |
170 | 83fa1010 | ths | void irq_info()
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171 | 83fa1010 | ths | { |
172 | 83fa1010 | ths | } |
173 | 83fa1010 | ths | |
174 | 83fa1010 | ths | QEMUMachine bareetraxfs_machine = { |
175 | 83fa1010 | ths | "bareetraxfs",
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176 | 83fa1010 | ths | "Bare ETRAX FS board",
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177 | 83fa1010 | ths | bareetraxfs_init, |
178 | 83fa1010 | ths | }; |