Revision 84108e12 hw/isa_mmio.c
| b/hw/isa_mmio.c | ||
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| 31 | 31 |
cpu_outb(addr & IOPORTS_MASK, val); |
| 32 | 32 |
} |
| 33 | 33 |
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static void isa_mmio_writew (void *opaque, target_phys_addr_t addr,
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uint32_t val)
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static void isa_mmio_writew_be(void *opaque, target_phys_addr_t addr,
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uint32_t val) |
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{
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#ifdef TARGET_WORDS_BIGENDIAN |
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val = bswap16(val); |
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#endif |
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| 40 | 38 |
cpu_outw(addr & IOPORTS_MASK, val); |
| 41 | 39 |
} |
| 42 | 40 |
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static void isa_mmio_writel (void *opaque, target_phys_addr_t addr, |
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uint32_t val) |
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static void isa_mmio_writew_le(void *opaque, target_phys_addr_t addr, |
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uint32_t val) |
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{
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cpu_outw(addr & IOPORTS_MASK, val); |
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} |
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static void isa_mmio_writel_be(void *opaque, target_phys_addr_t addr, |
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uint32_t val) |
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{
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#ifdef TARGET_WORDS_BIGENDIAN |
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val = bswap32(val); |
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#endif |
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cpu_outl(addr & IOPORTS_MASK, val); |
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} |
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static void isa_mmio_writel_le(void *opaque, target_phys_addr_t addr, |
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uint32_t val) |
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{
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cpu_outl(addr & IOPORTS_MASK, val); |
| 50 | 58 |
} |
| 51 | 59 |
|
| ... | ... | |
| 57 | 65 |
return val; |
| 58 | 66 |
} |
| 59 | 67 |
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static uint32_t isa_mmio_readw (void *opaque, target_phys_addr_t addr)
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static uint32_t isa_mmio_readw_be(void *opaque, target_phys_addr_t addr)
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{
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uint32_t val; |
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val = cpu_inw(addr & IOPORTS_MASK); |
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#ifdef TARGET_WORDS_BIGENDIAN |
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val = bswap16(val); |
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#endif |
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return val; |
| 69 | 75 |
} |
| 70 | 76 |
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static uint32_t isa_mmio_readl (void *opaque, target_phys_addr_t addr) |
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static uint32_t isa_mmio_readw_le(void *opaque, target_phys_addr_t addr) |
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{
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uint32_t val; |
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val = cpu_inw(addr & IOPORTS_MASK); |
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return val; |
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} |
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static uint32_t isa_mmio_readl_be(void *opaque, target_phys_addr_t addr) |
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| 72 | 86 |
{
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uint32_t val; |
| 74 | 88 |
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val = cpu_inl(addr & IOPORTS_MASK); |
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#ifdef TARGET_WORDS_BIGENDIAN |
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val = bswap32(val); |
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#endif |
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| 79 | 91 |
return val; |
| 80 | 92 |
} |
| 81 | 93 |
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static CPUWriteMemoryFunc * const isa_mmio_write[] = {
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static uint32_t isa_mmio_readl_le(void *opaque, target_phys_addr_t addr) |
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{
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uint32_t val; |
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val = cpu_inl(addr & IOPORTS_MASK); |
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return val; |
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} |
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static CPUWriteMemoryFunc * const isa_mmio_write_be[] = {
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&isa_mmio_writeb, |
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&isa_mmio_writew_be, |
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&isa_mmio_writel_be, |
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}; |
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static CPUReadMemoryFunc * const isa_mmio_read_be[] = {
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&isa_mmio_readb, |
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&isa_mmio_readw_be, |
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&isa_mmio_readl_be, |
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}; |
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static CPUWriteMemoryFunc * const isa_mmio_write_le[] = {
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&isa_mmio_writeb, |
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&isa_mmio_writew, |
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&isa_mmio_writel, |
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&isa_mmio_writew_le,
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&isa_mmio_writel_le,
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| 86 | 118 |
}; |
| 87 | 119 |
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static CPUReadMemoryFunc * const isa_mmio_read[] = {
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static CPUReadMemoryFunc * const isa_mmio_read_le[] = {
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&isa_mmio_readb, |
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&isa_mmio_readw, |
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&isa_mmio_readl, |
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&isa_mmio_readw_le,
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&isa_mmio_readl_le,
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}; |
| 93 | 125 |
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static int isa_mmio_iomemtype = 0; |
| 95 | 127 |
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void isa_mmio_init(target_phys_addr_t base, target_phys_addr_t size) |
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void isa_mmio_init(target_phys_addr_t base, target_phys_addr_t size, int be)
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{
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| 98 | 130 |
if (!isa_mmio_iomemtype) {
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isa_mmio_iomemtype = cpu_register_io_memory(isa_mmio_read, |
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isa_mmio_write, NULL); |
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if (be) {
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isa_mmio_iomemtype = cpu_register_io_memory(isa_mmio_read_be, |
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isa_mmio_write_be, |
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NULL); |
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} else {
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isa_mmio_iomemtype = cpu_register_io_memory(isa_mmio_read_le, |
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isa_mmio_write_le, |
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NULL); |
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} |
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| 101 | 140 |
} |
| 102 | 141 |
cpu_register_physical_memory(base, size, isa_mmio_iomemtype); |
| 103 | 142 |
} |
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