Revision 845769fc
| b/hw/a9mpcore.c | ||
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| 12 | 12 |
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/* A9MP private memory region. */ |
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typedef struct a9mp_priv_state {
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typedef struct A9MPPrivState {
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SysBusDevice busdev; |
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uint32_t scu_control; |
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uint32_t scu_status; |
| ... | ... | |
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DeviceState *mptimer; |
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DeviceState *gic; |
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uint32_t num_irq; |
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} a9mp_priv_state;
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} A9MPPrivState;
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static uint64_t a9_scu_read(void *opaque, hwaddr offset, |
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unsigned size) |
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{
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a9mp_priv_state *s = (a9mp_priv_state *)opaque;
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A9MPPrivState *s = (A9MPPrivState *)opaque;
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switch (offset) {
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case 0x00: /* Control */ |
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return s->scu_control; |
| ... | ... | |
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static void a9_scu_write(void *opaque, hwaddr offset, |
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uint64_t value, unsigned size) |
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{
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a9mp_priv_state *s = (a9mp_priv_state *)opaque;
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A9MPPrivState *s = (A9MPPrivState *)opaque;
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uint32_t mask; |
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uint32_t shift; |
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switch (size) {
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static void a9mp_priv_reset(DeviceState *dev) |
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{
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a9mp_priv_state *s = FROM_SYSBUS(a9mp_priv_state, SYS_BUS_DEVICE(dev));
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A9MPPrivState *s = FROM_SYSBUS(A9MPPrivState, SYS_BUS_DEVICE(dev));
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int i; |
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s->scu_control = 0; |
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for (i = 0; i < ARRAY_SIZE(s->old_timer_status); i++) {
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| ... | ... | |
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static void a9mp_priv_set_irq(void *opaque, int irq, int level) |
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{
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a9mp_priv_state *s = (a9mp_priv_state *)opaque;
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A9MPPrivState *s = (A9MPPrivState *)opaque;
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qemu_set_irq(qdev_get_gpio_in(s->gic, irq), level); |
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} |
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static int a9mp_priv_init(SysBusDevice *dev) |
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{
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a9mp_priv_state *s = FROM_SYSBUS(a9mp_priv_state, dev);
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A9MPPrivState *s = FROM_SYSBUS(A9MPPrivState, dev);
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SysBusDevice *busdev, *gicbusdev; |
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int i; |
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|
| ... | ... | |
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.version_id = 2, |
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.minimum_version_id = 1, |
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.fields = (VMStateField[]) {
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VMSTATE_UINT32(scu_control, a9mp_priv_state),
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VMSTATE_UINT32_ARRAY(old_timer_status, a9mp_priv_state, 8),
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VMSTATE_UINT32_V(scu_status, a9mp_priv_state, 2),
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VMSTATE_UINT32(scu_control, A9MPPrivState),
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VMSTATE_UINT32_ARRAY(old_timer_status, A9MPPrivState, 8),
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VMSTATE_UINT32_V(scu_status, A9MPPrivState, 2),
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VMSTATE_END_OF_LIST() |
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} |
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}; |
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static Property a9mp_priv_properties[] = {
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DEFINE_PROP_UINT32("num-cpu", a9mp_priv_state, num_cpu, 1),
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DEFINE_PROP_UINT32("num-cpu", A9MPPrivState, num_cpu, 1),
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/* The Cortex-A9MP may have anything from 0 to 224 external interrupt |
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* IRQ lines (with another 32 internal). We default to 64+32, which |
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* is the number provided by the Cortex-A9MP test chip in the |
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* Realview PBX-A9 and Versatile Express A9 development boards. |
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* Other boards may differ and should set this property appropriately. |
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*/ |
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DEFINE_PROP_UINT32("num-irq", a9mp_priv_state, num_irq, 96),
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DEFINE_PROP_UINT32("num-irq", A9MPPrivState, num_irq, 96),
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DEFINE_PROP_END_OF_LIST(), |
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}; |
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|
| ... | ... | |
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static const TypeInfo a9mp_priv_info = {
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.name = "a9mpcore_priv", |
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.parent = TYPE_SYS_BUS_DEVICE, |
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.instance_size = sizeof(a9mp_priv_state),
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.instance_size = sizeof(A9MPPrivState),
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.class_init = a9mp_priv_class_init, |
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}; |
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|
| b/hw/arm11mpcore.c | ||
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| 12 | 12 |
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/* MPCore private memory region. */ |
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typedef struct mpcore_priv_state {
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typedef struct ARM11MPCorePriveState {
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SysBusDevice busdev; |
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uint32_t scu_control; |
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int iomemtype; |
| ... | ... | |
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DeviceState *mptimer; |
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DeviceState *gic; |
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uint32_t num_irq; |
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} mpcore_priv_state;
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} ARM11MPCorePriveState;
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/* Per-CPU private memory mapped IO. */ |
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static uint64_t mpcore_scu_read(void *opaque, hwaddr offset, |
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unsigned size) |
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{
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mpcore_priv_state *s = (mpcore_priv_state *)opaque;
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ARM11MPCorePriveState *s = (ARM11MPCorePriveState *)opaque;
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int id; |
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/* SCU */ |
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switch (offset) {
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| ... | ... | |
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static void mpcore_scu_write(void *opaque, hwaddr offset, |
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uint64_t value, unsigned size) |
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{
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mpcore_priv_state *s = (mpcore_priv_state *)opaque;
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ARM11MPCorePriveState *s = (ARM11MPCorePriveState *)opaque;
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/* SCU */ |
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switch (offset) {
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case 0: /* Control register. */ |
| ... | ... | |
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static void mpcore_priv_set_irq(void *opaque, int irq, int level) |
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{
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mpcore_priv_state *s = (mpcore_priv_state *)opaque;
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ARM11MPCorePriveState *s = (ARM11MPCorePriveState *)opaque;
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qemu_set_irq(qdev_get_gpio_in(s->gic, irq), level); |
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} |
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static void mpcore_priv_map_setup(mpcore_priv_state *s)
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static void mpcore_priv_map_setup(ARM11MPCorePriveState *s)
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{
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int i; |
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SysBusDevice *gicbusdev = SYS_BUS_DEVICE(s->gic); |
| ... | ... | |
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static int mpcore_priv_init(SysBusDevice *dev) |
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{
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mpcore_priv_state *s = FROM_SYSBUS(mpcore_priv_state, dev);
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ARM11MPCorePriveState *s = FROM_SYSBUS(ARM11MPCorePriveState, dev);
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s->gic = qdev_create(NULL, "arm_gic"); |
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qdev_prop_set_uint32(s->gic, "num-cpu", s->num_cpu); |
| ... | ... | |
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}; |
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static Property mpcore_priv_properties[] = {
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DEFINE_PROP_UINT32("num-cpu", mpcore_priv_state, num_cpu, 1),
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DEFINE_PROP_UINT32("num-cpu", ARM11MPCorePriveState, num_cpu, 1),
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/* The ARM11 MPCORE TRM says the on-chip controller may have |
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* anything from 0 to 224 external interrupt IRQ lines (with another |
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* 32 internal). We default to 32+32, which is the number provided by |
| ... | ... | |
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* appropriately. Some Linux kernels may not boot if the hardware |
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* has more IRQ lines than the kernel expects. |
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*/ |
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DEFINE_PROP_UINT32("num-irq", mpcore_priv_state, num_irq, 64),
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DEFINE_PROP_UINT32("num-irq", ARM11MPCorePriveState, num_irq, 64),
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DEFINE_PROP_END_OF_LIST(), |
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}; |
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|
| ... | ... | |
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static const TypeInfo mpcore_priv_info = {
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.name = "arm11mpcore_priv", |
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.parent = TYPE_SYS_BUS_DEVICE, |
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.instance_size = sizeof(mpcore_priv_state),
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.instance_size = sizeof(ARM11MPCorePriveState),
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.class_init = mpcore_priv_class_init, |
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}; |
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