root / target-arm / translate-a64.c @ 845ea09a
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/*
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* AArch64 translation
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*
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* Copyright (c) 2013 Alexander Graf <agraf@suse.de>
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include <stdarg.h> |
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#include <stdlib.h> |
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#include <stdio.h> |
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#include <string.h> |
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#include <inttypes.h> |
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#include "cpu.h" |
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#include "tcg-op.h" |
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#include "qemu/log.h" |
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#include "translate.h" |
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#include "qemu/host-utils.h" |
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#include "exec/gen-icount.h" |
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#include "helper.h" |
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#define GEN_HELPER 1 |
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#include "helper.h" |
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static TCGv_i64 cpu_X[32]; |
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static TCGv_i64 cpu_pc;
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static TCGv_i32 cpu_NF, cpu_ZF, cpu_CF, cpu_VF;
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/* Load/store exclusive handling */
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static TCGv_i64 cpu_exclusive_addr;
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static TCGv_i64 cpu_exclusive_val;
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static TCGv_i64 cpu_exclusive_high;
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#ifdef CONFIG_USER_ONLY
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static TCGv_i64 cpu_exclusive_test;
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static TCGv_i32 cpu_exclusive_info;
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#endif
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static const char *regnames[] = { |
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"x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7", |
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"x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15", |
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"x16", "x17", "x18", "x19", "x20", "x21", "x22", "x23", |
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"x24", "x25", "x26", "x27", "x28", "x29", "lr", "sp" |
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}; |
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enum a64_shift_type {
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A64_SHIFT_TYPE_LSL = 0,
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A64_SHIFT_TYPE_LSR = 1,
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A64_SHIFT_TYPE_ASR = 2,
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A64_SHIFT_TYPE_ROR = 3
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}; |
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/* Table based decoder typedefs - used when the relevant bits for decode
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* are too awkwardly scattered across the instruction (eg SIMD).
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*/
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typedef void AArch64DecodeFn(DisasContext *s, uint32_t insn); |
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typedef struct AArch64DecodeTable { |
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uint32_t pattern; |
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uint32_t mask; |
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AArch64DecodeFn *disas_fn; |
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} AArch64DecodeTable; |
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/* Function prototype for gen_ functions for calling Neon helpers */
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typedef void NeonGenTwoOpFn(TCGv_i32, TCGv_i32, TCGv_i32); |
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/* initialize TCG globals. */
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void a64_translate_init(void) |
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{ |
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int i;
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cpu_pc = tcg_global_mem_new_i64(TCG_AREG0, |
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offsetof(CPUARMState, pc), |
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"pc");
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for (i = 0; i < 32; i++) { |
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cpu_X[i] = tcg_global_mem_new_i64(TCG_AREG0, |
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offsetof(CPUARMState, xregs[i]), |
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regnames[i]); |
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} |
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cpu_NF = tcg_global_mem_new_i32(TCG_AREG0, offsetof(CPUARMState, NF), "NF");
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cpu_ZF = tcg_global_mem_new_i32(TCG_AREG0, offsetof(CPUARMState, ZF), "ZF");
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cpu_CF = tcg_global_mem_new_i32(TCG_AREG0, offsetof(CPUARMState, CF), "CF");
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cpu_VF = tcg_global_mem_new_i32(TCG_AREG0, offsetof(CPUARMState, VF), "VF");
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cpu_exclusive_addr = tcg_global_mem_new_i64(TCG_AREG0, |
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offsetof(CPUARMState, exclusive_addr), "exclusive_addr");
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cpu_exclusive_val = tcg_global_mem_new_i64(TCG_AREG0, |
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offsetof(CPUARMState, exclusive_val), "exclusive_val");
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cpu_exclusive_high = tcg_global_mem_new_i64(TCG_AREG0, |
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offsetof(CPUARMState, exclusive_high), "exclusive_high");
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#ifdef CONFIG_USER_ONLY
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cpu_exclusive_test = tcg_global_mem_new_i64(TCG_AREG0, |
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offsetof(CPUARMState, exclusive_test), "exclusive_test");
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cpu_exclusive_info = tcg_global_mem_new_i32(TCG_AREG0, |
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offsetof(CPUARMState, exclusive_info), "exclusive_info");
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#endif
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} |
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void aarch64_cpu_dump_state(CPUState *cs, FILE *f,
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fprintf_function cpu_fprintf, int flags)
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{ |
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ARMCPU *cpu = ARM_CPU(cs); |
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CPUARMState *env = &cpu->env; |
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uint32_t psr = pstate_read(env); |
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int i;
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cpu_fprintf(f, "PC=%016"PRIx64" SP=%016"PRIx64"\n", |
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env->pc, env->xregs[31]);
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for (i = 0; i < 31; i++) { |
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cpu_fprintf(f, "X%02d=%016"PRIx64, i, env->xregs[i]);
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if ((i % 4) == 3) { |
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cpu_fprintf(f, "\n");
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} else {
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cpu_fprintf(f, " ");
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} |
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} |
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cpu_fprintf(f, "PSTATE=%08x (flags %c%c%c%c)\n",
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psr, |
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psr & PSTATE_N ? 'N' : '-', |
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psr & PSTATE_Z ? 'Z' : '-', |
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psr & PSTATE_C ? 'C' : '-', |
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psr & PSTATE_V ? 'V' : '-'); |
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cpu_fprintf(f, "\n");
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if (flags & CPU_DUMP_FPU) {
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int numvfpregs = 32; |
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for (i = 0; i < numvfpregs; i += 2) { |
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uint64_t vlo = float64_val(env->vfp.regs[i * 2]);
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uint64_t vhi = float64_val(env->vfp.regs[(i * 2) + 1]); |
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cpu_fprintf(f, "q%02d=%016" PRIx64 ":%016" PRIx64 " ", |
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i, vhi, vlo); |
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vlo = float64_val(env->vfp.regs[(i + 1) * 2]); |
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vhi = float64_val(env->vfp.regs[((i + 1) * 2) + 1]); |
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cpu_fprintf(f, "q%02d=%016" PRIx64 ":%016" PRIx64 "\n", |
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i + 1, vhi, vlo);
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} |
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cpu_fprintf(f, "FPCR: %08x FPSR: %08x\n",
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vfp_get_fpcr(env), vfp_get_fpsr(env)); |
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} |
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} |
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static int get_mem_index(DisasContext *s) |
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{ |
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#ifdef CONFIG_USER_ONLY
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return 1; |
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#else
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return s->user;
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#endif
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} |
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void gen_a64_set_pc_im(uint64_t val)
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{ |
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tcg_gen_movi_i64(cpu_pc, val); |
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} |
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static void gen_exception(int excp) |
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{ |
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TCGv_i32 tmp = tcg_temp_new_i32(); |
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tcg_gen_movi_i32(tmp, excp); |
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gen_helper_exception(cpu_env, tmp); |
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tcg_temp_free_i32(tmp); |
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} |
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static void gen_exception_insn(DisasContext *s, int offset, int excp) |
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{ |
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gen_a64_set_pc_im(s->pc - offset); |
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gen_exception(excp); |
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s->is_jmp = DISAS_EXC; |
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} |
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static inline bool use_goto_tb(DisasContext *s, int n, uint64_t dest) |
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{ |
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/* No direct tb linking with singlestep or deterministic io */
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if (s->singlestep_enabled || (s->tb->cflags & CF_LAST_IO)) {
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return false; |
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} |
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/* Only link tbs from inside the same guest page */
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if ((s->tb->pc & TARGET_PAGE_MASK) != (dest & TARGET_PAGE_MASK)) {
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return false; |
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} |
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return true; |
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} |
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static inline void gen_goto_tb(DisasContext *s, int n, uint64_t dest) |
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{ |
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TranslationBlock *tb; |
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tb = s->tb; |
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if (use_goto_tb(s, n, dest)) {
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tcg_gen_goto_tb(n); |
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gen_a64_set_pc_im(dest); |
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tcg_gen_exit_tb((tcg_target_long)tb + n); |
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s->is_jmp = DISAS_TB_JUMP; |
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} else {
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gen_a64_set_pc_im(dest); |
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if (s->singlestep_enabled) {
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gen_exception(EXCP_DEBUG); |
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} |
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tcg_gen_exit_tb(0);
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s->is_jmp = DISAS_JUMP; |
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} |
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} |
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static void unallocated_encoding(DisasContext *s) |
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{ |
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gen_exception_insn(s, 4, EXCP_UDEF);
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} |
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#define unsupported_encoding(s, insn) \
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do { \
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qemu_log_mask(LOG_UNIMP, \ |
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"%s:%d: unsupported instruction encoding 0x%08x " \
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"at pc=%016" PRIx64 "\n", \ |
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__FILE__, __LINE__, insn, s->pc - 4); \
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unallocated_encoding(s); \ |
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} while (0); |
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static void init_tmp_a64_array(DisasContext *s) |
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{ |
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#ifdef CONFIG_DEBUG_TCG
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int i;
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for (i = 0; i < ARRAY_SIZE(s->tmp_a64); i++) { |
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TCGV_UNUSED_I64(s->tmp_a64[i]); |
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} |
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#endif
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s->tmp_a64_count = 0;
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} |
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static void free_tmp_a64(DisasContext *s) |
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{ |
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int i;
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for (i = 0; i < s->tmp_a64_count; i++) { |
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tcg_temp_free_i64(s->tmp_a64[i]); |
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} |
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init_tmp_a64_array(s); |
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} |
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static TCGv_i64 new_tmp_a64(DisasContext *s)
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{ |
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assert(s->tmp_a64_count < TMP_A64_MAX); |
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return s->tmp_a64[s->tmp_a64_count++] = tcg_temp_new_i64();
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} |
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static TCGv_i64 new_tmp_a64_zero(DisasContext *s)
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{ |
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TCGv_i64 t = new_tmp_a64(s); |
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tcg_gen_movi_i64(t, 0);
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return t;
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} |
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/*
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* Register access functions
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*
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* These functions are used for directly accessing a register in where
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* changes to the final register value are likely to be made. If you
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* need to use a register for temporary calculation (e.g. index type
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* operations) use the read_* form.
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*
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* B1.2.1 Register mappings
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*
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* In instruction register encoding 31 can refer to ZR (zero register) or
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* the SP (stack pointer) depending on context. In QEMU's case we map SP
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* to cpu_X[31] and ZR accesses to a temporary which can be discarded.
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* This is the point of the _sp forms.
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*/
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static TCGv_i64 cpu_reg(DisasContext *s, int reg) |
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{ |
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if (reg == 31) { |
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return new_tmp_a64_zero(s);
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} else {
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return cpu_X[reg];
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} |
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} |
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/* register access for when 31 == SP */
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static TCGv_i64 cpu_reg_sp(DisasContext *s, int reg) |
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{ |
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return cpu_X[reg];
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} |
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/* read a cpu register in 32bit/64bit mode. Returns a TCGv_i64
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* representing the register contents. This TCGv is an auto-freed
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* temporary so it need not be explicitly freed, and may be modified.
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*/
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static TCGv_i64 read_cpu_reg(DisasContext *s, int reg, int sf) |
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{ |
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TCGv_i64 v = new_tmp_a64(s); |
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if (reg != 31) { |
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if (sf) {
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tcg_gen_mov_i64(v, cpu_X[reg]); |
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} else {
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tcg_gen_ext32u_i64(v, cpu_X[reg]); |
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} |
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} else {
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tcg_gen_movi_i64(v, 0);
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} |
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return v;
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} |
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static TCGv_i64 read_cpu_reg_sp(DisasContext *s, int reg, int sf) |
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{ |
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TCGv_i64 v = new_tmp_a64(s); |
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if (sf) {
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tcg_gen_mov_i64(v, cpu_X[reg]); |
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} else {
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tcg_gen_ext32u_i64(v, cpu_X[reg]); |
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} |
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return v;
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} |
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/* Return the offset into CPUARMState of an element of specified
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* size, 'element' places in from the least significant end of
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* the FP/vector register Qn.
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*/
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static inline int vec_reg_offset(int regno, int element, TCGMemOp size) |
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{ |
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int offs = offsetof(CPUARMState, vfp.regs[regno * 2]); |
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#ifdef HOST_WORDS_BIGENDIAN
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/* This is complicated slightly because vfp.regs[2n] is
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* still the low half and vfp.regs[2n+1] the high half
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* of the 128 bit vector, even on big endian systems.
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* Calculate the offset assuming a fully bigendian 128 bits,
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* then XOR to account for the order of the two 64 bit halves.
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*/
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offs += (16 - ((element + 1) * (1 << size))); |
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offs ^= 8;
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#else
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offs += element * (1 << size);
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#endif
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return offs;
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} |
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|
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/* Return the offset into CPUARMState of a slice (from
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* the least significant end) of FP register Qn (ie
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* Dn, Sn, Hn or Bn).
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* (Note that this is not the same mapping as for A32; see cpu.h)
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*/
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static inline int fp_reg_offset(int regno, TCGMemOp size) |
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{ |
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int offs = offsetof(CPUARMState, vfp.regs[regno * 2]); |
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#ifdef HOST_WORDS_BIGENDIAN
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offs += (8 - (1 << size)); |
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#endif
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return offs;
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} |
360 |
|
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/* Offset of the high half of the 128 bit vector Qn */
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static inline int fp_reg_hi_offset(int regno) |
363 |
{ |
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return offsetof(CPUARMState, vfp.regs[regno * 2 + 1]); |
365 |
} |
366 |
|
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/* Convenience accessors for reading and writing single and double
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* FP registers. Writing clears the upper parts of the associated
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* 128 bit vector register, as required by the architecture.
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* Note that unlike the GP register accessors, the values returned
|
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* by the read functions must be manually freed.
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*/
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static TCGv_i64 read_fp_dreg(DisasContext *s, int reg) |
374 |
{ |
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TCGv_i64 v = tcg_temp_new_i64(); |
376 |
|
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tcg_gen_ld_i64(v, cpu_env, fp_reg_offset(reg, MO_64)); |
378 |
return v;
|
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} |
380 |
|
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static TCGv_i32 read_fp_sreg(DisasContext *s, int reg) |
382 |
{ |
383 |
TCGv_i32 v = tcg_temp_new_i32(); |
384 |
|
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tcg_gen_ld_i32(v, cpu_env, fp_reg_offset(reg, MO_32)); |
386 |
return v;
|
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} |
388 |
|
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static void write_fp_dreg(DisasContext *s, int reg, TCGv_i64 v) |
390 |
{ |
391 |
TCGv_i64 tcg_zero = tcg_const_i64(0);
|
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|
393 |
tcg_gen_st_i64(v, cpu_env, fp_reg_offset(reg, MO_64)); |
394 |
tcg_gen_st_i64(tcg_zero, cpu_env, fp_reg_hi_offset(reg)); |
395 |
tcg_temp_free_i64(tcg_zero); |
396 |
} |
397 |
|
398 |
static void write_fp_sreg(DisasContext *s, int reg, TCGv_i32 v) |
399 |
{ |
400 |
TCGv_i64 tmp = tcg_temp_new_i64(); |
401 |
|
402 |
tcg_gen_extu_i32_i64(tmp, v); |
403 |
write_fp_dreg(s, reg, tmp); |
404 |
tcg_temp_free_i64(tmp); |
405 |
} |
406 |
|
407 |
static TCGv_ptr get_fpstatus_ptr(void) |
408 |
{ |
409 |
TCGv_ptr statusptr = tcg_temp_new_ptr(); |
410 |
int offset;
|
411 |
|
412 |
/* In A64 all instructions (both FP and Neon) use the FPCR;
|
413 |
* there is no equivalent of the A32 Neon "standard FPSCR value"
|
414 |
* and all operations use vfp.fp_status.
|
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*/
|
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offset = offsetof(CPUARMState, vfp.fp_status); |
417 |
tcg_gen_addi_ptr(statusptr, cpu_env, offset); |
418 |
return statusptr;
|
419 |
} |
420 |
|
421 |
/* Set ZF and NF based on a 64 bit result. This is alas fiddlier
|
422 |
* than the 32 bit equivalent.
|
423 |
*/
|
424 |
static inline void gen_set_NZ64(TCGv_i64 result) |
425 |
{ |
426 |
TCGv_i64 flag = tcg_temp_new_i64(); |
427 |
|
428 |
tcg_gen_setcondi_i64(TCG_COND_NE, flag, result, 0);
|
429 |
tcg_gen_trunc_i64_i32(cpu_ZF, flag); |
430 |
tcg_gen_shri_i64(flag, result, 32);
|
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tcg_gen_trunc_i64_i32(cpu_NF, flag); |
432 |
tcg_temp_free_i64(flag); |
433 |
} |
434 |
|
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/* Set NZCV as for a logical operation: NZ as per result, CV cleared. */
|
436 |
static inline void gen_logic_CC(int sf, TCGv_i64 result) |
437 |
{ |
438 |
if (sf) {
|
439 |
gen_set_NZ64(result); |
440 |
} else {
|
441 |
tcg_gen_trunc_i64_i32(cpu_ZF, result); |
442 |
tcg_gen_trunc_i64_i32(cpu_NF, result); |
443 |
} |
444 |
tcg_gen_movi_i32(cpu_CF, 0);
|
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tcg_gen_movi_i32(cpu_VF, 0);
|
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} |
447 |
|
448 |
/* dest = T0 + T1; compute C, N, V and Z flags */
|
449 |
static void gen_add_CC(int sf, TCGv_i64 dest, TCGv_i64 t0, TCGv_i64 t1) |
450 |
{ |
451 |
if (sf) {
|
452 |
TCGv_i64 result, flag, tmp; |
453 |
result = tcg_temp_new_i64(); |
454 |
flag = tcg_temp_new_i64(); |
455 |
tmp = tcg_temp_new_i64(); |
456 |
|
457 |
tcg_gen_movi_i64(tmp, 0);
|
458 |
tcg_gen_add2_i64(result, flag, t0, tmp, t1, tmp); |
459 |
|
460 |
tcg_gen_trunc_i64_i32(cpu_CF, flag); |
461 |
|
462 |
gen_set_NZ64(result); |
463 |
|
464 |
tcg_gen_xor_i64(flag, result, t0); |
465 |
tcg_gen_xor_i64(tmp, t0, t1); |
466 |
tcg_gen_andc_i64(flag, flag, tmp); |
467 |
tcg_temp_free_i64(tmp); |
468 |
tcg_gen_shri_i64(flag, flag, 32);
|
469 |
tcg_gen_trunc_i64_i32(cpu_VF, flag); |
470 |
|
471 |
tcg_gen_mov_i64(dest, result); |
472 |
tcg_temp_free_i64(result); |
473 |
tcg_temp_free_i64(flag); |
474 |
} else {
|
475 |
/* 32 bit arithmetic */
|
476 |
TCGv_i32 t0_32 = tcg_temp_new_i32(); |
477 |
TCGv_i32 t1_32 = tcg_temp_new_i32(); |
478 |
TCGv_i32 tmp = tcg_temp_new_i32(); |
479 |
|
480 |
tcg_gen_movi_i32(tmp, 0);
|
481 |
tcg_gen_trunc_i64_i32(t0_32, t0); |
482 |
tcg_gen_trunc_i64_i32(t1_32, t1); |
483 |
tcg_gen_add2_i32(cpu_NF, cpu_CF, t0_32, tmp, t1_32, tmp); |
484 |
tcg_gen_mov_i32(cpu_ZF, cpu_NF); |
485 |
tcg_gen_xor_i32(cpu_VF, cpu_NF, t0_32); |
486 |
tcg_gen_xor_i32(tmp, t0_32, t1_32); |
487 |
tcg_gen_andc_i32(cpu_VF, cpu_VF, tmp); |
488 |
tcg_gen_extu_i32_i64(dest, cpu_NF); |
489 |
|
490 |
tcg_temp_free_i32(tmp); |
491 |
tcg_temp_free_i32(t0_32); |
492 |
tcg_temp_free_i32(t1_32); |
493 |
} |
494 |
} |
495 |
|
496 |
/* dest = T0 - T1; compute C, N, V and Z flags */
|
497 |
static void gen_sub_CC(int sf, TCGv_i64 dest, TCGv_i64 t0, TCGv_i64 t1) |
498 |
{ |
499 |
if (sf) {
|
500 |
/* 64 bit arithmetic */
|
501 |
TCGv_i64 result, flag, tmp; |
502 |
|
503 |
result = tcg_temp_new_i64(); |
504 |
flag = tcg_temp_new_i64(); |
505 |
tcg_gen_sub_i64(result, t0, t1); |
506 |
|
507 |
gen_set_NZ64(result); |
508 |
|
509 |
tcg_gen_setcond_i64(TCG_COND_GEU, flag, t0, t1); |
510 |
tcg_gen_trunc_i64_i32(cpu_CF, flag); |
511 |
|
512 |
tcg_gen_xor_i64(flag, result, t0); |
513 |
tmp = tcg_temp_new_i64(); |
514 |
tcg_gen_xor_i64(tmp, t0, t1); |
515 |
tcg_gen_and_i64(flag, flag, tmp); |
516 |
tcg_temp_free_i64(tmp); |
517 |
tcg_gen_shri_i64(flag, flag, 32);
|
518 |
tcg_gen_trunc_i64_i32(cpu_VF, flag); |
519 |
tcg_gen_mov_i64(dest, result); |
520 |
tcg_temp_free_i64(flag); |
521 |
tcg_temp_free_i64(result); |
522 |
} else {
|
523 |
/* 32 bit arithmetic */
|
524 |
TCGv_i32 t0_32 = tcg_temp_new_i32(); |
525 |
TCGv_i32 t1_32 = tcg_temp_new_i32(); |
526 |
TCGv_i32 tmp; |
527 |
|
528 |
tcg_gen_trunc_i64_i32(t0_32, t0); |
529 |
tcg_gen_trunc_i64_i32(t1_32, t1); |
530 |
tcg_gen_sub_i32(cpu_NF, t0_32, t1_32); |
531 |
tcg_gen_mov_i32(cpu_ZF, cpu_NF); |
532 |
tcg_gen_setcond_i32(TCG_COND_GEU, cpu_CF, t0_32, t1_32); |
533 |
tcg_gen_xor_i32(cpu_VF, cpu_NF, t0_32); |
534 |
tmp = tcg_temp_new_i32(); |
535 |
tcg_gen_xor_i32(tmp, t0_32, t1_32); |
536 |
tcg_temp_free_i32(t0_32); |
537 |
tcg_temp_free_i32(t1_32); |
538 |
tcg_gen_and_i32(cpu_VF, cpu_VF, tmp); |
539 |
tcg_temp_free_i32(tmp); |
540 |
tcg_gen_extu_i32_i64(dest, cpu_NF); |
541 |
} |
542 |
} |
543 |
|
544 |
/* dest = T0 + T1 + CF; do not compute flags. */
|
545 |
static void gen_adc(int sf, TCGv_i64 dest, TCGv_i64 t0, TCGv_i64 t1) |
546 |
{ |
547 |
TCGv_i64 flag = tcg_temp_new_i64(); |
548 |
tcg_gen_extu_i32_i64(flag, cpu_CF); |
549 |
tcg_gen_add_i64(dest, t0, t1); |
550 |
tcg_gen_add_i64(dest, dest, flag); |
551 |
tcg_temp_free_i64(flag); |
552 |
|
553 |
if (!sf) {
|
554 |
tcg_gen_ext32u_i64(dest, dest); |
555 |
} |
556 |
} |
557 |
|
558 |
/* dest = T0 + T1 + CF; compute C, N, V and Z flags. */
|
559 |
static void gen_adc_CC(int sf, TCGv_i64 dest, TCGv_i64 t0, TCGv_i64 t1) |
560 |
{ |
561 |
if (sf) {
|
562 |
TCGv_i64 result, cf_64, vf_64, tmp; |
563 |
result = tcg_temp_new_i64(); |
564 |
cf_64 = tcg_temp_new_i64(); |
565 |
vf_64 = tcg_temp_new_i64(); |
566 |
tmp = tcg_const_i64(0);
|
567 |
|
568 |
tcg_gen_extu_i32_i64(cf_64, cpu_CF); |
569 |
tcg_gen_add2_i64(result, cf_64, t0, tmp, cf_64, tmp); |
570 |
tcg_gen_add2_i64(result, cf_64, result, cf_64, t1, tmp); |
571 |
tcg_gen_trunc_i64_i32(cpu_CF, cf_64); |
572 |
gen_set_NZ64(result); |
573 |
|
574 |
tcg_gen_xor_i64(vf_64, result, t0); |
575 |
tcg_gen_xor_i64(tmp, t0, t1); |
576 |
tcg_gen_andc_i64(vf_64, vf_64, tmp); |
577 |
tcg_gen_shri_i64(vf_64, vf_64, 32);
|
578 |
tcg_gen_trunc_i64_i32(cpu_VF, vf_64); |
579 |
|
580 |
tcg_gen_mov_i64(dest, result); |
581 |
|
582 |
tcg_temp_free_i64(tmp); |
583 |
tcg_temp_free_i64(vf_64); |
584 |
tcg_temp_free_i64(cf_64); |
585 |
tcg_temp_free_i64(result); |
586 |
} else {
|
587 |
TCGv_i32 t0_32, t1_32, tmp; |
588 |
t0_32 = tcg_temp_new_i32(); |
589 |
t1_32 = tcg_temp_new_i32(); |
590 |
tmp = tcg_const_i32(0);
|
591 |
|
592 |
tcg_gen_trunc_i64_i32(t0_32, t0); |
593 |
tcg_gen_trunc_i64_i32(t1_32, t1); |
594 |
tcg_gen_add2_i32(cpu_NF, cpu_CF, t0_32, tmp, cpu_CF, tmp); |
595 |
tcg_gen_add2_i32(cpu_NF, cpu_CF, cpu_NF, cpu_CF, t1_32, tmp); |
596 |
|
597 |
tcg_gen_mov_i32(cpu_ZF, cpu_NF); |
598 |
tcg_gen_xor_i32(cpu_VF, cpu_NF, t0_32); |
599 |
tcg_gen_xor_i32(tmp, t0_32, t1_32); |
600 |
tcg_gen_andc_i32(cpu_VF, cpu_VF, tmp); |
601 |
tcg_gen_extu_i32_i64(dest, cpu_NF); |
602 |
|
603 |
tcg_temp_free_i32(tmp); |
604 |
tcg_temp_free_i32(t1_32); |
605 |
tcg_temp_free_i32(t0_32); |
606 |
} |
607 |
} |
608 |
|
609 |
/*
|
610 |
* Load/Store generators
|
611 |
*/
|
612 |
|
613 |
/*
|
614 |
* Store from GPR register to memory
|
615 |
*/
|
616 |
static void do_gpr_st(DisasContext *s, TCGv_i64 source, |
617 |
TCGv_i64 tcg_addr, int size)
|
618 |
{ |
619 |
g_assert(size <= 3);
|
620 |
tcg_gen_qemu_st_i64(source, tcg_addr, get_mem_index(s), MO_TE + size); |
621 |
} |
622 |
|
623 |
/*
|
624 |
* Load from memory to GPR register
|
625 |
*/
|
626 |
static void do_gpr_ld(DisasContext *s, TCGv_i64 dest, TCGv_i64 tcg_addr, |
627 |
int size, bool is_signed, bool extend) |
628 |
{ |
629 |
TCGMemOp memop = MO_TE + size; |
630 |
|
631 |
g_assert(size <= 3);
|
632 |
|
633 |
if (is_signed) {
|
634 |
memop += MO_SIGN; |
635 |
} |
636 |
|
637 |
tcg_gen_qemu_ld_i64(dest, tcg_addr, get_mem_index(s), memop); |
638 |
|
639 |
if (extend && is_signed) {
|
640 |
g_assert(size < 3);
|
641 |
tcg_gen_ext32u_i64(dest, dest); |
642 |
} |
643 |
} |
644 |
|
645 |
/*
|
646 |
* Store from FP register to memory
|
647 |
*/
|
648 |
static void do_fp_st(DisasContext *s, int srcidx, TCGv_i64 tcg_addr, int size) |
649 |
{ |
650 |
/* This writes the bottom N bits of a 128 bit wide vector to memory */
|
651 |
TCGv_i64 tmp = tcg_temp_new_i64(); |
652 |
tcg_gen_ld_i64(tmp, cpu_env, fp_reg_offset(srcidx, MO_64)); |
653 |
if (size < 4) { |
654 |
tcg_gen_qemu_st_i64(tmp, tcg_addr, get_mem_index(s), MO_TE + size); |
655 |
} else {
|
656 |
TCGv_i64 tcg_hiaddr = tcg_temp_new_i64(); |
657 |
tcg_gen_qemu_st_i64(tmp, tcg_addr, get_mem_index(s), MO_TEQ); |
658 |
tcg_gen_qemu_st64(tmp, tcg_addr, get_mem_index(s)); |
659 |
tcg_gen_ld_i64(tmp, cpu_env, fp_reg_hi_offset(srcidx)); |
660 |
tcg_gen_addi_i64(tcg_hiaddr, tcg_addr, 8);
|
661 |
tcg_gen_qemu_st_i64(tmp, tcg_hiaddr, get_mem_index(s), MO_TEQ); |
662 |
tcg_temp_free_i64(tcg_hiaddr); |
663 |
} |
664 |
|
665 |
tcg_temp_free_i64(tmp); |
666 |
} |
667 |
|
668 |
/*
|
669 |
* Load from memory to FP register
|
670 |
*/
|
671 |
static void do_fp_ld(DisasContext *s, int destidx, TCGv_i64 tcg_addr, int size) |
672 |
{ |
673 |
/* This always zero-extends and writes to a full 128 bit wide vector */
|
674 |
TCGv_i64 tmplo = tcg_temp_new_i64(); |
675 |
TCGv_i64 tmphi; |
676 |
|
677 |
if (size < 4) { |
678 |
TCGMemOp memop = MO_TE + size; |
679 |
tmphi = tcg_const_i64(0);
|
680 |
tcg_gen_qemu_ld_i64(tmplo, tcg_addr, get_mem_index(s), memop); |
681 |
} else {
|
682 |
TCGv_i64 tcg_hiaddr; |
683 |
tmphi = tcg_temp_new_i64(); |
684 |
tcg_hiaddr = tcg_temp_new_i64(); |
685 |
|
686 |
tcg_gen_qemu_ld_i64(tmplo, tcg_addr, get_mem_index(s), MO_TEQ); |
687 |
tcg_gen_addi_i64(tcg_hiaddr, tcg_addr, 8);
|
688 |
tcg_gen_qemu_ld_i64(tmphi, tcg_hiaddr, get_mem_index(s), MO_TEQ); |
689 |
tcg_temp_free_i64(tcg_hiaddr); |
690 |
} |
691 |
|
692 |
tcg_gen_st_i64(tmplo, cpu_env, fp_reg_offset(destidx, MO_64)); |
693 |
tcg_gen_st_i64(tmphi, cpu_env, fp_reg_hi_offset(destidx)); |
694 |
|
695 |
tcg_temp_free_i64(tmplo); |
696 |
tcg_temp_free_i64(tmphi); |
697 |
} |
698 |
|
699 |
/*
|
700 |
* Vector load/store helpers.
|
701 |
*
|
702 |
* The principal difference between this and a FP load is that we don't
|
703 |
* zero extend as we are filling a partial chunk of the vector register.
|
704 |
* These functions don't support 128 bit loads/stores, which would be
|
705 |
* normal load/store operations.
|
706 |
*
|
707 |
* The _i32 versions are useful when operating on 32 bit quantities
|
708 |
* (eg for floating point single or using Neon helper functions).
|
709 |
*/
|
710 |
|
711 |
/* Get value of an element within a vector register */
|
712 |
static void read_vec_element(DisasContext *s, TCGv_i64 tcg_dest, int srcidx, |
713 |
int element, TCGMemOp memop)
|
714 |
{ |
715 |
int vect_off = vec_reg_offset(srcidx, element, memop & MO_SIZE);
|
716 |
switch (memop) {
|
717 |
case MO_8:
|
718 |
tcg_gen_ld8u_i64(tcg_dest, cpu_env, vect_off); |
719 |
break;
|
720 |
case MO_16:
|
721 |
tcg_gen_ld16u_i64(tcg_dest, cpu_env, vect_off); |
722 |
break;
|
723 |
case MO_32:
|
724 |
tcg_gen_ld32u_i64(tcg_dest, cpu_env, vect_off); |
725 |
break;
|
726 |
case MO_8|MO_SIGN:
|
727 |
tcg_gen_ld8s_i64(tcg_dest, cpu_env, vect_off); |
728 |
break;
|
729 |
case MO_16|MO_SIGN:
|
730 |
tcg_gen_ld16s_i64(tcg_dest, cpu_env, vect_off); |
731 |
break;
|
732 |
case MO_32|MO_SIGN:
|
733 |
tcg_gen_ld32s_i64(tcg_dest, cpu_env, vect_off); |
734 |
break;
|
735 |
case MO_64:
|
736 |
case MO_64|MO_SIGN:
|
737 |
tcg_gen_ld_i64(tcg_dest, cpu_env, vect_off); |
738 |
break;
|
739 |
default:
|
740 |
g_assert_not_reached(); |
741 |
} |
742 |
} |
743 |
|
744 |
static void read_vec_element_i32(DisasContext *s, TCGv_i32 tcg_dest, int srcidx, |
745 |
int element, TCGMemOp memop)
|
746 |
{ |
747 |
int vect_off = vec_reg_offset(srcidx, element, memop & MO_SIZE);
|
748 |
switch (memop) {
|
749 |
case MO_8:
|
750 |
tcg_gen_ld8u_i32(tcg_dest, cpu_env, vect_off); |
751 |
break;
|
752 |
case MO_16:
|
753 |
tcg_gen_ld16u_i32(tcg_dest, cpu_env, vect_off); |
754 |
break;
|
755 |
case MO_8|MO_SIGN:
|
756 |
tcg_gen_ld8s_i32(tcg_dest, cpu_env, vect_off); |
757 |
break;
|
758 |
case MO_16|MO_SIGN:
|
759 |
tcg_gen_ld16s_i32(tcg_dest, cpu_env, vect_off); |
760 |
break;
|
761 |
case MO_32:
|
762 |
case MO_32|MO_SIGN:
|
763 |
tcg_gen_ld_i32(tcg_dest, cpu_env, vect_off); |
764 |
break;
|
765 |
default:
|
766 |
g_assert_not_reached(); |
767 |
} |
768 |
} |
769 |
|
770 |
/* Set value of an element within a vector register */
|
771 |
static void write_vec_element(DisasContext *s, TCGv_i64 tcg_src, int destidx, |
772 |
int element, TCGMemOp memop)
|
773 |
{ |
774 |
int vect_off = vec_reg_offset(destidx, element, memop & MO_SIZE);
|
775 |
switch (memop) {
|
776 |
case MO_8:
|
777 |
tcg_gen_st8_i64(tcg_src, cpu_env, vect_off); |
778 |
break;
|
779 |
case MO_16:
|
780 |
tcg_gen_st16_i64(tcg_src, cpu_env, vect_off); |
781 |
break;
|
782 |
case MO_32:
|
783 |
tcg_gen_st32_i64(tcg_src, cpu_env, vect_off); |
784 |
break;
|
785 |
case MO_64:
|
786 |
tcg_gen_st_i64(tcg_src, cpu_env, vect_off); |
787 |
break;
|
788 |
default:
|
789 |
g_assert_not_reached(); |
790 |
} |
791 |
} |
792 |
|
793 |
static void write_vec_element_i32(DisasContext *s, TCGv_i32 tcg_src, |
794 |
int destidx, int element, TCGMemOp memop) |
795 |
{ |
796 |
int vect_off = vec_reg_offset(destidx, element, memop & MO_SIZE);
|
797 |
switch (memop) {
|
798 |
case MO_8:
|
799 |
tcg_gen_st8_i32(tcg_src, cpu_env, vect_off); |
800 |
break;
|
801 |
case MO_16:
|
802 |
tcg_gen_st16_i32(tcg_src, cpu_env, vect_off); |
803 |
break;
|
804 |
case MO_32:
|
805 |
tcg_gen_st_i32(tcg_src, cpu_env, vect_off); |
806 |
break;
|
807 |
default:
|
808 |
g_assert_not_reached(); |
809 |
} |
810 |
} |
811 |
|
812 |
/* Clear the high 64 bits of a 128 bit vector (in general non-quad
|
813 |
* vector ops all need to do this).
|
814 |
*/
|
815 |
static void clear_vec_high(DisasContext *s, int rd) |
816 |
{ |
817 |
TCGv_i64 tcg_zero = tcg_const_i64(0);
|
818 |
|
819 |
write_vec_element(s, tcg_zero, rd, 1, MO_64);
|
820 |
tcg_temp_free_i64(tcg_zero); |
821 |
} |
822 |
|
823 |
/* Store from vector register to memory */
|
824 |
static void do_vec_st(DisasContext *s, int srcidx, int element, |
825 |
TCGv_i64 tcg_addr, int size)
|
826 |
{ |
827 |
TCGMemOp memop = MO_TE + size; |
828 |
TCGv_i64 tcg_tmp = tcg_temp_new_i64(); |
829 |
|
830 |
read_vec_element(s, tcg_tmp, srcidx, element, size); |
831 |
tcg_gen_qemu_st_i64(tcg_tmp, tcg_addr, get_mem_index(s), memop); |
832 |
|
833 |
tcg_temp_free_i64(tcg_tmp); |
834 |
} |
835 |
|
836 |
/* Load from memory to vector register */
|
837 |
static void do_vec_ld(DisasContext *s, int destidx, int element, |
838 |
TCGv_i64 tcg_addr, int size)
|
839 |
{ |
840 |
TCGMemOp memop = MO_TE + size; |
841 |
TCGv_i64 tcg_tmp = tcg_temp_new_i64(); |
842 |
|
843 |
tcg_gen_qemu_ld_i64(tcg_tmp, tcg_addr, get_mem_index(s), memop); |
844 |
write_vec_element(s, tcg_tmp, destidx, element, size); |
845 |
|
846 |
tcg_temp_free_i64(tcg_tmp); |
847 |
} |
848 |
|
849 |
/*
|
850 |
* This utility function is for doing register extension with an
|
851 |
* optional shift. You will likely want to pass a temporary for the
|
852 |
* destination register. See DecodeRegExtend() in the ARM ARM.
|
853 |
*/
|
854 |
static void ext_and_shift_reg(TCGv_i64 tcg_out, TCGv_i64 tcg_in, |
855 |
int option, unsigned int shift) |
856 |
{ |
857 |
int extsize = extract32(option, 0, 2); |
858 |
bool is_signed = extract32(option, 2, 1); |
859 |
|
860 |
if (is_signed) {
|
861 |
switch (extsize) {
|
862 |
case 0: |
863 |
tcg_gen_ext8s_i64(tcg_out, tcg_in); |
864 |
break;
|
865 |
case 1: |
866 |
tcg_gen_ext16s_i64(tcg_out, tcg_in); |
867 |
break;
|
868 |
case 2: |
869 |
tcg_gen_ext32s_i64(tcg_out, tcg_in); |
870 |
break;
|
871 |
case 3: |
872 |
tcg_gen_mov_i64(tcg_out, tcg_in); |
873 |
break;
|
874 |
} |
875 |
} else {
|
876 |
switch (extsize) {
|
877 |
case 0: |
878 |
tcg_gen_ext8u_i64(tcg_out, tcg_in); |
879 |
break;
|
880 |
case 1: |
881 |
tcg_gen_ext16u_i64(tcg_out, tcg_in); |
882 |
break;
|
883 |
case 2: |
884 |
tcg_gen_ext32u_i64(tcg_out, tcg_in); |
885 |
break;
|
886 |
case 3: |
887 |
tcg_gen_mov_i64(tcg_out, tcg_in); |
888 |
break;
|
889 |
} |
890 |
} |
891 |
|
892 |
if (shift) {
|
893 |
tcg_gen_shli_i64(tcg_out, tcg_out, shift); |
894 |
} |
895 |
} |
896 |
|
897 |
static inline void gen_check_sp_alignment(DisasContext *s) |
898 |
{ |
899 |
/* The AArch64 architecture mandates that (if enabled via PSTATE
|
900 |
* or SCTLR bits) there is a check that SP is 16-aligned on every
|
901 |
* SP-relative load or store (with an exception generated if it is not).
|
902 |
* In line with general QEMU practice regarding misaligned accesses,
|
903 |
* we omit these checks for the sake of guest program performance.
|
904 |
* This function is provided as a hook so we can more easily add these
|
905 |
* checks in future (possibly as a "favour catching guest program bugs
|
906 |
* over speed" user selectable option).
|
907 |
*/
|
908 |
} |
909 |
|
910 |
/*
|
911 |
* This provides a simple table based table lookup decoder. It is
|
912 |
* intended to be used when the relevant bits for decode are too
|
913 |
* awkwardly placed and switch/if based logic would be confusing and
|
914 |
* deeply nested. Since it's a linear search through the table, tables
|
915 |
* should be kept small.
|
916 |
*
|
917 |
* It returns the first handler where insn & mask == pattern, or
|
918 |
* NULL if there is no match.
|
919 |
* The table is terminated by an empty mask (i.e. 0)
|
920 |
*/
|
921 |
static inline AArch64DecodeFn *lookup_disas_fn(const AArch64DecodeTable *table, |
922 |
uint32_t insn) |
923 |
{ |
924 |
const AArch64DecodeTable *tptr = table;
|
925 |
|
926 |
while (tptr->mask) {
|
927 |
if ((insn & tptr->mask) == tptr->pattern) {
|
928 |
return tptr->disas_fn;
|
929 |
} |
930 |
tptr++; |
931 |
} |
932 |
return NULL; |
933 |
} |
934 |
|
935 |
/*
|
936 |
* the instruction disassembly implemented here matches
|
937 |
* the instruction encoding classifications in chapter 3 (C3)
|
938 |
* of the ARM Architecture Reference Manual (DDI0487A_a)
|
939 |
*/
|
940 |
|
941 |
/* C3.2.7 Unconditional branch (immediate)
|
942 |
* 31 30 26 25 0
|
943 |
* +----+-----------+-------------------------------------+
|
944 |
* | op | 0 0 1 0 1 | imm26 |
|
945 |
* +----+-----------+-------------------------------------+
|
946 |
*/
|
947 |
static void disas_uncond_b_imm(DisasContext *s, uint32_t insn) |
948 |
{ |
949 |
uint64_t addr = s->pc + sextract32(insn, 0, 26) * 4 - 4; |
950 |
|
951 |
if (insn & (1 << 31)) { |
952 |
/* C5.6.26 BL Branch with link */
|
953 |
tcg_gen_movi_i64(cpu_reg(s, 30), s->pc);
|
954 |
} |
955 |
|
956 |
/* C5.6.20 B Branch / C5.6.26 BL Branch with link */
|
957 |
gen_goto_tb(s, 0, addr);
|
958 |
} |
959 |
|
960 |
/* C3.2.1 Compare & branch (immediate)
|
961 |
* 31 30 25 24 23 5 4 0
|
962 |
* +----+-------------+----+---------------------+--------+
|
963 |
* | sf | 0 1 1 0 1 0 | op | imm19 | Rt |
|
964 |
* +----+-------------+----+---------------------+--------+
|
965 |
*/
|
966 |
static void disas_comp_b_imm(DisasContext *s, uint32_t insn) |
967 |
{ |
968 |
unsigned int sf, op, rt; |
969 |
uint64_t addr; |
970 |
int label_match;
|
971 |
TCGv_i64 tcg_cmp; |
972 |
|
973 |
sf = extract32(insn, 31, 1); |
974 |
op = extract32(insn, 24, 1); /* 0: CBZ; 1: CBNZ */ |
975 |
rt = extract32(insn, 0, 5); |
976 |
addr = s->pc + sextract32(insn, 5, 19) * 4 - 4; |
977 |
|
978 |
tcg_cmp = read_cpu_reg(s, rt, sf); |
979 |
label_match = gen_new_label(); |
980 |
|
981 |
tcg_gen_brcondi_i64(op ? TCG_COND_NE : TCG_COND_EQ, |
982 |
tcg_cmp, 0, label_match);
|
983 |
|
984 |
gen_goto_tb(s, 0, s->pc);
|
985 |
gen_set_label(label_match); |
986 |
gen_goto_tb(s, 1, addr);
|
987 |
} |
988 |
|
989 |
/* C3.2.5 Test & branch (immediate)
|
990 |
* 31 30 25 24 23 19 18 5 4 0
|
991 |
* +----+-------------+----+-------+-------------+------+
|
992 |
* | b5 | 0 1 1 0 1 1 | op | b40 | imm14 | Rt |
|
993 |
* +----+-------------+----+-------+-------------+------+
|
994 |
*/
|
995 |
static void disas_test_b_imm(DisasContext *s, uint32_t insn) |
996 |
{ |
997 |
unsigned int bit_pos, op, rt; |
998 |
uint64_t addr; |
999 |
int label_match;
|
1000 |
TCGv_i64 tcg_cmp; |
1001 |
|
1002 |
bit_pos = (extract32(insn, 31, 1) << 5) | extract32(insn, 19, 5); |
1003 |
op = extract32(insn, 24, 1); /* 0: TBZ; 1: TBNZ */ |
1004 |
addr = s->pc + sextract32(insn, 5, 14) * 4 - 4; |
1005 |
rt = extract32(insn, 0, 5); |
1006 |
|
1007 |
tcg_cmp = tcg_temp_new_i64(); |
1008 |
tcg_gen_andi_i64(tcg_cmp, cpu_reg(s, rt), (1ULL << bit_pos));
|
1009 |
label_match = gen_new_label(); |
1010 |
tcg_gen_brcondi_i64(op ? TCG_COND_NE : TCG_COND_EQ, |
1011 |
tcg_cmp, 0, label_match);
|
1012 |
tcg_temp_free_i64(tcg_cmp); |
1013 |
gen_goto_tb(s, 0, s->pc);
|
1014 |
gen_set_label(label_match); |
1015 |
gen_goto_tb(s, 1, addr);
|
1016 |
} |
1017 |
|
1018 |
/* C3.2.2 / C5.6.19 Conditional branch (immediate)
|
1019 |
* 31 25 24 23 5 4 3 0
|
1020 |
* +---------------+----+---------------------+----+------+
|
1021 |
* | 0 1 0 1 0 1 0 | o1 | imm19 | o0 | cond |
|
1022 |
* +---------------+----+---------------------+----+------+
|
1023 |
*/
|
1024 |
static void disas_cond_b_imm(DisasContext *s, uint32_t insn) |
1025 |
{ |
1026 |
unsigned int cond; |
1027 |
uint64_t addr; |
1028 |
|
1029 |
if ((insn & (1 << 4)) || (insn & (1 << 24))) { |
1030 |
unallocated_encoding(s); |
1031 |
return;
|
1032 |
} |
1033 |
addr = s->pc + sextract32(insn, 5, 19) * 4 - 4; |
1034 |
cond = extract32(insn, 0, 4); |
1035 |
|
1036 |
if (cond < 0x0e) { |
1037 |
/* genuinely conditional branches */
|
1038 |
int label_match = gen_new_label();
|
1039 |
arm_gen_test_cc(cond, label_match); |
1040 |
gen_goto_tb(s, 0, s->pc);
|
1041 |
gen_set_label(label_match); |
1042 |
gen_goto_tb(s, 1, addr);
|
1043 |
} else {
|
1044 |
/* 0xe and 0xf are both "always" conditions */
|
1045 |
gen_goto_tb(s, 0, addr);
|
1046 |
} |
1047 |
} |
1048 |
|
1049 |
/* C5.6.68 HINT */
|
1050 |
static void handle_hint(DisasContext *s, uint32_t insn, |
1051 |
unsigned int op1, unsigned int op2, unsigned int crm) |
1052 |
{ |
1053 |
unsigned int selector = crm << 3 | op2; |
1054 |
|
1055 |
if (op1 != 3) { |
1056 |
unallocated_encoding(s); |
1057 |
return;
|
1058 |
} |
1059 |
|
1060 |
switch (selector) {
|
1061 |
case 0: /* NOP */ |
1062 |
return;
|
1063 |
case 1: /* YIELD */ |
1064 |
case 2: /* WFE */ |
1065 |
case 3: /* WFI */ |
1066 |
case 4: /* SEV */ |
1067 |
case 5: /* SEVL */ |
1068 |
/* we treat all as NOP at least for now */
|
1069 |
return;
|
1070 |
default:
|
1071 |
/* default specified as NOP equivalent */
|
1072 |
return;
|
1073 |
} |
1074 |
} |
1075 |
|
1076 |
static void gen_clrex(DisasContext *s, uint32_t insn) |
1077 |
{ |
1078 |
tcg_gen_movi_i64(cpu_exclusive_addr, -1);
|
1079 |
} |
1080 |
|
1081 |
/* CLREX, DSB, DMB, ISB */
|
1082 |
static void handle_sync(DisasContext *s, uint32_t insn, |
1083 |
unsigned int op1, unsigned int op2, unsigned int crm) |
1084 |
{ |
1085 |
if (op1 != 3) { |
1086 |
unallocated_encoding(s); |
1087 |
return;
|
1088 |
} |
1089 |
|
1090 |
switch (op2) {
|
1091 |
case 2: /* CLREX */ |
1092 |
gen_clrex(s, insn); |
1093 |
return;
|
1094 |
case 4: /* DSB */ |
1095 |
case 5: /* DMB */ |
1096 |
case 6: /* ISB */ |
1097 |
/* We don't emulate caches so barriers are no-ops */
|
1098 |
return;
|
1099 |
default:
|
1100 |
unallocated_encoding(s); |
1101 |
return;
|
1102 |
} |
1103 |
} |
1104 |
|
1105 |
/* C5.6.130 MSR (immediate) - move immediate to processor state field */
|
1106 |
static void handle_msr_i(DisasContext *s, uint32_t insn, |
1107 |
unsigned int op1, unsigned int op2, unsigned int crm) |
1108 |
{ |
1109 |
unsupported_encoding(s, insn); |
1110 |
} |
1111 |
|
1112 |
static void gen_get_nzcv(TCGv_i64 tcg_rt) |
1113 |
{ |
1114 |
TCGv_i32 tmp = tcg_temp_new_i32(); |
1115 |
TCGv_i32 nzcv = tcg_temp_new_i32(); |
1116 |
|
1117 |
/* build bit 31, N */
|
1118 |
tcg_gen_andi_i32(nzcv, cpu_NF, (1 << 31)); |
1119 |
/* build bit 30, Z */
|
1120 |
tcg_gen_setcondi_i32(TCG_COND_EQ, tmp, cpu_ZF, 0);
|
1121 |
tcg_gen_deposit_i32(nzcv, nzcv, tmp, 30, 1); |
1122 |
/* build bit 29, C */
|
1123 |
tcg_gen_deposit_i32(nzcv, nzcv, cpu_CF, 29, 1); |
1124 |
/* build bit 28, V */
|
1125 |
tcg_gen_shri_i32(tmp, cpu_VF, 31);
|
1126 |
tcg_gen_deposit_i32(nzcv, nzcv, tmp, 28, 1); |
1127 |
/* generate result */
|
1128 |
tcg_gen_extu_i32_i64(tcg_rt, nzcv); |
1129 |
|
1130 |
tcg_temp_free_i32(nzcv); |
1131 |
tcg_temp_free_i32(tmp); |
1132 |
} |
1133 |
|
1134 |
static void gen_set_nzcv(TCGv_i64 tcg_rt) |
1135 |
|
1136 |
{ |
1137 |
TCGv_i32 nzcv = tcg_temp_new_i32(); |
1138 |
|
1139 |
/* take NZCV from R[t] */
|
1140 |
tcg_gen_trunc_i64_i32(nzcv, tcg_rt); |
1141 |
|
1142 |
/* bit 31, N */
|
1143 |
tcg_gen_andi_i32(cpu_NF, nzcv, (1 << 31)); |
1144 |
/* bit 30, Z */
|
1145 |
tcg_gen_andi_i32(cpu_ZF, nzcv, (1 << 30)); |
1146 |
tcg_gen_setcondi_i32(TCG_COND_EQ, cpu_ZF, cpu_ZF, 0);
|
1147 |
/* bit 29, C */
|
1148 |
tcg_gen_andi_i32(cpu_CF, nzcv, (1 << 29)); |
1149 |
tcg_gen_shri_i32(cpu_CF, cpu_CF, 29);
|
1150 |
/* bit 28, V */
|
1151 |
tcg_gen_andi_i32(cpu_VF, nzcv, (1 << 28)); |
1152 |
tcg_gen_shli_i32(cpu_VF, cpu_VF, 3);
|
1153 |
tcg_temp_free_i32(nzcv); |
1154 |
} |
1155 |
|
1156 |
/* C5.6.129 MRS - move from system register
|
1157 |
* C5.6.131 MSR (register) - move to system register
|
1158 |
* C5.6.204 SYS
|
1159 |
* C5.6.205 SYSL
|
1160 |
* These are all essentially the same insn in 'read' and 'write'
|
1161 |
* versions, with varying op0 fields.
|
1162 |
*/
|
1163 |
static void handle_sys(DisasContext *s, uint32_t insn, bool isread, |
1164 |
unsigned int op0, unsigned int op1, unsigned int op2, |
1165 |
unsigned int crn, unsigned int crm, unsigned int rt) |
1166 |
{ |
1167 |
const ARMCPRegInfo *ri;
|
1168 |
TCGv_i64 tcg_rt; |
1169 |
|
1170 |
ri = get_arm_cp_reginfo(s->cp_regs, |
1171 |
ENCODE_AA64_CP_REG(CP_REG_ARM64_SYSREG_CP, |
1172 |
crn, crm, op0, op1, op2)); |
1173 |
|
1174 |
if (!ri) {
|
1175 |
/* Unknown register */
|
1176 |
unallocated_encoding(s); |
1177 |
return;
|
1178 |
} |
1179 |
|
1180 |
/* Check access permissions */
|
1181 |
if (!cp_access_ok(s->current_pl, ri, isread)) {
|
1182 |
unallocated_encoding(s); |
1183 |
return;
|
1184 |
} |
1185 |
|
1186 |
/* Handle special cases first */
|
1187 |
switch (ri->type & ~(ARM_CP_FLAG_MASK & ~ARM_CP_SPECIAL)) {
|
1188 |
case ARM_CP_NOP:
|
1189 |
return;
|
1190 |
case ARM_CP_NZCV:
|
1191 |
tcg_rt = cpu_reg(s, rt); |
1192 |
if (isread) {
|
1193 |
gen_get_nzcv(tcg_rt); |
1194 |
} else {
|
1195 |
gen_set_nzcv(tcg_rt); |
1196 |
} |
1197 |
return;
|
1198 |
default:
|
1199 |
break;
|
1200 |
} |
1201 |
|
1202 |
if (use_icount && (ri->type & ARM_CP_IO)) {
|
1203 |
gen_io_start(); |
1204 |
} |
1205 |
|
1206 |
tcg_rt = cpu_reg(s, rt); |
1207 |
|
1208 |
if (isread) {
|
1209 |
if (ri->type & ARM_CP_CONST) {
|
1210 |
tcg_gen_movi_i64(tcg_rt, ri->resetvalue); |
1211 |
} else if (ri->readfn) { |
1212 |
TCGv_ptr tmpptr; |
1213 |
gen_a64_set_pc_im(s->pc - 4);
|
1214 |
tmpptr = tcg_const_ptr(ri); |
1215 |
gen_helper_get_cp_reg64(tcg_rt, cpu_env, tmpptr); |
1216 |
tcg_temp_free_ptr(tmpptr); |
1217 |
} else {
|
1218 |
tcg_gen_ld_i64(tcg_rt, cpu_env, ri->fieldoffset); |
1219 |
} |
1220 |
} else {
|
1221 |
if (ri->type & ARM_CP_CONST) {
|
1222 |
/* If not forbidden by access permissions, treat as WI */
|
1223 |
return;
|
1224 |
} else if (ri->writefn) { |
1225 |
TCGv_ptr tmpptr; |
1226 |
gen_a64_set_pc_im(s->pc - 4);
|
1227 |
tmpptr = tcg_const_ptr(ri); |
1228 |
gen_helper_set_cp_reg64(cpu_env, tmpptr, tcg_rt); |
1229 |
tcg_temp_free_ptr(tmpptr); |
1230 |
} else {
|
1231 |
tcg_gen_st_i64(tcg_rt, cpu_env, ri->fieldoffset); |
1232 |
} |
1233 |
} |
1234 |
|
1235 |
if (use_icount && (ri->type & ARM_CP_IO)) {
|
1236 |
/* I/O operations must end the TB here (whether read or write) */
|
1237 |
gen_io_end(); |
1238 |
s->is_jmp = DISAS_UPDATE; |
1239 |
} else if (!isread && !(ri->type & ARM_CP_SUPPRESS_TB_END)) { |
1240 |
/* We default to ending the TB on a coprocessor register write,
|
1241 |
* but allow this to be suppressed by the register definition
|
1242 |
* (usually only necessary to work around guest bugs).
|
1243 |
*/
|
1244 |
s->is_jmp = DISAS_UPDATE; |
1245 |
} |
1246 |
} |
1247 |
|
1248 |
/* C3.2.4 System
|
1249 |
* 31 22 21 20 19 18 16 15 12 11 8 7 5 4 0
|
1250 |
* +---------------------+---+-----+-----+-------+-------+-----+------+
|
1251 |
* | 1 1 0 1 0 1 0 1 0 0 | L | op0 | op1 | CRn | CRm | op2 | Rt |
|
1252 |
* +---------------------+---+-----+-----+-------+-------+-----+------+
|
1253 |
*/
|
1254 |
static void disas_system(DisasContext *s, uint32_t insn) |
1255 |
{ |
1256 |
unsigned int l, op0, op1, crn, crm, op2, rt; |
1257 |
l = extract32(insn, 21, 1); |
1258 |
op0 = extract32(insn, 19, 2); |
1259 |
op1 = extract32(insn, 16, 3); |
1260 |
crn = extract32(insn, 12, 4); |
1261 |
crm = extract32(insn, 8, 4); |
1262 |
op2 = extract32(insn, 5, 3); |
1263 |
rt = extract32(insn, 0, 5); |
1264 |
|
1265 |
if (op0 == 0) { |
1266 |
if (l || rt != 31) { |
1267 |
unallocated_encoding(s); |
1268 |
return;
|
1269 |
} |
1270 |
switch (crn) {
|
1271 |
case 2: /* C5.6.68 HINT */ |
1272 |
handle_hint(s, insn, op1, op2, crm); |
1273 |
break;
|
1274 |
case 3: /* CLREX, DSB, DMB, ISB */ |
1275 |
handle_sync(s, insn, op1, op2, crm); |
1276 |
break;
|
1277 |
case 4: /* C5.6.130 MSR (immediate) */ |
1278 |
handle_msr_i(s, insn, op1, op2, crm); |
1279 |
break;
|
1280 |
default:
|
1281 |
unallocated_encoding(s); |
1282 |
break;
|
1283 |
} |
1284 |
return;
|
1285 |
} |
1286 |
handle_sys(s, insn, l, op0, op1, op2, crn, crm, rt); |
1287 |
} |
1288 |
|
1289 |
/* C3.2.3 Exception generation
|
1290 |
*
|
1291 |
* 31 24 23 21 20 5 4 2 1 0
|
1292 |
* +-----------------+-----+------------------------+-----+----+
|
1293 |
* | 1 1 0 1 0 1 0 0 | opc | imm16 | op2 | LL |
|
1294 |
* +-----------------------+------------------------+----------+
|
1295 |
*/
|
1296 |
static void disas_exc(DisasContext *s, uint32_t insn) |
1297 |
{ |
1298 |
int opc = extract32(insn, 21, 3); |
1299 |
int op2_ll = extract32(insn, 0, 5); |
1300 |
|
1301 |
switch (opc) {
|
1302 |
case 0: |
1303 |
/* SVC, HVC, SMC; since we don't support the Virtualization
|
1304 |
* or TrustZone extensions these all UNDEF except SVC.
|
1305 |
*/
|
1306 |
if (op2_ll != 1) { |
1307 |
unallocated_encoding(s); |
1308 |
break;
|
1309 |
} |
1310 |
gen_exception_insn(s, 0, EXCP_SWI);
|
1311 |
break;
|
1312 |
case 1: |
1313 |
if (op2_ll != 0) { |
1314 |
unallocated_encoding(s); |
1315 |
break;
|
1316 |
} |
1317 |
/* BRK */
|
1318 |
gen_exception_insn(s, 0, EXCP_BKPT);
|
1319 |
break;
|
1320 |
case 2: |
1321 |
if (op2_ll != 0) { |
1322 |
unallocated_encoding(s); |
1323 |
break;
|
1324 |
} |
1325 |
/* HLT */
|
1326 |
unsupported_encoding(s, insn); |
1327 |
break;
|
1328 |
case 5: |
1329 |
if (op2_ll < 1 || op2_ll > 3) { |
1330 |
unallocated_encoding(s); |
1331 |
break;
|
1332 |
} |
1333 |
/* DCPS1, DCPS2, DCPS3 */
|
1334 |
unsupported_encoding(s, insn); |
1335 |
break;
|
1336 |
default:
|
1337 |
unallocated_encoding(s); |
1338 |
break;
|
1339 |
} |
1340 |
} |
1341 |
|
1342 |
/* C3.2.7 Unconditional branch (register)
|
1343 |
* 31 25 24 21 20 16 15 10 9 5 4 0
|
1344 |
* +---------------+-------+-------+-------+------+-------+
|
1345 |
* | 1 1 0 1 0 1 1 | opc | op2 | op3 | Rn | op4 |
|
1346 |
* +---------------+-------+-------+-------+------+-------+
|
1347 |
*/
|
1348 |
static void disas_uncond_b_reg(DisasContext *s, uint32_t insn) |
1349 |
{ |
1350 |
unsigned int opc, op2, op3, rn, op4; |
1351 |
|
1352 |
opc = extract32(insn, 21, 4); |
1353 |
op2 = extract32(insn, 16, 5); |
1354 |
op3 = extract32(insn, 10, 6); |
1355 |
rn = extract32(insn, 5, 5); |
1356 |
op4 = extract32(insn, 0, 5); |
1357 |
|
1358 |
if (op4 != 0x0 || op3 != 0x0 || op2 != 0x1f) { |
1359 |
unallocated_encoding(s); |
1360 |
return;
|
1361 |
} |
1362 |
|
1363 |
switch (opc) {
|
1364 |
case 0: /* BR */ |
1365 |
case 2: /* RET */ |
1366 |
break;
|
1367 |
case 1: /* BLR */ |
1368 |
tcg_gen_movi_i64(cpu_reg(s, 30), s->pc);
|
1369 |
break;
|
1370 |
case 4: /* ERET */ |
1371 |
case 5: /* DRPS */ |
1372 |
if (rn != 0x1f) { |
1373 |
unallocated_encoding(s); |
1374 |
} else {
|
1375 |
unsupported_encoding(s, insn); |
1376 |
} |
1377 |
return;
|
1378 |
default:
|
1379 |
unallocated_encoding(s); |
1380 |
return;
|
1381 |
} |
1382 |
|
1383 |
tcg_gen_mov_i64(cpu_pc, cpu_reg(s, rn)); |
1384 |
s->is_jmp = DISAS_JUMP; |
1385 |
} |
1386 |
|
1387 |
/* C3.2 Branches, exception generating and system instructions */
|
1388 |
static void disas_b_exc_sys(DisasContext *s, uint32_t insn) |
1389 |
{ |
1390 |
switch (extract32(insn, 25, 7)) { |
1391 |
case 0x0a: case 0x0b: |
1392 |
case 0x4a: case 0x4b: /* Unconditional branch (immediate) */ |
1393 |
disas_uncond_b_imm(s, insn); |
1394 |
break;
|
1395 |
case 0x1a: case 0x5a: /* Compare & branch (immediate) */ |
1396 |
disas_comp_b_imm(s, insn); |
1397 |
break;
|
1398 |
case 0x1b: case 0x5b: /* Test & branch (immediate) */ |
1399 |
disas_test_b_imm(s, insn); |
1400 |
break;
|
1401 |
case 0x2a: /* Conditional branch (immediate) */ |
1402 |
disas_cond_b_imm(s, insn); |
1403 |
break;
|
1404 |
case 0x6a: /* Exception generation / System */ |
1405 |
if (insn & (1 << 24)) { |
1406 |
disas_system(s, insn); |
1407 |
} else {
|
1408 |
disas_exc(s, insn); |
1409 |
} |
1410 |
break;
|
1411 |
case 0x6b: /* Unconditional branch (register) */ |
1412 |
disas_uncond_b_reg(s, insn); |
1413 |
break;
|
1414 |
default:
|
1415 |
unallocated_encoding(s); |
1416 |
break;
|
1417 |
} |
1418 |
} |
1419 |
|
1420 |
/*
|
1421 |
* Load/Store exclusive instructions are implemented by remembering
|
1422 |
* the value/address loaded, and seeing if these are the same
|
1423 |
* when the store is performed. This is not actually the architecturally
|
1424 |
* mandated semantics, but it works for typical guest code sequences
|
1425 |
* and avoids having to monitor regular stores.
|
1426 |
*
|
1427 |
* In system emulation mode only one CPU will be running at once, so
|
1428 |
* this sequence is effectively atomic. In user emulation mode we
|
1429 |
* throw an exception and handle the atomic operation elsewhere.
|
1430 |
*/
|
1431 |
static void gen_load_exclusive(DisasContext *s, int rt, int rt2, |
1432 |
TCGv_i64 addr, int size, bool is_pair) |
1433 |
{ |
1434 |
TCGv_i64 tmp = tcg_temp_new_i64(); |
1435 |
TCGMemOp memop = MO_TE + size; |
1436 |
|
1437 |
g_assert(size <= 3);
|
1438 |
tcg_gen_qemu_ld_i64(tmp, addr, get_mem_index(s), memop); |
1439 |
|
1440 |
if (is_pair) {
|
1441 |
TCGv_i64 addr2 = tcg_temp_new_i64(); |
1442 |
TCGv_i64 hitmp = tcg_temp_new_i64(); |
1443 |
|
1444 |
g_assert(size >= 2);
|
1445 |
tcg_gen_addi_i64(addr2, addr, 1 << size);
|
1446 |
tcg_gen_qemu_ld_i64(hitmp, addr2, get_mem_index(s), memop); |
1447 |
tcg_temp_free_i64(addr2); |
1448 |
tcg_gen_mov_i64(cpu_exclusive_high, hitmp); |
1449 |
tcg_gen_mov_i64(cpu_reg(s, rt2), hitmp); |
1450 |
tcg_temp_free_i64(hitmp); |
1451 |
} |
1452 |
|
1453 |
tcg_gen_mov_i64(cpu_exclusive_val, tmp); |
1454 |
tcg_gen_mov_i64(cpu_reg(s, rt), tmp); |
1455 |
|
1456 |
tcg_temp_free_i64(tmp); |
1457 |
tcg_gen_mov_i64(cpu_exclusive_addr, addr); |
1458 |
} |
1459 |
|
1460 |
#ifdef CONFIG_USER_ONLY
|
1461 |
static void gen_store_exclusive(DisasContext *s, int rd, int rt, int rt2, |
1462 |
TCGv_i64 addr, int size, int is_pair) |
1463 |
{ |
1464 |
tcg_gen_mov_i64(cpu_exclusive_test, addr); |
1465 |
tcg_gen_movi_i32(cpu_exclusive_info, |
1466 |
size | is_pair << 2 | (rd << 4) | (rt << 9) | (rt2 << 14)); |
1467 |
gen_exception_insn(s, 4, EXCP_STREX);
|
1468 |
} |
1469 |
#else
|
1470 |
static void gen_store_exclusive(DisasContext *s, int rd, int rt, int rt2, |
1471 |
TCGv_i64 addr, int size, int is_pair) |
1472 |
{ |
1473 |
qemu_log_mask(LOG_UNIMP, |
1474 |
"%s:%d: system mode store_exclusive unsupported "
|
1475 |
"at pc=%016" PRIx64 "\n", |
1476 |
__FILE__, __LINE__, s->pc - 4);
|
1477 |
} |
1478 |
#endif
|
1479 |
|
1480 |
/* C3.3.6 Load/store exclusive
|
1481 |
*
|
1482 |
* 31 30 29 24 23 22 21 20 16 15 14 10 9 5 4 0
|
1483 |
* +-----+-------------+----+---+----+------+----+-------+------+------+
|
1484 |
* | sz | 0 0 1 0 0 0 | o2 | L | o1 | Rs | o0 | Rt2 | Rn | Rt |
|
1485 |
* +-----+-------------+----+---+----+------+----+-------+------+------+
|
1486 |
*
|
1487 |
* sz: 00 -> 8 bit, 01 -> 16 bit, 10 -> 32 bit, 11 -> 64 bit
|
1488 |
* L: 0 -> store, 1 -> load
|
1489 |
* o2: 0 -> exclusive, 1 -> not
|
1490 |
* o1: 0 -> single register, 1 -> register pair
|
1491 |
* o0: 1 -> load-acquire/store-release, 0 -> not
|
1492 |
*
|
1493 |
* o0 == 0 AND o2 == 1 is un-allocated
|
1494 |
* o1 == 1 is un-allocated except for 32 and 64 bit sizes
|
1495 |
*/
|
1496 |
static void disas_ldst_excl(DisasContext *s, uint32_t insn) |
1497 |
{ |
1498 |
int rt = extract32(insn, 0, 5); |
1499 |
int rn = extract32(insn, 5, 5); |
1500 |
int rt2 = extract32(insn, 10, 5); |
1501 |
int is_lasr = extract32(insn, 15, 1); |
1502 |
int rs = extract32(insn, 16, 5); |
1503 |
int is_pair = extract32(insn, 21, 1); |
1504 |
int is_store = !extract32(insn, 22, 1); |
1505 |
int is_excl = !extract32(insn, 23, 1); |
1506 |
int size = extract32(insn, 30, 2); |
1507 |
TCGv_i64 tcg_addr; |
1508 |
|
1509 |
if ((!is_excl && !is_lasr) ||
|
1510 |
(is_pair && size < 2)) {
|
1511 |
unallocated_encoding(s); |
1512 |
return;
|
1513 |
} |
1514 |
|
1515 |
if (rn == 31) { |
1516 |
gen_check_sp_alignment(s); |
1517 |
} |
1518 |
tcg_addr = read_cpu_reg_sp(s, rn, 1);
|
1519 |
|
1520 |
/* Note that since TCG is single threaded load-acquire/store-release
|
1521 |
* semantics require no extra if (is_lasr) { ... } handling.
|
1522 |
*/
|
1523 |
|
1524 |
if (is_excl) {
|
1525 |
if (!is_store) {
|
1526 |
gen_load_exclusive(s, rt, rt2, tcg_addr, size, is_pair); |
1527 |
} else {
|
1528 |
gen_store_exclusive(s, rs, rt, rt2, tcg_addr, size, is_pair); |
1529 |
} |
1530 |
} else {
|
1531 |
TCGv_i64 tcg_rt = cpu_reg(s, rt); |
1532 |
if (is_store) {
|
1533 |
do_gpr_st(s, tcg_rt, tcg_addr, size); |
1534 |
} else {
|
1535 |
do_gpr_ld(s, tcg_rt, tcg_addr, size, false, false); |
1536 |
} |
1537 |
if (is_pair) {
|
1538 |
TCGv_i64 tcg_rt2 = cpu_reg(s, rt); |
1539 |
tcg_gen_addi_i64(tcg_addr, tcg_addr, 1 << size);
|
1540 |
if (is_store) {
|
1541 |
do_gpr_st(s, tcg_rt2, tcg_addr, size); |
1542 |
} else {
|
1543 |
do_gpr_ld(s, tcg_rt2, tcg_addr, size, false, false); |
1544 |
} |
1545 |
} |
1546 |
} |
1547 |
} |
1548 |
|
1549 |
/*
|
1550 |
* C3.3.5 Load register (literal)
|
1551 |
*
|
1552 |
* 31 30 29 27 26 25 24 23 5 4 0
|
1553 |
* +-----+-------+---+-----+-------------------+-------+
|
1554 |
* | opc | 0 1 1 | V | 0 0 | imm19 | Rt |
|
1555 |
* +-----+-------+---+-----+-------------------+-------+
|
1556 |
*
|
1557 |
* V: 1 -> vector (simd/fp)
|
1558 |
* opc (non-vector): 00 -> 32 bit, 01 -> 64 bit,
|
1559 |
* 10-> 32 bit signed, 11 -> prefetch
|
1560 |
* opc (vector): 00 -> 32 bit, 01 -> 64 bit, 10 -> 128 bit (11 unallocated)
|
1561 |
*/
|
1562 |
static void disas_ld_lit(DisasContext *s, uint32_t insn) |
1563 |
{ |
1564 |
int rt = extract32(insn, 0, 5); |
1565 |
int64_t imm = sextract32(insn, 5, 19) << 2; |
1566 |
bool is_vector = extract32(insn, 26, 1); |
1567 |
int opc = extract32(insn, 30, 2); |
1568 |
bool is_signed = false; |
1569 |
int size = 2; |
1570 |
TCGv_i64 tcg_rt, tcg_addr; |
1571 |
|
1572 |
if (is_vector) {
|
1573 |
if (opc == 3) { |
1574 |
unallocated_encoding(s); |
1575 |
return;
|
1576 |
} |
1577 |
size = 2 + opc;
|
1578 |
} else {
|
1579 |
if (opc == 3) { |
1580 |
/* PRFM (literal) : prefetch */
|
1581 |
return;
|
1582 |
} |
1583 |
size = 2 + extract32(opc, 0, 1); |
1584 |
is_signed = extract32(opc, 1, 1); |
1585 |
} |
1586 |
|
1587 |
tcg_rt = cpu_reg(s, rt); |
1588 |
|
1589 |
tcg_addr = tcg_const_i64((s->pc - 4) + imm);
|
1590 |
if (is_vector) {
|
1591 |
do_fp_ld(s, rt, tcg_addr, size); |
1592 |
} else {
|
1593 |
do_gpr_ld(s, tcg_rt, tcg_addr, size, is_signed, false);
|
1594 |
} |
1595 |
tcg_temp_free_i64(tcg_addr); |
1596 |
} |
1597 |
|
1598 |
/*
|
1599 |
* C5.6.80 LDNP (Load Pair - non-temporal hint)
|
1600 |
* C5.6.81 LDP (Load Pair - non vector)
|
1601 |
* C5.6.82 LDPSW (Load Pair Signed Word - non vector)
|
1602 |
* C5.6.176 STNP (Store Pair - non-temporal hint)
|
1603 |
* C5.6.177 STP (Store Pair - non vector)
|
1604 |
* C6.3.165 LDNP (Load Pair of SIMD&FP - non-temporal hint)
|
1605 |
* C6.3.165 LDP (Load Pair of SIMD&FP)
|
1606 |
* C6.3.284 STNP (Store Pair of SIMD&FP - non-temporal hint)
|
1607 |
* C6.3.284 STP (Store Pair of SIMD&FP)
|
1608 |
*
|
1609 |
* 31 30 29 27 26 25 24 23 22 21 15 14 10 9 5 4 0
|
1610 |
* +-----+-------+---+---+-------+---+-----------------------------+
|
1611 |
* | opc | 1 0 1 | V | 0 | index | L | imm7 | Rt2 | Rn | Rt |
|
1612 |
* +-----+-------+---+---+-------+---+-------+-------+------+------+
|
1613 |
*
|
1614 |
* opc: LDP/STP/LDNP/STNP 00 -> 32 bit, 10 -> 64 bit
|
1615 |
* LDPSW 01
|
1616 |
* LDP/STP/LDNP/STNP (SIMD) 00 -> 32 bit, 01 -> 64 bit, 10 -> 128 bit
|
1617 |
* V: 0 -> GPR, 1 -> Vector
|
1618 |
* idx: 00 -> signed offset with non-temporal hint, 01 -> post-index,
|
1619 |
* 10 -> signed offset, 11 -> pre-index
|
1620 |
* L: 0 -> Store 1 -> Load
|
1621 |
*
|
1622 |
* Rt, Rt2 = GPR or SIMD registers to be stored
|
1623 |
* Rn = general purpose register containing address
|
1624 |
* imm7 = signed offset (multiple of 4 or 8 depending on size)
|
1625 |
*/
|
1626 |
static void disas_ldst_pair(DisasContext *s, uint32_t insn) |
1627 |
{ |
1628 |
int rt = extract32(insn, 0, 5); |
1629 |
int rn = extract32(insn, 5, 5); |
1630 |
int rt2 = extract32(insn, 10, 5); |
1631 |
int64_t offset = sextract32(insn, 15, 7); |
1632 |
int index = extract32(insn, 23, 2); |
1633 |
bool is_vector = extract32(insn, 26, 1); |
1634 |
bool is_load = extract32(insn, 22, 1); |
1635 |
int opc = extract32(insn, 30, 2); |
1636 |
|
1637 |
bool is_signed = false; |
1638 |
bool postindex = false; |
1639 |
bool wback = false; |
1640 |
|
1641 |
TCGv_i64 tcg_addr; /* calculated address */
|
1642 |
int size;
|
1643 |
|
1644 |
if (opc == 3) { |
1645 |
unallocated_encoding(s); |
1646 |
return;
|
1647 |
} |
1648 |
|
1649 |
if (is_vector) {
|
1650 |
size = 2 + opc;
|
1651 |
} else {
|
1652 |
size = 2 + extract32(opc, 1, 1); |
1653 |
is_signed = extract32(opc, 0, 1); |
1654 |
if (!is_load && is_signed) {
|
1655 |
unallocated_encoding(s); |
1656 |
return;
|
1657 |
} |
1658 |
} |
1659 |
|
1660 |
switch (index) {
|
1661 |
case 1: /* post-index */ |
1662 |
postindex = true;
|
1663 |
wback = true;
|
1664 |
break;
|
1665 |
case 0: |
1666 |
/* signed offset with "non-temporal" hint. Since we don't emulate
|
1667 |
* caches we don't care about hints to the cache system about
|
1668 |
* data access patterns, and handle this identically to plain
|
1669 |
* signed offset.
|
1670 |
*/
|
1671 |
if (is_signed) {
|
1672 |
/* There is no non-temporal-hint version of LDPSW */
|
1673 |
unallocated_encoding(s); |
1674 |
return;
|
1675 |
} |
1676 |
postindex = false;
|
1677 |
break;
|
1678 |
case 2: /* signed offset, rn not updated */ |
1679 |
postindex = false;
|
1680 |
break;
|
1681 |
case 3: /* pre-index */ |
1682 |
postindex = false;
|
1683 |
wback = true;
|
1684 |
break;
|
1685 |
} |
1686 |
|
1687 |
offset <<= size; |
1688 |
|
1689 |
if (rn == 31) { |
1690 |
gen_check_sp_alignment(s); |
1691 |
} |
1692 |
|
1693 |
tcg_addr = read_cpu_reg_sp(s, rn, 1);
|
1694 |
|
1695 |
if (!postindex) {
|
1696 |
tcg_gen_addi_i64(tcg_addr, tcg_addr, offset); |
1697 |
} |
1698 |
|
1699 |
if (is_vector) {
|
1700 |
if (is_load) {
|
1701 |
do_fp_ld(s, rt, tcg_addr, size); |
1702 |
} else {
|
1703 |
do_fp_st(s, rt, tcg_addr, size); |
1704 |
} |
1705 |
} else {
|
1706 |
TCGv_i64 tcg_rt = cpu_reg(s, rt); |
1707 |
if (is_load) {
|
1708 |
do_gpr_ld(s, tcg_rt, tcg_addr, size, is_signed, false);
|
1709 |
} else {
|
1710 |
do_gpr_st(s, tcg_rt, tcg_addr, size); |
1711 |
} |
1712 |
} |
1713 |
tcg_gen_addi_i64(tcg_addr, tcg_addr, 1 << size);
|
1714 |
if (is_vector) {
|
1715 |
if (is_load) {
|
1716 |
do_fp_ld(s, rt2, tcg_addr, size); |
1717 |
} else {
|
1718 |
do_fp_st(s, rt2, tcg_addr, size); |
1719 |
} |
1720 |
} else {
|
1721 |
TCGv_i64 tcg_rt2 = cpu_reg(s, rt2); |
1722 |
if (is_load) {
|
1723 |
do_gpr_ld(s, tcg_rt2, tcg_addr, size, is_signed, false);
|
1724 |
} else {
|
1725 |
do_gpr_st(s, tcg_rt2, tcg_addr, size); |
1726 |
} |
1727 |
} |
1728 |
|
1729 |
if (wback) {
|
1730 |
if (postindex) {
|
1731 |
tcg_gen_addi_i64(tcg_addr, tcg_addr, offset - (1 << size));
|
1732 |
} else {
|
1733 |
tcg_gen_subi_i64(tcg_addr, tcg_addr, 1 << size);
|
1734 |
} |
1735 |
tcg_gen_mov_i64(cpu_reg_sp(s, rn), tcg_addr); |
1736 |
} |
1737 |
} |
1738 |
|
1739 |
/*
|
1740 |
* C3.3.8 Load/store (immediate post-indexed)
|
1741 |
* C3.3.9 Load/store (immediate pre-indexed)
|
1742 |
* C3.3.12 Load/store (unscaled immediate)
|
1743 |
*
|
1744 |
* 31 30 29 27 26 25 24 23 22 21 20 12 11 10 9 5 4 0
|
1745 |
* +----+-------+---+-----+-----+---+--------+-----+------+------+
|
1746 |
* |size| 1 1 1 | V | 0 0 | opc | 0 | imm9 | idx | Rn | Rt |
|
1747 |
* +----+-------+---+-----+-----+---+--------+-----+------+------+
|
1748 |
*
|
1749 |
* idx = 01 -> post-indexed, 11 pre-indexed, 00 unscaled imm. (no writeback)
|
1750 |
* V = 0 -> non-vector
|
1751 |
* size: 00 -> 8 bit, 01 -> 16 bit, 10 -> 32 bit, 11 -> 64bit
|
1752 |
* opc: 00 -> store, 01 -> loadu, 10 -> loads 64, 11 -> loads 32
|
1753 |
*/
|
1754 |
static void disas_ldst_reg_imm9(DisasContext *s, uint32_t insn) |
1755 |
{ |
1756 |
int rt = extract32(insn, 0, 5); |
1757 |
int rn = extract32(insn, 5, 5); |
1758 |
int imm9 = sextract32(insn, 12, 9); |
1759 |
int opc = extract32(insn, 22, 2); |
1760 |
int size = extract32(insn, 30, 2); |
1761 |
int idx = extract32(insn, 10, 2); |
1762 |
bool is_signed = false; |
1763 |
bool is_store = false; |
1764 |
bool is_extended = false; |
1765 |
bool is_vector = extract32(insn, 26, 1); |
1766 |
bool post_index;
|
1767 |
bool writeback;
|
1768 |
|
1769 |
TCGv_i64 tcg_addr; |
1770 |
|
1771 |
if (is_vector) {
|
1772 |
size |= (opc & 2) << 1; |
1773 |
if (size > 4) { |
1774 |
unallocated_encoding(s); |
1775 |
return;
|
1776 |
} |
1777 |
is_store = ((opc & 1) == 0); |
1778 |
} else {
|
1779 |
if (size == 3 && opc == 2) { |
1780 |
/* PRFM - prefetch */
|
1781 |
return;
|
1782 |
} |
1783 |
if (opc == 3 && size > 1) { |
1784 |
unallocated_encoding(s); |
1785 |
return;
|
1786 |
} |
1787 |
is_store = (opc == 0);
|
1788 |
is_signed = opc & (1<<1); |
1789 |
is_extended = (size < 3) && (opc & 1); |
1790 |
} |
1791 |
|
1792 |
switch (idx) {
|
1793 |
case 0: |
1794 |
post_index = false;
|
1795 |
writeback = false;
|
1796 |
break;
|
1797 |
case 1: |
1798 |
post_index = true;
|
1799 |
writeback = true;
|
1800 |
break;
|
1801 |
case 3: |
1802 |
post_index = false;
|
1803 |
writeback = true;
|
1804 |
break;
|
1805 |
case 2: |
1806 |
g_assert(false);
|
1807 |
break;
|
1808 |
} |
1809 |
|
1810 |
if (rn == 31) { |
1811 |
gen_check_sp_alignment(s); |
1812 |
} |
1813 |
tcg_addr = read_cpu_reg_sp(s, rn, 1);
|
1814 |
|
1815 |
if (!post_index) {
|
1816 |
tcg_gen_addi_i64(tcg_addr, tcg_addr, imm9); |
1817 |
} |
1818 |
|
1819 |
if (is_vector) {
|
1820 |
if (is_store) {
|
1821 |
do_fp_st(s, rt, tcg_addr, size); |
1822 |
} else {
|
1823 |
do_fp_ld(s, rt, tcg_addr, size); |
1824 |
} |
1825 |
} else {
|
1826 |
TCGv_i64 tcg_rt = cpu_reg(s, rt); |
1827 |
if (is_store) {
|
1828 |
do_gpr_st(s, tcg_rt, tcg_addr, size); |
1829 |
} else {
|
1830 |
do_gpr_ld(s, tcg_rt, tcg_addr, size, is_signed, is_extended); |
1831 |
} |
1832 |
} |
1833 |
|
1834 |
if (writeback) {
|
1835 |
TCGv_i64 tcg_rn = cpu_reg_sp(s, rn); |
1836 |
if (post_index) {
|
1837 |
tcg_gen_addi_i64(tcg_addr, tcg_addr, imm9); |
1838 |
} |
1839 |
tcg_gen_mov_i64(tcg_rn, tcg_addr); |
1840 |
} |
1841 |
} |
1842 |
|
1843 |
/*
|
1844 |
* C3.3.10 Load/store (register offset)
|
1845 |
*
|
1846 |
* 31 30 29 27 26 25 24 23 22 21 20 16 15 13 12 11 10 9 5 4 0
|
1847 |
* +----+-------+---+-----+-----+---+------+-----+--+-----+----+----+
|
1848 |
* |size| 1 1 1 | V | 0 0 | opc | 1 | Rm | opt | S| 1 0 | Rn | Rt |
|
1849 |
* +----+-------+---+-----+-----+---+------+-----+--+-----+----+----+
|
1850 |
*
|
1851 |
* For non-vector:
|
1852 |
* size: 00-> byte, 01 -> 16 bit, 10 -> 32bit, 11 -> 64bit
|
1853 |
* opc: 00 -> store, 01 -> loadu, 10 -> loads 64, 11 -> loads 32
|
1854 |
* For vector:
|
1855 |
* size is opc<1>:size<1:0> so 100 -> 128 bit; 110 and 111 unallocated
|
1856 |
* opc<0>: 0 -> store, 1 -> load
|
1857 |
* V: 1 -> vector/simd
|
1858 |
* opt: extend encoding (see DecodeRegExtend)
|
1859 |
* S: if S=1 then scale (essentially index by sizeof(size))
|
1860 |
* Rt: register to transfer into/out of
|
1861 |
* Rn: address register or SP for base
|
1862 |
* Rm: offset register or ZR for offset
|
1863 |
*/
|
1864 |
static void disas_ldst_reg_roffset(DisasContext *s, uint32_t insn) |
1865 |
{ |
1866 |
int rt = extract32(insn, 0, 5); |
1867 |
int rn = extract32(insn, 5, 5); |
1868 |
int shift = extract32(insn, 12, 1); |
1869 |
int rm = extract32(insn, 16, 5); |
1870 |
int opc = extract32(insn, 22, 2); |
1871 |
int opt = extract32(insn, 13, 3); |
1872 |
int size = extract32(insn, 30, 2); |
1873 |
bool is_signed = false; |
1874 |
bool is_store = false; |
1875 |
bool is_extended = false; |
1876 |
bool is_vector = extract32(insn, 26, 1); |
1877 |
|
1878 |
TCGv_i64 tcg_rm; |
1879 |
TCGv_i64 tcg_addr; |
1880 |
|
1881 |
if (extract32(opt, 1, 1) == 0) { |
1882 |
unallocated_encoding(s); |
1883 |
return;
|
1884 |
} |
1885 |
|
1886 |
if (is_vector) {
|
1887 |
size |= (opc & 2) << 1; |
1888 |
if (size > 4) { |
1889 |
unallocated_encoding(s); |
1890 |
return;
|
1891 |
} |
1892 |
is_store = !extract32(opc, 0, 1); |
1893 |
} else {
|
1894 |
if (size == 3 && opc == 2) { |
1895 |
/* PRFM - prefetch */
|
1896 |
return;
|
1897 |
} |
1898 |
if (opc == 3 && size > 1) { |
1899 |
unallocated_encoding(s); |
1900 |
return;
|
1901 |
} |
1902 |
is_store = (opc == 0);
|
1903 |
is_signed = extract32(opc, 1, 1); |
1904 |
is_extended = (size < 3) && extract32(opc, 0, 1); |
1905 |
} |
1906 |
|
1907 |
if (rn == 31) { |
1908 |
gen_check_sp_alignment(s); |
1909 |
} |
1910 |
tcg_addr = read_cpu_reg_sp(s, rn, 1);
|
1911 |
|
1912 |
tcg_rm = read_cpu_reg(s, rm, 1);
|
1913 |
ext_and_shift_reg(tcg_rm, tcg_rm, opt, shift ? size : 0);
|
1914 |
|
1915 |
tcg_gen_add_i64(tcg_addr, tcg_addr, tcg_rm); |
1916 |
|
1917 |
if (is_vector) {
|
1918 |
if (is_store) {
|
1919 |
do_fp_st(s, rt, tcg_addr, size); |
1920 |
} else {
|
1921 |
do_fp_ld(s, rt, tcg_addr, size); |
1922 |
} |
1923 |
} else {
|
1924 |
TCGv_i64 tcg_rt = cpu_reg(s, rt); |
1925 |
if (is_store) {
|
1926 |
do_gpr_st(s, tcg_rt, tcg_addr, size); |
1927 |
} else {
|
1928 |
do_gpr_ld(s, tcg_rt, tcg_addr, size, is_signed, is_extended); |
1929 |
} |
1930 |
} |
1931 |
} |
1932 |
|
1933 |
/*
|
1934 |
* C3.3.13 Load/store (unsigned immediate)
|
1935 |
*
|
1936 |
* 31 30 29 27 26 25 24 23 22 21 10 9 5
|
1937 |
* +----+-------+---+-----+-----+------------+-------+------+
|
1938 |
* |size| 1 1 1 | V | 0 1 | opc | imm12 | Rn | Rt |
|
1939 |
* +----+-------+---+-----+-----+------------+-------+------+
|
1940 |
*
|
1941 |
* For non-vector:
|
1942 |
* size: 00-> byte, 01 -> 16 bit, 10 -> 32bit, 11 -> 64bit
|
1943 |
* opc: 00 -> store, 01 -> loadu, 10 -> loads 64, 11 -> loads 32
|
1944 |
* For vector:
|
1945 |
* size is opc<1>:size<1:0> so 100 -> 128 bit; 110 and 111 unallocated
|
1946 |
* opc<0>: 0 -> store, 1 -> load
|
1947 |
* Rn: base address register (inc SP)
|
1948 |
* Rt: target register
|
1949 |
*/
|
1950 |
static void disas_ldst_reg_unsigned_imm(DisasContext *s, uint32_t insn) |
1951 |
{ |
1952 |
int rt = extract32(insn, 0, 5); |
1953 |
int rn = extract32(insn, 5, 5); |
1954 |
unsigned int imm12 = extract32(insn, 10, 12); |
1955 |
bool is_vector = extract32(insn, 26, 1); |
1956 |
int size = extract32(insn, 30, 2); |
1957 |
int opc = extract32(insn, 22, 2); |
1958 |
unsigned int offset; |
1959 |
|
1960 |
TCGv_i64 tcg_addr; |
1961 |
|
1962 |
bool is_store;
|
1963 |
bool is_signed = false; |
1964 |
bool is_extended = false; |
1965 |
|
1966 |
if (is_vector) {
|
1967 |
size |= (opc & 2) << 1; |
1968 |
if (size > 4) { |
1969 |
unallocated_encoding(s); |
1970 |
return;
|
1971 |
} |
1972 |
is_store = !extract32(opc, 0, 1); |
1973 |
} else {
|
1974 |
if (size == 3 && opc == 2) { |
1975 |
/* PRFM - prefetch */
|
1976 |
return;
|
1977 |
} |
1978 |
if (opc == 3 && size > 1) { |
1979 |
unallocated_encoding(s); |
1980 |
return;
|
1981 |
} |
1982 |
is_store = (opc == 0);
|
1983 |
is_signed = extract32(opc, 1, 1); |
1984 |
is_extended = (size < 3) && extract32(opc, 0, 1); |
1985 |
} |
1986 |
|
1987 |
if (rn == 31) { |
1988 |
gen_check_sp_alignment(s); |
1989 |
} |
1990 |
tcg_addr = read_cpu_reg_sp(s, rn, 1);
|
1991 |
offset = imm12 << size; |
1992 |
tcg_gen_addi_i64(tcg_addr, tcg_addr, offset); |
1993 |
|
1994 |
if (is_vector) {
|
1995 |
if (is_store) {
|
1996 |
do_fp_st(s, rt, tcg_addr, size); |
1997 |
} else {
|
1998 |
do_fp_ld(s, rt, tcg_addr, size); |
1999 |
} |
2000 |
} else {
|
2001 |
TCGv_i64 tcg_rt = cpu_reg(s, rt); |
2002 |
if (is_store) {
|
2003 |
do_gpr_st(s, tcg_rt, tcg_addr, size); |
2004 |
} else {
|
2005 |
do_gpr_ld(s, tcg_rt, tcg_addr, size, is_signed, is_extended); |
2006 |
} |
2007 |
} |
2008 |
} |
2009 |
|
2010 |
/* Load/store register (immediate forms) */
|
2011 |
static void disas_ldst_reg_imm(DisasContext *s, uint32_t insn) |
2012 |
{ |
2013 |
switch (extract32(insn, 10, 2)) { |
2014 |
case 0: case 1: case 3: |
2015 |
/* Load/store register (unscaled immediate) */
|
2016 |
/* Load/store immediate pre/post-indexed */
|
2017 |
disas_ldst_reg_imm9(s, insn); |
2018 |
break;
|
2019 |
case 2: |
2020 |
/* Load/store register unprivileged */
|
2021 |
unsupported_encoding(s, insn); |
2022 |
break;
|
2023 |
default:
|
2024 |
unallocated_encoding(s); |
2025 |
break;
|
2026 |
} |
2027 |
} |
2028 |
|
2029 |
/* Load/store register (all forms) */
|
2030 |
static void disas_ldst_reg(DisasContext *s, uint32_t insn) |
2031 |
{ |
2032 |
switch (extract32(insn, 24, 2)) { |
2033 |
case 0: |
2034 |
if (extract32(insn, 21, 1) == 1 && extract32(insn, 10, 2) == 2) { |
2035 |
disas_ldst_reg_roffset(s, insn); |
2036 |
} else {
|
2037 |
disas_ldst_reg_imm(s, insn); |
2038 |
} |
2039 |
break;
|
2040 |
case 1: |
2041 |
disas_ldst_reg_unsigned_imm(s, insn); |
2042 |
break;
|
2043 |
default:
|
2044 |
unallocated_encoding(s); |
2045 |
break;
|
2046 |
} |
2047 |
} |
2048 |
|
2049 |
/* C3.3.1 AdvSIMD load/store multiple structures
|
2050 |
*
|
2051 |
* 31 30 29 23 22 21 16 15 12 11 10 9 5 4 0
|
2052 |
* +---+---+---------------+---+-------------+--------+------+------+------+
|
2053 |
* | 0 | Q | 0 0 1 1 0 0 0 | L | 0 0 0 0 0 0 | opcode | size | Rn | Rt |
|
2054 |
* +---+---+---------------+---+-------------+--------+------+------+------+
|
2055 |
*
|
2056 |
* C3.3.2 AdvSIMD load/store multiple structures (post-indexed)
|
2057 |
*
|
2058 |
* 31 30 29 23 22 21 20 16 15 12 11 10 9 5 4 0
|
2059 |
* +---+---+---------------+---+---+---------+--------+------+------+------+
|
2060 |
* | 0 | Q | 0 0 1 1 0 0 1 | L | 0 | Rm | opcode | size | Rn | Rt |
|
2061 |
* +---+---+---------------+---+---+---------+--------+------+------+------+
|
2062 |
*
|
2063 |
* Rt: first (or only) SIMD&FP register to be transferred
|
2064 |
* Rn: base address or SP
|
2065 |
* Rm (post-index only): post-index register (when !31) or size dependent #imm
|
2066 |
*/
|
2067 |
static void disas_ldst_multiple_struct(DisasContext *s, uint32_t insn) |
2068 |
{ |
2069 |
int rt = extract32(insn, 0, 5); |
2070 |
int rn = extract32(insn, 5, 5); |
2071 |
int size = extract32(insn, 10, 2); |
2072 |
int opcode = extract32(insn, 12, 4); |
2073 |
bool is_store = !extract32(insn, 22, 1); |
2074 |
bool is_postidx = extract32(insn, 23, 1); |
2075 |
bool is_q = extract32(insn, 30, 1); |
2076 |
TCGv_i64 tcg_addr, tcg_rn; |
2077 |
|
2078 |
int ebytes = 1 << size; |
2079 |
int elements = (is_q ? 128 : 64) / (8 << size); |
2080 |
int rpt; /* num iterations */ |
2081 |
int selem; /* structure elements */ |
2082 |
int r;
|
2083 |
|
2084 |
if (extract32(insn, 31, 1) || extract32(insn, 21, 1)) { |
2085 |
unallocated_encoding(s); |
2086 |
return;
|
2087 |
} |
2088 |
|
2089 |
/* From the shared decode logic */
|
2090 |
switch (opcode) {
|
2091 |
case 0x0: |
2092 |
rpt = 1;
|
2093 |
selem = 4;
|
2094 |
break;
|
2095 |
case 0x2: |
2096 |
rpt = 4;
|
2097 |
selem = 1;
|
2098 |
break;
|
2099 |
case 0x4: |
2100 |
rpt = 1;
|
2101 |
selem = 3;
|
2102 |
break;
|
2103 |
case 0x6: |
2104 |
rpt = 3;
|
2105 |
selem = 1;
|
2106 |
break;
|
2107 |
case 0x7: |
2108 |
rpt = 1;
|
2109 |
selem = 1;
|
2110 |
break;
|
2111 |
case 0x8: |
2112 |
rpt = 1;
|
2113 |
selem = 2;
|
2114 |
break;
|
2115 |
case 0xa: |
2116 |
rpt = 2;
|
2117 |
selem = 1;
|
2118 |
break;
|
2119 |
default:
|
2120 |
unallocated_encoding(s); |
2121 |
return;
|
2122 |
} |
2123 |
|
2124 |
if (size == 3 && !is_q && selem != 1) { |
2125 |
/* reserved */
|
2126 |
unallocated_encoding(s); |
2127 |
return;
|
2128 |
} |
2129 |
|
2130 |
if (rn == 31) { |
2131 |
gen_check_sp_alignment(s); |
2132 |
} |
2133 |
|
2134 |
tcg_rn = cpu_reg_sp(s, rn); |
2135 |
tcg_addr = tcg_temp_new_i64(); |
2136 |
tcg_gen_mov_i64(tcg_addr, tcg_rn); |
2137 |
|
2138 |
for (r = 0; r < rpt; r++) { |
2139 |
int e;
|
2140 |
for (e = 0; e < elements; e++) { |
2141 |
int tt = (rt + r) % 32; |
2142 |
int xs;
|
2143 |
for (xs = 0; xs < selem; xs++) { |
2144 |
if (is_store) {
|
2145 |
do_vec_st(s, tt, e, tcg_addr, size); |
2146 |
} else {
|
2147 |
do_vec_ld(s, tt, e, tcg_addr, size); |
2148 |
|
2149 |
/* For non-quad operations, setting a slice of the low
|
2150 |
* 64 bits of the register clears the high 64 bits (in
|
2151 |
* the ARM ARM pseudocode this is implicit in the fact
|
2152 |
* that 'rval' is a 64 bit wide variable). We optimize
|
2153 |
* by noticing that we only need to do this the first
|
2154 |
* time we touch a register.
|
2155 |
*/
|
2156 |
if (!is_q && e == 0 && (r == 0 || xs == selem - 1)) { |
2157 |
clear_vec_high(s, tt); |
2158 |
} |
2159 |
} |
2160 |
tcg_gen_addi_i64(tcg_addr, tcg_addr, ebytes); |
2161 |
tt = (tt + 1) % 32; |
2162 |
} |
2163 |
} |
2164 |
} |
2165 |
|
2166 |
if (is_postidx) {
|
2167 |
int rm = extract32(insn, 16, 5); |
2168 |
if (rm == 31) { |
2169 |
tcg_gen_mov_i64(tcg_rn, tcg_addr); |
2170 |
} else {
|
2171 |
tcg_gen_add_i64(tcg_rn, tcg_rn, cpu_reg(s, rm)); |
2172 |
} |
2173 |
} |
2174 |
tcg_temp_free_i64(tcg_addr); |
2175 |
} |
2176 |
|
2177 |
/* C3.3.3 AdvSIMD load/store single structure
|
2178 |
*
|
2179 |
* 31 30 29 23 22 21 20 16 15 13 12 11 10 9 5 4 0
|
2180 |
* +---+---+---------------+-----+-----------+-----+---+------+------+------+
|
2181 |
* | 0 | Q | 0 0 1 1 0 1 0 | L R | 0 0 0 0 0 | opc | S | size | Rn | Rt |
|
2182 |
* +---+---+---------------+-----+-----------+-----+---+------+------+------+
|
2183 |
*
|
2184 |
* C3.3.4 AdvSIMD load/store single structure (post-indexed)
|
2185 |
*
|
2186 |
* 31 30 29 23 22 21 20 16 15 13 12 11 10 9 5 4 0
|
2187 |
* +---+---+---------------+-----+-----------+-----+---+------+------+------+
|
2188 |
* | 0 | Q | 0 0 1 1 0 1 1 | L R | Rm | opc | S | size | Rn | Rt |
|
2189 |
* +---+---+---------------+-----+-----------+-----+---+------+------+------+
|
2190 |
*
|
2191 |
* Rt: first (or only) SIMD&FP register to be transferred
|
2192 |
* Rn: base address or SP
|
2193 |
* Rm (post-index only): post-index register (when !31) or size dependent #imm
|
2194 |
* index = encoded in Q:S:size dependent on size
|
2195 |
*
|
2196 |
* lane_size = encoded in R, opc
|
2197 |
* transfer width = encoded in opc, S, size
|
2198 |
*/
|
2199 |
static void disas_ldst_single_struct(DisasContext *s, uint32_t insn) |
2200 |
{ |
2201 |
int rt = extract32(insn, 0, 5); |
2202 |
int rn = extract32(insn, 5, 5); |
2203 |
int size = extract32(insn, 10, 2); |
2204 |
int S = extract32(insn, 12, 1); |
2205 |
int opc = extract32(insn, 13, 3); |
2206 |
int R = extract32(insn, 21, 1); |
2207 |
int is_load = extract32(insn, 22, 1); |
2208 |
int is_postidx = extract32(insn, 23, 1); |
2209 |
int is_q = extract32(insn, 30, 1); |
2210 |
|
2211 |
int scale = extract32(opc, 1, 2); |
2212 |
int selem = (extract32(opc, 0, 1) << 1 | R) + 1; |
2213 |
bool replicate = false; |
2214 |
int index = is_q << 3 | S << 2 | size; |
2215 |
int ebytes, xs;
|
2216 |
TCGv_i64 tcg_addr, tcg_rn; |
2217 |
|
2218 |
switch (scale) {
|
2219 |
case 3: |
2220 |
if (!is_load || S) {
|
2221 |
unallocated_encoding(s); |
2222 |
return;
|
2223 |
} |
2224 |
scale = size; |
2225 |
replicate = true;
|
2226 |
break;
|
2227 |
case 0: |
2228 |
break;
|
2229 |
case 1: |
2230 |
if (extract32(size, 0, 1)) { |
2231 |
unallocated_encoding(s); |
2232 |
return;
|
2233 |
} |
2234 |
index >>= 1;
|
2235 |
break;
|
2236 |
case 2: |
2237 |
if (extract32(size, 1, 1)) { |
2238 |
unallocated_encoding(s); |
2239 |
return;
|
2240 |
} |
2241 |
if (!extract32(size, 0, 1)) { |
2242 |
index >>= 2;
|
2243 |
} else {
|
2244 |
if (S) {
|
2245 |
unallocated_encoding(s); |
2246 |
return;
|
2247 |
} |
2248 |
index >>= 3;
|
2249 |
scale = 3;
|
2250 |
} |
2251 |
break;
|
2252 |
default:
|
2253 |
g_assert_not_reached(); |
2254 |
} |
2255 |
|
2256 |
ebytes = 1 << scale;
|
2257 |
|
2258 |
if (rn == 31) { |
2259 |
gen_check_sp_alignment(s); |
2260 |
} |
2261 |
|
2262 |
tcg_rn = cpu_reg_sp(s, rn); |
2263 |
tcg_addr = tcg_temp_new_i64(); |
2264 |
tcg_gen_mov_i64(tcg_addr, tcg_rn); |
2265 |
|
2266 |
for (xs = 0; xs < selem; xs++) { |
2267 |
if (replicate) {
|
2268 |
/* Load and replicate to all elements */
|
2269 |
uint64_t mulconst; |
2270 |
TCGv_i64 tcg_tmp = tcg_temp_new_i64(); |
2271 |
|
2272 |
tcg_gen_qemu_ld_i64(tcg_tmp, tcg_addr, |
2273 |
get_mem_index(s), MO_TE + scale); |
2274 |
switch (scale) {
|
2275 |
case 0: |
2276 |
mulconst = 0x0101010101010101ULL;
|
2277 |
break;
|
2278 |
case 1: |
2279 |
mulconst = 0x0001000100010001ULL;
|
2280 |
break;
|
2281 |
case 2: |
2282 |
mulconst = 0x0000000100000001ULL;
|
2283 |
break;
|
2284 |
case 3: |
2285 |
mulconst = 0;
|
2286 |
break;
|
2287 |
default:
|
2288 |
g_assert_not_reached(); |
2289 |
} |
2290 |
if (mulconst) {
|
2291 |
tcg_gen_muli_i64(tcg_tmp, tcg_tmp, mulconst); |
2292 |
} |
2293 |
write_vec_element(s, tcg_tmp, rt, 0, MO_64);
|
2294 |
if (is_q) {
|
2295 |
write_vec_element(s, tcg_tmp, rt, 1, MO_64);
|
2296 |
} else {
|
2297 |
clear_vec_high(s, rt); |
2298 |
} |
2299 |
tcg_temp_free_i64(tcg_tmp); |
2300 |
} else {
|
2301 |
/* Load/store one element per register */
|
2302 |
if (is_load) {
|
2303 |
do_vec_ld(s, rt, index, tcg_addr, MO_TE + scale); |
2304 |
} else {
|
2305 |
do_vec_st(s, rt, index, tcg_addr, MO_TE + scale); |
2306 |
} |
2307 |
} |
2308 |
tcg_gen_addi_i64(tcg_addr, tcg_addr, ebytes); |
2309 |
rt = (rt + 1) % 32; |
2310 |
} |
2311 |
|
2312 |
if (is_postidx) {
|
2313 |
int rm = extract32(insn, 16, 5); |
2314 |
if (rm == 31) { |
2315 |
tcg_gen_mov_i64(tcg_rn, tcg_addr); |
2316 |
} else {
|
2317 |
tcg_gen_add_i64(tcg_rn, tcg_rn, cpu_reg(s, rm)); |
2318 |
} |
2319 |
} |
2320 |
tcg_temp_free_i64(tcg_addr); |
2321 |
} |
2322 |
|
2323 |
/* C3.3 Loads and stores */
|
2324 |
static void disas_ldst(DisasContext *s, uint32_t insn) |
2325 |
{ |
2326 |
switch (extract32(insn, 24, 6)) { |
2327 |
case 0x08: /* Load/store exclusive */ |
2328 |
disas_ldst_excl(s, insn); |
2329 |
break;
|
2330 |
case 0x18: case 0x1c: /* Load register (literal) */ |
2331 |
disas_ld_lit(s, insn); |
2332 |
break;
|
2333 |
case 0x28: case 0x29: |
2334 |
case 0x2c: case 0x2d: /* Load/store pair (all forms) */ |
2335 |
disas_ldst_pair(s, insn); |
2336 |
break;
|
2337 |
case 0x38: case 0x39: |
2338 |
case 0x3c: case 0x3d: /* Load/store register (all forms) */ |
2339 |
disas_ldst_reg(s, insn); |
2340 |
break;
|
2341 |
case 0x0c: /* AdvSIMD load/store multiple structures */ |
2342 |
disas_ldst_multiple_struct(s, insn); |
2343 |
break;
|
2344 |
case 0x0d: /* AdvSIMD load/store single structure */ |
2345 |
disas_ldst_single_struct(s, insn); |
2346 |
break;
|
2347 |
default:
|
2348 |
unallocated_encoding(s); |
2349 |
break;
|
2350 |
} |
2351 |
} |
2352 |
|
2353 |
/* C3.4.6 PC-rel. addressing
|
2354 |
* 31 30 29 28 24 23 5 4 0
|
2355 |
* +----+-------+-----------+-------------------+------+
|
2356 |
* | op | immlo | 1 0 0 0 0 | immhi | Rd |
|
2357 |
* +----+-------+-----------+-------------------+------+
|
2358 |
*/
|
2359 |
static void disas_pc_rel_adr(DisasContext *s, uint32_t insn) |
2360 |
{ |
2361 |
unsigned int page, rd; |
2362 |
uint64_t base; |
2363 |
int64_t offset; |
2364 |
|
2365 |
page = extract32(insn, 31, 1); |
2366 |
/* SignExtend(immhi:immlo) -> offset */
|
2367 |
offset = ((int64_t)sextract32(insn, 5, 19) << 2) | extract32(insn, 29, 2); |
2368 |
rd = extract32(insn, 0, 5); |
2369 |
base = s->pc - 4;
|
2370 |
|
2371 |
if (page) {
|
2372 |
/* ADRP (page based) */
|
2373 |
base &= ~0xfff;
|
2374 |
offset <<= 12;
|
2375 |
} |
2376 |
|
2377 |
tcg_gen_movi_i64(cpu_reg(s, rd), base + offset); |
2378 |
} |
2379 |
|
2380 |
/*
|
2381 |
* C3.4.1 Add/subtract (immediate)
|
2382 |
*
|
2383 |
* 31 30 29 28 24 23 22 21 10 9 5 4 0
|
2384 |
* +--+--+--+-----------+-----+-------------+-----+-----+
|
2385 |
* |sf|op| S| 1 0 0 0 1 |shift| imm12 | Rn | Rd |
|
2386 |
* +--+--+--+-----------+-----+-------------+-----+-----+
|
2387 |
*
|
2388 |
* sf: 0 -> 32bit, 1 -> 64bit
|
2389 |
* op: 0 -> add , 1 -> sub
|
2390 |
* S: 1 -> set flags
|
2391 |
* shift: 00 -> LSL imm by 0, 01 -> LSL imm by 12
|
2392 |
*/
|
2393 |
static void disas_add_sub_imm(DisasContext *s, uint32_t insn) |
2394 |
{ |
2395 |
int rd = extract32(insn, 0, 5); |
2396 |
int rn = extract32(insn, 5, 5); |
2397 |
uint64_t imm = extract32(insn, 10, 12); |
2398 |
int shift = extract32(insn, 22, 2); |
2399 |
bool setflags = extract32(insn, 29, 1); |
2400 |
bool sub_op = extract32(insn, 30, 1); |
2401 |
bool is_64bit = extract32(insn, 31, 1); |
2402 |
|
2403 |
TCGv_i64 tcg_rn = cpu_reg_sp(s, rn); |
2404 |
TCGv_i64 tcg_rd = setflags ? cpu_reg(s, rd) : cpu_reg_sp(s, rd); |
2405 |
TCGv_i64 tcg_result; |
2406 |
|
2407 |
switch (shift) {
|
2408 |
case 0x0: |
2409 |
break;
|
2410 |
case 0x1: |
2411 |
imm <<= 12;
|
2412 |
break;
|
2413 |
default:
|
2414 |
unallocated_encoding(s); |
2415 |
return;
|
2416 |
} |
2417 |
|
2418 |
tcg_result = tcg_temp_new_i64(); |
2419 |
if (!setflags) {
|
2420 |
if (sub_op) {
|
2421 |
tcg_gen_subi_i64(tcg_result, tcg_rn, imm); |
2422 |
} else {
|
2423 |
tcg_gen_addi_i64(tcg_result, tcg_rn, imm); |
2424 |
} |
2425 |
} else {
|
2426 |
TCGv_i64 tcg_imm = tcg_const_i64(imm); |
2427 |
if (sub_op) {
|
2428 |
gen_sub_CC(is_64bit, tcg_result, tcg_rn, tcg_imm); |
2429 |
} else {
|
2430 |
gen_add_CC(is_64bit, tcg_result, tcg_rn, tcg_imm); |
2431 |
} |
2432 |
tcg_temp_free_i64(tcg_imm); |
2433 |
} |
2434 |
|
2435 |
if (is_64bit) {
|
2436 |
tcg_gen_mov_i64(tcg_rd, tcg_result); |
2437 |
} else {
|
2438 |
tcg_gen_ext32u_i64(tcg_rd, tcg_result); |
2439 |
} |
2440 |
|
2441 |
tcg_temp_free_i64(tcg_result); |
2442 |
} |
2443 |
|
2444 |
/* The input should be a value in the bottom e bits (with higher
|
2445 |
* bits zero); returns that value replicated into every element
|
2446 |
* of size e in a 64 bit integer.
|
2447 |
*/
|
2448 |
static uint64_t bitfield_replicate(uint64_t mask, unsigned int e) |
2449 |
{ |
2450 |
assert(e != 0);
|
2451 |
while (e < 64) { |
2452 |
mask |= mask << e; |
2453 |
e *= 2;
|
2454 |
} |
2455 |
return mask;
|
2456 |
} |
2457 |
|
2458 |
/* Return a value with the bottom len bits set (where 0 < len <= 64) */
|
2459 |
static inline uint64_t bitmask64(unsigned int length) |
2460 |
{ |
2461 |
assert(length > 0 && length <= 64); |
2462 |
return ~0ULL >> (64 - length); |
2463 |
} |
2464 |
|
2465 |
/* Simplified variant of pseudocode DecodeBitMasks() for the case where we
|
2466 |
* only require the wmask. Returns false if the imms/immr/immn are a reserved
|
2467 |
* value (ie should cause a guest UNDEF exception), and true if they are
|
2468 |
* valid, in which case the decoded bit pattern is written to result.
|
2469 |
*/
|
2470 |
static bool logic_imm_decode_wmask(uint64_t *result, unsigned int immn, |
2471 |
unsigned int imms, unsigned int immr) |
2472 |
{ |
2473 |
uint64_t mask; |
2474 |
unsigned e, levels, s, r;
|
2475 |
int len;
|
2476 |
|
2477 |
assert(immn < 2 && imms < 64 && immr < 64); |
2478 |
|
2479 |
/* The bit patterns we create here are 64 bit patterns which
|
2480 |
* are vectors of identical elements of size e = 2, 4, 8, 16, 32 or
|
2481 |
* 64 bits each. Each element contains the same value: a run
|
2482 |
* of between 1 and e-1 non-zero bits, rotated within the
|
2483 |
* element by between 0 and e-1 bits.
|
2484 |
*
|
2485 |
* The element size and run length are encoded into immn (1 bit)
|
2486 |
* and imms (6 bits) as follows:
|
2487 |
* 64 bit elements: immn = 1, imms = <length of run - 1>
|
2488 |
* 32 bit elements: immn = 0, imms = 0 : <length of run - 1>
|
2489 |
* 16 bit elements: immn = 0, imms = 10 : <length of run - 1>
|
2490 |
* 8 bit elements: immn = 0, imms = 110 : <length of run - 1>
|
2491 |
* 4 bit elements: immn = 0, imms = 1110 : <length of run - 1>
|
2492 |
* 2 bit elements: immn = 0, imms = 11110 : <length of run - 1>
|
2493 |
* Notice that immn = 0, imms = 11111x is the only combination
|
2494 |
* not covered by one of the above options; this is reserved.
|
2495 |
* Further, <length of run - 1> all-ones is a reserved pattern.
|
2496 |
*
|
2497 |
* In all cases the rotation is by immr % e (and immr is 6 bits).
|
2498 |
*/
|
2499 |
|
2500 |
/* First determine the element size */
|
2501 |
len = 31 - clz32((immn << 6) | (~imms & 0x3f)); |
2502 |
if (len < 1) { |
2503 |
/* This is the immn == 0, imms == 0x11111x case */
|
2504 |
return false; |
2505 |
} |
2506 |
e = 1 << len;
|
2507 |
|
2508 |
levels = e - 1;
|
2509 |
s = imms & levels; |
2510 |
r = immr & levels; |
2511 |
|
2512 |
if (s == levels) {
|
2513 |
/* <length of run - 1> mustn't be all-ones. */
|
2514 |
return false; |
2515 |
} |
2516 |
|
2517 |
/* Create the value of one element: s+1 set bits rotated
|
2518 |
* by r within the element (which is e bits wide)...
|
2519 |
*/
|
2520 |
mask = bitmask64(s + 1);
|
2521 |
mask = (mask >> r) | (mask << (e - r)); |
2522 |
/* ...then replicate the element over the whole 64 bit value */
|
2523 |
mask = bitfield_replicate(mask, e); |
2524 |
*result = mask; |
2525 |
return true; |
2526 |
} |
2527 |
|
2528 |
/* C3.4.4 Logical (immediate)
|
2529 |
* 31 30 29 28 23 22 21 16 15 10 9 5 4 0
|
2530 |
* +----+-----+-------------+---+------+------+------+------+
|
2531 |
* | sf | opc | 1 0 0 1 0 0 | N | immr | imms | Rn | Rd |
|
2532 |
* +----+-----+-------------+---+------+------+------+------+
|
2533 |
*/
|
2534 |
static void disas_logic_imm(DisasContext *s, uint32_t insn) |
2535 |
{ |
2536 |
unsigned int sf, opc, is_n, immr, imms, rn, rd; |
2537 |
TCGv_i64 tcg_rd, tcg_rn; |
2538 |
uint64_t wmask; |
2539 |
bool is_and = false; |
2540 |
|
2541 |
sf = extract32(insn, 31, 1); |
2542 |
opc = extract32(insn, 29, 2); |
2543 |
is_n = extract32(insn, 22, 1); |
2544 |
immr = extract32(insn, 16, 6); |
2545 |
imms = extract32(insn, 10, 6); |
2546 |
rn = extract32(insn, 5, 5); |
2547 |
rd = extract32(insn, 0, 5); |
2548 |
|
2549 |
if (!sf && is_n) {
|
2550 |
unallocated_encoding(s); |
2551 |
return;
|
2552 |
} |
2553 |
|
2554 |
if (opc == 0x3) { /* ANDS */ |
2555 |
tcg_rd = cpu_reg(s, rd); |
2556 |
} else {
|
2557 |
tcg_rd = cpu_reg_sp(s, rd); |
2558 |
} |
2559 |
tcg_rn = cpu_reg(s, rn); |
2560 |
|
2561 |
if (!logic_imm_decode_wmask(&wmask, is_n, imms, immr)) {
|
2562 |
/* some immediate field values are reserved */
|
2563 |
unallocated_encoding(s); |
2564 |
return;
|
2565 |
} |
2566 |
|
2567 |
if (!sf) {
|
2568 |
wmask &= 0xffffffff;
|
2569 |
} |
2570 |
|
2571 |
switch (opc) {
|
2572 |
case 0x3: /* ANDS */ |
2573 |
case 0x0: /* AND */ |
2574 |
tcg_gen_andi_i64(tcg_rd, tcg_rn, wmask); |
2575 |
is_and = true;
|
2576 |
break;
|
2577 |
case 0x1: /* ORR */ |
2578 |
tcg_gen_ori_i64(tcg_rd, tcg_rn, wmask); |
2579 |
break;
|
2580 |
case 0x2: /* EOR */ |
2581 |
tcg_gen_xori_i64(tcg_rd, tcg_rn, wmask); |
2582 |
break;
|
2583 |
default:
|
2584 |
assert(FALSE); /* must handle all above */
|
2585 |
break;
|
2586 |
} |
2587 |
|
2588 |
if (!sf && !is_and) {
|
2589 |
/* zero extend final result; we know we can skip this for AND
|
2590 |
* since the immediate had the high 32 bits clear.
|
2591 |
*/
|
2592 |
tcg_gen_ext32u_i64(tcg_rd, tcg_rd); |
2593 |
} |
2594 |
|
2595 |
if (opc == 3) { /* ANDS */ |
2596 |
gen_logic_CC(sf, tcg_rd); |
2597 |
} |
2598 |
} |
2599 |
|
2600 |
/*
|
2601 |
* C3.4.5 Move wide (immediate)
|
2602 |
*
|
2603 |
* 31 30 29 28 23 22 21 20 5 4 0
|
2604 |
* +--+-----+-------------+-----+----------------+------+
|
2605 |
* |sf| opc | 1 0 0 1 0 1 | hw | imm16 | Rd |
|
2606 |
* +--+-----+-------------+-----+----------------+------+
|
2607 |
*
|
2608 |
* sf: 0 -> 32 bit, 1 -> 64 bit
|
2609 |
* opc: 00 -> N, 10 -> Z, 11 -> K
|
2610 |
* hw: shift/16 (0,16, and sf only 32, 48)
|
2611 |
*/
|
2612 |
static void disas_movw_imm(DisasContext *s, uint32_t insn) |
2613 |
{ |
2614 |
int rd = extract32(insn, 0, 5); |
2615 |
uint64_t imm = extract32(insn, 5, 16); |
2616 |
int sf = extract32(insn, 31, 1); |
2617 |
int opc = extract32(insn, 29, 2); |
2618 |
int pos = extract32(insn, 21, 2) << 4; |
2619 |
TCGv_i64 tcg_rd = cpu_reg(s, rd); |
2620 |
TCGv_i64 tcg_imm; |
2621 |
|
2622 |
if (!sf && (pos >= 32)) { |
2623 |
unallocated_encoding(s); |
2624 |
return;
|
2625 |
} |
2626 |
|
2627 |
switch (opc) {
|
2628 |
case 0: /* MOVN */ |
2629 |
case 2: /* MOVZ */ |
2630 |
imm <<= pos; |
2631 |
if (opc == 0) { |
2632 |
imm = ~imm; |
2633 |
} |
2634 |
if (!sf) {
|
2635 |
imm &= 0xffffffffu;
|
2636 |
} |
2637 |
tcg_gen_movi_i64(tcg_rd, imm); |
2638 |
break;
|
2639 |
case 3: /* MOVK */ |
2640 |
tcg_imm = tcg_const_i64(imm); |
2641 |
tcg_gen_deposit_i64(tcg_rd, tcg_rd, tcg_imm, pos, 16);
|
2642 |
tcg_temp_free_i64(tcg_imm); |
2643 |
if (!sf) {
|
2644 |
tcg_gen_ext32u_i64(tcg_rd, tcg_rd); |
2645 |
} |
2646 |
break;
|
2647 |
default:
|
2648 |
unallocated_encoding(s); |
2649 |
break;
|
2650 |
} |
2651 |
} |
2652 |
|
2653 |
/* C3.4.2 Bitfield
|
2654 |
* 31 30 29 28 23 22 21 16 15 10 9 5 4 0
|
2655 |
* +----+-----+-------------+---+------+------+------+------+
|
2656 |
* | sf | opc | 1 0 0 1 1 0 | N | immr | imms | Rn | Rd |
|
2657 |
* +----+-----+-------------+---+------+------+------+------+
|
2658 |
*/
|
2659 |
static void disas_bitfield(DisasContext *s, uint32_t insn) |
2660 |
{ |
2661 |
unsigned int sf, n, opc, ri, si, rn, rd, bitsize, pos, len; |
2662 |
TCGv_i64 tcg_rd, tcg_tmp; |
2663 |
|
2664 |
sf = extract32(insn, 31, 1); |
2665 |
opc = extract32(insn, 29, 2); |
2666 |
n = extract32(insn, 22, 1); |
2667 |
ri = extract32(insn, 16, 6); |
2668 |
si = extract32(insn, 10, 6); |
2669 |
rn = extract32(insn, 5, 5); |
2670 |
rd = extract32(insn, 0, 5); |
2671 |
bitsize = sf ? 64 : 32; |
2672 |
|
2673 |
if (sf != n || ri >= bitsize || si >= bitsize || opc > 2) { |
2674 |
unallocated_encoding(s); |
2675 |
return;
|
2676 |
} |
2677 |
|
2678 |
tcg_rd = cpu_reg(s, rd); |
2679 |
tcg_tmp = read_cpu_reg(s, rn, sf); |
2680 |
|
2681 |
/* OPTME: probably worth recognizing common cases of ext{8,16,32}{u,s} */
|
2682 |
|
2683 |
if (opc != 1) { /* SBFM or UBFM */ |
2684 |
tcg_gen_movi_i64(tcg_rd, 0);
|
2685 |
} |
2686 |
|
2687 |
/* do the bit move operation */
|
2688 |
if (si >= ri) {
|
2689 |
/* Wd<s-r:0> = Wn<s:r> */
|
2690 |
tcg_gen_shri_i64(tcg_tmp, tcg_tmp, ri); |
2691 |
pos = 0;
|
2692 |
len = (si - ri) + 1;
|
2693 |
} else {
|
2694 |
/* Wd<32+s-r,32-r> = Wn<s:0> */
|
2695 |
pos = bitsize - ri; |
2696 |
len = si + 1;
|
2697 |
} |
2698 |
|
2699 |
tcg_gen_deposit_i64(tcg_rd, tcg_rd, tcg_tmp, pos, len); |
2700 |
|
2701 |
if (opc == 0) { /* SBFM - sign extend the destination field */ |
2702 |
tcg_gen_shli_i64(tcg_rd, tcg_rd, 64 - (pos + len));
|
2703 |
tcg_gen_sari_i64(tcg_rd, tcg_rd, 64 - (pos + len));
|
2704 |
} |
2705 |
|
2706 |
if (!sf) { /* zero extend final result */ |
2707 |
tcg_gen_ext32u_i64(tcg_rd, tcg_rd); |
2708 |
} |
2709 |
} |
2710 |
|
2711 |
/* C3.4.3 Extract
|
2712 |
* 31 30 29 28 23 22 21 20 16 15 10 9 5 4 0
|
2713 |
* +----+------+-------------+---+----+------+--------+------+------+
|
2714 |
* | sf | op21 | 1 0 0 1 1 1 | N | o0 | Rm | imms | Rn | Rd |
|
2715 |
* +----+------+-------------+---+----+------+--------+------+------+
|
2716 |
*/
|
2717 |
static void disas_extract(DisasContext *s, uint32_t insn) |
2718 |
{ |
2719 |
unsigned int sf, n, rm, imm, rn, rd, bitsize, op21, op0; |
2720 |
|
2721 |
sf = extract32(insn, 31, 1); |
2722 |
n = extract32(insn, 22, 1); |
2723 |
rm = extract32(insn, 16, 5); |
2724 |
imm = extract32(insn, 10, 6); |
2725 |
rn = extract32(insn, 5, 5); |
2726 |
rd = extract32(insn, 0, 5); |
2727 |
op21 = extract32(insn, 29, 2); |
2728 |
op0 = extract32(insn, 21, 1); |
2729 |
bitsize = sf ? 64 : 32; |
2730 |
|
2731 |
if (sf != n || op21 || op0 || imm >= bitsize) {
|
2732 |
unallocated_encoding(s); |
2733 |
} else {
|
2734 |
TCGv_i64 tcg_rd, tcg_rm, tcg_rn; |
2735 |
|
2736 |
tcg_rd = cpu_reg(s, rd); |
2737 |
|
2738 |
if (imm) {
|
2739 |
/* OPTME: we can special case rm==rn as a rotate */
|
2740 |
tcg_rm = read_cpu_reg(s, rm, sf); |
2741 |
tcg_rn = read_cpu_reg(s, rn, sf); |
2742 |
tcg_gen_shri_i64(tcg_rm, tcg_rm, imm); |
2743 |
tcg_gen_shli_i64(tcg_rn, tcg_rn, bitsize - imm); |
2744 |
tcg_gen_or_i64(tcg_rd, tcg_rm, tcg_rn); |
2745 |
if (!sf) {
|
2746 |
tcg_gen_ext32u_i64(tcg_rd, tcg_rd); |
2747 |
} |
2748 |
} else {
|
2749 |
/* tcg shl_i32/shl_i64 is undefined for 32/64 bit shifts,
|
2750 |
* so an extract from bit 0 is a special case.
|
2751 |
*/
|
2752 |
if (sf) {
|
2753 |
tcg_gen_mov_i64(tcg_rd, cpu_reg(s, rm)); |
2754 |
} else {
|
2755 |
tcg_gen_ext32u_i64(tcg_rd, cpu_reg(s, rm)); |
2756 |
} |
2757 |
} |
2758 |
|
2759 |
} |
2760 |
} |
2761 |
|
2762 |
/* C3.4 Data processing - immediate */
|
2763 |
static void disas_data_proc_imm(DisasContext *s, uint32_t insn) |
2764 |
{ |
2765 |
switch (extract32(insn, 23, 6)) { |
2766 |
case 0x20: case 0x21: /* PC-rel. addressing */ |
2767 |
disas_pc_rel_adr(s, insn); |
2768 |
break;
|
2769 |
case 0x22: case 0x23: /* Add/subtract (immediate) */ |
2770 |
disas_add_sub_imm(s, insn); |
2771 |
break;
|
2772 |
case 0x24: /* Logical (immediate) */ |
2773 |
disas_logic_imm(s, insn); |
2774 |
break;
|
2775 |
case 0x25: /* Move wide (immediate) */ |
2776 |
disas_movw_imm(s, insn); |
2777 |
break;
|
2778 |
case 0x26: /* Bitfield */ |
2779 |
disas_bitfield(s, insn); |
2780 |
break;
|
2781 |
case 0x27: /* Extract */ |
2782 |
disas_extract(s, insn); |
2783 |
break;
|
2784 |
default:
|
2785 |
unallocated_encoding(s); |
2786 |
break;
|
2787 |
} |
2788 |
} |
2789 |
|
2790 |
/* Shift a TCGv src by TCGv shift_amount, put result in dst.
|
2791 |
* Note that it is the caller's responsibility to ensure that the
|
2792 |
* shift amount is in range (ie 0..31 or 0..63) and provide the ARM
|
2793 |
* mandated semantics for out of range shifts.
|
2794 |
*/
|
2795 |
static void shift_reg(TCGv_i64 dst, TCGv_i64 src, int sf, |
2796 |
enum a64_shift_type shift_type, TCGv_i64 shift_amount)
|
2797 |
{ |
2798 |
switch (shift_type) {
|
2799 |
case A64_SHIFT_TYPE_LSL:
|
2800 |
tcg_gen_shl_i64(dst, src, shift_amount); |
2801 |
break;
|
2802 |
case A64_SHIFT_TYPE_LSR:
|
2803 |
tcg_gen_shr_i64(dst, src, shift_amount); |
2804 |
break;
|
2805 |
case A64_SHIFT_TYPE_ASR:
|
2806 |
if (!sf) {
|
2807 |
tcg_gen_ext32s_i64(dst, src); |
2808 |
} |
2809 |
tcg_gen_sar_i64(dst, sf ? src : dst, shift_amount); |
2810 |
break;
|
2811 |
case A64_SHIFT_TYPE_ROR:
|
2812 |
if (sf) {
|
2813 |
tcg_gen_rotr_i64(dst, src, shift_amount); |
2814 |
} else {
|
2815 |
TCGv_i32 t0, t1; |
2816 |
t0 = tcg_temp_new_i32(); |
2817 |
t1 = tcg_temp_new_i32(); |
2818 |
tcg_gen_trunc_i64_i32(t0, src); |
2819 |
tcg_gen_trunc_i64_i32(t1, shift_amount); |
2820 |
tcg_gen_rotr_i32(t0, t0, t1); |
2821 |
tcg_gen_extu_i32_i64(dst, t0); |
2822 |
tcg_temp_free_i32(t0); |
2823 |
tcg_temp_free_i32(t1); |
2824 |
} |
2825 |
break;
|
2826 |
default:
|
2827 |
assert(FALSE); /* all shift types should be handled */
|
2828 |
break;
|
2829 |
} |
2830 |
|
2831 |
if (!sf) { /* zero extend final result */ |
2832 |
tcg_gen_ext32u_i64(dst, dst); |
2833 |
} |
2834 |
} |
2835 |
|
2836 |
/* Shift a TCGv src by immediate, put result in dst.
|
2837 |
* The shift amount must be in range (this should always be true as the
|
2838 |
* relevant instructions will UNDEF on bad shift immediates).
|
2839 |
*/
|
2840 |
static void shift_reg_imm(TCGv_i64 dst, TCGv_i64 src, int sf, |
2841 |
enum a64_shift_type shift_type, unsigned int shift_i) |
2842 |
{ |
2843 |
assert(shift_i < (sf ? 64 : 32)); |
2844 |
|
2845 |
if (shift_i == 0) { |
2846 |
tcg_gen_mov_i64(dst, src); |
2847 |
} else {
|
2848 |
TCGv_i64 shift_const; |
2849 |
|
2850 |
shift_const = tcg_const_i64(shift_i); |
2851 |
shift_reg(dst, src, sf, shift_type, shift_const); |
2852 |
tcg_temp_free_i64(shift_const); |
2853 |
} |
2854 |
} |
2855 |
|
2856 |
/* C3.5.10 Logical (shifted register)
|
2857 |
* 31 30 29 28 24 23 22 21 20 16 15 10 9 5 4 0
|
2858 |
* +----+-----+-----------+-------+---+------+--------+------+------+
|
2859 |
* | sf | opc | 0 1 0 1 0 | shift | N | Rm | imm6 | Rn | Rd |
|
2860 |
* +----+-----+-----------+-------+---+------+--------+------+------+
|
2861 |
*/
|
2862 |
static void disas_logic_reg(DisasContext *s, uint32_t insn) |
2863 |
{ |
2864 |
TCGv_i64 tcg_rd, tcg_rn, tcg_rm; |
2865 |
unsigned int sf, opc, shift_type, invert, rm, shift_amount, rn, rd; |
2866 |
|
2867 |
sf = extract32(insn, 31, 1); |
2868 |
opc = extract32(insn, 29, 2); |
2869 |
shift_type = extract32(insn, 22, 2); |
2870 |
invert = extract32(insn, 21, 1); |
2871 |
rm = extract32(insn, 16, 5); |
2872 |
shift_amount = extract32(insn, 10, 6); |
2873 |
rn = extract32(insn, 5, 5); |
2874 |
rd = extract32(insn, 0, 5); |
2875 |
|
2876 |
if (!sf && (shift_amount & (1 << 5))) { |
2877 |
unallocated_encoding(s); |
2878 |
return;
|
2879 |
} |
2880 |
|
2881 |
tcg_rd = cpu_reg(s, rd); |
2882 |
|
2883 |
if (opc == 1 && shift_amount == 0 && shift_type == 0 && rn == 31) { |
2884 |
/* Unshifted ORR and ORN with WZR/XZR is the standard encoding for
|
2885 |
* register-register MOV and MVN, so it is worth special casing.
|
2886 |
*/
|
2887 |
tcg_rm = cpu_reg(s, rm); |
2888 |
if (invert) {
|
2889 |
tcg_gen_not_i64(tcg_rd, tcg_rm); |
2890 |
if (!sf) {
|
2891 |
tcg_gen_ext32u_i64(tcg_rd, tcg_rd); |
2892 |
} |
2893 |
} else {
|
2894 |
if (sf) {
|
2895 |
tcg_gen_mov_i64(tcg_rd, tcg_rm); |
2896 |
} else {
|
2897 |
tcg_gen_ext32u_i64(tcg_rd, tcg_rm); |
2898 |
} |
2899 |
} |
2900 |
return;
|
2901 |
} |
2902 |
|
2903 |
tcg_rm = read_cpu_reg(s, rm, sf); |
2904 |
|
2905 |
if (shift_amount) {
|
2906 |
shift_reg_imm(tcg_rm, tcg_rm, sf, shift_type, shift_amount); |
2907 |
} |
2908 |
|
2909 |
tcg_rn = cpu_reg(s, rn); |
2910 |
|
2911 |
switch (opc | (invert << 2)) { |
2912 |
case 0: /* AND */ |
2913 |
case 3: /* ANDS */ |
2914 |
tcg_gen_and_i64(tcg_rd, tcg_rn, tcg_rm); |
2915 |
break;
|
2916 |
case 1: /* ORR */ |
2917 |
tcg_gen_or_i64(tcg_rd, tcg_rn, tcg_rm); |
2918 |
break;
|
2919 |
case 2: /* EOR */ |
2920 |
tcg_gen_xor_i64(tcg_rd, tcg_rn, tcg_rm); |
2921 |
break;
|
2922 |
case 4: /* BIC */ |
2923 |
case 7: /* BICS */ |
2924 |
tcg_gen_andc_i64(tcg_rd, tcg_rn, tcg_rm); |
2925 |
break;
|
2926 |
case 5: /* ORN */ |
2927 |
tcg_gen_orc_i64(tcg_rd, tcg_rn, tcg_rm); |
2928 |
break;
|
2929 |
case 6: /* EON */ |
2930 |
tcg_gen_eqv_i64(tcg_rd, tcg_rn, tcg_rm); |
2931 |
break;
|
2932 |
default:
|
2933 |
assert(FALSE); |
2934 |
break;
|
2935 |
} |
2936 |
|
2937 |
if (!sf) {
|
2938 |
tcg_gen_ext32u_i64(tcg_rd, tcg_rd); |
2939 |
} |
2940 |
|
2941 |
if (opc == 3) { |
2942 |
gen_logic_CC(sf, tcg_rd); |
2943 |
} |
2944 |
} |
2945 |
|
2946 |
/*
|
2947 |
* C3.5.1 Add/subtract (extended register)
|
2948 |
*
|
2949 |
* 31|30|29|28 24|23 22|21|20 16|15 13|12 10|9 5|4 0|
|
2950 |
* +--+--+--+-----------+-----+--+-------+------+------+----+----+
|
2951 |
* |sf|op| S| 0 1 0 1 1 | opt | 1| Rm |option| imm3 | Rn | Rd |
|
2952 |
* +--+--+--+-----------+-----+--+-------+------+------+----+----+
|
2953 |
*
|
2954 |
* sf: 0 -> 32bit, 1 -> 64bit
|
2955 |
* op: 0 -> add , 1 -> sub
|
2956 |
* S: 1 -> set flags
|
2957 |
* opt: 00
|
2958 |
* option: extension type (see DecodeRegExtend)
|
2959 |
* imm3: optional shift to Rm
|
2960 |
*
|
2961 |
* Rd = Rn + LSL(extend(Rm), amount)
|
2962 |
*/
|
2963 |
static void disas_add_sub_ext_reg(DisasContext *s, uint32_t insn) |
2964 |
{ |
2965 |
int rd = extract32(insn, 0, 5); |
2966 |
int rn = extract32(insn, 5, 5); |
2967 |
int imm3 = extract32(insn, 10, 3); |
2968 |
int option = extract32(insn, 13, 3); |
2969 |
int rm = extract32(insn, 16, 5); |
2970 |
bool setflags = extract32(insn, 29, 1); |
2971 |
bool sub_op = extract32(insn, 30, 1); |
2972 |
bool sf = extract32(insn, 31, 1); |
2973 |
|
2974 |
TCGv_i64 tcg_rm, tcg_rn; /* temps */
|
2975 |
TCGv_i64 tcg_rd; |
2976 |
TCGv_i64 tcg_result; |
2977 |
|
2978 |
if (imm3 > 4) { |
2979 |
unallocated_encoding(s); |
2980 |
return;
|
2981 |
} |
2982 |
|
2983 |
/* non-flag setting ops may use SP */
|
2984 |
if (!setflags) {
|
2985 |
tcg_rn = read_cpu_reg_sp(s, rn, sf); |
2986 |
tcg_rd = cpu_reg_sp(s, rd); |
2987 |
} else {
|
2988 |
tcg_rn = read_cpu_reg(s, rn, sf); |
2989 |
tcg_rd = cpu_reg(s, rd); |
2990 |
} |
2991 |
|
2992 |
tcg_rm = read_cpu_reg(s, rm, sf); |
2993 |
ext_and_shift_reg(tcg_rm, tcg_rm, option, imm3); |
2994 |
|
2995 |
tcg_result = tcg_temp_new_i64(); |
2996 |
|
2997 |
if (!setflags) {
|
2998 |
if (sub_op) {
|
2999 |
tcg_gen_sub_i64(tcg_result, tcg_rn, tcg_rm); |
3000 |
} else {
|
3001 |
tcg_gen_add_i64(tcg_result, tcg_rn, tcg_rm); |
3002 |
} |
3003 |
} else {
|
3004 |
if (sub_op) {
|
3005 |
gen_sub_CC(sf, tcg_result, tcg_rn, tcg_rm); |
3006 |
} else {
|
3007 |
gen_add_CC(sf, tcg_result, tcg_rn, tcg_rm); |
3008 |
} |
3009 |
} |
3010 |
|
3011 |
if (sf) {
|
3012 |
tcg_gen_mov_i64(tcg_rd, tcg_result); |
3013 |
} else {
|
3014 |
tcg_gen_ext32u_i64(tcg_rd, tcg_result); |
3015 |
} |
3016 |
|
3017 |
tcg_temp_free_i64(tcg_result); |
3018 |
} |
3019 |
|
3020 |
/*
|
3021 |
* C3.5.2 Add/subtract (shifted register)
|
3022 |
*
|
3023 |
* 31 30 29 28 24 23 22 21 20 16 15 10 9 5 4 0
|
3024 |
* +--+--+--+-----------+-----+--+-------+---------+------+------+
|
3025 |
* |sf|op| S| 0 1 0 1 1 |shift| 0| Rm | imm6 | Rn | Rd |
|
3026 |
* +--+--+--+-----------+-----+--+-------+---------+------+------+
|
3027 |
*
|
3028 |
* sf: 0 -> 32bit, 1 -> 64bit
|
3029 |
* op: 0 -> add , 1 -> sub
|
3030 |
* S: 1 -> set flags
|
3031 |
* shift: 00 -> LSL, 01 -> LSR, 10 -> ASR, 11 -> RESERVED
|
3032 |
* imm6: Shift amount to apply to Rm before the add/sub
|
3033 |
*/
|
3034 |
static void disas_add_sub_reg(DisasContext *s, uint32_t insn) |
3035 |
{ |
3036 |
int rd = extract32(insn, 0, 5); |
3037 |
int rn = extract32(insn, 5, 5); |
3038 |
int imm6 = extract32(insn, 10, 6); |
3039 |
int rm = extract32(insn, 16, 5); |
3040 |
int shift_type = extract32(insn, 22, 2); |
3041 |
bool setflags = extract32(insn, 29, 1); |
3042 |
bool sub_op = extract32(insn, 30, 1); |
3043 |
bool sf = extract32(insn, 31, 1); |
3044 |
|
3045 |
TCGv_i64 tcg_rd = cpu_reg(s, rd); |
3046 |
TCGv_i64 tcg_rn, tcg_rm; |
3047 |
TCGv_i64 tcg_result; |
3048 |
|
3049 |
if ((shift_type == 3) || (!sf && (imm6 > 31))) { |
3050 |
unallocated_encoding(s); |
3051 |
return;
|
3052 |
} |
3053 |
|
3054 |
tcg_rn = read_cpu_reg(s, rn, sf); |
3055 |
tcg_rm = read_cpu_reg(s, rm, sf); |
3056 |
|
3057 |
shift_reg_imm(tcg_rm, tcg_rm, sf, shift_type, imm6); |
3058 |
|
3059 |
tcg_result = tcg_temp_new_i64(); |
3060 |
|
3061 |
if (!setflags) {
|
3062 |
if (sub_op) {
|
3063 |
tcg_gen_sub_i64(tcg_result, tcg_rn, tcg_rm); |
3064 |
} else {
|
3065 |
tcg_gen_add_i64(tcg_result, tcg_rn, tcg_rm); |
3066 |
} |
3067 |
} else {
|
3068 |
if (sub_op) {
|
3069 |
gen_sub_CC(sf, tcg_result, tcg_rn, tcg_rm); |
3070 |
} else {
|
3071 |
gen_add_CC(sf, tcg_result, tcg_rn, tcg_rm); |
3072 |
} |
3073 |
} |
3074 |
|
3075 |
if (sf) {
|
3076 |
tcg_gen_mov_i64(tcg_rd, tcg_result); |
3077 |
} else {
|
3078 |
tcg_gen_ext32u_i64(tcg_rd, tcg_result); |
3079 |
} |
3080 |
|
3081 |
tcg_temp_free_i64(tcg_result); |
3082 |
} |
3083 |
|
3084 |
/* C3.5.9 Data-processing (3 source)
|
3085 |
|
3086 |
31 30 29 28 24 23 21 20 16 15 14 10 9 5 4 0
|
3087 |
+--+------+-----------+------+------+----+------+------+------+
|
3088 |
|sf| op54 | 1 1 0 1 1 | op31 | Rm | o0 | Ra | Rn | Rd |
|
3089 |
+--+------+-----------+------+------+----+------+------+------+
|
3090 |
|
3091 |
*/
|
3092 |
static void disas_data_proc_3src(DisasContext *s, uint32_t insn) |
3093 |
{ |
3094 |
int rd = extract32(insn, 0, 5); |
3095 |
int rn = extract32(insn, 5, 5); |
3096 |
int ra = extract32(insn, 10, 5); |
3097 |
int rm = extract32(insn, 16, 5); |
3098 |
int op_id = (extract32(insn, 29, 3) << 4) | |
3099 |
(extract32(insn, 21, 3) << 1) | |
3100 |
extract32(insn, 15, 1); |
3101 |
bool sf = extract32(insn, 31, 1); |
3102 |
bool is_sub = extract32(op_id, 0, 1); |
3103 |
bool is_high = extract32(op_id, 2, 1); |
3104 |
bool is_signed = false; |
3105 |
TCGv_i64 tcg_op1; |
3106 |
TCGv_i64 tcg_op2; |
3107 |
TCGv_i64 tcg_tmp; |
3108 |
|
3109 |
/* Note that op_id is sf:op54:op31:o0 so it includes the 32/64 size flag */
|
3110 |
switch (op_id) {
|
3111 |
case 0x42: /* SMADDL */ |
3112 |
case 0x43: /* SMSUBL */ |
3113 |
case 0x44: /* SMULH */ |
3114 |
is_signed = true;
|
3115 |
break;
|
3116 |
case 0x0: /* MADD (32bit) */ |
3117 |
case 0x1: /* MSUB (32bit) */ |
3118 |
case 0x40: /* MADD (64bit) */ |
3119 |
case 0x41: /* MSUB (64bit) */ |
3120 |
case 0x4a: /* UMADDL */ |
3121 |
case 0x4b: /* UMSUBL */ |
3122 |
case 0x4c: /* UMULH */ |
3123 |
break;
|
3124 |
default:
|
3125 |
unallocated_encoding(s); |
3126 |
return;
|
3127 |
} |
3128 |
|
3129 |
if (is_high) {
|
3130 |
TCGv_i64 low_bits = tcg_temp_new_i64(); /* low bits discarded */
|
3131 |
TCGv_i64 tcg_rd = cpu_reg(s, rd); |
3132 |
TCGv_i64 tcg_rn = cpu_reg(s, rn); |
3133 |
TCGv_i64 tcg_rm = cpu_reg(s, rm); |
3134 |
|
3135 |
if (is_signed) {
|
3136 |
tcg_gen_muls2_i64(low_bits, tcg_rd, tcg_rn, tcg_rm); |
3137 |
} else {
|
3138 |
tcg_gen_mulu2_i64(low_bits, tcg_rd, tcg_rn, tcg_rm); |
3139 |
} |
3140 |
|
3141 |
tcg_temp_free_i64(low_bits); |
3142 |
return;
|
3143 |
} |
3144 |
|
3145 |
tcg_op1 = tcg_temp_new_i64(); |
3146 |
tcg_op2 = tcg_temp_new_i64(); |
3147 |
tcg_tmp = tcg_temp_new_i64(); |
3148 |
|
3149 |
if (op_id < 0x42) { |
3150 |
tcg_gen_mov_i64(tcg_op1, cpu_reg(s, rn)); |
3151 |
tcg_gen_mov_i64(tcg_op2, cpu_reg(s, rm)); |
3152 |
} else {
|
3153 |
if (is_signed) {
|
3154 |
tcg_gen_ext32s_i64(tcg_op1, cpu_reg(s, rn)); |
3155 |
tcg_gen_ext32s_i64(tcg_op2, cpu_reg(s, rm)); |
3156 |
} else {
|
3157 |
tcg_gen_ext32u_i64(tcg_op1, cpu_reg(s, rn)); |
3158 |
tcg_gen_ext32u_i64(tcg_op2, cpu_reg(s, rm)); |
3159 |
} |
3160 |
} |
3161 |
|
3162 |
if (ra == 31 && !is_sub) { |
3163 |
/* Special-case MADD with rA == XZR; it is the standard MUL alias */
|
3164 |
tcg_gen_mul_i64(cpu_reg(s, rd), tcg_op1, tcg_op2); |
3165 |
} else {
|
3166 |
tcg_gen_mul_i64(tcg_tmp, tcg_op1, tcg_op2); |
3167 |
if (is_sub) {
|
3168 |
tcg_gen_sub_i64(cpu_reg(s, rd), cpu_reg(s, ra), tcg_tmp); |
3169 |
} else {
|
3170 |
tcg_gen_add_i64(cpu_reg(s, rd), cpu_reg(s, ra), tcg_tmp); |
3171 |
} |
3172 |
} |
3173 |
|
3174 |
if (!sf) {
|
3175 |
tcg_gen_ext32u_i64(cpu_reg(s, rd), cpu_reg(s, rd)); |
3176 |
} |
3177 |
|
3178 |
tcg_temp_free_i64(tcg_op1); |
3179 |
tcg_temp_free_i64(tcg_op2); |
3180 |
tcg_temp_free_i64(tcg_tmp); |
3181 |
} |
3182 |
|
3183 |
/* C3.5.3 - Add/subtract (with carry)
|
3184 |
* 31 30 29 28 27 26 25 24 23 22 21 20 16 15 10 9 5 4 0
|
3185 |
* +--+--+--+------------------------+------+---------+------+-----+
|
3186 |
* |sf|op| S| 1 1 0 1 0 0 0 0 | rm | opcode2 | Rn | Rd |
|
3187 |
* +--+--+--+------------------------+------+---------+------+-----+
|
3188 |
* [000000]
|
3189 |
*/
|
3190 |
|
3191 |
static void disas_adc_sbc(DisasContext *s, uint32_t insn) |
3192 |
{ |
3193 |
unsigned int sf, op, setflags, rm, rn, rd; |
3194 |
TCGv_i64 tcg_y, tcg_rn, tcg_rd; |
3195 |
|
3196 |
if (extract32(insn, 10, 6) != 0) { |
3197 |
unallocated_encoding(s); |
3198 |
return;
|
3199 |
} |
3200 |
|
3201 |
sf = extract32(insn, 31, 1); |
3202 |
op = extract32(insn, 30, 1); |
3203 |
setflags = extract32(insn, 29, 1); |
3204 |
rm = extract32(insn, 16, 5); |
3205 |
rn = extract32(insn, 5, 5); |
3206 |
rd = extract32(insn, 0, 5); |
3207 |
|
3208 |
tcg_rd = cpu_reg(s, rd); |
3209 |
tcg_rn = cpu_reg(s, rn); |
3210 |
|
3211 |
if (op) {
|
3212 |
tcg_y = new_tmp_a64(s); |
3213 |
tcg_gen_not_i64(tcg_y, cpu_reg(s, rm)); |
3214 |
} else {
|
3215 |
tcg_y = cpu_reg(s, rm); |
3216 |
} |
3217 |
|
3218 |
if (setflags) {
|
3219 |
gen_adc_CC(sf, tcg_rd, tcg_rn, tcg_y); |
3220 |
} else {
|
3221 |
gen_adc(sf, tcg_rd, tcg_rn, tcg_y); |
3222 |
} |
3223 |
} |
3224 |
|
3225 |
/* C3.5.4 - C3.5.5 Conditional compare (immediate / register)
|
3226 |
* 31 30 29 28 27 26 25 24 23 22 21 20 16 15 12 11 10 9 5 4 3 0
|
3227 |
* +--+--+--+------------------------+--------+------+----+--+------+--+-----+
|
3228 |
* |sf|op| S| 1 1 0 1 0 0 1 0 |imm5/rm | cond |i/r |o2| Rn |o3|nzcv |
|
3229 |
* +--+--+--+------------------------+--------+------+----+--+------+--+-----+
|
3230 |
* [1] y [0] [0]
|
3231 |
*/
|
3232 |
static void disas_cc(DisasContext *s, uint32_t insn) |
3233 |
{ |
3234 |
unsigned int sf, op, y, cond, rn, nzcv, is_imm; |
3235 |
int label_continue = -1; |
3236 |
TCGv_i64 tcg_tmp, tcg_y, tcg_rn; |
3237 |
|
3238 |
if (!extract32(insn, 29, 1)) { |
3239 |
unallocated_encoding(s); |
3240 |
return;
|
3241 |
} |
3242 |
if (insn & (1 << 10 | 1 << 4)) { |
3243 |
unallocated_encoding(s); |
3244 |
return;
|
3245 |
} |
3246 |
sf = extract32(insn, 31, 1); |
3247 |
op = extract32(insn, 30, 1); |
3248 |
is_imm = extract32(insn, 11, 1); |
3249 |
y = extract32(insn, 16, 5); /* y = rm (reg) or imm5 (imm) */ |
3250 |
cond = extract32(insn, 12, 4); |
3251 |
rn = extract32(insn, 5, 5); |
3252 |
nzcv = extract32(insn, 0, 4); |
3253 |
|
3254 |
if (cond < 0x0e) { /* not always */ |
3255 |
int label_match = gen_new_label();
|
3256 |
label_continue = gen_new_label(); |
3257 |
arm_gen_test_cc(cond, label_match); |
3258 |
/* nomatch: */
|
3259 |
tcg_tmp = tcg_temp_new_i64(); |
3260 |
tcg_gen_movi_i64(tcg_tmp, nzcv << 28);
|
3261 |
gen_set_nzcv(tcg_tmp); |
3262 |
tcg_temp_free_i64(tcg_tmp); |
3263 |
tcg_gen_br(label_continue); |
3264 |
gen_set_label(label_match); |
3265 |
} |
3266 |
/* match, or condition is always */
|
3267 |
if (is_imm) {
|
3268 |
tcg_y = new_tmp_a64(s); |
3269 |
tcg_gen_movi_i64(tcg_y, y); |
3270 |
} else {
|
3271 |
tcg_y = cpu_reg(s, y); |
3272 |
} |
3273 |
tcg_rn = cpu_reg(s, rn); |
3274 |
|
3275 |
tcg_tmp = tcg_temp_new_i64(); |
3276 |
if (op) {
|
3277 |
gen_sub_CC(sf, tcg_tmp, tcg_rn, tcg_y); |
3278 |
} else {
|
3279 |
gen_add_CC(sf, tcg_tmp, tcg_rn, tcg_y); |
3280 |
} |
3281 |
tcg_temp_free_i64(tcg_tmp); |
3282 |
|
3283 |
if (cond < 0x0e) { /* continue */ |
3284 |
gen_set_label(label_continue); |
3285 |
} |
3286 |
} |
3287 |
|
3288 |
/* C3.5.6 Conditional select
|
3289 |
* 31 30 29 28 21 20 16 15 12 11 10 9 5 4 0
|
3290 |
* +----+----+---+-----------------+------+------+-----+------+------+
|
3291 |
* | sf | op | S | 1 1 0 1 0 1 0 0 | Rm | cond | op2 | Rn | Rd |
|
3292 |
* +----+----+---+-----------------+------+------+-----+------+------+
|
3293 |
*/
|
3294 |
static void disas_cond_select(DisasContext *s, uint32_t insn) |
3295 |
{ |
3296 |
unsigned int sf, else_inv, rm, cond, else_inc, rn, rd; |
3297 |
TCGv_i64 tcg_rd, tcg_src; |
3298 |
|
3299 |
if (extract32(insn, 29, 1) || extract32(insn, 11, 1)) { |
3300 |
/* S == 1 or op2<1> == 1 */
|
3301 |
unallocated_encoding(s); |
3302 |
return;
|
3303 |
} |
3304 |
sf = extract32(insn, 31, 1); |
3305 |
else_inv = extract32(insn, 30, 1); |
3306 |
rm = extract32(insn, 16, 5); |
3307 |
cond = extract32(insn, 12, 4); |
3308 |
else_inc = extract32(insn, 10, 1); |
3309 |
rn = extract32(insn, 5, 5); |
3310 |
rd = extract32(insn, 0, 5); |
3311 |
|
3312 |
if (rd == 31) { |
3313 |
/* silly no-op write; until we use movcond we must special-case
|
3314 |
* this to avoid a dead temporary across basic blocks.
|
3315 |
*/
|
3316 |
return;
|
3317 |
} |
3318 |
|
3319 |
tcg_rd = cpu_reg(s, rd); |
3320 |
|
3321 |
if (cond >= 0x0e) { /* condition "always" */ |
3322 |
tcg_src = read_cpu_reg(s, rn, sf); |
3323 |
tcg_gen_mov_i64(tcg_rd, tcg_src); |
3324 |
} else {
|
3325 |
/* OPTME: we could use movcond here, at the cost of duplicating
|
3326 |
* a lot of the arm_gen_test_cc() logic.
|
3327 |
*/
|
3328 |
int label_match = gen_new_label();
|
3329 |
int label_continue = gen_new_label();
|
3330 |
|
3331 |
arm_gen_test_cc(cond, label_match); |
3332 |
/* nomatch: */
|
3333 |
tcg_src = cpu_reg(s, rm); |
3334 |
|
3335 |
if (else_inv && else_inc) {
|
3336 |
tcg_gen_neg_i64(tcg_rd, tcg_src); |
3337 |
} else if (else_inv) { |
3338 |
tcg_gen_not_i64(tcg_rd, tcg_src); |
3339 |
} else if (else_inc) { |
3340 |
tcg_gen_addi_i64(tcg_rd, tcg_src, 1);
|
3341 |
} else {
|
3342 |
tcg_gen_mov_i64(tcg_rd, tcg_src); |
3343 |
} |
3344 |
if (!sf) {
|
3345 |
tcg_gen_ext32u_i64(tcg_rd, tcg_rd); |
3346 |
} |
3347 |
tcg_gen_br(label_continue); |
3348 |
/* match: */
|
3349 |
gen_set_label(label_match); |
3350 |
tcg_src = read_cpu_reg(s, rn, sf); |
3351 |
tcg_gen_mov_i64(tcg_rd, tcg_src); |
3352 |
/* continue: */
|
3353 |
gen_set_label(label_continue); |
3354 |
} |
3355 |
} |
3356 |
|
3357 |
static void handle_clz(DisasContext *s, unsigned int sf, |
3358 |
unsigned int rn, unsigned int rd) |
3359 |
{ |
3360 |
TCGv_i64 tcg_rd, tcg_rn; |
3361 |
tcg_rd = cpu_reg(s, rd); |
3362 |
tcg_rn = cpu_reg(s, rn); |
3363 |
|
3364 |
if (sf) {
|
3365 |
gen_helper_clz64(tcg_rd, tcg_rn); |
3366 |
} else {
|
3367 |
TCGv_i32 tcg_tmp32 = tcg_temp_new_i32(); |
3368 |
tcg_gen_trunc_i64_i32(tcg_tmp32, tcg_rn); |
3369 |
gen_helper_clz(tcg_tmp32, tcg_tmp32); |
3370 |
tcg_gen_extu_i32_i64(tcg_rd, tcg_tmp32); |
3371 |
tcg_temp_free_i32(tcg_tmp32); |
3372 |
} |
3373 |
} |
3374 |
|
3375 |
static void handle_cls(DisasContext *s, unsigned int sf, |
3376 |
unsigned int rn, unsigned int rd) |
3377 |
{ |
3378 |
TCGv_i64 tcg_rd, tcg_rn; |
3379 |
tcg_rd = cpu_reg(s, rd); |
3380 |
tcg_rn = cpu_reg(s, rn); |
3381 |
|
3382 |
if (sf) {
|
3383 |
gen_helper_cls64(tcg_rd, tcg_rn); |
3384 |
} else {
|
3385 |
TCGv_i32 tcg_tmp32 = tcg_temp_new_i32(); |
3386 |
tcg_gen_trunc_i64_i32(tcg_tmp32, tcg_rn); |
3387 |
gen_helper_cls32(tcg_tmp32, tcg_tmp32); |
3388 |
tcg_gen_extu_i32_i64(tcg_rd, tcg_tmp32); |
3389 |
tcg_temp_free_i32(tcg_tmp32); |
3390 |
} |
3391 |
} |
3392 |
|
3393 |
static void handle_rbit(DisasContext *s, unsigned int sf, |
3394 |
unsigned int rn, unsigned int rd) |
3395 |
{ |
3396 |
TCGv_i64 tcg_rd, tcg_rn; |
3397 |
tcg_rd = cpu_reg(s, rd); |
3398 |
tcg_rn = cpu_reg(s, rn); |
3399 |
|
3400 |
if (sf) {
|
3401 |
gen_helper_rbit64(tcg_rd, tcg_rn); |
3402 |
} else {
|
3403 |
TCGv_i32 tcg_tmp32 = tcg_temp_new_i32(); |
3404 |
tcg_gen_trunc_i64_i32(tcg_tmp32, tcg_rn); |
3405 |
gen_helper_rbit(tcg_tmp32, tcg_tmp32); |
3406 |
tcg_gen_extu_i32_i64(tcg_rd, tcg_tmp32); |
3407 |
tcg_temp_free_i32(tcg_tmp32); |
3408 |
} |
3409 |
} |
3410 |
|
3411 |
/* C5.6.149 REV with sf==1, opcode==3 ("REV64") */
|
3412 |
static void handle_rev64(DisasContext *s, unsigned int sf, |
3413 |
unsigned int rn, unsigned int rd) |
3414 |
{ |
3415 |
if (!sf) {
|
3416 |
unallocated_encoding(s); |
3417 |
return;
|
3418 |
} |
3419 |
tcg_gen_bswap64_i64(cpu_reg(s, rd), cpu_reg(s, rn)); |
3420 |
} |
3421 |
|
3422 |
/* C5.6.149 REV with sf==0, opcode==2
|
3423 |
* C5.6.151 REV32 (sf==1, opcode==2)
|
3424 |
*/
|
3425 |
static void handle_rev32(DisasContext *s, unsigned int sf, |
3426 |
unsigned int rn, unsigned int rd) |
3427 |
{ |
3428 |
TCGv_i64 tcg_rd = cpu_reg(s, rd); |
3429 |
|
3430 |
if (sf) {
|
3431 |
TCGv_i64 tcg_tmp = tcg_temp_new_i64(); |
3432 |
TCGv_i64 tcg_rn = read_cpu_reg(s, rn, sf); |
3433 |
|
3434 |
/* bswap32_i64 requires zero high word */
|
3435 |
tcg_gen_ext32u_i64(tcg_tmp, tcg_rn); |
3436 |
tcg_gen_bswap32_i64(tcg_rd, tcg_tmp); |
3437 |
tcg_gen_shri_i64(tcg_tmp, tcg_rn, 32);
|
3438 |
tcg_gen_bswap32_i64(tcg_tmp, tcg_tmp); |
3439 |
tcg_gen_concat32_i64(tcg_rd, tcg_rd, tcg_tmp); |
3440 |
|
3441 |
tcg_temp_free_i64(tcg_tmp); |
3442 |
} else {
|
3443 |
tcg_gen_ext32u_i64(tcg_rd, cpu_reg(s, rn)); |
3444 |
tcg_gen_bswap32_i64(tcg_rd, tcg_rd); |
3445 |
} |
3446 |
} |
3447 |
|
3448 |
/* C5.6.150 REV16 (opcode==1) */
|
3449 |
static void handle_rev16(DisasContext *s, unsigned int sf, |
3450 |
unsigned int rn, unsigned int rd) |
3451 |
{ |
3452 |
TCGv_i64 tcg_rd = cpu_reg(s, rd); |
3453 |
TCGv_i64 tcg_tmp = tcg_temp_new_i64(); |
3454 |
TCGv_i64 tcg_rn = read_cpu_reg(s, rn, sf); |
3455 |
|
3456 |
tcg_gen_andi_i64(tcg_tmp, tcg_rn, 0xffff);
|
3457 |
tcg_gen_bswap16_i64(tcg_rd, tcg_tmp); |
3458 |
|
3459 |
tcg_gen_shri_i64(tcg_tmp, tcg_rn, 16);
|
3460 |
tcg_gen_andi_i64(tcg_tmp, tcg_tmp, 0xffff);
|
3461 |
tcg_gen_bswap16_i64(tcg_tmp, tcg_tmp); |
3462 |
tcg_gen_deposit_i64(tcg_rd, tcg_rd, tcg_tmp, 16, 16); |
3463 |
|
3464 |
if (sf) {
|
3465 |
tcg_gen_shri_i64(tcg_tmp, tcg_rn, 32);
|
3466 |
tcg_gen_andi_i64(tcg_tmp, tcg_tmp, 0xffff);
|
3467 |
tcg_gen_bswap16_i64(tcg_tmp, tcg_tmp); |
3468 |
tcg_gen_deposit_i64(tcg_rd, tcg_rd, tcg_tmp, 32, 16); |
3469 |
|
3470 |
tcg_gen_shri_i64(tcg_tmp, tcg_rn, 48);
|
3471 |
tcg_gen_bswap16_i64(tcg_tmp, tcg_tmp); |
3472 |
tcg_gen_deposit_i64(tcg_rd, tcg_rd, tcg_tmp, 48, 16); |
3473 |
} |
3474 |
|
3475 |
tcg_temp_free_i64(tcg_tmp); |
3476 |
} |
3477 |
|
3478 |
/* C3.5.7 Data-processing (1 source)
|
3479 |
* 31 30 29 28 21 20 16 15 10 9 5 4 0
|
3480 |
* +----+---+---+-----------------+---------+--------+------+------+
|
3481 |
* | sf | 1 | S | 1 1 0 1 0 1 1 0 | opcode2 | opcode | Rn | Rd |
|
3482 |
* +----+---+---+-----------------+---------+--------+------+------+
|
3483 |
*/
|
3484 |
static void disas_data_proc_1src(DisasContext *s, uint32_t insn) |
3485 |
{ |
3486 |
unsigned int sf, opcode, rn, rd; |
3487 |
|
3488 |
if (extract32(insn, 29, 1) || extract32(insn, 16, 5)) { |
3489 |
unallocated_encoding(s); |
3490 |
return;
|
3491 |
} |
3492 |
|
3493 |
sf = extract32(insn, 31, 1); |
3494 |
opcode = extract32(insn, 10, 6); |
3495 |
rn = extract32(insn, 5, 5); |
3496 |
rd = extract32(insn, 0, 5); |
3497 |
|
3498 |
switch (opcode) {
|
3499 |
case 0: /* RBIT */ |
3500 |
handle_rbit(s, sf, rn, rd); |
3501 |
break;
|
3502 |
case 1: /* REV16 */ |
3503 |
handle_rev16(s, sf, rn, rd); |
3504 |
break;
|
3505 |
case 2: /* REV32 */ |
3506 |
handle_rev32(s, sf, rn, rd); |
3507 |
break;
|
3508 |
case 3: /* REV64 */ |
3509 |
handle_rev64(s, sf, rn, rd); |
3510 |
break;
|
3511 |
case 4: /* CLZ */ |
3512 |
handle_clz(s, sf, rn, rd); |
3513 |
break;
|
3514 |
case 5: /* CLS */ |
3515 |
handle_cls(s, sf, rn, rd); |
3516 |
break;
|
3517 |
} |
3518 |
} |
3519 |
|
3520 |
static void handle_div(DisasContext *s, bool is_signed, unsigned int sf, |
3521 |
unsigned int rm, unsigned int rn, unsigned int rd) |
3522 |
{ |
3523 |
TCGv_i64 tcg_n, tcg_m, tcg_rd; |
3524 |
tcg_rd = cpu_reg(s, rd); |
3525 |
|
3526 |
if (!sf && is_signed) {
|
3527 |
tcg_n = new_tmp_a64(s); |
3528 |
tcg_m = new_tmp_a64(s); |
3529 |
tcg_gen_ext32s_i64(tcg_n, cpu_reg(s, rn)); |
3530 |
tcg_gen_ext32s_i64(tcg_m, cpu_reg(s, rm)); |
3531 |
} else {
|
3532 |
tcg_n = read_cpu_reg(s, rn, sf); |
3533 |
tcg_m = read_cpu_reg(s, rm, sf); |
3534 |
} |
3535 |
|
3536 |
if (is_signed) {
|
3537 |
gen_helper_sdiv64(tcg_rd, tcg_n, tcg_m); |
3538 |
} else {
|
3539 |
gen_helper_udiv64(tcg_rd, tcg_n, tcg_m); |
3540 |
} |
3541 |
|
3542 |
if (!sf) { /* zero extend final result */ |
3543 |
tcg_gen_ext32u_i64(tcg_rd, tcg_rd); |
3544 |
} |
3545 |
} |
3546 |
|
3547 |
/* C5.6.115 LSLV, C5.6.118 LSRV, C5.6.17 ASRV, C5.6.154 RORV */
|
3548 |
static void handle_shift_reg(DisasContext *s, |
3549 |
enum a64_shift_type shift_type, unsigned int sf, |
3550 |
unsigned int rm, unsigned int rn, unsigned int rd) |
3551 |
{ |
3552 |
TCGv_i64 tcg_shift = tcg_temp_new_i64(); |
3553 |
TCGv_i64 tcg_rd = cpu_reg(s, rd); |
3554 |
TCGv_i64 tcg_rn = read_cpu_reg(s, rn, sf); |
3555 |
|
3556 |
tcg_gen_andi_i64(tcg_shift, cpu_reg(s, rm), sf ? 63 : 31); |
3557 |
shift_reg(tcg_rd, tcg_rn, sf, shift_type, tcg_shift); |
3558 |
tcg_temp_free_i64(tcg_shift); |
3559 |
} |
3560 |
|
3561 |
/* C3.5.8 Data-processing (2 source)
|
3562 |
* 31 30 29 28 21 20 16 15 10 9 5 4 0
|
3563 |
* +----+---+---+-----------------+------+--------+------+------+
|
3564 |
* | sf | 0 | S | 1 1 0 1 0 1 1 0 | Rm | opcode | Rn | Rd |
|
3565 |
* +----+---+---+-----------------+------+--------+------+------+
|
3566 |
*/
|
3567 |
static void disas_data_proc_2src(DisasContext *s, uint32_t insn) |
3568 |
{ |
3569 |
unsigned int sf, rm, opcode, rn, rd; |
3570 |
sf = extract32(insn, 31, 1); |
3571 |
rm = extract32(insn, 16, 5); |
3572 |
opcode = extract32(insn, 10, 6); |
3573 |
rn = extract32(insn, 5, 5); |
3574 |
rd = extract32(insn, 0, 5); |
3575 |
|
3576 |
if (extract32(insn, 29, 1)) { |
3577 |
unallocated_encoding(s); |
3578 |
return;
|
3579 |
} |
3580 |
|
3581 |
switch (opcode) {
|
3582 |
case 2: /* UDIV */ |
3583 |
handle_div(s, false, sf, rm, rn, rd);
|
3584 |
break;
|
3585 |
case 3: /* SDIV */ |
3586 |
handle_div(s, true, sf, rm, rn, rd);
|
3587 |
break;
|
3588 |
case 8: /* LSLV */ |
3589 |
handle_shift_reg(s, A64_SHIFT_TYPE_LSL, sf, rm, rn, rd); |
3590 |
break;
|
3591 |
case 9: /* LSRV */ |
3592 |
handle_shift_reg(s, A64_SHIFT_TYPE_LSR, sf, rm, rn, rd); |
3593 |
break;
|
3594 |
case 10: /* ASRV */ |
3595 |
handle_shift_reg(s, A64_SHIFT_TYPE_ASR, sf, rm, rn, rd); |
3596 |
break;
|
3597 |
case 11: /* RORV */ |
3598 |
handle_shift_reg(s, A64_SHIFT_TYPE_ROR, sf, rm, rn, rd); |
3599 |
break;
|
3600 |
case 16: |
3601 |
case 17: |
3602 |
case 18: |
3603 |
case 19: |
3604 |
case 20: |
3605 |
case 21: |
3606 |
case 22: |
3607 |
case 23: /* CRC32 */ |
3608 |
unsupported_encoding(s, insn); |
3609 |
break;
|
3610 |
default:
|
3611 |
unallocated_encoding(s); |
3612 |
break;
|
3613 |
} |
3614 |
} |
3615 |
|
3616 |
/* C3.5 Data processing - register */
|
3617 |
static void disas_data_proc_reg(DisasContext *s, uint32_t insn) |
3618 |
{ |
3619 |
switch (extract32(insn, 24, 5)) { |
3620 |
case 0x0a: /* Logical (shifted register) */ |
3621 |
disas_logic_reg(s, insn); |
3622 |
break;
|
3623 |
case 0x0b: /* Add/subtract */ |
3624 |
if (insn & (1 << 21)) { /* (extended register) */ |
3625 |
disas_add_sub_ext_reg(s, insn); |
3626 |
} else {
|
3627 |
disas_add_sub_reg(s, insn); |
3628 |
} |
3629 |
break;
|
3630 |
case 0x1b: /* Data-processing (3 source) */ |
3631 |
disas_data_proc_3src(s, insn); |
3632 |
break;
|
3633 |
case 0x1a: |
3634 |
switch (extract32(insn, 21, 3)) { |
3635 |
case 0x0: /* Add/subtract (with carry) */ |
3636 |
disas_adc_sbc(s, insn); |
3637 |
break;
|
3638 |
case 0x2: /* Conditional compare */ |
3639 |
disas_cc(s, insn); /* both imm and reg forms */
|
3640 |
break;
|
3641 |
case 0x4: /* Conditional select */ |
3642 |
disas_cond_select(s, insn); |
3643 |
break;
|
3644 |
case 0x6: /* Data-processing */ |
3645 |
if (insn & (1 << 30)) { /* (1 source) */ |
3646 |
disas_data_proc_1src(s, insn); |
3647 |
} else { /* (2 source) */ |
3648 |
disas_data_proc_2src(s, insn); |
3649 |
} |
3650 |
break;
|
3651 |
default:
|
3652 |
unallocated_encoding(s); |
3653 |
break;
|
3654 |
} |
3655 |
break;
|
3656 |
default:
|
3657 |
unallocated_encoding(s); |
3658 |
break;
|
3659 |
} |
3660 |
} |
3661 |
|
3662 |
static void handle_fp_compare(DisasContext *s, bool is_double, |
3663 |
unsigned int rn, unsigned int rm, |
3664 |
bool cmp_with_zero, bool signal_all_nans) |
3665 |
{ |
3666 |
TCGv_i64 tcg_flags = tcg_temp_new_i64(); |
3667 |
TCGv_ptr fpst = get_fpstatus_ptr(); |
3668 |
|
3669 |
if (is_double) {
|
3670 |
TCGv_i64 tcg_vn, tcg_vm; |
3671 |
|
3672 |
tcg_vn = read_fp_dreg(s, rn); |
3673 |
if (cmp_with_zero) {
|
3674 |
tcg_vm = tcg_const_i64(0);
|
3675 |
} else {
|
3676 |
tcg_vm = read_fp_dreg(s, rm); |
3677 |
} |
3678 |
if (signal_all_nans) {
|
3679 |
gen_helper_vfp_cmped_a64(tcg_flags, tcg_vn, tcg_vm, fpst); |
3680 |
} else {
|
3681 |
gen_helper_vfp_cmpd_a64(tcg_flags, tcg_vn, tcg_vm, fpst); |
3682 |
} |
3683 |
tcg_temp_free_i64(tcg_vn); |
3684 |
tcg_temp_free_i64(tcg_vm); |
3685 |
} else {
|
3686 |
TCGv_i32 tcg_vn, tcg_vm; |
3687 |
|
3688 |
tcg_vn = read_fp_sreg(s, rn); |
3689 |
if (cmp_with_zero) {
|
3690 |
tcg_vm = tcg_const_i32(0);
|
3691 |
} else {
|
3692 |
tcg_vm = read_fp_sreg(s, rm); |
3693 |
} |
3694 |
if (signal_all_nans) {
|
3695 |
gen_helper_vfp_cmpes_a64(tcg_flags, tcg_vn, tcg_vm, fpst); |
3696 |
} else {
|
3697 |
gen_helper_vfp_cmps_a64(tcg_flags, tcg_vn, tcg_vm, fpst); |
3698 |
} |
3699 |
tcg_temp_free_i32(tcg_vn); |
3700 |
tcg_temp_free_i32(tcg_vm); |
3701 |
} |
3702 |
|
3703 |
tcg_temp_free_ptr(fpst); |
3704 |
|
3705 |
gen_set_nzcv(tcg_flags); |
3706 |
|
3707 |
tcg_temp_free_i64(tcg_flags); |
3708 |
} |
3709 |
|
3710 |
/* C3.6.22 Floating point compare
|
3711 |
* 31 30 29 28 24 23 22 21 20 16 15 14 13 10 9 5 4 0
|
3712 |
* +---+---+---+-----------+------+---+------+-----+---------+------+-------+
|
3713 |
* | M | 0 | S | 1 1 1 1 0 | type | 1 | Rm | op | 1 0 0 0 | Rn | op2 |
|
3714 |
* +---+---+---+-----------+------+---+------+-----+---------+------+-------+
|
3715 |
*/
|
3716 |
static void disas_fp_compare(DisasContext *s, uint32_t insn) |
3717 |
{ |
3718 |
unsigned int mos, type, rm, op, rn, opc, op2r; |
3719 |
|
3720 |
mos = extract32(insn, 29, 3); |
3721 |
type = extract32(insn, 22, 2); /* 0 = single, 1 = double */ |
3722 |
rm = extract32(insn, 16, 5); |
3723 |
op = extract32(insn, 14, 2); |
3724 |
rn = extract32(insn, 5, 5); |
3725 |
opc = extract32(insn, 3, 2); |
3726 |
op2r = extract32(insn, 0, 3); |
3727 |
|
3728 |
if (mos || op || op2r || type > 1) { |
3729 |
unallocated_encoding(s); |
3730 |
return;
|
3731 |
} |
3732 |
|
3733 |
handle_fp_compare(s, type, rn, rm, opc & 1, opc & 2); |
3734 |
} |
3735 |
|
3736 |
/* C3.6.23 Floating point conditional compare
|
3737 |
* 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 3 0
|
3738 |
* +---+---+---+-----------+------+---+------+------+-----+------+----+------+
|
3739 |
* | M | 0 | S | 1 1 1 1 0 | type | 1 | Rm | cond | 0 1 | Rn | op | nzcv |
|
3740 |
* +---+---+---+-----------+------+---+------+------+-----+------+----+------+
|
3741 |
*/
|
3742 |
static void disas_fp_ccomp(DisasContext *s, uint32_t insn) |
3743 |
{ |
3744 |
unsigned int mos, type, rm, cond, rn, op, nzcv; |
3745 |
TCGv_i64 tcg_flags; |
3746 |
int label_continue = -1; |
3747 |
|
3748 |
mos = extract32(insn, 29, 3); |
3749 |
type = extract32(insn, 22, 2); /* 0 = single, 1 = double */ |
3750 |
rm = extract32(insn, 16, 5); |
3751 |
cond = extract32(insn, 12, 4); |
3752 |
rn = extract32(insn, 5, 5); |
3753 |
op = extract32(insn, 4, 1); |
3754 |
nzcv = extract32(insn, 0, 4); |
3755 |
|
3756 |
if (mos || type > 1) { |
3757 |
unallocated_encoding(s); |
3758 |
return;
|
3759 |
} |
3760 |
|
3761 |
if (cond < 0x0e) { /* not always */ |
3762 |
int label_match = gen_new_label();
|
3763 |
label_continue = gen_new_label(); |
3764 |
arm_gen_test_cc(cond, label_match); |
3765 |
/* nomatch: */
|
3766 |
tcg_flags = tcg_const_i64(nzcv << 28);
|
3767 |
gen_set_nzcv(tcg_flags); |
3768 |
tcg_temp_free_i64(tcg_flags); |
3769 |
tcg_gen_br(label_continue); |
3770 |
gen_set_label(label_match); |
3771 |
} |
3772 |
|
3773 |
handle_fp_compare(s, type, rn, rm, false, op);
|
3774 |
|
3775 |
if (cond < 0x0e) { |
3776 |
gen_set_label(label_continue); |
3777 |
} |
3778 |
} |
3779 |
|
3780 |
/* copy src FP register to dst FP register; type specifies single or double */
|
3781 |
static void gen_mov_fp2fp(DisasContext *s, int type, int dst, int src) |
3782 |
{ |
3783 |
if (type) {
|
3784 |
TCGv_i64 v = read_fp_dreg(s, src); |
3785 |
write_fp_dreg(s, dst, v); |
3786 |
tcg_temp_free_i64(v); |
3787 |
} else {
|
3788 |
TCGv_i32 v = read_fp_sreg(s, src); |
3789 |
write_fp_sreg(s, dst, v); |
3790 |
tcg_temp_free_i32(v); |
3791 |
} |
3792 |
} |
3793 |
|
3794 |
/* C3.6.24 Floating point conditional select
|
3795 |
* 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0
|
3796 |
* +---+---+---+-----------+------+---+------+------+-----+------+------+
|
3797 |
* | M | 0 | S | 1 1 1 1 0 | type | 1 | Rm | cond | 1 1 | Rn | Rd |
|
3798 |
* +---+---+---+-----------+------+---+------+------+-----+------+------+
|
3799 |
*/
|
3800 |
static void disas_fp_csel(DisasContext *s, uint32_t insn) |
3801 |
{ |
3802 |
unsigned int mos, type, rm, cond, rn, rd; |
3803 |
int label_continue = -1; |
3804 |
|
3805 |
mos = extract32(insn, 29, 3); |
3806 |
type = extract32(insn, 22, 2); /* 0 = single, 1 = double */ |
3807 |
rm = extract32(insn, 16, 5); |
3808 |
cond = extract32(insn, 12, 4); |
3809 |
rn = extract32(insn, 5, 5); |
3810 |
rd = extract32(insn, 0, 5); |
3811 |
|
3812 |
if (mos || type > 1) { |
3813 |
unallocated_encoding(s); |
3814 |
return;
|
3815 |
} |
3816 |
|
3817 |
if (cond < 0x0e) { /* not always */ |
3818 |
int label_match = gen_new_label();
|
3819 |
label_continue = gen_new_label(); |
3820 |
arm_gen_test_cc(cond, label_match); |
3821 |
/* nomatch: */
|
3822 |
gen_mov_fp2fp(s, type, rd, rm); |
3823 |
tcg_gen_br(label_continue); |
3824 |
gen_set_label(label_match); |
3825 |
} |
3826 |
|
3827 |
gen_mov_fp2fp(s, type, rd, rn); |
3828 |
|
3829 |
if (cond < 0x0e) { /* continue */ |
3830 |
gen_set_label(label_continue); |
3831 |
} |
3832 |
} |
3833 |
|
3834 |
/* C3.6.25 Floating-point data-processing (1 source) - single precision */
|
3835 |
static void handle_fp_1src_single(DisasContext *s, int opcode, int rd, int rn) |
3836 |
{ |
3837 |
TCGv_ptr fpst; |
3838 |
TCGv_i32 tcg_op; |
3839 |
TCGv_i32 tcg_res; |
3840 |
|
3841 |
fpst = get_fpstatus_ptr(); |
3842 |
tcg_op = read_fp_sreg(s, rn); |
3843 |
tcg_res = tcg_temp_new_i32(); |
3844 |
|
3845 |
switch (opcode) {
|
3846 |
case 0x0: /* FMOV */ |
3847 |
tcg_gen_mov_i32(tcg_res, tcg_op); |
3848 |
break;
|
3849 |
case 0x1: /* FABS */ |
3850 |
gen_helper_vfp_abss(tcg_res, tcg_op); |
3851 |
break;
|
3852 |
case 0x2: /* FNEG */ |
3853 |
gen_helper_vfp_negs(tcg_res, tcg_op); |
3854 |
break;
|
3855 |
case 0x3: /* FSQRT */ |
3856 |
gen_helper_vfp_sqrts(tcg_res, tcg_op, cpu_env); |
3857 |
break;
|
3858 |
case 0x8: /* FRINTN */ |
3859 |
case 0x9: /* FRINTP */ |
3860 |
case 0xa: /* FRINTM */ |
3861 |
case 0xb: /* FRINTZ */ |
3862 |
case 0xc: /* FRINTA */ |
3863 |
{ |
3864 |
TCGv_i32 tcg_rmode = tcg_const_i32(arm_rmode_to_sf(opcode & 7));
|
3865 |
|
3866 |
gen_helper_set_rmode(tcg_rmode, tcg_rmode, cpu_env); |
3867 |
gen_helper_rints(tcg_res, tcg_op, fpst); |
3868 |
|
3869 |
gen_helper_set_rmode(tcg_rmode, tcg_rmode, cpu_env); |
3870 |
tcg_temp_free_i32(tcg_rmode); |
3871 |
break;
|
3872 |
} |
3873 |
case 0xe: /* FRINTX */ |
3874 |
gen_helper_rints_exact(tcg_res, tcg_op, fpst); |
3875 |
break;
|
3876 |
case 0xf: /* FRINTI */ |
3877 |
gen_helper_rints(tcg_res, tcg_op, fpst); |
3878 |
break;
|
3879 |
default:
|
3880 |
abort(); |
3881 |
} |
3882 |
|
3883 |
write_fp_sreg(s, rd, tcg_res); |
3884 |
|
3885 |
tcg_temp_free_ptr(fpst); |
3886 |
tcg_temp_free_i32(tcg_op); |
3887 |
tcg_temp_free_i32(tcg_res); |
3888 |
} |
3889 |
|
3890 |
/* C3.6.25 Floating-point data-processing (1 source) - double precision */
|
3891 |
static void handle_fp_1src_double(DisasContext *s, int opcode, int rd, int rn) |
3892 |
{ |
3893 |
TCGv_ptr fpst; |
3894 |
TCGv_i64 tcg_op; |
3895 |
TCGv_i64 tcg_res; |
3896 |
|
3897 |
fpst = get_fpstatus_ptr(); |
3898 |
tcg_op = read_fp_dreg(s, rn); |
3899 |
tcg_res = tcg_temp_new_i64(); |
3900 |
|
3901 |
switch (opcode) {
|
3902 |
case 0x0: /* FMOV */ |
3903 |
tcg_gen_mov_i64(tcg_res, tcg_op); |
3904 |
break;
|
3905 |
case 0x1: /* FABS */ |
3906 |
gen_helper_vfp_absd(tcg_res, tcg_op); |
3907 |
break;
|
3908 |
case 0x2: /* FNEG */ |
3909 |
gen_helper_vfp_negd(tcg_res, tcg_op); |
3910 |
break;
|
3911 |
case 0x3: /* FSQRT */ |
3912 |
gen_helper_vfp_sqrtd(tcg_res, tcg_op, cpu_env); |
3913 |
break;
|
3914 |
case 0x8: /* FRINTN */ |
3915 |
case 0x9: /* FRINTP */ |
3916 |
case 0xa: /* FRINTM */ |
3917 |
case 0xb: /* FRINTZ */ |
3918 |
case 0xc: /* FRINTA */ |
3919 |
{ |
3920 |
TCGv_i32 tcg_rmode = tcg_const_i32(arm_rmode_to_sf(opcode & 7));
|
3921 |
|
3922 |
gen_helper_set_rmode(tcg_rmode, tcg_rmode, cpu_env); |
3923 |
gen_helper_rintd(tcg_res, tcg_op, fpst); |
3924 |
|
3925 |
gen_helper_set_rmode(tcg_rmode, tcg_rmode, cpu_env); |
3926 |
tcg_temp_free_i32(tcg_rmode); |
3927 |
break;
|
3928 |
} |
3929 |
case 0xe: /* FRINTX */ |
3930 |
gen_helper_rintd_exact(tcg_res, tcg_op, fpst); |
3931 |
break;
|
3932 |
case 0xf: /* FRINTI */ |
3933 |
gen_helper_rintd(tcg_res, tcg_op, fpst); |
3934 |
break;
|
3935 |
default:
|
3936 |
abort(); |
3937 |
} |
3938 |
|
3939 |
write_fp_dreg(s, rd, tcg_res); |
3940 |
|
3941 |
tcg_temp_free_ptr(fpst); |
3942 |
tcg_temp_free_i64(tcg_op); |
3943 |
tcg_temp_free_i64(tcg_res); |
3944 |
} |
3945 |
|
3946 |
static void handle_fp_fcvt(DisasContext *s, int opcode, |
3947 |
int rd, int rn, int dtype, int ntype) |
3948 |
{ |
3949 |
switch (ntype) {
|
3950 |
case 0x0: |
3951 |
{ |
3952 |
TCGv_i32 tcg_rn = read_fp_sreg(s, rn); |
3953 |
if (dtype == 1) { |
3954 |
/* Single to double */
|
3955 |
TCGv_i64 tcg_rd = tcg_temp_new_i64(); |
3956 |
gen_helper_vfp_fcvtds(tcg_rd, tcg_rn, cpu_env); |
3957 |
write_fp_dreg(s, rd, tcg_rd); |
3958 |
tcg_temp_free_i64(tcg_rd); |
3959 |
} else {
|
3960 |
/* Single to half */
|
3961 |
TCGv_i32 tcg_rd = tcg_temp_new_i32(); |
3962 |
gen_helper_vfp_fcvt_f32_to_f16(tcg_rd, tcg_rn, cpu_env); |
3963 |
/* write_fp_sreg is OK here because top half of tcg_rd is zero */
|
3964 |
write_fp_sreg(s, rd, tcg_rd); |
3965 |
tcg_temp_free_i32(tcg_rd); |
3966 |
} |
3967 |
tcg_temp_free_i32(tcg_rn); |
3968 |
break;
|
3969 |
} |
3970 |
case 0x1: |
3971 |
{ |
3972 |
TCGv_i64 tcg_rn = read_fp_dreg(s, rn); |
3973 |
TCGv_i32 tcg_rd = tcg_temp_new_i32(); |
3974 |
if (dtype == 0) { |
3975 |
/* Double to single */
|
3976 |
gen_helper_vfp_fcvtsd(tcg_rd, tcg_rn, cpu_env); |
3977 |
} else {
|
3978 |
/* Double to half */
|
3979 |
gen_helper_vfp_fcvt_f64_to_f16(tcg_rd, tcg_rn, cpu_env); |
3980 |
/* write_fp_sreg is OK here because top half of tcg_rd is zero */
|
3981 |
} |
3982 |
write_fp_sreg(s, rd, tcg_rd); |
3983 |
tcg_temp_free_i32(tcg_rd); |
3984 |
tcg_temp_free_i64(tcg_rn); |
3985 |
break;
|
3986 |
} |
3987 |
case 0x3: |
3988 |
{ |
3989 |
TCGv_i32 tcg_rn = read_fp_sreg(s, rn); |
3990 |
tcg_gen_ext16u_i32(tcg_rn, tcg_rn); |
3991 |
if (dtype == 0) { |
3992 |
/* Half to single */
|
3993 |
TCGv_i32 tcg_rd = tcg_temp_new_i32(); |
3994 |
gen_helper_vfp_fcvt_f16_to_f32(tcg_rd, tcg_rn, cpu_env); |
3995 |
write_fp_sreg(s, rd, tcg_rd); |
3996 |
tcg_temp_free_i32(tcg_rd); |
3997 |
} else {
|
3998 |
/* Half to double */
|
3999 |
TCGv_i64 tcg_rd = tcg_temp_new_i64(); |
4000 |
gen_helper_vfp_fcvt_f16_to_f64(tcg_rd, tcg_rn, cpu_env); |
4001 |
write_fp_dreg(s, rd, tcg_rd); |
4002 |
tcg_temp_free_i64(tcg_rd); |
4003 |
} |
4004 |
tcg_temp_free_i32(tcg_rn); |
4005 |
break;
|
4006 |
} |
4007 |
default:
|
4008 |
abort(); |
4009 |
} |
4010 |
} |
4011 |
|
4012 |
/* C3.6.25 Floating point data-processing (1 source)
|
4013 |
* 31 30 29 28 24 23 22 21 20 15 14 10 9 5 4 0
|
4014 |
* +---+---+---+-----------+------+---+--------+-----------+------+------+
|
4015 |
* | M | 0 | S | 1 1 1 1 0 | type | 1 | opcode | 1 0 0 0 0 | Rn | Rd |
|
4016 |
* +---+---+---+-----------+------+---+--------+-----------+------+------+
|
4017 |
*/
|
4018 |
static void disas_fp_1src(DisasContext *s, uint32_t insn) |
4019 |
{ |
4020 |
int type = extract32(insn, 22, 2); |
4021 |
int opcode = extract32(insn, 15, 6); |
4022 |
int rn = extract32(insn, 5, 5); |
4023 |
int rd = extract32(insn, 0, 5); |
4024 |
|
4025 |
switch (opcode) {
|
4026 |
case 0x4: case 0x5: case 0x7: |
4027 |
{ |
4028 |
/* FCVT between half, single and double precision */
|
4029 |
int dtype = extract32(opcode, 0, 2); |
4030 |
if (type == 2 || dtype == type) { |
4031 |
unallocated_encoding(s); |
4032 |
return;
|
4033 |
} |
4034 |
handle_fp_fcvt(s, opcode, rd, rn, dtype, type); |
4035 |
break;
|
4036 |
} |
4037 |
case 0x0 ... 0x3: |
4038 |
case 0x8 ... 0xc: |
4039 |
case 0xe ... 0xf: |
4040 |
/* 32-to-32 and 64-to-64 ops */
|
4041 |
switch (type) {
|
4042 |
case 0: |
4043 |
handle_fp_1src_single(s, opcode, rd, rn); |
4044 |
break;
|
4045 |
case 1: |
4046 |
handle_fp_1src_double(s, opcode, rd, rn); |
4047 |
break;
|
4048 |
default:
|
4049 |
unallocated_encoding(s); |
4050 |
} |
4051 |
break;
|
4052 |
default:
|
4053 |
unallocated_encoding(s); |
4054 |
break;
|
4055 |
} |
4056 |
} |
4057 |
|
4058 |
/* C3.6.26 Floating-point data-processing (2 source) - single precision */
|
4059 |
static void handle_fp_2src_single(DisasContext *s, int opcode, |
4060 |
int rd, int rn, int rm) |
4061 |
{ |
4062 |
TCGv_i32 tcg_op1; |
4063 |
TCGv_i32 tcg_op2; |
4064 |
TCGv_i32 tcg_res; |
4065 |
TCGv_ptr fpst; |
4066 |
|
4067 |
tcg_res = tcg_temp_new_i32(); |
4068 |
fpst = get_fpstatus_ptr(); |
4069 |
tcg_op1 = read_fp_sreg(s, rn); |
4070 |
tcg_op2 = read_fp_sreg(s, rm); |
4071 |
|
4072 |
switch (opcode) {
|
4073 |
case 0x0: /* FMUL */ |
4074 |
gen_helper_vfp_muls(tcg_res, tcg_op1, tcg_op2, fpst); |
4075 |
break;
|
4076 |
case 0x1: /* FDIV */ |
4077 |
gen_helper_vfp_divs(tcg_res, tcg_op1, tcg_op2, fpst); |
4078 |
break;
|
4079 |
case 0x2: /* FADD */ |
4080 |
gen_helper_vfp_adds(tcg_res, tcg_op1, tcg_op2, fpst); |
4081 |
break;
|
4082 |
case 0x3: /* FSUB */ |
4083 |
gen_helper_vfp_subs(tcg_res, tcg_op1, tcg_op2, fpst); |
4084 |
break;
|
4085 |
case 0x4: /* FMAX */ |
4086 |
gen_helper_vfp_maxs(tcg_res, tcg_op1, tcg_op2, fpst); |
4087 |
break;
|
4088 |
case 0x5: /* FMIN */ |
4089 |
gen_helper_vfp_mins(tcg_res, tcg_op1, tcg_op2, fpst); |
4090 |
break;
|
4091 |
case 0x6: /* FMAXNM */ |
4092 |
gen_helper_vfp_maxnums(tcg_res, tcg_op1, tcg_op2, fpst); |
4093 |
break;
|
4094 |
case 0x7: /* FMINNM */ |
4095 |
gen_helper_vfp_minnums(tcg_res, tcg_op1, tcg_op2, fpst); |
4096 |
break;
|
4097 |
case 0x8: /* FNMUL */ |
4098 |
gen_helper_vfp_muls(tcg_res, tcg_op1, tcg_op2, fpst); |
4099 |
gen_helper_vfp_negs(tcg_res, tcg_res); |
4100 |
break;
|
4101 |
} |
4102 |
|
4103 |
write_fp_sreg(s, rd, tcg_res); |
4104 |
|
4105 |
tcg_temp_free_ptr(fpst); |
4106 |
tcg_temp_free_i32(tcg_op1); |
4107 |
tcg_temp_free_i32(tcg_op2); |
4108 |
tcg_temp_free_i32(tcg_res); |
4109 |
} |
4110 |
|
4111 |
/* C3.6.26 Floating-point data-processing (2 source) - double precision */
|
4112 |
static void handle_fp_2src_double(DisasContext *s, int opcode, |
4113 |
int rd, int rn, int rm) |
4114 |
{ |
4115 |
TCGv_i64 tcg_op1; |
4116 |
TCGv_i64 tcg_op2; |
4117 |
TCGv_i64 tcg_res; |
4118 |
TCGv_ptr fpst; |
4119 |
|
4120 |
tcg_res = tcg_temp_new_i64(); |
4121 |
fpst = get_fpstatus_ptr(); |
4122 |
tcg_op1 = read_fp_dreg(s, rn); |
4123 |
tcg_op2 = read_fp_dreg(s, rm); |
4124 |
|
4125 |
switch (opcode) {
|
4126 |
case 0x0: /* FMUL */ |
4127 |
gen_helper_vfp_muld(tcg_res, tcg_op1, tcg_op2, fpst); |
4128 |
break;
|
4129 |
case 0x1: /* FDIV */ |
4130 |
gen_helper_vfp_divd(tcg_res, tcg_op1, tcg_op2, fpst); |
4131 |
break;
|
4132 |
case 0x2: /* FADD */ |
4133 |
gen_helper_vfp_addd(tcg_res, tcg_op1, tcg_op2, fpst); |
4134 |
break;
|
4135 |
case 0x3: /* FSUB */ |
4136 |
gen_helper_vfp_subd(tcg_res, tcg_op1, tcg_op2, fpst); |
4137 |
break;
|
4138 |
case 0x4: /* FMAX */ |
4139 |
gen_helper_vfp_maxd(tcg_res, tcg_op1, tcg_op2, fpst); |
4140 |
break;
|
4141 |
case 0x5: /* FMIN */ |
4142 |
gen_helper_vfp_mind(tcg_res, tcg_op1, tcg_op2, fpst); |
4143 |
break;
|
4144 |
case 0x6: /* FMAXNM */ |
4145 |
gen_helper_vfp_maxnumd(tcg_res, tcg_op1, tcg_op2, fpst); |
4146 |
break;
|
4147 |
case 0x7: /* FMINNM */ |
4148 |
gen_helper_vfp_minnumd(tcg_res, tcg_op1, tcg_op2, fpst); |
4149 |
break;
|
4150 |
case 0x8: /* FNMUL */ |
4151 |
gen_helper_vfp_muld(tcg_res, tcg_op1, tcg_op2, fpst); |
4152 |
gen_helper_vfp_negd(tcg_res, tcg_res); |
4153 |
break;
|
4154 |
} |
4155 |
|
4156 |
write_fp_dreg(s, rd, tcg_res); |
4157 |
|
4158 |
tcg_temp_free_ptr(fpst); |
4159 |
tcg_temp_free_i64(tcg_op1); |
4160 |
tcg_temp_free_i64(tcg_op2); |
4161 |
tcg_temp_free_i64(tcg_res); |
4162 |
} |
4163 |
|
4164 |
/* C3.6.26 Floating point data-processing (2 source)
|
4165 |
* 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0
|
4166 |
* +---+---+---+-----------+------+---+------+--------+-----+------+------+
|
4167 |
* | M | 0 | S | 1 1 1 1 0 | type | 1 | Rm | opcode | 1 0 | Rn | Rd |
|
4168 |
* +---+---+---+-----------+------+---+------+--------+-----+------+------+
|
4169 |
*/
|
4170 |
static void disas_fp_2src(DisasContext *s, uint32_t insn) |
4171 |
{ |
4172 |
int type = extract32(insn, 22, 2); |
4173 |
int rd = extract32(insn, 0, 5); |
4174 |
int rn = extract32(insn, 5, 5); |
4175 |
int rm = extract32(insn, 16, 5); |
4176 |
int opcode = extract32(insn, 12, 4); |
4177 |
|
4178 |
if (opcode > 8) { |
4179 |
unallocated_encoding(s); |
4180 |
return;
|
4181 |
} |
4182 |
|
4183 |
switch (type) {
|
4184 |
case 0: |
4185 |
handle_fp_2src_single(s, opcode, rd, rn, rm); |
4186 |
break;
|
4187 |
case 1: |
4188 |
handle_fp_2src_double(s, opcode, rd, rn, rm); |
4189 |
break;
|
4190 |
default:
|
4191 |
unallocated_encoding(s); |
4192 |
} |
4193 |
} |
4194 |
|
4195 |
/* C3.6.27 Floating-point data-processing (3 source) - single precision */
|
4196 |
static void handle_fp_3src_single(DisasContext *s, bool o0, bool o1, |
4197 |
int rd, int rn, int rm, int ra) |
4198 |
{ |
4199 |
TCGv_i32 tcg_op1, tcg_op2, tcg_op3; |
4200 |
TCGv_i32 tcg_res = tcg_temp_new_i32(); |
4201 |
TCGv_ptr fpst = get_fpstatus_ptr(); |
4202 |
|
4203 |
tcg_op1 = read_fp_sreg(s, rn); |
4204 |
tcg_op2 = read_fp_sreg(s, rm); |
4205 |
tcg_op3 = read_fp_sreg(s, ra); |
4206 |
|
4207 |
/* These are fused multiply-add, and must be done as one
|
4208 |
* floating point operation with no rounding between the
|
4209 |
* multiplication and addition steps.
|
4210 |
* NB that doing the negations here as separate steps is
|
4211 |
* correct : an input NaN should come out with its sign bit
|
4212 |
* flipped if it is a negated-input.
|
4213 |
*/
|
4214 |
if (o1 == true) { |
4215 |
gen_helper_vfp_negs(tcg_op3, tcg_op3); |
4216 |
} |
4217 |
|
4218 |
if (o0 != o1) {
|
4219 |
gen_helper_vfp_negs(tcg_op1, tcg_op1); |
4220 |
} |
4221 |
|
4222 |
gen_helper_vfp_muladds(tcg_res, tcg_op1, tcg_op2, tcg_op3, fpst); |
4223 |
|
4224 |
write_fp_sreg(s, rd, tcg_res); |
4225 |
|
4226 |
tcg_temp_free_ptr(fpst); |
4227 |
tcg_temp_free_i32(tcg_op1); |
4228 |
tcg_temp_free_i32(tcg_op2); |
4229 |
tcg_temp_free_i32(tcg_op3); |
4230 |
tcg_temp_free_i32(tcg_res); |
4231 |
} |
4232 |
|
4233 |
/* C3.6.27 Floating-point data-processing (3 source) - double precision */
|
4234 |
static void handle_fp_3src_double(DisasContext *s, bool o0, bool o1, |
4235 |
int rd, int rn, int rm, int ra) |
4236 |
{ |
4237 |
TCGv_i64 tcg_op1, tcg_op2, tcg_op3; |
4238 |
TCGv_i64 tcg_res = tcg_temp_new_i64(); |
4239 |
TCGv_ptr fpst = get_fpstatus_ptr(); |
4240 |
|
4241 |
tcg_op1 = read_fp_dreg(s, rn); |
4242 |
tcg_op2 = read_fp_dreg(s, rm); |
4243 |
tcg_op3 = read_fp_dreg(s, ra); |
4244 |
|
4245 |
/* These are fused multiply-add, and must be done as one
|
4246 |
* floating point operation with no rounding between the
|
4247 |
* multiplication and addition steps.
|
4248 |
* NB that doing the negations here as separate steps is
|
4249 |
* correct : an input NaN should come out with its sign bit
|
4250 |
* flipped if it is a negated-input.
|
4251 |
*/
|
4252 |
if (o1 == true) { |
4253 |
gen_helper_vfp_negd(tcg_op3, tcg_op3); |
4254 |
} |
4255 |
|
4256 |
if (o0 != o1) {
|
4257 |
gen_helper_vfp_negd(tcg_op1, tcg_op1); |
4258 |
} |
4259 |
|
4260 |
gen_helper_vfp_muladdd(tcg_res, tcg_op1, tcg_op2, tcg_op3, fpst); |
4261 |
|
4262 |
write_fp_dreg(s, rd, tcg_res); |
4263 |
|
4264 |
tcg_temp_free_ptr(fpst); |
4265 |
tcg_temp_free_i64(tcg_op1); |
4266 |
tcg_temp_free_i64(tcg_op2); |
4267 |
tcg_temp_free_i64(tcg_op3); |
4268 |
tcg_temp_free_i64(tcg_res); |
4269 |
} |
4270 |
|
4271 |
/* C3.6.27 Floating point data-processing (3 source)
|
4272 |
* 31 30 29 28 24 23 22 21 20 16 15 14 10 9 5 4 0
|
4273 |
* +---+---+---+-----------+------+----+------+----+------+------+------+
|
4274 |
* | M | 0 | S | 1 1 1 1 1 | type | o1 | Rm | o0 | Ra | Rn | Rd |
|
4275 |
* +---+---+---+-----------+------+----+------+----+------+------+------+
|
4276 |
*/
|
4277 |
static void disas_fp_3src(DisasContext *s, uint32_t insn) |
4278 |
{ |
4279 |
int type = extract32(insn, 22, 2); |
4280 |
int rd = extract32(insn, 0, 5); |
4281 |
int rn = extract32(insn, 5, 5); |
4282 |
int ra = extract32(insn, 10, 5); |
4283 |
int rm = extract32(insn, 16, 5); |
4284 |
bool o0 = extract32(insn, 15, 1); |
4285 |
bool o1 = extract32(insn, 21, 1); |
4286 |
|
4287 |
switch (type) {
|
4288 |
case 0: |
4289 |
handle_fp_3src_single(s, o0, o1, rd, rn, rm, ra); |
4290 |
break;
|
4291 |
case 1: |
4292 |
handle_fp_3src_double(s, o0, o1, rd, rn, rm, ra); |
4293 |
break;
|
4294 |
default:
|
4295 |
unallocated_encoding(s); |
4296 |
} |
4297 |
} |
4298 |
|
4299 |
/* C3.6.28 Floating point immediate
|
4300 |
* 31 30 29 28 24 23 22 21 20 13 12 10 9 5 4 0
|
4301 |
* +---+---+---+-----------+------+---+------------+-------+------+------+
|
4302 |
* | M | 0 | S | 1 1 1 1 0 | type | 1 | imm8 | 1 0 0 | imm5 | Rd |
|
4303 |
* +---+---+---+-----------+------+---+------------+-------+------+------+
|
4304 |
*/
|
4305 |
static void disas_fp_imm(DisasContext *s, uint32_t insn) |
4306 |
{ |
4307 |
int rd = extract32(insn, 0, 5); |
4308 |
int imm8 = extract32(insn, 13, 8); |
4309 |
int is_double = extract32(insn, 22, 2); |
4310 |
uint64_t imm; |
4311 |
TCGv_i64 tcg_res; |
4312 |
|
4313 |
if (is_double > 1) { |
4314 |
unallocated_encoding(s); |
4315 |
return;
|
4316 |
} |
4317 |
|
4318 |
/* The imm8 encodes the sign bit, enough bits to represent
|
4319 |
* an exponent in the range 01....1xx to 10....0xx,
|
4320 |
* and the most significant 4 bits of the mantissa; see
|
4321 |
* VFPExpandImm() in the v8 ARM ARM.
|
4322 |
*/
|
4323 |
if (is_double) {
|
4324 |
imm = (extract32(imm8, 7, 1) ? 0x8000 : 0) | |
4325 |
(extract32(imm8, 6, 1) ? 0x3fc0 : 0x4000) | |
4326 |
extract32(imm8, 0, 6); |
4327 |
imm <<= 48;
|
4328 |
} else {
|
4329 |
imm = (extract32(imm8, 7, 1) ? 0x8000 : 0) | |
4330 |
(extract32(imm8, 6, 1) ? 0x3e00 : 0x4000) | |
4331 |
(extract32(imm8, 0, 6) << 3); |
4332 |
imm <<= 16;
|
4333 |
} |
4334 |
|
4335 |
tcg_res = tcg_const_i64(imm); |
4336 |
write_fp_dreg(s, rd, tcg_res); |
4337 |
tcg_temp_free_i64(tcg_res); |
4338 |
} |
4339 |
|
4340 |
/* Handle floating point <=> fixed point conversions. Note that we can
|
4341 |
* also deal with fp <=> integer conversions as a special case (scale == 64)
|
4342 |
* OPTME: consider handling that special case specially or at least skipping
|
4343 |
* the call to scalbn in the helpers for zero shifts.
|
4344 |
*/
|
4345 |
static void handle_fpfpcvt(DisasContext *s, int rd, int rn, int opcode, |
4346 |
bool itof, int rmode, int scale, int sf, int type) |
4347 |
{ |
4348 |
bool is_signed = !(opcode & 1); |
4349 |
bool is_double = type;
|
4350 |
TCGv_ptr tcg_fpstatus; |
4351 |
TCGv_i32 tcg_shift; |
4352 |
|
4353 |
tcg_fpstatus = get_fpstatus_ptr(); |
4354 |
|
4355 |
tcg_shift = tcg_const_i32(64 - scale);
|
4356 |
|
4357 |
if (itof) {
|
4358 |
TCGv_i64 tcg_int = cpu_reg(s, rn); |
4359 |
if (!sf) {
|
4360 |
TCGv_i64 tcg_extend = new_tmp_a64(s); |
4361 |
|
4362 |
if (is_signed) {
|
4363 |
tcg_gen_ext32s_i64(tcg_extend, tcg_int); |
4364 |
} else {
|
4365 |
tcg_gen_ext32u_i64(tcg_extend, tcg_int); |
4366 |
} |
4367 |
|
4368 |
tcg_int = tcg_extend; |
4369 |
} |
4370 |
|
4371 |
if (is_double) {
|
4372 |
TCGv_i64 tcg_double = tcg_temp_new_i64(); |
4373 |
if (is_signed) {
|
4374 |
gen_helper_vfp_sqtod(tcg_double, tcg_int, |
4375 |
tcg_shift, tcg_fpstatus); |
4376 |
} else {
|
4377 |
gen_helper_vfp_uqtod(tcg_double, tcg_int, |
4378 |
tcg_shift, tcg_fpstatus); |
4379 |
} |
4380 |
write_fp_dreg(s, rd, tcg_double); |
4381 |
tcg_temp_free_i64(tcg_double); |
4382 |
} else {
|
4383 |
TCGv_i32 tcg_single = tcg_temp_new_i32(); |
4384 |
if (is_signed) {
|
4385 |
gen_helper_vfp_sqtos(tcg_single, tcg_int, |
4386 |
tcg_shift, tcg_fpstatus); |
4387 |
} else {
|
4388 |
gen_helper_vfp_uqtos(tcg_single, tcg_int, |
4389 |
tcg_shift, tcg_fpstatus); |
4390 |
} |
4391 |
write_fp_sreg(s, rd, tcg_single); |
4392 |
tcg_temp_free_i32(tcg_single); |
4393 |
} |
4394 |
} else {
|
4395 |
TCGv_i64 tcg_int = cpu_reg(s, rd); |
4396 |
TCGv_i32 tcg_rmode; |
4397 |
|
4398 |
if (extract32(opcode, 2, 1)) { |
4399 |
/* There are too many rounding modes to all fit into rmode,
|
4400 |
* so FCVTA[US] is a special case.
|
4401 |
*/
|
4402 |
rmode = FPROUNDING_TIEAWAY; |
4403 |
} |
4404 |
|
4405 |
tcg_rmode = tcg_const_i32(arm_rmode_to_sf(rmode)); |
4406 |
|
4407 |
gen_helper_set_rmode(tcg_rmode, tcg_rmode, cpu_env); |
4408 |
|
4409 |
if (is_double) {
|
4410 |
TCGv_i64 tcg_double = read_fp_dreg(s, rn); |
4411 |
if (is_signed) {
|
4412 |
if (!sf) {
|
4413 |
gen_helper_vfp_tosld(tcg_int, tcg_double, |
4414 |
tcg_shift, tcg_fpstatus); |
4415 |
} else {
|
4416 |
gen_helper_vfp_tosqd(tcg_int, tcg_double, |
4417 |
tcg_shift, tcg_fpstatus); |
4418 |
} |
4419 |
} else {
|
4420 |
if (!sf) {
|
4421 |
gen_helper_vfp_tould(tcg_int, tcg_double, |
4422 |
tcg_shift, tcg_fpstatus); |
4423 |
} else {
|
4424 |
gen_helper_vfp_touqd(tcg_int, tcg_double, |
4425 |
tcg_shift, tcg_fpstatus); |
4426 |
} |
4427 |
} |
4428 |
tcg_temp_free_i64(tcg_double); |
4429 |
} else {
|
4430 |
TCGv_i32 tcg_single = read_fp_sreg(s, rn); |
4431 |
if (sf) {
|
4432 |
if (is_signed) {
|
4433 |
gen_helper_vfp_tosqs(tcg_int, tcg_single, |
4434 |
tcg_shift, tcg_fpstatus); |
4435 |
} else {
|
4436 |
gen_helper_vfp_touqs(tcg_int, tcg_single, |
4437 |
tcg_shift, tcg_fpstatus); |
4438 |
} |
4439 |
} else {
|
4440 |
TCGv_i32 tcg_dest = tcg_temp_new_i32(); |
4441 |
if (is_signed) {
|
4442 |
gen_helper_vfp_tosls(tcg_dest, tcg_single, |
4443 |
tcg_shift, tcg_fpstatus); |
4444 |
} else {
|
4445 |
gen_helper_vfp_touls(tcg_dest, tcg_single, |
4446 |
tcg_shift, tcg_fpstatus); |
4447 |
} |
4448 |
tcg_gen_extu_i32_i64(tcg_int, tcg_dest); |
4449 |
tcg_temp_free_i32(tcg_dest); |
4450 |
} |
4451 |
tcg_temp_free_i32(tcg_single); |
4452 |
} |
4453 |
|
4454 |
gen_helper_set_rmode(tcg_rmode, tcg_rmode, cpu_env); |
4455 |
tcg_temp_free_i32(tcg_rmode); |
4456 |
|
4457 |
if (!sf) {
|
4458 |
tcg_gen_ext32u_i64(tcg_int, tcg_int); |
4459 |
} |
4460 |
} |
4461 |
|
4462 |
tcg_temp_free_ptr(tcg_fpstatus); |
4463 |
tcg_temp_free_i32(tcg_shift); |
4464 |
} |
4465 |
|
4466 |
/* C3.6.29 Floating point <-> fixed point conversions
|
4467 |
* 31 30 29 28 24 23 22 21 20 19 18 16 15 10 9 5 4 0
|
4468 |
* +----+---+---+-----------+------+---+-------+--------+-------+------+------+
|
4469 |
* | sf | 0 | S | 1 1 1 1 0 | type | 0 | rmode | opcode | scale | Rn | Rd |
|
4470 |
* +----+---+---+-----------+------+---+-------+--------+-------+------+------+
|
4471 |
*/
|
4472 |
static void disas_fp_fixed_conv(DisasContext *s, uint32_t insn) |
4473 |
{ |
4474 |
int rd = extract32(insn, 0, 5); |
4475 |
int rn = extract32(insn, 5, 5); |
4476 |
int scale = extract32(insn, 10, 6); |
4477 |
int opcode = extract32(insn, 16, 3); |
4478 |
int rmode = extract32(insn, 19, 2); |
4479 |
int type = extract32(insn, 22, 2); |
4480 |
bool sbit = extract32(insn, 29, 1); |
4481 |
bool sf = extract32(insn, 31, 1); |
4482 |
bool itof;
|
4483 |
|
4484 |
if (sbit || (type > 1) |
4485 |
|| (!sf && scale < 32)) {
|
4486 |
unallocated_encoding(s); |
4487 |
return;
|
4488 |
} |
4489 |
|
4490 |
switch ((rmode << 3) | opcode) { |
4491 |
case 0x2: /* SCVTF */ |
4492 |
case 0x3: /* UCVTF */ |
4493 |
itof = true;
|
4494 |
break;
|
4495 |
case 0x18: /* FCVTZS */ |
4496 |
case 0x19: /* FCVTZU */ |
4497 |
itof = false;
|
4498 |
break;
|
4499 |
default:
|
4500 |
unallocated_encoding(s); |
4501 |
return;
|
4502 |
} |
4503 |
|
4504 |
handle_fpfpcvt(s, rd, rn, opcode, itof, FPROUNDING_ZERO, scale, sf, type); |
4505 |
} |
4506 |
|
4507 |
static void handle_fmov(DisasContext *s, int rd, int rn, int type, bool itof) |
4508 |
{ |
4509 |
/* FMOV: gpr to or from float, double, or top half of quad fp reg,
|
4510 |
* without conversion.
|
4511 |
*/
|
4512 |
|
4513 |
if (itof) {
|
4514 |
TCGv_i64 tcg_rn = cpu_reg(s, rn); |
4515 |
|
4516 |
switch (type) {
|
4517 |
case 0: |
4518 |
{ |
4519 |
/* 32 bit */
|
4520 |
TCGv_i64 tmp = tcg_temp_new_i64(); |
4521 |
tcg_gen_ext32u_i64(tmp, tcg_rn); |
4522 |
tcg_gen_st_i64(tmp, cpu_env, fp_reg_offset(rd, MO_64)); |
4523 |
tcg_gen_movi_i64(tmp, 0);
|
4524 |
tcg_gen_st_i64(tmp, cpu_env, fp_reg_hi_offset(rd)); |
4525 |
tcg_temp_free_i64(tmp); |
4526 |
break;
|
4527 |
} |
4528 |
case 1: |
4529 |
{ |
4530 |
/* 64 bit */
|
4531 |
TCGv_i64 tmp = tcg_const_i64(0);
|
4532 |
tcg_gen_st_i64(tcg_rn, cpu_env, fp_reg_offset(rd, MO_64)); |
4533 |
tcg_gen_st_i64(tmp, cpu_env, fp_reg_hi_offset(rd)); |
4534 |
tcg_temp_free_i64(tmp); |
4535 |
break;
|
4536 |
} |
4537 |
case 2: |
4538 |
/* 64 bit to top half. */
|
4539 |
tcg_gen_st_i64(tcg_rn, cpu_env, fp_reg_hi_offset(rd)); |
4540 |
break;
|
4541 |
} |
4542 |
} else {
|
4543 |
TCGv_i64 tcg_rd = cpu_reg(s, rd); |
4544 |
|
4545 |
switch (type) {
|
4546 |
case 0: |
4547 |
/* 32 bit */
|
4548 |
tcg_gen_ld32u_i64(tcg_rd, cpu_env, fp_reg_offset(rn, MO_32)); |
4549 |
break;
|
4550 |
case 1: |
4551 |
/* 64 bit */
|
4552 |
tcg_gen_ld_i64(tcg_rd, cpu_env, fp_reg_offset(rn, MO_64)); |
4553 |
break;
|
4554 |
case 2: |
4555 |
/* 64 bits from top half */
|
4556 |
tcg_gen_ld_i64(tcg_rd, cpu_env, fp_reg_hi_offset(rn)); |
4557 |
break;
|
4558 |
} |
4559 |
} |
4560 |
} |
4561 |
|
4562 |
/* C3.6.30 Floating point <-> integer conversions
|
4563 |
* 31 30 29 28 24 23 22 21 20 19 18 16 15 10 9 5 4 0
|
4564 |
* +----+---+---+-----------+------+---+-------+-----+-------------+----+----+
|
4565 |
* | sf | 0 | S | 1 1 1 1 0 | type | 1 | rmode | opc | 0 0 0 0 0 0 | Rn | Rd |
|
4566 |
* +----+---+---+-----------+------+---+-------+-----+-------------+----+----+
|
4567 |
*/
|
4568 |
static void disas_fp_int_conv(DisasContext *s, uint32_t insn) |
4569 |
{ |
4570 |
int rd = extract32(insn, 0, 5); |
4571 |
int rn = extract32(insn, 5, 5); |
4572 |
int opcode = extract32(insn, 16, 3); |
4573 |
int rmode = extract32(insn, 19, 2); |
4574 |
int type = extract32(insn, 22, 2); |
4575 |
bool sbit = extract32(insn, 29, 1); |
4576 |
bool sf = extract32(insn, 31, 1); |
4577 |
|
4578 |
if (sbit) {
|
4579 |
unallocated_encoding(s); |
4580 |
return;
|
4581 |
} |
4582 |
|
4583 |
if (opcode > 5) { |
4584 |
/* FMOV */
|
4585 |
bool itof = opcode & 1; |
4586 |
|
4587 |
if (rmode >= 2) { |
4588 |
unallocated_encoding(s); |
4589 |
return;
|
4590 |
} |
4591 |
|
4592 |
switch (sf << 3 | type << 1 | rmode) { |
4593 |
case 0x0: /* 32 bit */ |
4594 |
case 0xa: /* 64 bit */ |
4595 |
case 0xd: /* 64 bit to top half of quad */ |
4596 |
break;
|
4597 |
default:
|
4598 |
/* all other sf/type/rmode combinations are invalid */
|
4599 |
unallocated_encoding(s); |
4600 |
break;
|
4601 |
} |
4602 |
|
4603 |
handle_fmov(s, rd, rn, type, itof); |
4604 |
} else {
|
4605 |
/* actual FP conversions */
|
4606 |
bool itof = extract32(opcode, 1, 1); |
4607 |
|
4608 |
if (type > 1 || (rmode != 0 && opcode > 1)) { |
4609 |
unallocated_encoding(s); |
4610 |
return;
|
4611 |
} |
4612 |
|
4613 |
handle_fpfpcvt(s, rd, rn, opcode, itof, rmode, 64, sf, type);
|
4614 |
} |
4615 |
} |
4616 |
|
4617 |
/* FP-specific subcases of table C3-6 (SIMD and FP data processing)
|
4618 |
* 31 30 29 28 25 24 0
|
4619 |
* +---+---+---+---------+-----------------------------+
|
4620 |
* | | 0 | | 1 1 1 1 | |
|
4621 |
* +---+---+---+---------+-----------------------------+
|
4622 |
*/
|
4623 |
static void disas_data_proc_fp(DisasContext *s, uint32_t insn) |
4624 |
{ |
4625 |
if (extract32(insn, 24, 1)) { |
4626 |
/* Floating point data-processing (3 source) */
|
4627 |
disas_fp_3src(s, insn); |
4628 |
} else if (extract32(insn, 21, 1) == 0) { |
4629 |
/* Floating point to fixed point conversions */
|
4630 |
disas_fp_fixed_conv(s, insn); |
4631 |
} else {
|
4632 |
switch (extract32(insn, 10, 2)) { |
4633 |
case 1: |
4634 |
/* Floating point conditional compare */
|
4635 |
disas_fp_ccomp(s, insn); |
4636 |
break;
|
4637 |
case 2: |
4638 |
/* Floating point data-processing (2 source) */
|
4639 |
disas_fp_2src(s, insn); |
4640 |
break;
|
4641 |
case 3: |
4642 |
/* Floating point conditional select */
|
4643 |
disas_fp_csel(s, insn); |
4644 |
break;
|
4645 |
case 0: |
4646 |
switch (ctz32(extract32(insn, 12, 4))) { |
4647 |
case 0: /* [15:12] == xxx1 */ |
4648 |
/* Floating point immediate */
|
4649 |
disas_fp_imm(s, insn); |
4650 |
break;
|
4651 |
case 1: /* [15:12] == xx10 */ |
4652 |
/* Floating point compare */
|
4653 |
disas_fp_compare(s, insn); |
4654 |
break;
|
4655 |
case 2: /* [15:12] == x100 */ |
4656 |
/* Floating point data-processing (1 source) */
|
4657 |
disas_fp_1src(s, insn); |
4658 |
break;
|
4659 |
case 3: /* [15:12] == 1000 */ |
4660 |
unallocated_encoding(s); |
4661 |
break;
|
4662 |
default: /* [15:12] == 0000 */ |
4663 |
/* Floating point <-> integer conversions */
|
4664 |
disas_fp_int_conv(s, insn); |
4665 |
break;
|
4666 |
} |
4667 |
break;
|
4668 |
} |
4669 |
} |
4670 |
} |
4671 |
|
4672 |
static void do_ext64(DisasContext *s, TCGv_i64 tcg_left, TCGv_i64 tcg_right, |
4673 |
int pos)
|
4674 |
{ |
4675 |
/* Extract 64 bits from the middle of two concatenated 64 bit
|
4676 |
* vector register slices left:right. The extracted bits start
|
4677 |
* at 'pos' bits into the right (least significant) side.
|
4678 |
* We return the result in tcg_right, and guarantee not to
|
4679 |
* trash tcg_left.
|
4680 |
*/
|
4681 |
TCGv_i64 tcg_tmp = tcg_temp_new_i64(); |
4682 |
assert(pos > 0 && pos < 64); |
4683 |
|
4684 |
tcg_gen_shri_i64(tcg_right, tcg_right, pos); |
4685 |
tcg_gen_shli_i64(tcg_tmp, tcg_left, 64 - pos);
|
4686 |
tcg_gen_or_i64(tcg_right, tcg_right, tcg_tmp); |
4687 |
|
4688 |
tcg_temp_free_i64(tcg_tmp); |
4689 |
} |
4690 |
|
4691 |
/* C3.6.1 EXT
|
4692 |
* 31 30 29 24 23 22 21 20 16 15 14 11 10 9 5 4 0
|
4693 |
* +---+---+-------------+-----+---+------+---+------+---+------+------+
|
4694 |
* | 0 | Q | 1 0 1 1 1 0 | op2 | 0 | Rm | 0 | imm4 | 0 | Rn | Rd |
|
4695 |
* +---+---+-------------+-----+---+------+---+------+---+------+------+
|
4696 |
*/
|
4697 |
static void disas_simd_ext(DisasContext *s, uint32_t insn) |
4698 |
{ |
4699 |
int is_q = extract32(insn, 30, 1); |
4700 |
int op2 = extract32(insn, 22, 2); |
4701 |
int imm4 = extract32(insn, 11, 4); |
4702 |
int rm = extract32(insn, 16, 5); |
4703 |
int rn = extract32(insn, 5, 5); |
4704 |
int rd = extract32(insn, 0, 5); |
4705 |
int pos = imm4 << 3; |
4706 |
TCGv_i64 tcg_resl, tcg_resh; |
4707 |
|
4708 |
if (op2 != 0 || (!is_q && extract32(imm4, 3, 1))) { |
4709 |
unallocated_encoding(s); |
4710 |
return;
|
4711 |
} |
4712 |
|
4713 |
tcg_resh = tcg_temp_new_i64(); |
4714 |
tcg_resl = tcg_temp_new_i64(); |
4715 |
|
4716 |
/* Vd gets bits starting at pos bits into Vm:Vn. This is
|
4717 |
* either extracting 128 bits from a 128:128 concatenation, or
|
4718 |
* extracting 64 bits from a 64:64 concatenation.
|
4719 |
*/
|
4720 |
if (!is_q) {
|
4721 |
read_vec_element(s, tcg_resl, rn, 0, MO_64);
|
4722 |
if (pos != 0) { |
4723 |
read_vec_element(s, tcg_resh, rm, 0, MO_64);
|
4724 |
do_ext64(s, tcg_resh, tcg_resl, pos); |
4725 |
} |
4726 |
tcg_gen_movi_i64(tcg_resh, 0);
|
4727 |
} else {
|
4728 |
TCGv_i64 tcg_hh; |
4729 |
typedef struct { |
4730 |
int reg;
|
4731 |
int elt;
|
4732 |
} EltPosns; |
4733 |
EltPosns eltposns[] = { {rn, 0}, {rn, 1}, {rm, 0}, {rm, 1} }; |
4734 |
EltPosns *elt = eltposns; |
4735 |
|
4736 |
if (pos >= 64) { |
4737 |
elt++; |
4738 |
pos -= 64;
|
4739 |
} |
4740 |
|
4741 |
read_vec_element(s, tcg_resl, elt->reg, elt->elt, MO_64); |
4742 |
elt++; |
4743 |
read_vec_element(s, tcg_resh, elt->reg, elt->elt, MO_64); |
4744 |
elt++; |
4745 |
if (pos != 0) { |
4746 |
do_ext64(s, tcg_resh, tcg_resl, pos); |
4747 |
tcg_hh = tcg_temp_new_i64(); |
4748 |
read_vec_element(s, tcg_hh, elt->reg, elt->elt, MO_64); |
4749 |
do_ext64(s, tcg_hh, tcg_resh, pos); |
4750 |
tcg_temp_free_i64(tcg_hh); |
4751 |
} |
4752 |
} |
4753 |
|
4754 |
write_vec_element(s, tcg_resl, rd, 0, MO_64);
|
4755 |
tcg_temp_free_i64(tcg_resl); |
4756 |
write_vec_element(s, tcg_resh, rd, 1, MO_64);
|
4757 |
tcg_temp_free_i64(tcg_resh); |
4758 |
} |
4759 |
|
4760 |
/* C3.6.2 TBL/TBX
|
4761 |
* 31 30 29 24 23 22 21 20 16 15 14 13 12 11 10 9 5 4 0
|
4762 |
* +---+---+-------------+-----+---+------+---+-----+----+-----+------+------+
|
4763 |
* | 0 | Q | 0 0 1 1 1 0 | op2 | 0 | Rm | 0 | len | op | 0 0 | Rn | Rd |
|
4764 |
* +---+---+-------------+-----+---+------+---+-----+----+-----+------+------+
|
4765 |
*/
|
4766 |
static void disas_simd_tb(DisasContext *s, uint32_t insn) |
4767 |
{ |
4768 |
int op2 = extract32(insn, 22, 2); |
4769 |
int is_q = extract32(insn, 30, 1); |
4770 |
int rm = extract32(insn, 16, 5); |
4771 |
int rn = extract32(insn, 5, 5); |
4772 |
int rd = extract32(insn, 0, 5); |
4773 |
int is_tblx = extract32(insn, 12, 1); |
4774 |
int len = extract32(insn, 13, 2); |
4775 |
TCGv_i64 tcg_resl, tcg_resh, tcg_idx; |
4776 |
TCGv_i32 tcg_regno, tcg_numregs; |
4777 |
|
4778 |
if (op2 != 0) { |
4779 |
unallocated_encoding(s); |
4780 |
return;
|
4781 |
} |
4782 |
|
4783 |
/* This does a table lookup: for every byte element in the input
|
4784 |
* we index into a table formed from up to four vector registers,
|
4785 |
* and then the output is the result of the lookups. Our helper
|
4786 |
* function does the lookup operation for a single 64 bit part of
|
4787 |
* the input.
|
4788 |
*/
|
4789 |
tcg_resl = tcg_temp_new_i64(); |
4790 |
tcg_resh = tcg_temp_new_i64(); |
4791 |
|
4792 |
if (is_tblx) {
|
4793 |
read_vec_element(s, tcg_resl, rd, 0, MO_64);
|
4794 |
} else {
|
4795 |
tcg_gen_movi_i64(tcg_resl, 0);
|
4796 |
} |
4797 |
if (is_tblx && is_q) {
|
4798 |
read_vec_element(s, tcg_resh, rd, 1, MO_64);
|
4799 |
} else {
|
4800 |
tcg_gen_movi_i64(tcg_resh, 0);
|
4801 |
} |
4802 |
|
4803 |
tcg_idx = tcg_temp_new_i64(); |
4804 |
tcg_regno = tcg_const_i32(rn); |
4805 |
tcg_numregs = tcg_const_i32(len + 1);
|
4806 |
read_vec_element(s, tcg_idx, rm, 0, MO_64);
|
4807 |
gen_helper_simd_tbl(tcg_resl, cpu_env, tcg_resl, tcg_idx, |
4808 |
tcg_regno, tcg_numregs); |
4809 |
if (is_q) {
|
4810 |
read_vec_element(s, tcg_idx, rm, 1, MO_64);
|
4811 |
gen_helper_simd_tbl(tcg_resh, cpu_env, tcg_resh, tcg_idx, |
4812 |
tcg_regno, tcg_numregs); |
4813 |
} |
4814 |
tcg_temp_free_i64(tcg_idx); |
4815 |
tcg_temp_free_i32(tcg_regno); |
4816 |
tcg_temp_free_i32(tcg_numregs); |
4817 |
|
4818 |
write_vec_element(s, tcg_resl, rd, 0, MO_64);
|
4819 |
tcg_temp_free_i64(tcg_resl); |
4820 |
write_vec_element(s, tcg_resh, rd, 1, MO_64);
|
4821 |
tcg_temp_free_i64(tcg_resh); |
4822 |
} |
4823 |
|
4824 |
/* C3.6.3 ZIP/UZP/TRN
|
4825 |
* 31 30 29 24 23 22 21 20 16 15 14 12 11 10 9 5 4 0
|
4826 |
* +---+---+-------------+------+---+------+---+------------------+------+
|
4827 |
* | 0 | Q | 0 0 1 1 1 0 | size | 0 | Rm | 0 | opc | 1 0 | Rn | Rd |
|
4828 |
* +---+---+-------------+------+---+------+---+------------------+------+
|
4829 |
*/
|
4830 |
static void disas_simd_zip_trn(DisasContext *s, uint32_t insn) |
4831 |
{ |
4832 |
int rd = extract32(insn, 0, 5); |
4833 |
int rn = extract32(insn, 5, 5); |
4834 |
int rm = extract32(insn, 16, 5); |
4835 |
int size = extract32(insn, 22, 2); |
4836 |
/* opc field bits [1:0] indicate ZIP/UZP/TRN;
|
4837 |
* bit 2 indicates 1 vs 2 variant of the insn.
|
4838 |
*/
|
4839 |
int opcode = extract32(insn, 12, 2); |
4840 |
bool part = extract32(insn, 14, 1); |
4841 |
bool is_q = extract32(insn, 30, 1); |
4842 |
int esize = 8 << size; |
4843 |
int i, ofs;
|
4844 |
int datasize = is_q ? 128 : 64; |
4845 |
int elements = datasize / esize;
|
4846 |
TCGv_i64 tcg_res, tcg_resl, tcg_resh; |
4847 |
|
4848 |
if (opcode == 0 || (size == 3 && !is_q)) { |
4849 |
unallocated_encoding(s); |
4850 |
return;
|
4851 |
} |
4852 |
|
4853 |
tcg_resl = tcg_const_i64(0);
|
4854 |
tcg_resh = tcg_const_i64(0);
|
4855 |
tcg_res = tcg_temp_new_i64(); |
4856 |
|
4857 |
for (i = 0; i < elements; i++) { |
4858 |
switch (opcode) {
|
4859 |
case 1: /* UZP1/2 */ |
4860 |
{ |
4861 |
int midpoint = elements / 2; |
4862 |
if (i < midpoint) {
|
4863 |
read_vec_element(s, tcg_res, rn, 2 * i + part, size);
|
4864 |
} else {
|
4865 |
read_vec_element(s, tcg_res, rm, |
4866 |
2 * (i - midpoint) + part, size);
|
4867 |
} |
4868 |
break;
|
4869 |
} |
4870 |
case 2: /* TRN1/2 */ |
4871 |
if (i & 1) { |
4872 |
read_vec_element(s, tcg_res, rm, (i & ~1) + part, size);
|
4873 |
} else {
|
4874 |
read_vec_element(s, tcg_res, rn, (i & ~1) + part, size);
|
4875 |
} |
4876 |
break;
|
4877 |
case 3: /* ZIP1/2 */ |
4878 |
{ |
4879 |
int base = part * elements / 2; |
4880 |
if (i & 1) { |
4881 |
read_vec_element(s, tcg_res, rm, base + (i >> 1), size);
|
4882 |
} else {
|
4883 |
read_vec_element(s, tcg_res, rn, base + (i >> 1), size);
|
4884 |
} |
4885 |
break;
|
4886 |
} |
4887 |
default:
|
4888 |
g_assert_not_reached(); |
4889 |
} |
4890 |
|
4891 |
ofs = i * esize; |
4892 |
if (ofs < 64) { |
4893 |
tcg_gen_shli_i64(tcg_res, tcg_res, ofs); |
4894 |
tcg_gen_or_i64(tcg_resl, tcg_resl, tcg_res); |
4895 |
} else {
|
4896 |
tcg_gen_shli_i64(tcg_res, tcg_res, ofs - 64);
|
4897 |
tcg_gen_or_i64(tcg_resh, tcg_resh, tcg_res); |
4898 |
} |
4899 |
} |
4900 |
|
4901 |
tcg_temp_free_i64(tcg_res); |
4902 |
|
4903 |
write_vec_element(s, tcg_resl, rd, 0, MO_64);
|
4904 |
tcg_temp_free_i64(tcg_resl); |
4905 |
write_vec_element(s, tcg_resh, rd, 1, MO_64);
|
4906 |
tcg_temp_free_i64(tcg_resh); |
4907 |
} |
4908 |
|
4909 |
static void do_minmaxop(DisasContext *s, TCGv_i32 tcg_elt1, TCGv_i32 tcg_elt2, |
4910 |
int opc, bool is_min, TCGv_ptr fpst) |
4911 |
{ |
4912 |
/* Helper function for disas_simd_across_lanes: do a single precision
|
4913 |
* min/max operation on the specified two inputs,
|
4914 |
* and return the result in tcg_elt1.
|
4915 |
*/
|
4916 |
if (opc == 0xc) { |
4917 |
if (is_min) {
|
4918 |
gen_helper_vfp_minnums(tcg_elt1, tcg_elt1, tcg_elt2, fpst); |
4919 |
} else {
|
4920 |
gen_helper_vfp_maxnums(tcg_elt1, tcg_elt1, tcg_elt2, fpst); |
4921 |
} |
4922 |
} else {
|
4923 |
assert(opc == 0xf);
|
4924 |
if (is_min) {
|
4925 |
gen_helper_vfp_mins(tcg_elt1, tcg_elt1, tcg_elt2, fpst); |
4926 |
} else {
|
4927 |
gen_helper_vfp_maxs(tcg_elt1, tcg_elt1, tcg_elt2, fpst); |
4928 |
} |
4929 |
} |
4930 |
} |
4931 |
|
4932 |
/* C3.6.4 AdvSIMD across lanes
|
4933 |
* 31 30 29 28 24 23 22 21 17 16 12 11 10 9 5 4 0
|
4934 |
* +---+---+---+-----------+------+-----------+--------+-----+------+------+
|
4935 |
* | 0 | Q | U | 0 1 1 1 0 | size | 1 1 0 0 0 | opcode | 1 0 | Rn | Rd |
|
4936 |
* +---+---+---+-----------+------+-----------+--------+-----+------+------+
|
4937 |
*/
|
4938 |
static void disas_simd_across_lanes(DisasContext *s, uint32_t insn) |
4939 |
{ |
4940 |
int rd = extract32(insn, 0, 5); |
4941 |
int rn = extract32(insn, 5, 5); |
4942 |
int size = extract32(insn, 22, 2); |
4943 |
int opcode = extract32(insn, 12, 5); |
4944 |
bool is_q = extract32(insn, 30, 1); |
4945 |
bool is_u = extract32(insn, 29, 1); |
4946 |
bool is_fp = false; |
4947 |
bool is_min = false; |
4948 |
int esize;
|
4949 |
int elements;
|
4950 |
int i;
|
4951 |
TCGv_i64 tcg_res, tcg_elt; |
4952 |
|
4953 |
switch (opcode) {
|
4954 |
case 0x1b: /* ADDV */ |
4955 |
if (is_u) {
|
4956 |
unallocated_encoding(s); |
4957 |
return;
|
4958 |
} |
4959 |
/* fall through */
|
4960 |
case 0x3: /* SADDLV, UADDLV */ |
4961 |
case 0xa: /* SMAXV, UMAXV */ |
4962 |
case 0x1a: /* SMINV, UMINV */ |
4963 |
if (size == 3 || (size == 2 && !is_q)) { |
4964 |
unallocated_encoding(s); |
4965 |
return;
|
4966 |
} |
4967 |
break;
|
4968 |
case 0xc: /* FMAXNMV, FMINNMV */ |
4969 |
case 0xf: /* FMAXV, FMINV */ |
4970 |
if (!is_u || !is_q || extract32(size, 0, 1)) { |
4971 |
unallocated_encoding(s); |
4972 |
return;
|
4973 |
} |
4974 |
/* Bit 1 of size field encodes min vs max, and actual size is always
|
4975 |
* 32 bits: adjust the size variable so following code can rely on it
|
4976 |
*/
|
4977 |
is_min = extract32(size, 1, 1); |
4978 |
is_fp = true;
|
4979 |
size = 2;
|
4980 |
break;
|
4981 |
default:
|
4982 |
unallocated_encoding(s); |
4983 |
return;
|
4984 |
} |
4985 |
|
4986 |
esize = 8 << size;
|
4987 |
elements = (is_q ? 128 : 64) / esize; |
4988 |
|
4989 |
tcg_res = tcg_temp_new_i64(); |
4990 |
tcg_elt = tcg_temp_new_i64(); |
4991 |
|
4992 |
/* These instructions operate across all lanes of a vector
|
4993 |
* to produce a single result. We can guarantee that a 64
|
4994 |
* bit intermediate is sufficient:
|
4995 |
* + for [US]ADDLV the maximum element size is 32 bits, and
|
4996 |
* the result type is 64 bits
|
4997 |
* + for FMAX*V, FMIN*V, ADDV the intermediate type is the
|
4998 |
* same as the element size, which is 32 bits at most
|
4999 |
* For the integer operations we can choose to work at 64
|
5000 |
* or 32 bits and truncate at the end; for simplicity
|
5001 |
* we use 64 bits always. The floating point
|
5002 |
* ops do require 32 bit intermediates, though.
|
5003 |
*/
|
5004 |
if (!is_fp) {
|
5005 |
read_vec_element(s, tcg_res, rn, 0, size | (is_u ? 0 : MO_SIGN)); |
5006 |
|
5007 |
for (i = 1; i < elements; i++) { |
5008 |
read_vec_element(s, tcg_elt, rn, i, size | (is_u ? 0 : MO_SIGN));
|
5009 |
|
5010 |
switch (opcode) {
|
5011 |
case 0x03: /* SADDLV / UADDLV */ |
5012 |
case 0x1b: /* ADDV */ |
5013 |
tcg_gen_add_i64(tcg_res, tcg_res, tcg_elt); |
5014 |
break;
|
5015 |
case 0x0a: /* SMAXV / UMAXV */ |
5016 |
tcg_gen_movcond_i64(is_u ? TCG_COND_GEU : TCG_COND_GE, |
5017 |
tcg_res, |
5018 |
tcg_res, tcg_elt, tcg_res, tcg_elt); |
5019 |
break;
|
5020 |
case 0x1a: /* SMINV / UMINV */ |
5021 |
tcg_gen_movcond_i64(is_u ? TCG_COND_LEU : TCG_COND_LE, |
5022 |
tcg_res, |
5023 |
tcg_res, tcg_elt, tcg_res, tcg_elt); |
5024 |
break;
|
5025 |
break;
|
5026 |
default:
|
5027 |
g_assert_not_reached(); |
5028 |
} |
5029 |
|
5030 |
} |
5031 |
} else {
|
5032 |
/* Floating point ops which work on 32 bit (single) intermediates.
|
5033 |
* Note that correct NaN propagation requires that we do these
|
5034 |
* operations in exactly the order specified by the pseudocode.
|
5035 |
*/
|
5036 |
TCGv_i32 tcg_elt1 = tcg_temp_new_i32(); |
5037 |
TCGv_i32 tcg_elt2 = tcg_temp_new_i32(); |
5038 |
TCGv_i32 tcg_elt3 = tcg_temp_new_i32(); |
5039 |
TCGv_ptr fpst = get_fpstatus_ptr(); |
5040 |
|
5041 |
assert(esize == 32);
|
5042 |
assert(elements == 4);
|
5043 |
|
5044 |
read_vec_element(s, tcg_elt, rn, 0, MO_32);
|
5045 |
tcg_gen_trunc_i64_i32(tcg_elt1, tcg_elt); |
5046 |
read_vec_element(s, tcg_elt, rn, 1, MO_32);
|
5047 |
tcg_gen_trunc_i64_i32(tcg_elt2, tcg_elt); |
5048 |
|
5049 |
do_minmaxop(s, tcg_elt1, tcg_elt2, opcode, is_min, fpst); |
5050 |
|
5051 |
read_vec_element(s, tcg_elt, rn, 2, MO_32);
|
5052 |
tcg_gen_trunc_i64_i32(tcg_elt2, tcg_elt); |
5053 |
read_vec_element(s, tcg_elt, rn, 3, MO_32);
|
5054 |
tcg_gen_trunc_i64_i32(tcg_elt3, tcg_elt); |
5055 |
|
5056 |
do_minmaxop(s, tcg_elt2, tcg_elt3, opcode, is_min, fpst); |
5057 |
|
5058 |
do_minmaxop(s, tcg_elt1, tcg_elt2, opcode, is_min, fpst); |
5059 |
|
5060 |
tcg_gen_extu_i32_i64(tcg_res, tcg_elt1); |
5061 |
tcg_temp_free_i32(tcg_elt1); |
5062 |
tcg_temp_free_i32(tcg_elt2); |
5063 |
tcg_temp_free_i32(tcg_elt3); |
5064 |
tcg_temp_free_ptr(fpst); |
5065 |
} |
5066 |
|
5067 |
tcg_temp_free_i64(tcg_elt); |
5068 |
|
5069 |
/* Now truncate the result to the width required for the final output */
|
5070 |
if (opcode == 0x03) { |
5071 |
/* SADDLV, UADDLV: result is 2*esize */
|
5072 |
size++; |
5073 |
} |
5074 |
|
5075 |
switch (size) {
|
5076 |
case 0: |
5077 |
tcg_gen_ext8u_i64(tcg_res, tcg_res); |
5078 |
break;
|
5079 |
case 1: |
5080 |
tcg_gen_ext16u_i64(tcg_res, tcg_res); |
5081 |
break;
|
5082 |
case 2: |
5083 |
tcg_gen_ext32u_i64(tcg_res, tcg_res); |
5084 |
break;
|
5085 |
case 3: |
5086 |
break;
|
5087 |
default:
|
5088 |
g_assert_not_reached(); |
5089 |
} |
5090 |
|
5091 |
write_fp_dreg(s, rd, tcg_res); |
5092 |
tcg_temp_free_i64(tcg_res); |
5093 |
} |
5094 |
|
5095 |
/* C6.3.31 DUP (Element, Vector)
|
5096 |
*
|
5097 |
* 31 30 29 21 20 16 15 10 9 5 4 0
|
5098 |
* +---+---+-------------------+--------+-------------+------+------+
|
5099 |
* | 0 | Q | 0 0 1 1 1 0 0 0 0 | imm5 | 0 0 0 0 0 1 | Rn | Rd |
|
5100 |
* +---+---+-------------------+--------+-------------+------+------+
|
5101 |
*
|
5102 |
* size: encoded in imm5 (see ARM ARM LowestSetBit())
|
5103 |
*/
|
5104 |
static void handle_simd_dupe(DisasContext *s, int is_q, int rd, int rn, |
5105 |
int imm5)
|
5106 |
{ |
5107 |
int size = ctz32(imm5);
|
5108 |
int esize = 8 << size; |
5109 |
int elements = (is_q ? 128 : 64) / esize; |
5110 |
int index, i;
|
5111 |
TCGv_i64 tmp; |
5112 |
|
5113 |
if (size > 3 || (size == 3 && !is_q)) { |
5114 |
unallocated_encoding(s); |
5115 |
return;
|
5116 |
} |
5117 |
|
5118 |
index = imm5 >> (size + 1);
|
5119 |
|
5120 |
tmp = tcg_temp_new_i64(); |
5121 |
read_vec_element(s, tmp, rn, index, size); |
5122 |
|
5123 |
for (i = 0; i < elements; i++) { |
5124 |
write_vec_element(s, tmp, rd, i, size); |
5125 |
} |
5126 |
|
5127 |
if (!is_q) {
|
5128 |
clear_vec_high(s, rd); |
5129 |
} |
5130 |
|
5131 |
tcg_temp_free_i64(tmp); |
5132 |
} |
5133 |
|
5134 |
/* C6.3.31 DUP (element, scalar)
|
5135 |
* 31 21 20 16 15 10 9 5 4 0
|
5136 |
* +-----------------------+--------+-------------+------+------+
|
5137 |
* | 0 1 0 1 1 1 1 0 0 0 0 | imm5 | 0 0 0 0 0 1 | Rn | Rd |
|
5138 |
* +-----------------------+--------+-------------+------+------+
|
5139 |
*/
|
5140 |
static void handle_simd_dupes(DisasContext *s, int rd, int rn, |
5141 |
int imm5)
|
5142 |
{ |
5143 |
int size = ctz32(imm5);
|
5144 |
int index;
|
5145 |
TCGv_i64 tmp; |
5146 |
|
5147 |
if (size > 3) { |
5148 |
unallocated_encoding(s); |
5149 |
return;
|
5150 |
} |
5151 |
|
5152 |
index = imm5 >> (size + 1);
|
5153 |
|
5154 |
/* This instruction just extracts the specified element and
|
5155 |
* zero-extends it into the bottom of the destination register.
|
5156 |
*/
|
5157 |
tmp = tcg_temp_new_i64(); |
5158 |
read_vec_element(s, tmp, rn, index, size); |
5159 |
write_fp_dreg(s, rd, tmp); |
5160 |
tcg_temp_free_i64(tmp); |
5161 |
} |
5162 |
|
5163 |
/* C6.3.32 DUP (General)
|
5164 |
*
|
5165 |
* 31 30 29 21 20 16 15 10 9 5 4 0
|
5166 |
* +---+---+-------------------+--------+-------------+------+------+
|
5167 |
* | 0 | Q | 0 0 1 1 1 0 0 0 0 | imm5 | 0 0 0 0 1 1 | Rn | Rd |
|
5168 |
* +---+---+-------------------+--------+-------------+------+------+
|
5169 |
*
|
5170 |
* size: encoded in imm5 (see ARM ARM LowestSetBit())
|
5171 |
*/
|
5172 |
static void handle_simd_dupg(DisasContext *s, int is_q, int rd, int rn, |
5173 |
int imm5)
|
5174 |
{ |
5175 |
int size = ctz32(imm5);
|
5176 |
int esize = 8 << size; |
5177 |
int elements = (is_q ? 128 : 64)/esize; |
5178 |
int i = 0; |
5179 |
|
5180 |
if (size > 3 || ((size == 3) && !is_q)) { |
5181 |
unallocated_encoding(s); |
5182 |
return;
|
5183 |
} |
5184 |
for (i = 0; i < elements; i++) { |
5185 |
write_vec_element(s, cpu_reg(s, rn), rd, i, size); |
5186 |
} |
5187 |
if (!is_q) {
|
5188 |
clear_vec_high(s, rd); |
5189 |
} |
5190 |
} |
5191 |
|
5192 |
/* C6.3.150 INS (Element)
|
5193 |
*
|
5194 |
* 31 21 20 16 15 14 11 10 9 5 4 0
|
5195 |
* +-----------------------+--------+------------+---+------+------+
|
5196 |
* | 0 1 1 0 1 1 1 0 0 0 0 | imm5 | 0 | imm4 | 1 | Rn | Rd |
|
5197 |
* +-----------------------+--------+------------+---+------+------+
|
5198 |
*
|
5199 |
* size: encoded in imm5 (see ARM ARM LowestSetBit())
|
5200 |
* index: encoded in imm5<4:size+1>
|
5201 |
*/
|
5202 |
static void handle_simd_inse(DisasContext *s, int rd, int rn, |
5203 |
int imm4, int imm5) |
5204 |
{ |
5205 |
int size = ctz32(imm5);
|
5206 |
int src_index, dst_index;
|
5207 |
TCGv_i64 tmp; |
5208 |
|
5209 |
if (size > 3) { |
5210 |
unallocated_encoding(s); |
5211 |
return;
|
5212 |
} |
5213 |
dst_index = extract32(imm5, 1+size, 5); |
5214 |
src_index = extract32(imm4, size, 4);
|
5215 |
|
5216 |
tmp = tcg_temp_new_i64(); |
5217 |
|
5218 |
read_vec_element(s, tmp, rn, src_index, size); |
5219 |
write_vec_element(s, tmp, rd, dst_index, size); |
5220 |
|
5221 |
tcg_temp_free_i64(tmp); |
5222 |
} |
5223 |
|
5224 |
|
5225 |
/* C6.3.151 INS (General)
|
5226 |
*
|
5227 |
* 31 21 20 16 15 10 9 5 4 0
|
5228 |
* +-----------------------+--------+-------------+------+------+
|
5229 |
* | 0 1 0 0 1 1 1 0 0 0 0 | imm5 | 0 0 0 1 1 1 | Rn | Rd |
|
5230 |
* +-----------------------+--------+-------------+------+------+
|
5231 |
*
|
5232 |
* size: encoded in imm5 (see ARM ARM LowestSetBit())
|
5233 |
* index: encoded in imm5<4:size+1>
|
5234 |
*/
|
5235 |
static void handle_simd_insg(DisasContext *s, int rd, int rn, int imm5) |
5236 |
{ |
5237 |
int size = ctz32(imm5);
|
5238 |
int idx;
|
5239 |
|
5240 |
if (size > 3) { |
5241 |
unallocated_encoding(s); |
5242 |
return;
|
5243 |
} |
5244 |
|
5245 |
idx = extract32(imm5, 1 + size, 4 - size); |
5246 |
write_vec_element(s, cpu_reg(s, rn), rd, idx, size); |
5247 |
} |
5248 |
|
5249 |
/*
|
5250 |
* C6.3.321 UMOV (General)
|
5251 |
* C6.3.237 SMOV (General)
|
5252 |
*
|
5253 |
* 31 30 29 21 20 16 15 12 10 9 5 4 0
|
5254 |
* +---+---+-------------------+--------+-------------+------+------+
|
5255 |
* | 0 | Q | 0 0 1 1 1 0 0 0 0 | imm5 | 0 0 1 U 1 1 | Rn | Rd |
|
5256 |
* +---+---+-------------------+--------+-------------+------+------+
|
5257 |
*
|
5258 |
* U: unsigned when set
|
5259 |
* size: encoded in imm5 (see ARM ARM LowestSetBit())
|
5260 |
*/
|
5261 |
static void handle_simd_umov_smov(DisasContext *s, int is_q, int is_signed, |
5262 |
int rn, int rd, int imm5) |
5263 |
{ |
5264 |
int size = ctz32(imm5);
|
5265 |
int element;
|
5266 |
TCGv_i64 tcg_rd; |
5267 |
|
5268 |
/* Check for UnallocatedEncodings */
|
5269 |
if (is_signed) {
|
5270 |
if (size > 2 || (size == 2 && !is_q)) { |
5271 |
unallocated_encoding(s); |
5272 |
return;
|
5273 |
} |
5274 |
} else {
|
5275 |
if (size > 3 |
5276 |
|| (size < 3 && is_q)
|
5277 |
|| (size == 3 && !is_q)) {
|
5278 |
unallocated_encoding(s); |
5279 |
return;
|
5280 |
} |
5281 |
} |
5282 |
element = extract32(imm5, 1+size, 4); |
5283 |
|
5284 |
tcg_rd = cpu_reg(s, rd); |
5285 |
read_vec_element(s, tcg_rd, rn, element, size | (is_signed ? MO_SIGN : 0));
|
5286 |
if (is_signed && !is_q) {
|
5287 |
tcg_gen_ext32u_i64(tcg_rd, tcg_rd); |
5288 |
} |
5289 |
} |
5290 |
|
5291 |
/* C3.6.5 AdvSIMD copy
|
5292 |
* 31 30 29 28 21 20 16 15 14 11 10 9 5 4 0
|
5293 |
* +---+---+----+-----------------+------+---+------+---+------+------+
|
5294 |
* | 0 | Q | op | 0 1 1 1 0 0 0 0 | imm5 | 0 | imm4 | 1 | Rn | Rd |
|
5295 |
* +---+---+----+-----------------+------+---+------+---+------+------+
|
5296 |
*/
|
5297 |
static void disas_simd_copy(DisasContext *s, uint32_t insn) |
5298 |
{ |
5299 |
int rd = extract32(insn, 0, 5); |
5300 |
int rn = extract32(insn, 5, 5); |
5301 |
int imm4 = extract32(insn, 11, 4); |
5302 |
int op = extract32(insn, 29, 1); |
5303 |
int is_q = extract32(insn, 30, 1); |
5304 |
int imm5 = extract32(insn, 16, 5); |
5305 |
|
5306 |
if (op) {
|
5307 |
if (is_q) {
|
5308 |
/* INS (element) */
|
5309 |
handle_simd_inse(s, rd, rn, imm4, imm5); |
5310 |
} else {
|
5311 |
unallocated_encoding(s); |
5312 |
} |
5313 |
} else {
|
5314 |
switch (imm4) {
|
5315 |
case 0: |
5316 |
/* DUP (element - vector) */
|
5317 |
handle_simd_dupe(s, is_q, rd, rn, imm5); |
5318 |
break;
|
5319 |
case 1: |
5320 |
/* DUP (general) */
|
5321 |
handle_simd_dupg(s, is_q, rd, rn, imm5); |
5322 |
break;
|
5323 |
case 3: |
5324 |
if (is_q) {
|
5325 |
/* INS (general) */
|
5326 |
handle_simd_insg(s, rd, rn, imm5); |
5327 |
} else {
|
5328 |
unallocated_encoding(s); |
5329 |
} |
5330 |
break;
|
5331 |
case 5: |
5332 |
case 7: |
5333 |
/* UMOV/SMOV (is_q indicates 32/64; imm4 indicates signedness) */
|
5334 |
handle_simd_umov_smov(s, is_q, (imm4 == 5), rn, rd, imm5);
|
5335 |
break;
|
5336 |
default:
|
5337 |
unallocated_encoding(s); |
5338 |
break;
|
5339 |
} |
5340 |
} |
5341 |
} |
5342 |
|
5343 |
/* C3.6.6 AdvSIMD modified immediate
|
5344 |
* 31 30 29 28 19 18 16 15 12 11 10 9 5 4 0
|
5345 |
* +---+---+----+---------------------+-----+-------+----+---+-------+------+
|
5346 |
* | 0 | Q | op | 0 1 1 1 1 0 0 0 0 0 | abc | cmode | o2 | 1 | defgh | Rd |
|
5347 |
* +---+---+----+---------------------+-----+-------+----+---+-------+------+
|
5348 |
*
|
5349 |
* There are a number of operations that can be carried out here:
|
5350 |
* MOVI - move (shifted) imm into register
|
5351 |
* MVNI - move inverted (shifted) imm into register
|
5352 |
* ORR - bitwise OR of (shifted) imm with register
|
5353 |
* BIC - bitwise clear of (shifted) imm with register
|
5354 |
*/
|
5355 |
static void disas_simd_mod_imm(DisasContext *s, uint32_t insn) |
5356 |
{ |
5357 |
int rd = extract32(insn, 0, 5); |
5358 |
int cmode = extract32(insn, 12, 4); |
5359 |
int cmode_3_1 = extract32(cmode, 1, 3); |
5360 |
int cmode_0 = extract32(cmode, 0, 1); |
5361 |
int o2 = extract32(insn, 11, 1); |
5362 |
uint64_t abcdefgh = extract32(insn, 5, 5) | (extract32(insn, 16, 3) << 5); |
5363 |
bool is_neg = extract32(insn, 29, 1); |
5364 |
bool is_q = extract32(insn, 30, 1); |
5365 |
uint64_t imm = 0;
|
5366 |
TCGv_i64 tcg_rd, tcg_imm; |
5367 |
int i;
|
5368 |
|
5369 |
if (o2 != 0 || ((cmode == 0xf) && is_neg && !is_q)) { |
5370 |
unallocated_encoding(s); |
5371 |
return;
|
5372 |
} |
5373 |
|
5374 |
/* See AdvSIMDExpandImm() in ARM ARM */
|
5375 |
switch (cmode_3_1) {
|
5376 |
case 0: /* Replicate(Zeros(24):imm8, 2) */ |
5377 |
case 1: /* Replicate(Zeros(16):imm8:Zeros(8), 2) */ |
5378 |
case 2: /* Replicate(Zeros(8):imm8:Zeros(16), 2) */ |
5379 |
case 3: /* Replicate(imm8:Zeros(24), 2) */ |
5380 |
{ |
5381 |
int shift = cmode_3_1 * 8; |
5382 |
imm = bitfield_replicate(abcdefgh << shift, 32);
|
5383 |
break;
|
5384 |
} |
5385 |
case 4: /* Replicate(Zeros(8):imm8, 4) */ |
5386 |
case 5: /* Replicate(imm8:Zeros(8), 4) */ |
5387 |
{ |
5388 |
int shift = (cmode_3_1 & 0x1) * 8; |
5389 |
imm = bitfield_replicate(abcdefgh << shift, 16);
|
5390 |
break;
|
5391 |
} |
5392 |
case 6: |
5393 |
if (cmode_0) {
|
5394 |
/* Replicate(Zeros(8):imm8:Ones(16), 2) */
|
5395 |
imm = (abcdefgh << 16) | 0xffff; |
5396 |
} else {
|
5397 |
/* Replicate(Zeros(16):imm8:Ones(8), 2) */
|
5398 |
imm = (abcdefgh << 8) | 0xff; |
5399 |
} |
5400 |
imm = bitfield_replicate(imm, 32);
|
5401 |
break;
|
5402 |
case 7: |
5403 |
if (!cmode_0 && !is_neg) {
|
5404 |
imm = bitfield_replicate(abcdefgh, 8);
|
5405 |
} else if (!cmode_0 && is_neg) { |
5406 |
int i;
|
5407 |
imm = 0;
|
5408 |
for (i = 0; i < 8; i++) { |
5409 |
if ((abcdefgh) & (1 << i)) { |
5410 |
imm |= 0xffULL << (i * 8); |
5411 |
} |
5412 |
} |
5413 |
} else if (cmode_0) { |
5414 |
if (is_neg) {
|
5415 |
imm = (abcdefgh & 0x3f) << 48; |
5416 |
if (abcdefgh & 0x80) { |
5417 |
imm |= 0x8000000000000000ULL;
|
5418 |
} |
5419 |
if (abcdefgh & 0x40) { |
5420 |
imm |= 0x3fc0000000000000ULL;
|
5421 |
} else {
|
5422 |
imm |= 0x4000000000000000ULL;
|
5423 |
} |
5424 |
} else {
|
5425 |
imm = (abcdefgh & 0x3f) << 19; |
5426 |
if (abcdefgh & 0x80) { |
5427 |
imm |= 0x80000000;
|
5428 |
} |
5429 |
if (abcdefgh & 0x40) { |
5430 |
imm |= 0x3e000000;
|
5431 |
} else {
|
5432 |
imm |= 0x40000000;
|
5433 |
} |
5434 |
imm |= (imm << 32);
|
5435 |
} |
5436 |
} |
5437 |
break;
|
5438 |
} |
5439 |
|
5440 |
if (cmode_3_1 != 7 && is_neg) { |
5441 |
imm = ~imm; |
5442 |
} |
5443 |
|
5444 |
tcg_imm = tcg_const_i64(imm); |
5445 |
tcg_rd = new_tmp_a64(s); |
5446 |
|
5447 |
for (i = 0; i < 2; i++) { |
5448 |
int foffs = i ? fp_reg_hi_offset(rd) : fp_reg_offset(rd, MO_64);
|
5449 |
|
5450 |
if (i == 1 && !is_q) { |
5451 |
/* non-quad ops clear high half of vector */
|
5452 |
tcg_gen_movi_i64(tcg_rd, 0);
|
5453 |
} else if ((cmode & 0x9) == 0x1 || (cmode & 0xd) == 0x9) { |
5454 |
tcg_gen_ld_i64(tcg_rd, cpu_env, foffs); |
5455 |
if (is_neg) {
|
5456 |
/* AND (BIC) */
|
5457 |
tcg_gen_and_i64(tcg_rd, tcg_rd, tcg_imm); |
5458 |
} else {
|
5459 |
/* ORR */
|
5460 |
tcg_gen_or_i64(tcg_rd, tcg_rd, tcg_imm); |
5461 |
} |
5462 |
} else {
|
5463 |
/* MOVI */
|
5464 |
tcg_gen_mov_i64(tcg_rd, tcg_imm); |
5465 |
} |
5466 |
tcg_gen_st_i64(tcg_rd, cpu_env, foffs); |
5467 |
} |
5468 |
|
5469 |
tcg_temp_free_i64(tcg_imm); |
5470 |
} |
5471 |
|
5472 |
/* C3.6.7 AdvSIMD scalar copy
|
5473 |
* 31 30 29 28 21 20 16 15 14 11 10 9 5 4 0
|
5474 |
* +-----+----+-----------------+------+---+------+---+------+------+
|
5475 |
* | 0 1 | op | 1 1 1 1 0 0 0 0 | imm5 | 0 | imm4 | 1 | Rn | Rd |
|
5476 |
* +-----+----+-----------------+------+---+------+---+------+------+
|
5477 |
*/
|
5478 |
static void disas_simd_scalar_copy(DisasContext *s, uint32_t insn) |
5479 |
{ |
5480 |
int rd = extract32(insn, 0, 5); |
5481 |
int rn = extract32(insn, 5, 5); |
5482 |
int imm4 = extract32(insn, 11, 4); |
5483 |
int imm5 = extract32(insn, 16, 5); |
5484 |
int op = extract32(insn, 29, 1); |
5485 |
|
5486 |
if (op != 0 || imm4 != 0) { |
5487 |
unallocated_encoding(s); |
5488 |
return;
|
5489 |
} |
5490 |
|
5491 |
/* DUP (element, scalar) */
|
5492 |
handle_simd_dupes(s, rd, rn, imm5); |
5493 |
} |
5494 |
|
5495 |
/* C3.6.8 AdvSIMD scalar pairwise
|
5496 |
* 31 30 29 28 24 23 22 21 17 16 12 11 10 9 5 4 0
|
5497 |
* +-----+---+-----------+------+-----------+--------+-----+------+------+
|
5498 |
* | 0 1 | U | 1 1 1 1 0 | size | 1 1 0 0 0 | opcode | 1 0 | Rn | Rd |
|
5499 |
* +-----+---+-----------+------+-----------+--------+-----+------+------+
|
5500 |
*/
|
5501 |
static void disas_simd_scalar_pairwise(DisasContext *s, uint32_t insn) |
5502 |
{ |
5503 |
unsupported_encoding(s, insn); |
5504 |
} |
5505 |
|
5506 |
/* C3.6.9 AdvSIMD scalar shift by immediate
|
5507 |
* 31 30 29 28 23 22 19 18 16 15 11 10 9 5 4 0
|
5508 |
* +-----+---+-------------+------+------+--------+---+------+------+
|
5509 |
* | 0 1 | U | 1 1 1 1 1 0 | immh | immb | opcode | 1 | Rn | Rd |
|
5510 |
* +-----+---+-------------+------+------+--------+---+------+------+
|
5511 |
*/
|
5512 |
static void disas_simd_scalar_shift_imm(DisasContext *s, uint32_t insn) |
5513 |
{ |
5514 |
unsupported_encoding(s, insn); |
5515 |
} |
5516 |
|
5517 |
/* C3.6.10 AdvSIMD scalar three different
|
5518 |
* 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0
|
5519 |
* +-----+---+-----------+------+---+------+--------+-----+------+------+
|
5520 |
* | 0 1 | U | 1 1 1 1 0 | size | 1 | Rm | opcode | 0 0 | Rn | Rd |
|
5521 |
* +-----+---+-----------+------+---+------+--------+-----+------+------+
|
5522 |
*/
|
5523 |
static void disas_simd_scalar_three_reg_diff(DisasContext *s, uint32_t insn) |
5524 |
{ |
5525 |
unsupported_encoding(s, insn); |
5526 |
} |
5527 |
|
5528 |
static void handle_3same_64(DisasContext *s, int opcode, bool u, |
5529 |
TCGv_i64 tcg_rd, TCGv_i64 tcg_rn, TCGv_i64 tcg_rm) |
5530 |
{ |
5531 |
/* Handle 64x64->64 opcodes which are shared between the scalar
|
5532 |
* and vector 3-same groups. We cover every opcode where size == 3
|
5533 |
* is valid in either the three-reg-same (integer, not pairwise)
|
5534 |
* or scalar-three-reg-same groups. (Some opcodes are not yet
|
5535 |
* implemented.)
|
5536 |
*/
|
5537 |
TCGCond cond; |
5538 |
|
5539 |
switch (opcode) {
|
5540 |
case 0x6: /* CMGT, CMHI */ |
5541 |
/* 64 bit integer comparison, result = test ? (2^64 - 1) : 0.
|
5542 |
* We implement this using setcond (test) and then negating.
|
5543 |
*/
|
5544 |
cond = u ? TCG_COND_GTU : TCG_COND_GT; |
5545 |
do_cmop:
|
5546 |
tcg_gen_setcond_i64(cond, tcg_rd, tcg_rn, tcg_rm); |
5547 |
tcg_gen_neg_i64(tcg_rd, tcg_rd); |
5548 |
break;
|
5549 |
case 0x7: /* CMGE, CMHS */ |
5550 |
cond = u ? TCG_COND_GEU : TCG_COND_GE; |
5551 |
goto do_cmop;
|
5552 |
case 0x11: /* CMTST, CMEQ */ |
5553 |
if (u) {
|
5554 |
cond = TCG_COND_EQ; |
5555 |
goto do_cmop;
|
5556 |
} |
5557 |
/* CMTST : test is "if (X & Y != 0)". */
|
5558 |
tcg_gen_and_i64(tcg_rd, tcg_rn, tcg_rm); |
5559 |
tcg_gen_setcondi_i64(TCG_COND_NE, tcg_rd, tcg_rd, 0);
|
5560 |
tcg_gen_neg_i64(tcg_rd, tcg_rd); |
5561 |
break;
|
5562 |
case 0x10: /* ADD, SUB */ |
5563 |
if (u) {
|
5564 |
tcg_gen_sub_i64(tcg_rd, tcg_rn, tcg_rm); |
5565 |
} else {
|
5566 |
tcg_gen_add_i64(tcg_rd, tcg_rn, tcg_rm); |
5567 |
} |
5568 |
break;
|
5569 |
case 0x1: /* SQADD */ |
5570 |
case 0x5: /* SQSUB */ |
5571 |
case 0x8: /* SSHL, USHL */ |
5572 |
case 0x9: /* SQSHL, UQSHL */ |
5573 |
case 0xa: /* SRSHL, URSHL */ |
5574 |
case 0xb: /* SQRSHL, UQRSHL */ |
5575 |
default:
|
5576 |
g_assert_not_reached(); |
5577 |
} |
5578 |
} |
5579 |
|
5580 |
/* Handle the 3-same-operands float operations; shared by the scalar
|
5581 |
* and vector encodings. The caller must filter out any encodings
|
5582 |
* not allocated for the encoding it is dealing with.
|
5583 |
*/
|
5584 |
static void handle_3same_float(DisasContext *s, int size, int elements, |
5585 |
int fpopcode, int rd, int rn, int rm) |
5586 |
{ |
5587 |
int pass;
|
5588 |
TCGv_ptr fpst = get_fpstatus_ptr(); |
5589 |
|
5590 |
for (pass = 0; pass < elements; pass++) { |
5591 |
if (size) {
|
5592 |
/* Double */
|
5593 |
TCGv_i64 tcg_op1 = tcg_temp_new_i64(); |
5594 |
TCGv_i64 tcg_op2 = tcg_temp_new_i64(); |
5595 |
TCGv_i64 tcg_res = tcg_temp_new_i64(); |
5596 |
|
5597 |
read_vec_element(s, tcg_op1, rn, pass, MO_64); |
5598 |
read_vec_element(s, tcg_op2, rm, pass, MO_64); |
5599 |
|
5600 |
switch (fpopcode) {
|
5601 |
case 0x18: /* FMAXNM */ |
5602 |
gen_helper_vfp_maxnumd(tcg_res, tcg_op1, tcg_op2, fpst); |
5603 |
break;
|
5604 |
case 0x1a: /* FADD */ |
5605 |
gen_helper_vfp_addd(tcg_res, tcg_op1, tcg_op2, fpst); |
5606 |
break;
|
5607 |
case 0x1e: /* FMAX */ |
5608 |
gen_helper_vfp_maxd(tcg_res, tcg_op1, tcg_op2, fpst); |
5609 |
break;
|
5610 |
case 0x38: /* FMINNM */ |
5611 |
gen_helper_vfp_minnumd(tcg_res, tcg_op1, tcg_op2, fpst); |
5612 |
break;
|
5613 |
case 0x3a: /* FSUB */ |
5614 |
gen_helper_vfp_subd(tcg_res, tcg_op1, tcg_op2, fpst); |
5615 |
break;
|
5616 |
case 0x3e: /* FMIN */ |
5617 |
gen_helper_vfp_mind(tcg_res, tcg_op1, tcg_op2, fpst); |
5618 |
break;
|
5619 |
case 0x5b: /* FMUL */ |
5620 |
gen_helper_vfp_muld(tcg_res, tcg_op1, tcg_op2, fpst); |
5621 |
break;
|
5622 |
case 0x5f: /* FDIV */ |
5623 |
gen_helper_vfp_divd(tcg_res, tcg_op1, tcg_op2, fpst); |
5624 |
break;
|
5625 |
case 0x7a: /* FABD */ |
5626 |
gen_helper_vfp_subd(tcg_res, tcg_op1, tcg_op2, fpst); |
5627 |
gen_helper_vfp_absd(tcg_res, tcg_res); |
5628 |
break;
|
5629 |
default:
|
5630 |
g_assert_not_reached(); |
5631 |
} |
5632 |
|
5633 |
write_vec_element(s, tcg_res, rd, pass, MO_64); |
5634 |
|
5635 |
tcg_temp_free_i64(tcg_res); |
5636 |
tcg_temp_free_i64(tcg_op1); |
5637 |
tcg_temp_free_i64(tcg_op2); |
5638 |
} else {
|
5639 |
/* Single */
|
5640 |
TCGv_i32 tcg_op1 = tcg_temp_new_i32(); |
5641 |
TCGv_i32 tcg_op2 = tcg_temp_new_i32(); |
5642 |
TCGv_i32 tcg_res = tcg_temp_new_i32(); |
5643 |
|
5644 |
read_vec_element_i32(s, tcg_op1, rn, pass, MO_32); |
5645 |
read_vec_element_i32(s, tcg_op2, rm, pass, MO_32); |
5646 |
|
5647 |
switch (fpopcode) {
|
5648 |
case 0x1a: /* FADD */ |
5649 |
gen_helper_vfp_adds(tcg_res, tcg_op1, tcg_op2, fpst); |
5650 |
break;
|
5651 |
case 0x1e: /* FMAX */ |
5652 |
gen_helper_vfp_maxs(tcg_res, tcg_op1, tcg_op2, fpst); |
5653 |
break;
|
5654 |
case 0x18: /* FMAXNM */ |
5655 |
gen_helper_vfp_maxnums(tcg_res, tcg_op1, tcg_op2, fpst); |
5656 |
break;
|
5657 |
case 0x38: /* FMINNM */ |
5658 |
gen_helper_vfp_minnums(tcg_res, tcg_op1, tcg_op2, fpst); |
5659 |
break;
|
5660 |
case 0x3a: /* FSUB */ |
5661 |
gen_helper_vfp_subs(tcg_res, tcg_op1, tcg_op2, fpst); |
5662 |
break;
|
5663 |
case 0x3e: /* FMIN */ |
5664 |
gen_helper_vfp_mins(tcg_res, tcg_op1, tcg_op2, fpst); |
5665 |
break;
|
5666 |
case 0x5b: /* FMUL */ |
5667 |
gen_helper_vfp_muls(tcg_res, tcg_op1, tcg_op2, fpst); |
5668 |
break;
|
5669 |
case 0x5f: /* FDIV */ |
5670 |
gen_helper_vfp_divs(tcg_res, tcg_op1, tcg_op2, fpst); |
5671 |
break;
|
5672 |
case 0x7a: /* FABD */ |
5673 |
gen_helper_vfp_subs(tcg_res, tcg_op1, tcg_op2, fpst); |
5674 |
gen_helper_vfp_abss(tcg_res, tcg_res); |
5675 |
break;
|
5676 |
default:
|
5677 |
g_assert_not_reached(); |
5678 |
} |
5679 |
|
5680 |
if (elements == 1) { |
5681 |
/* scalar single so clear high part */
|
5682 |
TCGv_i64 tcg_tmp = tcg_temp_new_i64(); |
5683 |
|
5684 |
tcg_gen_extu_i32_i64(tcg_tmp, tcg_res); |
5685 |
write_vec_element(s, tcg_tmp, rd, pass, MO_64); |
5686 |
tcg_temp_free_i64(tcg_tmp); |
5687 |
} else {
|
5688 |
write_vec_element_i32(s, tcg_res, rd, pass, MO_32); |
5689 |
} |
5690 |
|
5691 |
tcg_temp_free_i32(tcg_res); |
5692 |
tcg_temp_free_i32(tcg_op1); |
5693 |
tcg_temp_free_i32(tcg_op2); |
5694 |
} |
5695 |
} |
5696 |
|
5697 |
tcg_temp_free_ptr(fpst); |
5698 |
|
5699 |
if ((elements << size) < 4) { |
5700 |
/* scalar, or non-quad vector op */
|
5701 |
clear_vec_high(s, rd); |
5702 |
} |
5703 |
} |
5704 |
|
5705 |
/* C3.6.11 AdvSIMD scalar three same
|
5706 |
* 31 30 29 28 24 23 22 21 20 16 15 11 10 9 5 4 0
|
5707 |
* +-----+---+-----------+------+---+------+--------+---+------+------+
|
5708 |
* | 0 1 | U | 1 1 1 1 0 | size | 1 | Rm | opcode | 1 | Rn | Rd |
|
5709 |
* +-----+---+-----------+------+---+------+--------+---+------+------+
|
5710 |
*/
|
5711 |
static void disas_simd_scalar_three_reg_same(DisasContext *s, uint32_t insn) |
5712 |
{ |
5713 |
int rd = extract32(insn, 0, 5); |
5714 |
int rn = extract32(insn, 5, 5); |
5715 |
int opcode = extract32(insn, 11, 5); |
5716 |
int rm = extract32(insn, 16, 5); |
5717 |
int size = extract32(insn, 22, 2); |
5718 |
bool u = extract32(insn, 29, 1); |
5719 |
TCGv_i64 tcg_rn; |
5720 |
TCGv_i64 tcg_rm; |
5721 |
TCGv_i64 tcg_rd; |
5722 |
|
5723 |
if (opcode >= 0x18) { |
5724 |
/* Floating point: U, size[1] and opcode indicate operation */
|
5725 |
int fpopcode = opcode | (extract32(size, 1, 1) << 5) | (u << 6); |
5726 |
switch (fpopcode) {
|
5727 |
case 0x1b: /* FMULX */ |
5728 |
case 0x1c: /* FCMEQ */ |
5729 |
case 0x1f: /* FRECPS */ |
5730 |
case 0x3f: /* FRSQRTS */ |
5731 |
case 0x5c: /* FCMGE */ |
5732 |
case 0x5d: /* FACGE */ |
5733 |
case 0x7c: /* FCMGT */ |
5734 |
case 0x7d: /* FACGT */ |
5735 |
unsupported_encoding(s, insn); |
5736 |
return;
|
5737 |
case 0x7a: /* FABD */ |
5738 |
break;
|
5739 |
default:
|
5740 |
unallocated_encoding(s); |
5741 |
return;
|
5742 |
} |
5743 |
|
5744 |
handle_3same_float(s, extract32(size, 0, 1), 1, fpopcode, rd, rn, rm); |
5745 |
return;
|
5746 |
} |
5747 |
|
5748 |
switch (opcode) {
|
5749 |
case 0x1: /* SQADD, UQADD */ |
5750 |
case 0x5: /* SQSUB, UQSUB */ |
5751 |
case 0x8: /* SSHL, USHL */ |
5752 |
case 0xa: /* SRSHL, URSHL */ |
5753 |
unsupported_encoding(s, insn); |
5754 |
return;
|
5755 |
case 0x6: /* CMGT, CMHI */ |
5756 |
case 0x7: /* CMGE, CMHS */ |
5757 |
case 0x11: /* CMTST, CMEQ */ |
5758 |
case 0x10: /* ADD, SUB (vector) */ |
5759 |
if (size != 3) { |
5760 |
unallocated_encoding(s); |
5761 |
return;
|
5762 |
} |
5763 |
break;
|
5764 |
case 0x9: /* SQSHL, UQSHL */ |
5765 |
case 0xb: /* SQRSHL, UQRSHL */ |
5766 |
unsupported_encoding(s, insn); |
5767 |
return;
|
5768 |
case 0x16: /* SQDMULH, SQRDMULH (vector) */ |
5769 |
if (size != 1 && size != 2) { |
5770 |
unallocated_encoding(s); |
5771 |
return;
|
5772 |
} |
5773 |
unsupported_encoding(s, insn); |
5774 |
return;
|
5775 |
default:
|
5776 |
unallocated_encoding(s); |
5777 |
return;
|
5778 |
} |
5779 |
|
5780 |
tcg_rn = read_fp_dreg(s, rn); /* op1 */
|
5781 |
tcg_rm = read_fp_dreg(s, rm); /* op2 */
|
5782 |
tcg_rd = tcg_temp_new_i64(); |
5783 |
|
5784 |
/* For the moment we only support the opcodes which are
|
5785 |
* 64-bit-width only. The size != 3 cases will
|
5786 |
* be handled later when the relevant ops are implemented.
|
5787 |
*/
|
5788 |
handle_3same_64(s, opcode, u, tcg_rd, tcg_rn, tcg_rm); |
5789 |
|
5790 |
write_fp_dreg(s, rd, tcg_rd); |
5791 |
|
5792 |
tcg_temp_free_i64(tcg_rn); |
5793 |
tcg_temp_free_i64(tcg_rm); |
5794 |
tcg_temp_free_i64(tcg_rd); |
5795 |
} |
5796 |
|
5797 |
/* C3.6.12 AdvSIMD scalar two reg misc
|
5798 |
* 31 30 29 28 24 23 22 21 17 16 12 11 10 9 5 4 0
|
5799 |
* +-----+---+-----------+------+-----------+--------+-----+------+------+
|
5800 |
* | 0 1 | U | 1 1 1 1 0 | size | 1 0 0 0 0 | opcode | 1 0 | Rn | Rd |
|
5801 |
* +-----+---+-----------+------+-----------+--------+-----+------+------+
|
5802 |
*/
|
5803 |
static void disas_simd_scalar_two_reg_misc(DisasContext *s, uint32_t insn) |
5804 |
{ |
5805 |
unsupported_encoding(s, insn); |
5806 |
} |
5807 |
|
5808 |
/* C3.6.13 AdvSIMD scalar x indexed element
|
5809 |
* 31 30 29 28 24 23 22 21 20 19 16 15 12 11 10 9 5 4 0
|
5810 |
* +-----+---+-----------+------+---+---+------+-----+---+---+------+------+
|
5811 |
* | 0 1 | U | 1 1 1 1 1 | size | L | M | Rm | opc | H | 0 | Rn | Rd |
|
5812 |
* +-----+---+-----------+------+---+---+------+-----+---+---+------+------+
|
5813 |
*/
|
5814 |
static void disas_simd_scalar_indexed(DisasContext *s, uint32_t insn) |
5815 |
{ |
5816 |
unsupported_encoding(s, insn); |
5817 |
} |
5818 |
|
5819 |
/* C3.6.14 AdvSIMD shift by immediate
|
5820 |
* 31 30 29 28 23 22 19 18 16 15 11 10 9 5 4 0
|
5821 |
* +---+---+---+-------------+------+------+--------+---+------+------+
|
5822 |
* | 0 | Q | U | 0 1 1 1 1 0 | immh | immb | opcode | 1 | Rn | Rd |
|
5823 |
* +---+---+---+-------------+------+------+--------+---+------+------+
|
5824 |
*/
|
5825 |
static void disas_simd_shift_imm(DisasContext *s, uint32_t insn) |
5826 |
{ |
5827 |
unsupported_encoding(s, insn); |
5828 |
} |
5829 |
|
5830 |
static void handle_3rd_widening(DisasContext *s, int is_q, int is_u, int size, |
5831 |
int opcode, int rd, int rn, int rm) |
5832 |
{ |
5833 |
/* 3-reg-different widening insns: 64 x 64 -> 128 */
|
5834 |
TCGv_i64 tcg_res[2];
|
5835 |
int pass, accop;
|
5836 |
|
5837 |
tcg_res[0] = tcg_temp_new_i64();
|
5838 |
tcg_res[1] = tcg_temp_new_i64();
|
5839 |
|
5840 |
/* Does this op do an adding accumulate, a subtracting accumulate,
|
5841 |
* or no accumulate at all?
|
5842 |
*/
|
5843 |
switch (opcode) {
|
5844 |
case 5: |
5845 |
case 8: |
5846 |
case 9: |
5847 |
accop = 1;
|
5848 |
break;
|
5849 |
case 10: |
5850 |
case 11: |
5851 |
accop = -1;
|
5852 |
break;
|
5853 |
default:
|
5854 |
accop = 0;
|
5855 |
break;
|
5856 |
} |
5857 |
|
5858 |
if (accop != 0) { |
5859 |
read_vec_element(s, tcg_res[0], rd, 0, MO_64); |
5860 |
read_vec_element(s, tcg_res[1], rd, 1, MO_64); |
5861 |
} |
5862 |
|
5863 |
/* size == 2 means two 32x32->64 operations; this is worth special
|
5864 |
* casing because we can generally handle it inline.
|
5865 |
*/
|
5866 |
if (size == 2) { |
5867 |
for (pass = 0; pass < 2; pass++) { |
5868 |
TCGv_i64 tcg_op1 = tcg_temp_new_i64(); |
5869 |
TCGv_i64 tcg_op2 = tcg_temp_new_i64(); |
5870 |
TCGv_i64 tcg_passres; |
5871 |
TCGMemOp memop = MO_32 | (is_u ? 0 : MO_SIGN);
|
5872 |
|
5873 |
int elt = pass + is_q * 2; |
5874 |
|
5875 |
read_vec_element(s, tcg_op1, rn, elt, memop); |
5876 |
read_vec_element(s, tcg_op2, rm, elt, memop); |
5877 |
|
5878 |
if (accop == 0) { |
5879 |
tcg_passres = tcg_res[pass]; |
5880 |
} else {
|
5881 |
tcg_passres = tcg_temp_new_i64(); |
5882 |
} |
5883 |
|
5884 |
switch (opcode) {
|
5885 |
case 5: /* SABAL, SABAL2, UABAL, UABAL2 */ |
5886 |
case 7: /* SABDL, SABDL2, UABDL, UABDL2 */ |
5887 |
{ |
5888 |
TCGv_i64 tcg_tmp1 = tcg_temp_new_i64(); |
5889 |
TCGv_i64 tcg_tmp2 = tcg_temp_new_i64(); |
5890 |
|
5891 |
tcg_gen_sub_i64(tcg_tmp1, tcg_op1, tcg_op2); |
5892 |
tcg_gen_sub_i64(tcg_tmp2, tcg_op2, tcg_op1); |
5893 |
tcg_gen_movcond_i64(is_u ? TCG_COND_GEU : TCG_COND_GE, |
5894 |
tcg_passres, |
5895 |
tcg_op1, tcg_op2, tcg_tmp1, tcg_tmp2); |
5896 |
tcg_temp_free_i64(tcg_tmp1); |
5897 |
tcg_temp_free_i64(tcg_tmp2); |
5898 |
break;
|
5899 |
} |
5900 |
case 8: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */ |
5901 |
case 10: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */ |
5902 |
case 12: /* UMULL, UMULL2, SMULL, SMULL2 */ |
5903 |
tcg_gen_mul_i64(tcg_passres, tcg_op1, tcg_op2); |
5904 |
break;
|
5905 |
default:
|
5906 |
g_assert_not_reached(); |
5907 |
} |
5908 |
|
5909 |
if (accop > 0) { |
5910 |
tcg_gen_add_i64(tcg_res[pass], tcg_res[pass], tcg_passres); |
5911 |
tcg_temp_free_i64(tcg_passres); |
5912 |
} else if (accop < 0) { |
5913 |
tcg_gen_sub_i64(tcg_res[pass], tcg_res[pass], tcg_passres); |
5914 |
tcg_temp_free_i64(tcg_passres); |
5915 |
} |
5916 |
|
5917 |
tcg_temp_free_i64(tcg_op1); |
5918 |
tcg_temp_free_i64(tcg_op2); |
5919 |
} |
5920 |
} else {
|
5921 |
/* size 0 or 1, generally helper functions */
|
5922 |
for (pass = 0; pass < 2; pass++) { |
5923 |
TCGv_i32 tcg_op1 = tcg_temp_new_i32(); |
5924 |
TCGv_i32 tcg_op2 = tcg_temp_new_i32(); |
5925 |
TCGv_i64 tcg_passres; |
5926 |
int elt = pass + is_q * 2; |
5927 |
|
5928 |
read_vec_element_i32(s, tcg_op1, rn, elt, MO_32); |
5929 |
read_vec_element_i32(s, tcg_op2, rm, elt, MO_32); |
5930 |
|
5931 |
if (accop == 0) { |
5932 |
tcg_passres = tcg_res[pass]; |
5933 |
} else {
|
5934 |
tcg_passres = tcg_temp_new_i64(); |
5935 |
} |
5936 |
|
5937 |
switch (opcode) {
|
5938 |
case 5: /* SABAL, SABAL2, UABAL, UABAL2 */ |
5939 |
case 7: /* SABDL, SABDL2, UABDL, UABDL2 */ |
5940 |
if (size == 0) { |
5941 |
if (is_u) {
|
5942 |
gen_helper_neon_abdl_u16(tcg_passres, tcg_op1, tcg_op2); |
5943 |
} else {
|
5944 |
gen_helper_neon_abdl_s16(tcg_passres, tcg_op1, tcg_op2); |
5945 |
} |
5946 |
} else {
|
5947 |
if (is_u) {
|
5948 |
gen_helper_neon_abdl_u32(tcg_passres, tcg_op1, tcg_op2); |
5949 |
} else {
|
5950 |
gen_helper_neon_abdl_s32(tcg_passres, tcg_op1, tcg_op2); |
5951 |
} |
5952 |
} |
5953 |
break;
|
5954 |
case 8: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */ |
5955 |
case 10: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */ |
5956 |
case 12: /* UMULL, UMULL2, SMULL, SMULL2 */ |
5957 |
if (size == 0) { |
5958 |
if (is_u) {
|
5959 |
gen_helper_neon_mull_u8(tcg_passres, tcg_op1, tcg_op2); |
5960 |
} else {
|
5961 |
gen_helper_neon_mull_s8(tcg_passres, tcg_op1, tcg_op2); |
5962 |
} |
5963 |
} else {
|
5964 |
if (is_u) {
|
5965 |
gen_helper_neon_mull_u16(tcg_passres, tcg_op1, tcg_op2); |
5966 |
} else {
|
5967 |
gen_helper_neon_mull_s16(tcg_passres, tcg_op1, tcg_op2); |
5968 |
} |
5969 |
} |
5970 |
break;
|
5971 |
default:
|
5972 |
g_assert_not_reached(); |
5973 |
} |
5974 |
tcg_temp_free_i32(tcg_op1); |
5975 |
tcg_temp_free_i32(tcg_op2); |
5976 |
|
5977 |
if (accop > 0) { |
5978 |
if (size == 0) { |
5979 |
gen_helper_neon_addl_u16(tcg_res[pass], tcg_res[pass], |
5980 |
tcg_passres); |
5981 |
} else {
|
5982 |
gen_helper_neon_addl_u32(tcg_res[pass], tcg_res[pass], |
5983 |
tcg_passres); |
5984 |
} |
5985 |
tcg_temp_free_i64(tcg_passres); |
5986 |
} else if (accop < 0) { |
5987 |
if (size == 0) { |
5988 |
gen_helper_neon_subl_u16(tcg_res[pass], tcg_res[pass], |
5989 |
tcg_passres); |
5990 |
} else {
|
5991 |
gen_helper_neon_subl_u32(tcg_res[pass], tcg_res[pass], |
5992 |
tcg_passres); |
5993 |
} |
5994 |
tcg_temp_free_i64(tcg_passres); |
5995 |
} |
5996 |
} |
5997 |
} |
5998 |
|
5999 |
write_vec_element(s, tcg_res[0], rd, 0, MO_64); |
6000 |
write_vec_element(s, tcg_res[1], rd, 1, MO_64); |
6001 |
tcg_temp_free_i64(tcg_res[0]);
|
6002 |
tcg_temp_free_i64(tcg_res[1]);
|
6003 |
} |
6004 |
|
6005 |
/* C3.6.15 AdvSIMD three different
|
6006 |
* 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0
|
6007 |
* +---+---+---+-----------+------+---+------+--------+-----+------+------+
|
6008 |
* | 0 | Q | U | 0 1 1 1 0 | size | 1 | Rm | opcode | 0 0 | Rn | Rd |
|
6009 |
* +---+---+---+-----------+------+---+------+--------+-----+------+------+
|
6010 |
*/
|
6011 |
static void disas_simd_three_reg_diff(DisasContext *s, uint32_t insn) |
6012 |
{ |
6013 |
/* Instructions in this group fall into three basic classes
|
6014 |
* (in each case with the operation working on each element in
|
6015 |
* the input vectors):
|
6016 |
* (1) widening 64 x 64 -> 128 (with possibly Vd as an extra
|
6017 |
* 128 bit input)
|
6018 |
* (2) wide 64 x 128 -> 128
|
6019 |
* (3) narrowing 128 x 128 -> 64
|
6020 |
* Here we do initial decode, catch unallocated cases and
|
6021 |
* dispatch to separate functions for each class.
|
6022 |
*/
|
6023 |
int is_q = extract32(insn, 30, 1); |
6024 |
int is_u = extract32(insn, 29, 1); |
6025 |
int size = extract32(insn, 22, 2); |
6026 |
int opcode = extract32(insn, 12, 4); |
6027 |
int rm = extract32(insn, 16, 5); |
6028 |
int rn = extract32(insn, 5, 5); |
6029 |
int rd = extract32(insn, 0, 5); |
6030 |
|
6031 |
switch (opcode) {
|
6032 |
case 1: /* SADDW, SADDW2, UADDW, UADDW2 */ |
6033 |
case 3: /* SSUBW, SSUBW2, USUBW, USUBW2 */ |
6034 |
/* 64 x 128 -> 128 */
|
6035 |
unsupported_encoding(s, insn); |
6036 |
break;
|
6037 |
case 4: /* ADDHN, ADDHN2, RADDHN, RADDHN2 */ |
6038 |
case 6: /* SUBHN, SUBHN2, RSUBHN, RSUBHN2 */ |
6039 |
/* 128 x 128 -> 64 */
|
6040 |
unsupported_encoding(s, insn); |
6041 |
break;
|
6042 |
case 9: |
6043 |
case 11: |
6044 |
case 13: |
6045 |
case 14: |
6046 |
if (is_u) {
|
6047 |
unallocated_encoding(s); |
6048 |
return;
|
6049 |
} |
6050 |
/* fall through */
|
6051 |
case 0: |
6052 |
case 2: |
6053 |
unsupported_encoding(s, insn); |
6054 |
break;
|
6055 |
case 5: |
6056 |
case 7: |
6057 |
case 8: |
6058 |
case 10: |
6059 |
case 12: |
6060 |
/* 64 x 64 -> 128 */
|
6061 |
if (size == 3) { |
6062 |
unallocated_encoding(s); |
6063 |
return;
|
6064 |
} |
6065 |
handle_3rd_widening(s, is_q, is_u, size, opcode, rd, rn, rm); |
6066 |
break;
|
6067 |
default:
|
6068 |
/* opcode 15 not allocated */
|
6069 |
unallocated_encoding(s); |
6070 |
break;
|
6071 |
} |
6072 |
} |
6073 |
|
6074 |
/* Logic op (opcode == 3) subgroup of C3.6.16. */
|
6075 |
static void disas_simd_3same_logic(DisasContext *s, uint32_t insn) |
6076 |
{ |
6077 |
int rd = extract32(insn, 0, 5); |
6078 |
int rn = extract32(insn, 5, 5); |
6079 |
int rm = extract32(insn, 16, 5); |
6080 |
int size = extract32(insn, 22, 2); |
6081 |
bool is_u = extract32(insn, 29, 1); |
6082 |
bool is_q = extract32(insn, 30, 1); |
6083 |
TCGv_i64 tcg_op1 = tcg_temp_new_i64(); |
6084 |
TCGv_i64 tcg_op2 = tcg_temp_new_i64(); |
6085 |
TCGv_i64 tcg_res[2];
|
6086 |
int pass;
|
6087 |
|
6088 |
tcg_res[0] = tcg_temp_new_i64();
|
6089 |
tcg_res[1] = tcg_temp_new_i64();
|
6090 |
|
6091 |
for (pass = 0; pass < (is_q ? 2 : 1); pass++) { |
6092 |
read_vec_element(s, tcg_op1, rn, pass, MO_64); |
6093 |
read_vec_element(s, tcg_op2, rm, pass, MO_64); |
6094 |
|
6095 |
if (!is_u) {
|
6096 |
switch (size) {
|
6097 |
case 0: /* AND */ |
6098 |
tcg_gen_and_i64(tcg_res[pass], tcg_op1, tcg_op2); |
6099 |
break;
|
6100 |
case 1: /* BIC */ |
6101 |
tcg_gen_andc_i64(tcg_res[pass], tcg_op1, tcg_op2); |
6102 |
break;
|
6103 |
case 2: /* ORR */ |
6104 |
tcg_gen_or_i64(tcg_res[pass], tcg_op1, tcg_op2); |
6105 |
break;
|
6106 |
case 3: /* ORN */ |
6107 |
tcg_gen_orc_i64(tcg_res[pass], tcg_op1, tcg_op2); |
6108 |
break;
|
6109 |
} |
6110 |
} else {
|
6111 |
if (size != 0) { |
6112 |
/* B* ops need res loaded to operate on */
|
6113 |
read_vec_element(s, tcg_res[pass], rd, pass, MO_64); |
6114 |
} |
6115 |
|
6116 |
switch (size) {
|
6117 |
case 0: /* EOR */ |
6118 |
tcg_gen_xor_i64(tcg_res[pass], tcg_op1, tcg_op2); |
6119 |
break;
|
6120 |
case 1: /* BSL bitwise select */ |
6121 |
tcg_gen_xor_i64(tcg_op1, tcg_op1, tcg_op2); |
6122 |
tcg_gen_and_i64(tcg_op1, tcg_op1, tcg_res[pass]); |
6123 |
tcg_gen_xor_i64(tcg_res[pass], tcg_op2, tcg_op1); |
6124 |
break;
|
6125 |
case 2: /* BIT, bitwise insert if true */ |
6126 |
tcg_gen_xor_i64(tcg_op1, tcg_op1, tcg_res[pass]); |
6127 |
tcg_gen_and_i64(tcg_op1, tcg_op1, tcg_op2); |
6128 |
tcg_gen_xor_i64(tcg_res[pass], tcg_res[pass], tcg_op1); |
6129 |
break;
|
6130 |
case 3: /* BIF, bitwise insert if false */ |
6131 |
tcg_gen_xor_i64(tcg_op1, tcg_op1, tcg_res[pass]); |
6132 |
tcg_gen_andc_i64(tcg_op1, tcg_op1, tcg_op2); |
6133 |
tcg_gen_xor_i64(tcg_res[pass], tcg_res[pass], tcg_op1); |
6134 |
break;
|
6135 |
} |
6136 |
} |
6137 |
} |
6138 |
|
6139 |
write_vec_element(s, tcg_res[0], rd, 0, MO_64); |
6140 |
if (!is_q) {
|
6141 |
tcg_gen_movi_i64(tcg_res[1], 0); |
6142 |
} |
6143 |
write_vec_element(s, tcg_res[1], rd, 1, MO_64); |
6144 |
|
6145 |
tcg_temp_free_i64(tcg_op1); |
6146 |
tcg_temp_free_i64(tcg_op2); |
6147 |
tcg_temp_free_i64(tcg_res[0]);
|
6148 |
tcg_temp_free_i64(tcg_res[1]);
|
6149 |
} |
6150 |
|
6151 |
/* Pairwise op subgroup of C3.6.16. */
|
6152 |
static void disas_simd_3same_pair(DisasContext *s, uint32_t insn) |
6153 |
{ |
6154 |
unsupported_encoding(s, insn); |
6155 |
} |
6156 |
|
6157 |
/* Floating point op subgroup of C3.6.16. */
|
6158 |
static void disas_simd_3same_float(DisasContext *s, uint32_t insn) |
6159 |
{ |
6160 |
/* For floating point ops, the U, size[1] and opcode bits
|
6161 |
* together indicate the operation. size[0] indicates single
|
6162 |
* or double.
|
6163 |
*/
|
6164 |
int fpopcode = extract32(insn, 11, 5) |
6165 |
| (extract32(insn, 23, 1) << 5) |
6166 |
| (extract32(insn, 29, 1) << 6); |
6167 |
int is_q = extract32(insn, 30, 1); |
6168 |
int size = extract32(insn, 22, 1); |
6169 |
int rm = extract32(insn, 16, 5); |
6170 |
int rn = extract32(insn, 5, 5); |
6171 |
int rd = extract32(insn, 0, 5); |
6172 |
|
6173 |
int datasize = is_q ? 128 : 64; |
6174 |
int esize = 32 << size; |
6175 |
int elements = datasize / esize;
|
6176 |
|
6177 |
if (size == 1 && !is_q) { |
6178 |
unallocated_encoding(s); |
6179 |
return;
|
6180 |
} |
6181 |
|
6182 |
switch (fpopcode) {
|
6183 |
case 0x58: /* FMAXNMP */ |
6184 |
case 0x5a: /* FADDP */ |
6185 |
case 0x5e: /* FMAXP */ |
6186 |
case 0x78: /* FMINNMP */ |
6187 |
case 0x7e: /* FMINP */ |
6188 |
/* pairwise ops */
|
6189 |
unsupported_encoding(s, insn); |
6190 |
return;
|
6191 |
case 0x1b: /* FMULX */ |
6192 |
case 0x1c: /* FCMEQ */ |
6193 |
case 0x1f: /* FRECPS */ |
6194 |
case 0x3f: /* FRSQRTS */ |
6195 |
case 0x5c: /* FCMGE */ |
6196 |
case 0x5d: /* FACGE */ |
6197 |
case 0x7c: /* FCMGT */ |
6198 |
case 0x7d: /* FACGT */ |
6199 |
case 0x19: /* FMLA */ |
6200 |
case 0x39: /* FMLS */ |
6201 |
unsupported_encoding(s, insn); |
6202 |
return;
|
6203 |
case 0x18: /* FMAXNM */ |
6204 |
case 0x1a: /* FADD */ |
6205 |
case 0x1e: /* FMAX */ |
6206 |
case 0x38: /* FMINNM */ |
6207 |
case 0x3a: /* FSUB */ |
6208 |
case 0x3e: /* FMIN */ |
6209 |
case 0x5b: /* FMUL */ |
6210 |
case 0x5f: /* FDIV */ |
6211 |
case 0x7a: /* FABD */ |
6212 |
handle_3same_float(s, size, elements, fpopcode, rd, rn, rm); |
6213 |
return;
|
6214 |
default:
|
6215 |
unallocated_encoding(s); |
6216 |
return;
|
6217 |
} |
6218 |
} |
6219 |
|
6220 |
/* Integer op subgroup of C3.6.16. */
|
6221 |
static void disas_simd_3same_int(DisasContext *s, uint32_t insn) |
6222 |
{ |
6223 |
int is_q = extract32(insn, 30, 1); |
6224 |
int u = extract32(insn, 29, 1); |
6225 |
int size = extract32(insn, 22, 2); |
6226 |
int opcode = extract32(insn, 11, 5); |
6227 |
int rm = extract32(insn, 16, 5); |
6228 |
int rn = extract32(insn, 5, 5); |
6229 |
int rd = extract32(insn, 0, 5); |
6230 |
int pass;
|
6231 |
|
6232 |
switch (opcode) {
|
6233 |
case 0x13: /* MUL, PMUL */ |
6234 |
if (u && size != 0) { |
6235 |
unallocated_encoding(s); |
6236 |
return;
|
6237 |
} |
6238 |
/* fall through */
|
6239 |
case 0x0: /* SHADD, UHADD */ |
6240 |
case 0x2: /* SRHADD, URHADD */ |
6241 |
case 0x4: /* SHSUB, UHSUB */ |
6242 |
case 0xc: /* SMAX, UMAX */ |
6243 |
case 0xd: /* SMIN, UMIN */ |
6244 |
case 0xe: /* SABD, UABD */ |
6245 |
case 0xf: /* SABA, UABA */ |
6246 |
case 0x12: /* MLA, MLS */ |
6247 |
if (size == 3) { |
6248 |
unallocated_encoding(s); |
6249 |
return;
|
6250 |
} |
6251 |
unsupported_encoding(s, insn); |
6252 |
return;
|
6253 |
case 0x1: /* SQADD */ |
6254 |
case 0x5: /* SQSUB */ |
6255 |
case 0x8: /* SSHL, USHL */ |
6256 |
case 0x9: /* SQSHL, UQSHL */ |
6257 |
case 0xa: /* SRSHL, URSHL */ |
6258 |
case 0xb: /* SQRSHL, UQRSHL */ |
6259 |
if (size == 3 && !is_q) { |
6260 |
unallocated_encoding(s); |
6261 |
return;
|
6262 |
} |
6263 |
unsupported_encoding(s, insn); |
6264 |
return;
|
6265 |
case 0x16: /* SQDMULH, SQRDMULH */ |
6266 |
if (size == 0 || size == 3) { |
6267 |
unallocated_encoding(s); |
6268 |
return;
|
6269 |
} |
6270 |
unsupported_encoding(s, insn); |
6271 |
return;
|
6272 |
default:
|
6273 |
if (size == 3 && !is_q) { |
6274 |
unallocated_encoding(s); |
6275 |
return;
|
6276 |
} |
6277 |
break;
|
6278 |
} |
6279 |
|
6280 |
if (size == 3) { |
6281 |
for (pass = 0; pass < (is_q ? 2 : 1); pass++) { |
6282 |
TCGv_i64 tcg_op1 = tcg_temp_new_i64(); |
6283 |
TCGv_i64 tcg_op2 = tcg_temp_new_i64(); |
6284 |
TCGv_i64 tcg_res = tcg_temp_new_i64(); |
6285 |
|
6286 |
read_vec_element(s, tcg_op1, rn, pass, MO_64); |
6287 |
read_vec_element(s, tcg_op2, rm, pass, MO_64); |
6288 |
|
6289 |
handle_3same_64(s, opcode, u, tcg_res, tcg_op1, tcg_op2); |
6290 |
|
6291 |
write_vec_element(s, tcg_res, rd, pass, MO_64); |
6292 |
|
6293 |
tcg_temp_free_i64(tcg_res); |
6294 |
tcg_temp_free_i64(tcg_op1); |
6295 |
tcg_temp_free_i64(tcg_op2); |
6296 |
} |
6297 |
} else {
|
6298 |
for (pass = 0; pass < (is_q ? 4 : 2); pass++) { |
6299 |
TCGv_i32 tcg_op1 = tcg_temp_new_i32(); |
6300 |
TCGv_i32 tcg_op2 = tcg_temp_new_i32(); |
6301 |
TCGv_i32 tcg_res = tcg_temp_new_i32(); |
6302 |
NeonGenTwoOpFn *genfn; |
6303 |
|
6304 |
read_vec_element_i32(s, tcg_op1, rn, pass, MO_32); |
6305 |
read_vec_element_i32(s, tcg_op2, rm, pass, MO_32); |
6306 |
|
6307 |
switch (opcode) {
|
6308 |
case 0x6: /* CMGT, CMHI */ |
6309 |
{ |
6310 |
static NeonGenTwoOpFn * const fns[3][2] = { |
6311 |
{ gen_helper_neon_cgt_s8, gen_helper_neon_cgt_u8 }, |
6312 |
{ gen_helper_neon_cgt_s16, gen_helper_neon_cgt_u16 }, |
6313 |
{ gen_helper_neon_cgt_s32, gen_helper_neon_cgt_u32 }, |
6314 |
}; |
6315 |
genfn = fns[size][u]; |
6316 |
break;
|
6317 |
} |
6318 |
case 0x7: /* CMGE, CMHS */ |
6319 |
{ |
6320 |
static NeonGenTwoOpFn * const fns[3][2] = { |
6321 |
{ gen_helper_neon_cge_s8, gen_helper_neon_cge_u8 }, |
6322 |
{ gen_helper_neon_cge_s16, gen_helper_neon_cge_u16 }, |
6323 |
{ gen_helper_neon_cge_s32, gen_helper_neon_cge_u32 }, |
6324 |
}; |
6325 |
genfn = fns[size][u]; |
6326 |
break;
|
6327 |
} |
6328 |
case 0x10: /* ADD, SUB */ |
6329 |
{ |
6330 |
static NeonGenTwoOpFn * const fns[3][2] = { |
6331 |
{ gen_helper_neon_add_u8, gen_helper_neon_sub_u8 }, |
6332 |
{ gen_helper_neon_add_u16, gen_helper_neon_sub_u16 }, |
6333 |
{ tcg_gen_add_i32, tcg_gen_sub_i32 }, |
6334 |
}; |
6335 |
genfn = fns[size][u]; |
6336 |
break;
|
6337 |
} |
6338 |
case 0x11: /* CMTST, CMEQ */ |
6339 |
{ |
6340 |
static NeonGenTwoOpFn * const fns[3][2] = { |
6341 |
{ gen_helper_neon_tst_u8, gen_helper_neon_ceq_u8 }, |
6342 |
{ gen_helper_neon_tst_u16, gen_helper_neon_ceq_u16 }, |
6343 |
{ gen_helper_neon_tst_u32, gen_helper_neon_ceq_u32 }, |
6344 |
}; |
6345 |
genfn = fns[size][u]; |
6346 |
break;
|
6347 |
} |
6348 |
default:
|
6349 |
g_assert_not_reached(); |
6350 |
} |
6351 |
|
6352 |
genfn(tcg_res, tcg_op1, tcg_op2); |
6353 |
|
6354 |
write_vec_element_i32(s, tcg_res, rd, pass, MO_32); |
6355 |
|
6356 |
tcg_temp_free_i32(tcg_res); |
6357 |
tcg_temp_free_i32(tcg_op1); |
6358 |
tcg_temp_free_i32(tcg_op2); |
6359 |
} |
6360 |
} |
6361 |
|
6362 |
if (!is_q) {
|
6363 |
clear_vec_high(s, rd); |
6364 |
} |
6365 |
} |
6366 |
|
6367 |
/* C3.6.16 AdvSIMD three same
|
6368 |
* 31 30 29 28 24 23 22 21 20 16 15 11 10 9 5 4 0
|
6369 |
* +---+---+---+-----------+------+---+------+--------+---+------+------+
|
6370 |
* | 0 | Q | U | 0 1 1 1 0 | size | 1 | Rm | opcode | 1 | Rn | Rd |
|
6371 |
* +---+---+---+-----------+------+---+------+--------+---+------+------+
|
6372 |
*/
|
6373 |
static void disas_simd_three_reg_same(DisasContext *s, uint32_t insn) |
6374 |
{ |
6375 |
int opcode = extract32(insn, 11, 5); |
6376 |
|
6377 |
switch (opcode) {
|
6378 |
case 0x3: /* logic ops */ |
6379 |
disas_simd_3same_logic(s, insn); |
6380 |
break;
|
6381 |
case 0x17: /* ADDP */ |
6382 |
case 0x14: /* SMAXP, UMAXP */ |
6383 |
case 0x15: /* SMINP, UMINP */ |
6384 |
/* Pairwise operations */
|
6385 |
disas_simd_3same_pair(s, insn); |
6386 |
break;
|
6387 |
case 0x18 ... 0x31: |
6388 |
/* floating point ops, sz[1] and U are part of opcode */
|
6389 |
disas_simd_3same_float(s, insn); |
6390 |
break;
|
6391 |
default:
|
6392 |
disas_simd_3same_int(s, insn); |
6393 |
break;
|
6394 |
} |
6395 |
} |
6396 |
|
6397 |
/* C3.6.17 AdvSIMD two reg misc
|
6398 |
* 31 30 29 28 24 23 22 21 17 16 12 11 10 9 5 4 0
|
6399 |
* +---+---+---+-----------+------+-----------+--------+-----+------+------+
|
6400 |
* | 0 | Q | U | 0 1 1 1 0 | size | 1 0 0 0 0 | opcode | 1 0 | Rn | Rd |
|
6401 |
* +---+---+---+-----------+------+-----------+--------+-----+------+------+
|
6402 |
*/
|
6403 |
static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn) |
6404 |
{ |
6405 |
unsupported_encoding(s, insn); |
6406 |
} |
6407 |
|
6408 |
/* C3.6.18 AdvSIMD vector x indexed element
|
6409 |
* 31 30 29 28 24 23 22 21 20 19 16 15 12 11 10 9 5 4 0
|
6410 |
* +---+---+---+-----------+------+---+---+------+-----+---+---+------+------+
|
6411 |
* | 0 | Q | U | 0 1 1 1 1 | size | L | M | Rm | opc | H | 0 | Rn | Rd |
|
6412 |
* +---+---+---+-----------+------+---+---+------+-----+---+---+------+------+
|
6413 |
*/
|
6414 |
static void disas_simd_indexed_vector(DisasContext *s, uint32_t insn) |
6415 |
{ |
6416 |
unsupported_encoding(s, insn); |
6417 |
} |
6418 |
|
6419 |
/* C3.6.19 Crypto AES
|
6420 |
* 31 24 23 22 21 17 16 12 11 10 9 5 4 0
|
6421 |
* +-----------------+------+-----------+--------+-----+------+------+
|
6422 |
* | 0 1 0 0 1 1 1 0 | size | 1 0 1 0 0 | opcode | 1 0 | Rn | Rd |
|
6423 |
* +-----------------+------+-----------+--------+-----+------+------+
|
6424 |
*/
|
6425 |
static void disas_crypto_aes(DisasContext *s, uint32_t insn) |
6426 |
{ |
6427 |
unsupported_encoding(s, insn); |
6428 |
} |
6429 |
|
6430 |
/* C3.6.20 Crypto three-reg SHA
|
6431 |
* 31 24 23 22 21 20 16 15 14 12 11 10 9 5 4 0
|
6432 |
* +-----------------+------+---+------+---+--------+-----+------+------+
|
6433 |
* | 0 1 0 1 1 1 1 0 | size | 0 | Rm | 0 | opcode | 0 0 | Rn | Rd |
|
6434 |
* +-----------------+------+---+------+---+--------+-----+------+------+
|
6435 |
*/
|
6436 |
static void disas_crypto_three_reg_sha(DisasContext *s, uint32_t insn) |
6437 |
{ |
6438 |
unsupported_encoding(s, insn); |
6439 |
} |
6440 |
|
6441 |
/* C3.6.21 Crypto two-reg SHA
|
6442 |
* 31 24 23 22 21 17 16 12 11 10 9 5 4 0
|
6443 |
* +-----------------+------+-----------+--------+-----+------+------+
|
6444 |
* | 0 1 0 1 1 1 1 0 | size | 1 0 1 0 0 | opcode | 1 0 | Rn | Rd |
|
6445 |
* +-----------------+------+-----------+--------+-----+------+------+
|
6446 |
*/
|
6447 |
static void disas_crypto_two_reg_sha(DisasContext *s, uint32_t insn) |
6448 |
{ |
6449 |
unsupported_encoding(s, insn); |
6450 |
} |
6451 |
|
6452 |
/* C3.6 Data processing - SIMD, inc Crypto
|
6453 |
*
|
6454 |
* As the decode gets a little complex we are using a table based
|
6455 |
* approach for this part of the decode.
|
6456 |
*/
|
6457 |
static const AArch64DecodeTable data_proc_simd[] = { |
6458 |
/* pattern , mask , fn */
|
6459 |
{ 0x0e200400, 0x9f200400, disas_simd_three_reg_same }, |
6460 |
{ 0x0e200000, 0x9f200c00, disas_simd_three_reg_diff }, |
6461 |
{ 0x0e200800, 0x9f3e0c00, disas_simd_two_reg_misc }, |
6462 |
{ 0x0e300800, 0x9f3e0c00, disas_simd_across_lanes }, |
6463 |
{ 0x0e000400, 0x9fe08400, disas_simd_copy }, |
6464 |
{ 0x0f000000, 0x9f000400, disas_simd_indexed_vector }, |
6465 |
/* simd_mod_imm decode is a subset of simd_shift_imm, so must precede it */
|
6466 |
{ 0x0f000400, 0x9ff80400, disas_simd_mod_imm }, |
6467 |
{ 0x0f000400, 0x9f800400, disas_simd_shift_imm }, |
6468 |
{ 0x0e000000, 0xbf208c00, disas_simd_tb }, |
6469 |
{ 0x0e000800, 0xbf208c00, disas_simd_zip_trn }, |
6470 |
{ 0x2e000000, 0xbf208400, disas_simd_ext }, |
6471 |
{ 0x5e200400, 0xdf200400, disas_simd_scalar_three_reg_same }, |
6472 |
{ 0x5e200000, 0xdf200c00, disas_simd_scalar_three_reg_diff }, |
6473 |
{ 0x5e200800, 0xdf3e0c00, disas_simd_scalar_two_reg_misc }, |
6474 |
{ 0x5e300800, 0xdf3e0c00, disas_simd_scalar_pairwise }, |
6475 |
{ 0x5e000400, 0xdfe08400, disas_simd_scalar_copy }, |
6476 |
{ 0x5f000000, 0xdf000400, disas_simd_scalar_indexed }, |
6477 |
{ 0x5f000400, 0xdf800400, disas_simd_scalar_shift_imm }, |
6478 |
{ 0x4e280800, 0xff3e0c00, disas_crypto_aes }, |
6479 |
{ 0x5e000000, 0xff208c00, disas_crypto_three_reg_sha }, |
6480 |
{ 0x5e280800, 0xff3e0c00, disas_crypto_two_reg_sha }, |
6481 |
{ 0x00000000, 0x00000000, NULL } |
6482 |
}; |
6483 |
|
6484 |
static void disas_data_proc_simd(DisasContext *s, uint32_t insn) |
6485 |
{ |
6486 |
/* Note that this is called with all non-FP cases from
|
6487 |
* table C3-6 so it must UNDEF for entries not specifically
|
6488 |
* allocated to instructions in that table.
|
6489 |
*/
|
6490 |
AArch64DecodeFn *fn = lookup_disas_fn(&data_proc_simd[0], insn);
|
6491 |
if (fn) {
|
6492 |
fn(s, insn); |
6493 |
} else {
|
6494 |
unallocated_encoding(s); |
6495 |
} |
6496 |
} |
6497 |
|
6498 |
/* C3.6 Data processing - SIMD and floating point */
|
6499 |
static void disas_data_proc_simd_fp(DisasContext *s, uint32_t insn) |
6500 |
{ |
6501 |
if (extract32(insn, 28, 1) == 1 && extract32(insn, 30, 1) == 0) { |
6502 |
disas_data_proc_fp(s, insn); |
6503 |
} else {
|
6504 |
/* SIMD, including crypto */
|
6505 |
disas_data_proc_simd(s, insn); |
6506 |
} |
6507 |
} |
6508 |
|
6509 |
/* C3.1 A64 instruction index by encoding */
|
6510 |
static void disas_a64_insn(CPUARMState *env, DisasContext *s) |
6511 |
{ |
6512 |
uint32_t insn; |
6513 |
|
6514 |
insn = arm_ldl_code(env, s->pc, s->bswap_code); |
6515 |
s->insn = insn; |
6516 |
s->pc += 4;
|
6517 |
|
6518 |
switch (extract32(insn, 25, 4)) { |
6519 |
case 0x0: case 0x1: case 0x2: case 0x3: /* UNALLOCATED */ |
6520 |
unallocated_encoding(s); |
6521 |
break;
|
6522 |
case 0x8: case 0x9: /* Data processing - immediate */ |
6523 |
disas_data_proc_imm(s, insn); |
6524 |
break;
|
6525 |
case 0xa: case 0xb: /* Branch, exception generation and system insns */ |
6526 |
disas_b_exc_sys(s, insn); |
6527 |
break;
|
6528 |
case 0x4: |
6529 |
case 0x6: |
6530 |
case 0xc: |
6531 |
case 0xe: /* Loads and stores */ |
6532 |
disas_ldst(s, insn); |
6533 |
break;
|
6534 |
case 0x5: |
6535 |
case 0xd: /* Data processing - register */ |
6536 |
disas_data_proc_reg(s, insn); |
6537 |
break;
|
6538 |
case 0x7: |
6539 |
case 0xf: /* Data processing - SIMD and floating point */ |
6540 |
disas_data_proc_simd_fp(s, insn); |
6541 |
break;
|
6542 |
default:
|
6543 |
assert(FALSE); /* all 15 cases should be handled above */
|
6544 |
break;
|
6545 |
} |
6546 |
|
6547 |
/* if we allocated any temporaries, free them here */
|
6548 |
free_tmp_a64(s); |
6549 |
} |
6550 |
|
6551 |
void gen_intermediate_code_internal_a64(ARMCPU *cpu,
|
6552 |
TranslationBlock *tb, |
6553 |
bool search_pc)
|
6554 |
{ |
6555 |
CPUState *cs = CPU(cpu); |
6556 |
CPUARMState *env = &cpu->env; |
6557 |
DisasContext dc1, *dc = &dc1; |
6558 |
CPUBreakpoint *bp; |
6559 |
uint16_t *gen_opc_end; |
6560 |
int j, lj;
|
6561 |
target_ulong pc_start; |
6562 |
target_ulong next_page_start; |
6563 |
int num_insns;
|
6564 |
int max_insns;
|
6565 |
|
6566 |
pc_start = tb->pc; |
6567 |
|
6568 |
dc->tb = tb; |
6569 |
|
6570 |
gen_opc_end = tcg_ctx.gen_opc_buf + OPC_MAX_SIZE; |
6571 |
|
6572 |
dc->is_jmp = DISAS_NEXT; |
6573 |
dc->pc = pc_start; |
6574 |
dc->singlestep_enabled = cs->singlestep_enabled; |
6575 |
dc->condjmp = 0;
|
6576 |
|
6577 |
dc->aarch64 = 1;
|
6578 |
dc->thumb = 0;
|
6579 |
dc->bswap_code = 0;
|
6580 |
dc->condexec_mask = 0;
|
6581 |
dc->condexec_cond = 0;
|
6582 |
#if !defined(CONFIG_USER_ONLY)
|
6583 |
dc->user = 0;
|
6584 |
#endif
|
6585 |
dc->vfp_enabled = 0;
|
6586 |
dc->vec_len = 0;
|
6587 |
dc->vec_stride = 0;
|
6588 |
dc->cp_regs = cpu->cp_regs; |
6589 |
dc->current_pl = arm_current_pl(env); |
6590 |
|
6591 |
init_tmp_a64_array(dc); |
6592 |
|
6593 |
next_page_start = (pc_start & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE; |
6594 |
lj = -1;
|
6595 |
num_insns = 0;
|
6596 |
max_insns = tb->cflags & CF_COUNT_MASK; |
6597 |
if (max_insns == 0) { |
6598 |
max_insns = CF_COUNT_MASK; |
6599 |
} |
6600 |
|
6601 |
gen_tb_start(); |
6602 |
|
6603 |
tcg_clear_temp_count(); |
6604 |
|
6605 |
do {
|
6606 |
if (unlikely(!QTAILQ_EMPTY(&env->breakpoints))) {
|
6607 |
QTAILQ_FOREACH(bp, &env->breakpoints, entry) { |
6608 |
if (bp->pc == dc->pc) {
|
6609 |
gen_exception_insn(dc, 0, EXCP_DEBUG);
|
6610 |
/* Advance PC so that clearing the breakpoint will
|
6611 |
invalidate this TB. */
|
6612 |
dc->pc += 2;
|
6613 |
goto done_generating;
|
6614 |
} |
6615 |
} |
6616 |
} |
6617 |
|
6618 |
if (search_pc) {
|
6619 |
j = tcg_ctx.gen_opc_ptr - tcg_ctx.gen_opc_buf; |
6620 |
if (lj < j) {
|
6621 |
lj++; |
6622 |
while (lj < j) {
|
6623 |
tcg_ctx.gen_opc_instr_start[lj++] = 0;
|
6624 |
} |
6625 |
} |
6626 |
tcg_ctx.gen_opc_pc[lj] = dc->pc; |
6627 |
tcg_ctx.gen_opc_instr_start[lj] = 1;
|
6628 |
tcg_ctx.gen_opc_icount[lj] = num_insns; |
6629 |
} |
6630 |
|
6631 |
if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO)) { |
6632 |
gen_io_start(); |
6633 |
} |
6634 |
|
6635 |
if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP | CPU_LOG_TB_OP_OPT))) {
|
6636 |
tcg_gen_debug_insn_start(dc->pc); |
6637 |
} |
6638 |
|
6639 |
disas_a64_insn(env, dc); |
6640 |
|
6641 |
if (tcg_check_temp_count()) {
|
6642 |
fprintf(stderr, "TCG temporary leak before "TARGET_FMT_lx"\n", |
6643 |
dc->pc); |
6644 |
} |
6645 |
|
6646 |
/* Translation stops when a conditional branch is encountered.
|
6647 |
* Otherwise the subsequent code could get translated several times.
|
6648 |
* Also stop translation when a page boundary is reached. This
|
6649 |
* ensures prefetch aborts occur at the right place.
|
6650 |
*/
|
6651 |
num_insns++; |
6652 |
} while (!dc->is_jmp && tcg_ctx.gen_opc_ptr < gen_opc_end &&
|
6653 |
!cs->singlestep_enabled && |
6654 |
!singlestep && |
6655 |
dc->pc < next_page_start && |
6656 |
num_insns < max_insns); |
6657 |
|
6658 |
if (tb->cflags & CF_LAST_IO) {
|
6659 |
gen_io_end(); |
6660 |
} |
6661 |
|
6662 |
if (unlikely(cs->singlestep_enabled) && dc->is_jmp != DISAS_EXC) {
|
6663 |
/* Note that this means single stepping WFI doesn't halt the CPU.
|
6664 |
* For conditional branch insns this is harmless unreachable code as
|
6665 |
* gen_goto_tb() has already handled emitting the debug exception
|
6666 |
* (and thus a tb-jump is not possible when singlestepping).
|
6667 |
*/
|
6668 |
assert(dc->is_jmp != DISAS_TB_JUMP); |
6669 |
if (dc->is_jmp != DISAS_JUMP) {
|
6670 |
gen_a64_set_pc_im(dc->pc); |
6671 |
} |
6672 |
gen_exception(EXCP_DEBUG); |
6673 |
} else {
|
6674 |
switch (dc->is_jmp) {
|
6675 |
case DISAS_NEXT:
|
6676 |
gen_goto_tb(dc, 1, dc->pc);
|
6677 |
break;
|
6678 |
default:
|
6679 |
case DISAS_UPDATE:
|
6680 |
gen_a64_set_pc_im(dc->pc); |
6681 |
/* fall through */
|
6682 |
case DISAS_JUMP:
|
6683 |
/* indicate that the hash table must be used to find the next TB */
|
6684 |
tcg_gen_exit_tb(0);
|
6685 |
break;
|
6686 |
case DISAS_TB_JUMP:
|
6687 |
case DISAS_EXC:
|
6688 |
case DISAS_SWI:
|
6689 |
break;
|
6690 |
case DISAS_WFI:
|
6691 |
/* This is a special case because we don't want to just halt the CPU
|
6692 |
* if trying to debug across a WFI.
|
6693 |
*/
|
6694 |
gen_helper_wfi(cpu_env); |
6695 |
break;
|
6696 |
} |
6697 |
} |
6698 |
|
6699 |
done_generating:
|
6700 |
gen_tb_end(tb, num_insns); |
6701 |
*tcg_ctx.gen_opc_ptr = INDEX_op_end; |
6702 |
|
6703 |
#ifdef DEBUG_DISAS
|
6704 |
if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
|
6705 |
qemu_log("----------------\n");
|
6706 |
qemu_log("IN: %s\n", lookup_symbol(pc_start));
|
6707 |
log_target_disas(env, pc_start, dc->pc - pc_start, |
6708 |
dc->thumb | (dc->bswap_code << 1));
|
6709 |
qemu_log("\n");
|
6710 |
} |
6711 |
#endif
|
6712 |
if (search_pc) {
|
6713 |
j = tcg_ctx.gen_opc_ptr - tcg_ctx.gen_opc_buf; |
6714 |
lj++; |
6715 |
while (lj <= j) {
|
6716 |
tcg_ctx.gen_opc_instr_start[lj++] = 0;
|
6717 |
} |
6718 |
} else {
|
6719 |
tb->size = dc->pc - pc_start; |
6720 |
tb->icount = num_insns; |
6721 |
} |
6722 |
} |