root / hw / pxa2xx_pic.c @ 847c25d0
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1 | c1713132 | balrog | /*
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2 | c1713132 | balrog | * Intel XScale PXA Programmable Interrupt Controller.
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3 | c1713132 | balrog | *
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4 | c1713132 | balrog | * Copyright (c) 2006 Openedhand Ltd.
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5 | c1713132 | balrog | * Copyright (c) 2006 Thorsten Zitterell
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6 | c1713132 | balrog | * Written by Andrzej Zaborowski <balrog@zabor.org>
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7 | c1713132 | balrog | *
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8 | 8e31bf38 | Matthew Fernandez | * This code is licensed under the GPL.
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9 | c1713132 | balrog | */
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10 | c1713132 | balrog | |
11 | 87ecb68b | pbrook | #include "hw.h" |
12 | 87ecb68b | pbrook | #include "pxa.h" |
13 | e1f8c729 | Dmitry Eremin-Solenikov | #include "sysbus.h" |
14 | c1713132 | balrog | |
15 | c1713132 | balrog | #define ICIP 0x00 /* Interrupt Controller IRQ Pending register */ |
16 | c1713132 | balrog | #define ICMR 0x04 /* Interrupt Controller Mask register */ |
17 | c1713132 | balrog | #define ICLR 0x08 /* Interrupt Controller Level register */ |
18 | c1713132 | balrog | #define ICFP 0x0c /* Interrupt Controller FIQ Pending register */ |
19 | c1713132 | balrog | #define ICPR 0x10 /* Interrupt Controller Pending register */ |
20 | c1713132 | balrog | #define ICCR 0x14 /* Interrupt Controller Control register */ |
21 | c1713132 | balrog | #define ICHP 0x18 /* Interrupt Controller Highest Priority register */ |
22 | c1713132 | balrog | #define IPR0 0x1c /* Interrupt Controller Priority register 0 */ |
23 | c1713132 | balrog | #define IPR31 0x98 /* Interrupt Controller Priority register 31 */ |
24 | c1713132 | balrog | #define ICIP2 0x9c /* Interrupt Controller IRQ Pending register 2 */ |
25 | c1713132 | balrog | #define ICMR2 0xa0 /* Interrupt Controller Mask register 2 */ |
26 | c1713132 | balrog | #define ICLR2 0xa4 /* Interrupt Controller Level register 2 */ |
27 | c1713132 | balrog | #define ICFP2 0xa8 /* Interrupt Controller FIQ Pending register 2 */ |
28 | c1713132 | balrog | #define ICPR2 0xac /* Interrupt Controller Pending register 2 */ |
29 | c1713132 | balrog | #define IPR32 0xb0 /* Interrupt Controller Priority register 32 */ |
30 | c1713132 | balrog | #define IPR39 0xcc /* Interrupt Controller Priority register 39 */ |
31 | c1713132 | balrog | |
32 | c1713132 | balrog | #define PXA2XX_PIC_SRCS 40 |
33 | c1713132 | balrog | |
34 | bc24a225 | Paul Brook | typedef struct { |
35 | e1f8c729 | Dmitry Eremin-Solenikov | SysBusDevice busdev; |
36 | 90e8e5a3 | Benoît Canet | MemoryRegion iomem; |
37 | 5ae93306 | Andreas Färber | CPUARMState *cpu_env; |
38 | c1713132 | balrog | uint32_t int_enabled[2];
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39 | c1713132 | balrog | uint32_t int_pending[2];
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40 | c1713132 | balrog | uint32_t is_fiq[2];
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41 | c1713132 | balrog | uint32_t int_idle; |
42 | c1713132 | balrog | uint32_t priority[PXA2XX_PIC_SRCS]; |
43 | bc24a225 | Paul Brook | } PXA2xxPICState; |
44 | c1713132 | balrog | |
45 | c1713132 | balrog | static void pxa2xx_pic_update(void *opaque) |
46 | c1713132 | balrog | { |
47 | c1713132 | balrog | uint32_t mask[2];
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48 | bc24a225 | Paul Brook | PXA2xxPICState *s = (PXA2xxPICState *) opaque; |
49 | c1713132 | balrog | |
50 | c1713132 | balrog | if (s->cpu_env->halted) {
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51 | c1713132 | balrog | mask[0] = s->int_pending[0] & (s->int_enabled[0] | s->int_idle); |
52 | c1713132 | balrog | mask[1] = s->int_pending[1] & (s->int_enabled[1] | s->int_idle); |
53 | c1713132 | balrog | if (mask[0] || mask[1]) |
54 | c1713132 | balrog | cpu_interrupt(s->cpu_env, CPU_INTERRUPT_EXITTB); |
55 | c1713132 | balrog | } |
56 | c1713132 | balrog | |
57 | c1713132 | balrog | mask[0] = s->int_pending[0] & s->int_enabled[0]; |
58 | c1713132 | balrog | mask[1] = s->int_pending[1] & s->int_enabled[1]; |
59 | c1713132 | balrog | |
60 | c1713132 | balrog | if ((mask[0] & s->is_fiq[0]) || (mask[1] & s->is_fiq[1])) |
61 | c1713132 | balrog | cpu_interrupt(s->cpu_env, CPU_INTERRUPT_FIQ); |
62 | c1713132 | balrog | else
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63 | c1713132 | balrog | cpu_reset_interrupt(s->cpu_env, CPU_INTERRUPT_FIQ); |
64 | c1713132 | balrog | |
65 | c1713132 | balrog | if ((mask[0] & ~s->is_fiq[0]) || (mask[1] & ~s->is_fiq[1])) |
66 | c1713132 | balrog | cpu_interrupt(s->cpu_env, CPU_INTERRUPT_HARD); |
67 | c1713132 | balrog | else
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68 | c1713132 | balrog | cpu_reset_interrupt(s->cpu_env, CPU_INTERRUPT_HARD); |
69 | c1713132 | balrog | } |
70 | c1713132 | balrog | |
71 | c1713132 | balrog | /* Note: Here level means state of the signal on a pin, not
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72 | c1713132 | balrog | * IRQ/FIQ distinction as in PXA Developer Manual. */
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73 | c1713132 | balrog | static void pxa2xx_pic_set_irq(void *opaque, int irq, int level) |
74 | c1713132 | balrog | { |
75 | bc24a225 | Paul Brook | PXA2xxPICState *s = (PXA2xxPICState *) opaque; |
76 | c1713132 | balrog | int int_set = (irq >= 32); |
77 | c1713132 | balrog | irq &= 31;
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78 | c1713132 | balrog | |
79 | c1713132 | balrog | if (level)
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80 | c1713132 | balrog | s->int_pending[int_set] |= 1 << irq;
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81 | c1713132 | balrog | else
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82 | c1713132 | balrog | s->int_pending[int_set] &= ~(1 << irq);
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83 | c1713132 | balrog | |
84 | c1713132 | balrog | pxa2xx_pic_update(opaque); |
85 | c1713132 | balrog | } |
86 | c1713132 | balrog | |
87 | bc24a225 | Paul Brook | static inline uint32_t pxa2xx_pic_highest(PXA2xxPICState *s) { |
88 | c1713132 | balrog | int i, int_set, irq;
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89 | c1713132 | balrog | uint32_t bit, mask[2];
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90 | c1713132 | balrog | uint32_t ichp = 0x003f003f; /* Both IDs invalid */ |
91 | c1713132 | balrog | |
92 | c1713132 | balrog | mask[0] = s->int_pending[0] & s->int_enabled[0]; |
93 | c1713132 | balrog | mask[1] = s->int_pending[1] & s->int_enabled[1]; |
94 | c1713132 | balrog | |
95 | c1713132 | balrog | for (i = PXA2XX_PIC_SRCS - 1; i >= 0; i --) { |
96 | c1713132 | balrog | irq = s->priority[i] & 0x3f;
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97 | c1713132 | balrog | if ((s->priority[i] & (1 << 31)) && irq < PXA2XX_PIC_SRCS) { |
98 | c1713132 | balrog | /* Source peripheral ID is valid. */
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99 | c1713132 | balrog | bit = 1 << (irq & 31); |
100 | c1713132 | balrog | int_set = (irq >= 32);
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101 | c1713132 | balrog | |
102 | c1713132 | balrog | if (mask[int_set] & bit & s->is_fiq[int_set]) {
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103 | c1713132 | balrog | /* FIQ asserted */
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104 | c1713132 | balrog | ichp &= 0xffff0000;
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105 | c1713132 | balrog | ichp |= (1 << 15) | irq; |
106 | c1713132 | balrog | } |
107 | c1713132 | balrog | |
108 | c1713132 | balrog | if (mask[int_set] & bit & ~s->is_fiq[int_set]) {
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109 | c1713132 | balrog | /* IRQ asserted */
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110 | c1713132 | balrog | ichp &= 0x0000ffff;
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111 | c1713132 | balrog | ichp |= (1 << 31) | (irq << 16); |
112 | c1713132 | balrog | } |
113 | c1713132 | balrog | } |
114 | c1713132 | balrog | } |
115 | c1713132 | balrog | |
116 | c1713132 | balrog | return ichp;
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117 | c1713132 | balrog | } |
118 | c1713132 | balrog | |
119 | 90e8e5a3 | Benoît Canet | static uint64_t pxa2xx_pic_mem_read(void *opaque, target_phys_addr_t offset, |
120 | 90e8e5a3 | Benoît Canet | unsigned size)
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121 | c1713132 | balrog | { |
122 | bc24a225 | Paul Brook | PXA2xxPICState *s = (PXA2xxPICState *) opaque; |
123 | c1713132 | balrog | |
124 | c1713132 | balrog | switch (offset) {
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125 | c1713132 | balrog | case ICIP: /* IRQ Pending register */ |
126 | c1713132 | balrog | return s->int_pending[0] & ~s->is_fiq[0] & s->int_enabled[0]; |
127 | c1713132 | balrog | case ICIP2: /* IRQ Pending register 2 */ |
128 | c1713132 | balrog | return s->int_pending[1] & ~s->is_fiq[1] & s->int_enabled[1]; |
129 | c1713132 | balrog | case ICMR: /* Mask register */ |
130 | c1713132 | balrog | return s->int_enabled[0]; |
131 | c1713132 | balrog | case ICMR2: /* Mask register 2 */ |
132 | c1713132 | balrog | return s->int_enabled[1]; |
133 | c1713132 | balrog | case ICLR: /* Level register */ |
134 | c1713132 | balrog | return s->is_fiq[0]; |
135 | c1713132 | balrog | case ICLR2: /* Level register 2 */ |
136 | c1713132 | balrog | return s->is_fiq[1]; |
137 | c1713132 | balrog | case ICCR: /* Idle mask */ |
138 | c1713132 | balrog | return (s->int_idle == 0); |
139 | c1713132 | balrog | case ICFP: /* FIQ Pending register */ |
140 | c1713132 | balrog | return s->int_pending[0] & s->is_fiq[0] & s->int_enabled[0]; |
141 | c1713132 | balrog | case ICFP2: /* FIQ Pending register 2 */ |
142 | c1713132 | balrog | return s->int_pending[1] & s->is_fiq[1] & s->int_enabled[1]; |
143 | c1713132 | balrog | case ICPR: /* Pending register */ |
144 | c1713132 | balrog | return s->int_pending[0]; |
145 | c1713132 | balrog | case ICPR2: /* Pending register 2 */ |
146 | c1713132 | balrog | return s->int_pending[1]; |
147 | c1713132 | balrog | case IPR0 ... IPR31:
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148 | c1713132 | balrog | return s->priority[0 + ((offset - IPR0 ) >> 2)]; |
149 | c1713132 | balrog | case IPR32 ... IPR39:
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150 | c1713132 | balrog | return s->priority[32 + ((offset - IPR32) >> 2)]; |
151 | c1713132 | balrog | case ICHP: /* Highest Priority register */ |
152 | c1713132 | balrog | return pxa2xx_pic_highest(s);
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153 | c1713132 | balrog | default:
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154 | c1713132 | balrog | printf("%s: Bad register offset " REG_FMT "\n", __FUNCTION__, offset); |
155 | c1713132 | balrog | return 0; |
156 | c1713132 | balrog | } |
157 | c1713132 | balrog | } |
158 | c1713132 | balrog | |
159 | c227f099 | Anthony Liguori | static void pxa2xx_pic_mem_write(void *opaque, target_phys_addr_t offset, |
160 | 90e8e5a3 | Benoît Canet | uint64_t value, unsigned size)
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161 | c1713132 | balrog | { |
162 | bc24a225 | Paul Brook | PXA2xxPICState *s = (PXA2xxPICState *) opaque; |
163 | c1713132 | balrog | |
164 | c1713132 | balrog | switch (offset) {
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165 | c1713132 | balrog | case ICMR: /* Mask register */ |
166 | c1713132 | balrog | s->int_enabled[0] = value;
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167 | c1713132 | balrog | break;
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168 | c1713132 | balrog | case ICMR2: /* Mask register 2 */ |
169 | c1713132 | balrog | s->int_enabled[1] = value;
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170 | c1713132 | balrog | break;
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171 | c1713132 | balrog | case ICLR: /* Level register */ |
172 | c1713132 | balrog | s->is_fiq[0] = value;
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173 | c1713132 | balrog | break;
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174 | c1713132 | balrog | case ICLR2: /* Level register 2 */ |
175 | c1713132 | balrog | s->is_fiq[1] = value;
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176 | c1713132 | balrog | break;
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177 | c1713132 | balrog | case ICCR: /* Idle mask */ |
178 | c1713132 | balrog | s->int_idle = (value & 1) ? 0 : ~0; |
179 | c1713132 | balrog | break;
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180 | c1713132 | balrog | case IPR0 ... IPR31:
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181 | c1713132 | balrog | s->priority[0 + ((offset - IPR0 ) >> 2)] = value & 0x8000003f; |
182 | c1713132 | balrog | break;
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183 | c1713132 | balrog | case IPR32 ... IPR39:
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184 | c1713132 | balrog | s->priority[32 + ((offset - IPR32) >> 2)] = value & 0x8000003f; |
185 | c1713132 | balrog | break;
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186 | c1713132 | balrog | default:
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187 | c1713132 | balrog | printf("%s: Bad register offset " REG_FMT "\n", __FUNCTION__, offset); |
188 | c1713132 | balrog | return;
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189 | c1713132 | balrog | } |
190 | c1713132 | balrog | pxa2xx_pic_update(opaque); |
191 | c1713132 | balrog | } |
192 | c1713132 | balrog | |
193 | c1713132 | balrog | /* Interrupt Controller Coprocessor Space Register Mapping */
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194 | c1713132 | balrog | static const int pxa2xx_cp_reg_map[0x10] = { |
195 | c1713132 | balrog | [0x0 ... 0xf] = -1, |
196 | c1713132 | balrog | [0x0] = ICIP,
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197 | c1713132 | balrog | [0x1] = ICMR,
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198 | c1713132 | balrog | [0x2] = ICLR,
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199 | c1713132 | balrog | [0x3] = ICFP,
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200 | c1713132 | balrog | [0x4] = ICPR,
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201 | c1713132 | balrog | [0x5] = ICHP,
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202 | c1713132 | balrog | [0x6] = ICIP2,
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203 | c1713132 | balrog | [0x7] = ICMR2,
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204 | c1713132 | balrog | [0x8] = ICLR2,
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205 | c1713132 | balrog | [0x9] = ICFP2,
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206 | c1713132 | balrog | [0xa] = ICPR2,
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207 | c1713132 | balrog | }; |
208 | c1713132 | balrog | |
209 | c1713132 | balrog | static uint32_t pxa2xx_pic_cp_read(void *opaque, int op2, int reg, int crm) |
210 | c1713132 | balrog | { |
211 | c227f099 | Anthony Liguori | target_phys_addr_t offset; |
212 | c1713132 | balrog | |
213 | c1713132 | balrog | if (pxa2xx_cp_reg_map[reg] == -1) { |
214 | c1713132 | balrog | printf("%s: Bad register 0x%x\n", __FUNCTION__, reg);
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215 | c1713132 | balrog | return 0; |
216 | c1713132 | balrog | } |
217 | c1713132 | balrog | |
218 | 8da3ff18 | pbrook | offset = pxa2xx_cp_reg_map[reg]; |
219 | 90e8e5a3 | Benoît Canet | return pxa2xx_pic_mem_read(opaque, offset, 4); |
220 | c1713132 | balrog | } |
221 | c1713132 | balrog | |
222 | c1713132 | balrog | static void pxa2xx_pic_cp_write(void *opaque, int op2, int reg, int crm, |
223 | c1713132 | balrog | uint32_t value) |
224 | c1713132 | balrog | { |
225 | c227f099 | Anthony Liguori | target_phys_addr_t offset; |
226 | c1713132 | balrog | |
227 | c1713132 | balrog | if (pxa2xx_cp_reg_map[reg] == -1) { |
228 | c1713132 | balrog | printf("%s: Bad register 0x%x\n", __FUNCTION__, reg);
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229 | c1713132 | balrog | return;
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230 | c1713132 | balrog | } |
231 | c1713132 | balrog | |
232 | 8da3ff18 | pbrook | offset = pxa2xx_cp_reg_map[reg]; |
233 | 90e8e5a3 | Benoît Canet | pxa2xx_pic_mem_write(opaque, offset, value, 4);
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234 | c1713132 | balrog | } |
235 | c1713132 | balrog | |
236 | 90e8e5a3 | Benoît Canet | static const MemoryRegionOps pxa2xx_pic_ops = { |
237 | 90e8e5a3 | Benoît Canet | .read = pxa2xx_pic_mem_read, |
238 | 90e8e5a3 | Benoît Canet | .write = pxa2xx_pic_mem_write, |
239 | 90e8e5a3 | Benoît Canet | .endianness = DEVICE_NATIVE_ENDIAN, |
240 | c1713132 | balrog | }; |
241 | c1713132 | balrog | |
242 | e1f8c729 | Dmitry Eremin-Solenikov | static int pxa2xx_pic_post_load(void *opaque, int version_id) |
243 | aa941b94 | balrog | { |
244 | aa941b94 | balrog | pxa2xx_pic_update(opaque); |
245 | aa941b94 | balrog | return 0; |
246 | aa941b94 | balrog | } |
247 | aa941b94 | balrog | |
248 | 5ae93306 | Andreas Färber | DeviceState *pxa2xx_pic_init(target_phys_addr_t base, CPUARMState *env) |
249 | c1713132 | balrog | { |
250 | e1f8c729 | Dmitry Eremin-Solenikov | DeviceState *dev = qdev_create(NULL, "pxa2xx_pic"); |
251 | e1f8c729 | Dmitry Eremin-Solenikov | PXA2xxPICState *s = FROM_SYSBUS(PXA2xxPICState, sysbus_from_qdev(dev)); |
252 | c1713132 | balrog | |
253 | c1713132 | balrog | s->cpu_env = env; |
254 | c1713132 | balrog | |
255 | c1713132 | balrog | s->int_pending[0] = 0; |
256 | c1713132 | balrog | s->int_pending[1] = 0; |
257 | c1713132 | balrog | s->int_enabled[0] = 0; |
258 | c1713132 | balrog | s->int_enabled[1] = 0; |
259 | c1713132 | balrog | s->is_fiq[0] = 0; |
260 | c1713132 | balrog | s->is_fiq[1] = 0; |
261 | c1713132 | balrog | |
262 | e1f8c729 | Dmitry Eremin-Solenikov | qdev_init_nofail(dev); |
263 | e1f8c729 | Dmitry Eremin-Solenikov | |
264 | e1f8c729 | Dmitry Eremin-Solenikov | qdev_init_gpio_in(dev, pxa2xx_pic_set_irq, PXA2XX_PIC_SRCS); |
265 | c1713132 | balrog | |
266 | c1713132 | balrog | /* Enable IC memory-mapped registers access. */
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267 | 90e8e5a3 | Benoît Canet | memory_region_init_io(&s->iomem, &pxa2xx_pic_ops, s, |
268 | 90e8e5a3 | Benoît Canet | "pxa2xx-pic", 0x00100000); |
269 | 750ecd44 | Avi Kivity | sysbus_init_mmio(sysbus_from_qdev(dev), &s->iomem); |
270 | 7c29d6ce | Andrzej Zaborowski | sysbus_mmio_map(sysbus_from_qdev(dev), 0, base);
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271 | c1713132 | balrog | |
272 | c1713132 | balrog | /* Enable IC coprocessor access. */
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273 | c1713132 | balrog | cpu_arm_set_cp_io(env, 6, pxa2xx_pic_cp_read, pxa2xx_pic_cp_write, s);
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274 | c1713132 | balrog | |
275 | e1f8c729 | Dmitry Eremin-Solenikov | return dev;
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276 | e1f8c729 | Dmitry Eremin-Solenikov | } |
277 | e1f8c729 | Dmitry Eremin-Solenikov | |
278 | e1f8c729 | Dmitry Eremin-Solenikov | static VMStateDescription vmstate_pxa2xx_pic_regs = {
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279 | e1f8c729 | Dmitry Eremin-Solenikov | .name = "pxa2xx_pic",
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280 | e1f8c729 | Dmitry Eremin-Solenikov | .version_id = 0,
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281 | e1f8c729 | Dmitry Eremin-Solenikov | .minimum_version_id = 0,
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282 | e1f8c729 | Dmitry Eremin-Solenikov | .minimum_version_id_old = 0,
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283 | e1f8c729 | Dmitry Eremin-Solenikov | .post_load = pxa2xx_pic_post_load, |
284 | e1f8c729 | Dmitry Eremin-Solenikov | .fields = (VMStateField[]) { |
285 | e1f8c729 | Dmitry Eremin-Solenikov | VMSTATE_UINT32_ARRAY(int_enabled, PXA2xxPICState, 2),
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286 | e1f8c729 | Dmitry Eremin-Solenikov | VMSTATE_UINT32_ARRAY(int_pending, PXA2xxPICState, 2),
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287 | e1f8c729 | Dmitry Eremin-Solenikov | VMSTATE_UINT32_ARRAY(is_fiq, PXA2xxPICState, 2),
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288 | e1f8c729 | Dmitry Eremin-Solenikov | VMSTATE_UINT32(int_idle, PXA2xxPICState), |
289 | e1f8c729 | Dmitry Eremin-Solenikov | VMSTATE_UINT32_ARRAY(priority, PXA2xxPICState, PXA2XX_PIC_SRCS), |
290 | e1f8c729 | Dmitry Eremin-Solenikov | VMSTATE_END_OF_LIST(), |
291 | e1f8c729 | Dmitry Eremin-Solenikov | }, |
292 | e1f8c729 | Dmitry Eremin-Solenikov | }; |
293 | aa941b94 | balrog | |
294 | e1f8c729 | Dmitry Eremin-Solenikov | static int pxa2xx_pic_initfn(SysBusDevice *dev) |
295 | e1f8c729 | Dmitry Eremin-Solenikov | { |
296 | e1f8c729 | Dmitry Eremin-Solenikov | return 0; |
297 | e1f8c729 | Dmitry Eremin-Solenikov | } |
298 | e1f8c729 | Dmitry Eremin-Solenikov | |
299 | 999e12bb | Anthony Liguori | static void pxa2xx_pic_class_init(ObjectClass *klass, void *data) |
300 | 999e12bb | Anthony Liguori | { |
301 | 39bffca2 | Anthony Liguori | DeviceClass *dc = DEVICE_CLASS(klass); |
302 | 999e12bb | Anthony Liguori | SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); |
303 | 999e12bb | Anthony Liguori | |
304 | 999e12bb | Anthony Liguori | k->init = pxa2xx_pic_initfn; |
305 | 39bffca2 | Anthony Liguori | dc->desc = "PXA2xx PIC";
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306 | 39bffca2 | Anthony Liguori | dc->vmsd = &vmstate_pxa2xx_pic_regs; |
307 | 999e12bb | Anthony Liguori | } |
308 | 999e12bb | Anthony Liguori | |
309 | 39bffca2 | Anthony Liguori | static TypeInfo pxa2xx_pic_info = {
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310 | 39bffca2 | Anthony Liguori | .name = "pxa2xx_pic",
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311 | 39bffca2 | Anthony Liguori | .parent = TYPE_SYS_BUS_DEVICE, |
312 | 39bffca2 | Anthony Liguori | .instance_size = sizeof(PXA2xxPICState),
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313 | 39bffca2 | Anthony Liguori | .class_init = pxa2xx_pic_class_init, |
314 | e1f8c729 | Dmitry Eremin-Solenikov | }; |
315 | e1f8c729 | Dmitry Eremin-Solenikov | |
316 | 83f7d43a | Andreas Färber | static void pxa2xx_pic_register_types(void) |
317 | e1f8c729 | Dmitry Eremin-Solenikov | { |
318 | 39bffca2 | Anthony Liguori | type_register_static(&pxa2xx_pic_info); |
319 | c1713132 | balrog | } |
320 | 83f7d43a | Andreas Färber | |
321 | 83f7d43a | Andreas Färber | type_init(pxa2xx_pic_register_types) |