Revision 84e4fccb hw/arm_gic.c
| b/hw/arm_gic.c | ||
|---|---|---|
| 36 | 36 |
#define DPRINTF(fmt, ...) do {} while(0)
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| 37 | 37 |
#endif |
| 38 | 38 |
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| 39 |
#ifdef NVIC |
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| 40 | 39 |
/* The NVIC has 16 internal vectors. However these are not exposed |
| 41 | 40 |
through the normal GIC interface. */ |
| 42 |
#define GIC_BASE_IRQ 32 |
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| 43 |
#else |
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#define GIC_BASE_IRQ 0 |
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#endif |
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#define GIC_BASE_IRQ ((s->revision == REV_NVIC) ? 32 : 0) |
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| 46 | 42 |
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| 47 | 43 |
static const uint8_t gic_id[] = {
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| 48 | 44 |
0x90, 0x13, 0x04, 0x00, 0x0d, 0xf0, 0x05, 0xb1 |
| ... | ... | |
| 839 | 835 |
} |
| 840 | 836 |
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| 841 | 837 |
i = s->num_irq - GIC_INTERNAL; |
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#ifndef NVIC |
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| 843 | 838 |
/* For the GIC, also expose incoming GPIO lines for PPIs for each CPU. |
| 844 | 839 |
* GPIO array layout is thus: |
| 845 | 840 |
* [0..N-1] SPIs |
| ... | ... | |
| 847 | 842 |
* [N+32..N+63] PPIs for CPU 1 |
| 848 | 843 |
* ... |
| 849 | 844 |
*/ |
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i += (GIC_INTERNAL * s->num_cpu); |
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#endif |
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if (s->revision != REV_NVIC) {
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i += (GIC_INTERNAL * s->num_cpu); |
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} |
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| 852 | 848 |
qdev_init_gpio_in(&s->busdev.qdev, gic_set_irq, i); |
| 853 | 849 |
for (i = 0; i < NUM_CPU(s); i++) {
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| 854 | 850 |
sysbus_init_irq(&s->busdev, &s->parent_irq[i]); |
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