Revision 85df3786 target-arm/cpu.c
| b/target-arm/cpu.c | ||
|---|---|---|
| 270 | 270 |
cpu->id_isar2 = 0x21232031; |
| 271 | 271 |
cpu->id_isar3 = 0x11112131; |
| 272 | 272 |
cpu->id_isar4 = 0x00111142; |
| 273 |
cpu->clidr = (1 << 27) | (2 << 24) | 3; |
|
| 274 |
cpu->ccsidr[0] = 0xe007e01a; /* 16k L1 dcache. */ |
|
| 275 |
cpu->ccsidr[1] = 0x2007e01a; /* 16k L1 icache. */ |
|
| 276 |
cpu->ccsidr[2] = 0xf0000000; /* No L2 icache. */ |
|
| 273 | 277 |
} |
| 274 | 278 |
|
| 275 | 279 |
static void cortex_a9_initfn(Object *obj) |
| ... | ... | |
| 304 | 308 |
cpu->id_isar2 = 0x21232041; |
| 305 | 309 |
cpu->id_isar3 = 0x11112131; |
| 306 | 310 |
cpu->id_isar4 = 0x00111142; |
| 311 |
cpu->clidr = (1 << 27) | (1 << 24) | 3; |
|
| 312 |
cpu->ccsidr[0] = 0xe00fe015; /* 16k L1 dcache. */ |
|
| 313 |
cpu->ccsidr[1] = 0x200fe015; /* 16k L1 icache. */ |
|
| 307 | 314 |
} |
| 308 | 315 |
|
| 309 | 316 |
static void cortex_a15_initfn(Object *obj) |
| ... | ... | |
| 336 | 343 |
cpu->id_isar2 = 0x21232041; |
| 337 | 344 |
cpu->id_isar3 = 0x11112131; |
| 338 | 345 |
cpu->id_isar4 = 0x10011142; |
| 346 |
cpu->clidr = 0x0a200023; |
|
| 347 |
cpu->ccsidr[0] = 0x701fe00a; /* 32K L1 dcache */ |
|
| 348 |
cpu->ccsidr[1] = 0x201fe00a; /* 32K L1 icache */ |
|
| 349 |
cpu->ccsidr[2] = 0x711fe07a; /* 4096K L2 unified cache */ |
|
| 339 | 350 |
} |
| 340 | 351 |
|
| 341 | 352 |
static void ti925t_initfn(Object *obj) |
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