Revision 85df3786 target-arm/helper.c

b/target-arm/helper.c
25 25 
    case ARM_CPUID_ARM11MPCORE:
26 26 
        break;
27 27 
    case ARM_CPUID_CORTEXA8:
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        env->cp15.c0_clid = (1 << 27) | (2 << 24) | 3;
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        env->cp15.c0_ccsid[0] = 0xe007e01a; /* 16k L1 dcache. */
30 
        env->cp15.c0_ccsid[1] = 0x2007e01a; /* 16k L1 icache. */
31 
        env->cp15.c0_ccsid[2] = 0xf0000000; /* No L2 icache. */
32 28 
        break;
33 29 
    case ARM_CPUID_CORTEXA9:
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        env->cp15.c0_clid = (1 << 27) | (1 << 24) | 3;
35 
        env->cp15.c0_ccsid[0] = 0xe00fe015; /* 16k L1 dcache. */
36 
        env->cp15.c0_ccsid[1] = 0x200fe015; /* 16k L1 icache. */
37 30 
        break;
38 31 
    case ARM_CPUID_CORTEXA15:
39 
        env->cp15.c0_clid = 0x0a200023;
40 
        env->cp15.c0_ccsid[0] = 0x701fe00a; /* 32K L1 dcache */
41 
        env->cp15.c0_ccsid[1] = 0x201fe00a; /* 32K L1 icache */
42 
        env->cp15.c0_ccsid[2] = 0x711fe07a; /* 4096K L2 unified cache */
43 32 
        break;
44 33 
    case ARM_CPUID_CORTEXM3:
45 34 
        break;
......
113 102 
    env->cp15.c0_c2[4] = cpu->id_isar4;
114 103 
    env->cp15.c0_c2[5] = cpu->id_isar5;
115 104 
    env->cp15.c15_i_min = 0xff0;
105 
    env->cp15.c0_clid = cpu->clidr;
106 
    memcpy(env->cp15.c0_ccsid, cpu->ccsidr, ARRAY_SIZE(cpu->ccsidr));
116 107 

  		





  117
  108
  
    
    if (arm_feature(env, ARM_FEATURE_IWMMXT)) {


  		





  118
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        env->iwmmxt.cregs[ARM_IWMMXT_wCID] = 0x69051000 | 'Q';


  		












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