root / softmmu_header.h @ 85e8dab1
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1 | b92e5a22 | bellard | /*
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2 | b92e5a22 | bellard | * Software MMU support
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3 | 5fafdf24 | ths | *
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4 | efbf29b6 | Blue Swirl | * Generate inline load/store functions for one MMU mode and data
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5 | efbf29b6 | Blue Swirl | * size.
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6 | efbf29b6 | Blue Swirl | *
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7 | efbf29b6 | Blue Swirl | * Generate a store function as well as signed and unsigned loads. For
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8 | efbf29b6 | Blue Swirl | * 32 and 64 bit cases, also generate floating point functions with
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9 | efbf29b6 | Blue Swirl | * the same size.
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10 | efbf29b6 | Blue Swirl | *
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11 | efbf29b6 | Blue Swirl | * Not used directly but included from softmmu_exec.h and exec-all.h.
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12 | efbf29b6 | Blue Swirl | *
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13 | b92e5a22 | bellard | * Copyright (c) 2003 Fabrice Bellard
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14 | b92e5a22 | bellard | *
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15 | b92e5a22 | bellard | * This library is free software; you can redistribute it and/or
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16 | b92e5a22 | bellard | * modify it under the terms of the GNU Lesser General Public
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17 | b92e5a22 | bellard | * License as published by the Free Software Foundation; either
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18 | b92e5a22 | bellard | * version 2 of the License, or (at your option) any later version.
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19 | b92e5a22 | bellard | *
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20 | b92e5a22 | bellard | * This library is distributed in the hope that it will be useful,
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21 | b92e5a22 | bellard | * but WITHOUT ANY WARRANTY; without even the implied warranty of
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22 | b92e5a22 | bellard | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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23 | b92e5a22 | bellard | * Lesser General Public License for more details.
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24 | b92e5a22 | bellard | *
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25 | b92e5a22 | bellard | * You should have received a copy of the GNU Lesser General Public
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26 | 8167ee88 | Blue Swirl | * License along with this library; if not, see <http://www.gnu.org/licenses/>.
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27 | b92e5a22 | bellard | */
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28 | b92e5a22 | bellard | #if DATA_SIZE == 8 |
29 | b92e5a22 | bellard | #define SUFFIX q
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30 | 61382a50 | bellard | #define USUFFIX q
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31 | b92e5a22 | bellard | #define DATA_TYPE uint64_t
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32 | b92e5a22 | bellard | #elif DATA_SIZE == 4 |
33 | b92e5a22 | bellard | #define SUFFIX l
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34 | 61382a50 | bellard | #define USUFFIX l
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35 | b92e5a22 | bellard | #define DATA_TYPE uint32_t
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36 | b92e5a22 | bellard | #elif DATA_SIZE == 2 |
37 | b92e5a22 | bellard | #define SUFFIX w
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38 | 61382a50 | bellard | #define USUFFIX uw
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39 | b92e5a22 | bellard | #define DATA_TYPE uint16_t
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40 | b92e5a22 | bellard | #define DATA_STYPE int16_t
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41 | b92e5a22 | bellard | #elif DATA_SIZE == 1 |
42 | b92e5a22 | bellard | #define SUFFIX b
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43 | 61382a50 | bellard | #define USUFFIX ub
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44 | b92e5a22 | bellard | #define DATA_TYPE uint8_t
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45 | b92e5a22 | bellard | #define DATA_STYPE int8_t
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46 | b92e5a22 | bellard | #else
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47 | b92e5a22 | bellard | #error unsupported data size
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48 | b92e5a22 | bellard | #endif
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49 | b92e5a22 | bellard | |
50 | 6ebbf390 | j_mayer | #if ACCESS_TYPE < (NB_MMU_MODES)
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51 | 61382a50 | bellard | |
52 | 6ebbf390 | j_mayer | #define CPU_MMU_INDEX ACCESS_TYPE
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53 | 61382a50 | bellard | #define MMUSUFFIX _mmu
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54 | 61382a50 | bellard | |
55 | 6ebbf390 | j_mayer | #elif ACCESS_TYPE == (NB_MMU_MODES)
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56 | 61382a50 | bellard | |
57 | 6ebbf390 | j_mayer | #define CPU_MMU_INDEX (cpu_mmu_index(env))
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58 | 61382a50 | bellard | #define MMUSUFFIX _mmu
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59 | 61382a50 | bellard | |
60 | 6ebbf390 | j_mayer | #elif ACCESS_TYPE == (NB_MMU_MODES + 1) |
61 | 61382a50 | bellard | |
62 | 6ebbf390 | j_mayer | #define CPU_MMU_INDEX (cpu_mmu_index(env))
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63 | 61382a50 | bellard | #define MMUSUFFIX _cmmu
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64 | 61382a50 | bellard | |
65 | b92e5a22 | bellard | #else
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66 | 61382a50 | bellard | #error invalid ACCESS_TYPE
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67 | b92e5a22 | bellard | #endif
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68 | b92e5a22 | bellard | |
69 | b92e5a22 | bellard | #if DATA_SIZE == 8 |
70 | b92e5a22 | bellard | #define RES_TYPE uint64_t
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71 | b92e5a22 | bellard | #else
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72 | c086b783 | Igor V. Kovalenko | #define RES_TYPE uint32_t
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73 | b92e5a22 | bellard | #endif
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74 | b92e5a22 | bellard | |
75 | 6ebbf390 | j_mayer | #if ACCESS_TYPE == (NB_MMU_MODES + 1) |
76 | 84b7b8e7 | bellard | #define ADDR_READ addr_code
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77 | 84b7b8e7 | bellard | #else
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78 | 84b7b8e7 | bellard | #define ADDR_READ addr_read
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79 | 84b7b8e7 | bellard | #endif
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80 | b92e5a22 | bellard | |
81 | e141ab52 | Blue Swirl | #ifndef CONFIG_TCG_PASS_AREG0
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82 | e141ab52 | Blue Swirl | #define ENV_PARAM
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83 | e141ab52 | Blue Swirl | #define ENV_VAR
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84 | e141ab52 | Blue Swirl | #define CPU_PREFIX
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85 | e141ab52 | Blue Swirl | #define HELPER_PREFIX __
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86 | e141ab52 | Blue Swirl | #else
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87 | e141ab52 | Blue Swirl | #define ENV_PARAM CPUArchState *env,
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88 | e141ab52 | Blue Swirl | #define ENV_VAR env,
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89 | e141ab52 | Blue Swirl | #define CPU_PREFIX cpu_
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90 | e141ab52 | Blue Swirl | #define HELPER_PREFIX helper_
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91 | e141ab52 | Blue Swirl | #endif
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92 | e141ab52 | Blue Swirl | |
93 | e16c53fa | bellard | /* generic load/store macros */
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94 | e16c53fa | bellard | |
95 | e141ab52 | Blue Swirl | static inline RES_TYPE |
96 | e141ab52 | Blue Swirl | glue(glue(glue(CPU_PREFIX, ld), USUFFIX), MEMSUFFIX)(ENV_PARAM |
97 | e141ab52 | Blue Swirl | target_ulong ptr) |
98 | b92e5a22 | bellard | { |
99 | 4d7a0880 | blueswir1 | int page_index;
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100 | b92e5a22 | bellard | RES_TYPE res; |
101 | c27004ec | bellard | target_ulong addr; |
102 | c27004ec | bellard | unsigned long physaddr; |
103 | 6ebbf390 | j_mayer | int mmu_idx;
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104 | 61382a50 | bellard | |
105 | c27004ec | bellard | addr = ptr; |
106 | 4d7a0880 | blueswir1 | page_index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
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107 | 6ebbf390 | j_mayer | mmu_idx = CPU_MMU_INDEX; |
108 | 551bd27f | ths | if (unlikely(env->tlb_table[mmu_idx][page_index].ADDR_READ !=
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109 | 551bd27f | ths | (addr & (TARGET_PAGE_MASK | (DATA_SIZE - 1))))) {
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110 | e141ab52 | Blue Swirl | res = glue(glue(glue(HELPER_PREFIX, ld), SUFFIX), MMUSUFFIX)(ENV_VAR |
111 | e141ab52 | Blue Swirl | addr, |
112 | e141ab52 | Blue Swirl | mmu_idx); |
113 | b92e5a22 | bellard | } else {
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114 | 4d7a0880 | blueswir1 | physaddr = addr + env->tlb_table[mmu_idx][page_index].addend; |
115 | 61382a50 | bellard | res = glue(glue(ld, USUFFIX), _raw)((uint8_t *)physaddr); |
116 | b92e5a22 | bellard | } |
117 | b92e5a22 | bellard | return res;
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118 | b92e5a22 | bellard | } |
119 | b92e5a22 | bellard | |
120 | b92e5a22 | bellard | #if DATA_SIZE <= 2 |
121 | e141ab52 | Blue Swirl | static inline int |
122 | e141ab52 | Blue Swirl | glue(glue(glue(CPU_PREFIX, lds), SUFFIX), MEMSUFFIX)(ENV_PARAM |
123 | e141ab52 | Blue Swirl | target_ulong ptr) |
124 | b92e5a22 | bellard | { |
125 | 4d7a0880 | blueswir1 | int res, page_index;
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126 | c27004ec | bellard | target_ulong addr; |
127 | c27004ec | bellard | unsigned long physaddr; |
128 | 6ebbf390 | j_mayer | int mmu_idx;
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129 | 61382a50 | bellard | |
130 | c27004ec | bellard | addr = ptr; |
131 | 4d7a0880 | blueswir1 | page_index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
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132 | 6ebbf390 | j_mayer | mmu_idx = CPU_MMU_INDEX; |
133 | 551bd27f | ths | if (unlikely(env->tlb_table[mmu_idx][page_index].ADDR_READ !=
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134 | 551bd27f | ths | (addr & (TARGET_PAGE_MASK | (DATA_SIZE - 1))))) {
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135 | e141ab52 | Blue Swirl | res = (DATA_STYPE)glue(glue(glue(HELPER_PREFIX, ld), SUFFIX), |
136 | e141ab52 | Blue Swirl | MMUSUFFIX)(ENV_VAR addr, mmu_idx); |
137 | b92e5a22 | bellard | } else {
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138 | 4d7a0880 | blueswir1 | physaddr = addr + env->tlb_table[mmu_idx][page_index].addend; |
139 | b92e5a22 | bellard | res = glue(glue(lds, SUFFIX), _raw)((uint8_t *)physaddr); |
140 | b92e5a22 | bellard | } |
141 | b92e5a22 | bellard | return res;
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142 | b92e5a22 | bellard | } |
143 | b92e5a22 | bellard | #endif
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144 | b92e5a22 | bellard | |
145 | 6ebbf390 | j_mayer | #if ACCESS_TYPE != (NB_MMU_MODES + 1) |
146 | 84b7b8e7 | bellard | |
147 | e16c53fa | bellard | /* generic store macro */
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148 | e16c53fa | bellard | |
149 | e141ab52 | Blue Swirl | static inline void |
150 | e141ab52 | Blue Swirl | glue(glue(glue(CPU_PREFIX, st), SUFFIX), MEMSUFFIX)(ENV_PARAM target_ulong ptr, |
151 | e141ab52 | Blue Swirl | RES_TYPE v) |
152 | b92e5a22 | bellard | { |
153 | 4d7a0880 | blueswir1 | int page_index;
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154 | c27004ec | bellard | target_ulong addr; |
155 | c27004ec | bellard | unsigned long physaddr; |
156 | 6ebbf390 | j_mayer | int mmu_idx;
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157 | 61382a50 | bellard | |
158 | c27004ec | bellard | addr = ptr; |
159 | 4d7a0880 | blueswir1 | page_index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
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160 | 6ebbf390 | j_mayer | mmu_idx = CPU_MMU_INDEX; |
161 | 551bd27f | ths | if (unlikely(env->tlb_table[mmu_idx][page_index].addr_write !=
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162 | 551bd27f | ths | (addr & (TARGET_PAGE_MASK | (DATA_SIZE - 1))))) {
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163 | e141ab52 | Blue Swirl | glue(glue(glue(HELPER_PREFIX, st), SUFFIX), MMUSUFFIX)(ENV_VAR addr, v, |
164 | e141ab52 | Blue Swirl | mmu_idx); |
165 | b92e5a22 | bellard | } else {
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166 | 4d7a0880 | blueswir1 | physaddr = addr + env->tlb_table[mmu_idx][page_index].addend; |
167 | b92e5a22 | bellard | glue(glue(st, SUFFIX), _raw)((uint8_t *)physaddr, v); |
168 | b92e5a22 | bellard | } |
169 | b92e5a22 | bellard | } |
170 | b92e5a22 | bellard | |
171 | 6ebbf390 | j_mayer | #endif /* ACCESS_TYPE != (NB_MMU_MODES + 1) */ |
172 | 84b7b8e7 | bellard | |
173 | 6ebbf390 | j_mayer | #if ACCESS_TYPE != (NB_MMU_MODES + 1) |
174 | e16c53fa | bellard | |
175 | 2d603d22 | bellard | #if DATA_SIZE == 8 |
176 | e141ab52 | Blue Swirl | static inline float64 glue(glue(CPU_PREFIX, ldfq), MEMSUFFIX)(ENV_PARAM |
177 | e141ab52 | Blue Swirl | target_ulong ptr) |
178 | 2d603d22 | bellard | { |
179 | 2d603d22 | bellard | union {
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180 | 3f87bf69 | bellard | float64 d; |
181 | 2d603d22 | bellard | uint64_t i; |
182 | 2d603d22 | bellard | } u; |
183 | e141ab52 | Blue Swirl | u.i = glue(glue(CPU_PREFIX, ldq), MEMSUFFIX)(ENV_VAR ptr); |
184 | 2d603d22 | bellard | return u.d;
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185 | 2d603d22 | bellard | } |
186 | 2d603d22 | bellard | |
187 | e141ab52 | Blue Swirl | static inline void glue(glue(CPU_PREFIX, stfq), MEMSUFFIX)(ENV_PARAM |
188 | e141ab52 | Blue Swirl | target_ulong ptr, |
189 | e141ab52 | Blue Swirl | float64 v) |
190 | 2d603d22 | bellard | { |
191 | 2d603d22 | bellard | union {
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192 | 3f87bf69 | bellard | float64 d; |
193 | 2d603d22 | bellard | uint64_t i; |
194 | 2d603d22 | bellard | } u; |
195 | 2d603d22 | bellard | u.d = v; |
196 | e141ab52 | Blue Swirl | glue(glue(CPU_PREFIX, stq), MEMSUFFIX)(ENV_VAR ptr, u.i); |
197 | 2d603d22 | bellard | } |
198 | 2d603d22 | bellard | #endif /* DATA_SIZE == 8 */ |
199 | 2d603d22 | bellard | |
200 | 2d603d22 | bellard | #if DATA_SIZE == 4 |
201 | e141ab52 | Blue Swirl | static inline float32 glue(glue(CPU_PREFIX, ldfl), MEMSUFFIX)(ENV_PARAM |
202 | e141ab52 | Blue Swirl | target_ulong ptr) |
203 | 2d603d22 | bellard | { |
204 | 2d603d22 | bellard | union {
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205 | 3f87bf69 | bellard | float32 f; |
206 | 2d603d22 | bellard | uint32_t i; |
207 | 2d603d22 | bellard | } u; |
208 | e141ab52 | Blue Swirl | u.i = glue(glue(CPU_PREFIX, ldl), MEMSUFFIX)(ENV_VAR ptr); |
209 | 2d603d22 | bellard | return u.f;
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210 | 2d603d22 | bellard | } |
211 | 2d603d22 | bellard | |
212 | e141ab52 | Blue Swirl | static inline void glue(glue(CPU_PREFIX, stfl), MEMSUFFIX)(ENV_PARAM |
213 | e141ab52 | Blue Swirl | target_ulong ptr, |
214 | e141ab52 | Blue Swirl | float32 v) |
215 | 2d603d22 | bellard | { |
216 | 2d603d22 | bellard | union {
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217 | 3f87bf69 | bellard | float32 f; |
218 | 2d603d22 | bellard | uint32_t i; |
219 | 2d603d22 | bellard | } u; |
220 | 2d603d22 | bellard | u.f = v; |
221 | e141ab52 | Blue Swirl | glue(glue(CPU_PREFIX, stl), MEMSUFFIX)(ENV_VAR ptr, u.i); |
222 | 2d603d22 | bellard | } |
223 | 2d603d22 | bellard | #endif /* DATA_SIZE == 4 */ |
224 | 2d603d22 | bellard | |
225 | 6ebbf390 | j_mayer | #endif /* ACCESS_TYPE != (NB_MMU_MODES + 1) */ |
226 | 84b7b8e7 | bellard | |
227 | b92e5a22 | bellard | #undef RES_TYPE
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228 | b92e5a22 | bellard | #undef DATA_TYPE
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229 | b92e5a22 | bellard | #undef DATA_STYPE
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230 | b92e5a22 | bellard | #undef SUFFIX
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231 | 61382a50 | bellard | #undef USUFFIX
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232 | b92e5a22 | bellard | #undef DATA_SIZE
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233 | 6ebbf390 | j_mayer | #undef CPU_MMU_INDEX
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234 | 61382a50 | bellard | #undef MMUSUFFIX
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235 | 84b7b8e7 | bellard | #undef ADDR_READ
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236 | e141ab52 | Blue Swirl | #undef ENV_PARAM
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237 | e141ab52 | Blue Swirl | #undef ENV_VAR
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238 | e141ab52 | Blue Swirl | #undef CPU_PREFIX
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239 | e141ab52 | Blue Swirl | #undef HELPER_PREFIX |