Revision 8641136c target-arm/helper.c
| b/target-arm/helper.c | ||
|---|---|---|
| 537 | 537 |
return 0; |
| 538 | 538 |
} |
| 539 | 539 |
|
| 540 |
static int vbar_write(CPUARMState *env, const ARMCPRegInfo *ri, |
|
| 541 |
uint64_t value) |
|
| 542 |
{
|
|
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env->cp15.c12_vbar = value & ~0x1Ful; |
|
| 544 |
return 0; |
|
| 545 |
} |
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| 546 |
|
|
| 540 | 547 |
static int ccsidr_read(CPUARMState *env, const ARMCPRegInfo *ri, |
| 541 | 548 |
uint64_t *value) |
| 542 | 549 |
{
|
| ... | ... | |
| 622 | 629 |
.access = PL1_RW, .type = ARM_CP_NO_MIGRATE, |
| 623 | 630 |
.fieldoffset = offsetof(CPUARMState, cp15.c9_pminten), |
| 624 | 631 |
.resetvalue = 0, .writefn = pmintenclr_write, }, |
| 632 |
{ .name = "VBAR", .cp = 15, .crn = 12, .crm = 0, .opc1 = 0, .opc2 = 0,
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|
| 633 |
.access = PL1_RW, .writefn = vbar_write, |
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.fieldoffset = offsetof(CPUARMState, cp15.c12_vbar), |
|
| 635 |
.resetvalue = 0 }, |
|
| 625 | 636 |
{ .name = "SCR", .cp = 15, .crn = 1, .crm = 1, .opc1 = 0, .opc2 = 0,
|
| 626 | 637 |
.access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c1_scr), |
| 627 | 638 |
.resetvalue = 0, }, |
| ... | ... | |
| 2470 | 2481 |
} |
| 2471 | 2482 |
/* High vectors. */ |
| 2472 | 2483 |
if (env->cp15.c1_sys & (1 << 13)) {
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/* when enabled, base address cannot be remapped. */ |
|
| 2473 | 2485 |
addr += 0xffff0000; |
| 2486 |
} else {
|
|
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/* ARM v7 architectures provide a vector base address register to remap |
|
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* the interrupt vector table. |
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* This register is only followed in non-monitor mode, and has a secure |
|
| 2490 |
* and un-secure copy. Since the cpu is always in a un-secure operation |
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| 2491 |
* and is never in monitor mode this feature is always active. |
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* Note: only bits 31:5 are valid. |
|
| 2493 |
*/ |
|
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addr += env->cp15.c12_vbar; |
|
| 2474 | 2495 |
} |
| 2475 | 2496 |
switch_mode (env, new_mode); |
| 2476 | 2497 |
env->spsr = cpsr_read(env); |
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