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/*
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* Tiny Code Generator for QEMU
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*
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* Copyright (c) 2008 Fabrice Bellard
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include <assert.h> |
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#include <stdarg.h> |
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#include <stdlib.h> |
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#include <stdio.h> |
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#include <string.h> |
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#include <inttypes.h> |
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#include "config.h" |
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#include "osdep.h" |
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#include "tcg.h" |
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int __op_param1, __op_param2, __op_param3;
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#if defined(__sparc__) || defined(__arm__)
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void __op_gen_label1(){}
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void __op_gen_label2(){}
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void __op_gen_label3(){}
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#else
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int __op_gen_label1, __op_gen_label2, __op_gen_label3;
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#endif
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int __op_jmp0, __op_jmp1, __op_jmp2, __op_jmp3;
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#if 0
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#if defined(__s390__)
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static inline void flush_icache_range(unsigned long start, unsigned long stop)
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{
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}
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#elif defined(__ia64__)
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static inline void flush_icache_range(unsigned long start, unsigned long stop) |
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{ |
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while (start < stop) {
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asm volatile ("fc %0" :: "r"(start)); |
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start += 32;
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} |
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asm volatile (";;sync.i;;srlz.i;;"); |
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} |
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#elif defined(__powerpc__)
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#define MIN_CACHE_LINE_SIZE 8 /* conservative value */ |
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static inline void flush_icache_range(unsigned long start, unsigned long stop) |
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{ |
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unsigned long p; |
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start &= ~(MIN_CACHE_LINE_SIZE - 1);
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stop = (stop + MIN_CACHE_LINE_SIZE - 1) & ~(MIN_CACHE_LINE_SIZE - 1); |
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for (p = start; p < stop; p += MIN_CACHE_LINE_SIZE) {
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asm volatile ("dcbst 0,%0" : : "r"(p) : "memory"); |
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} |
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asm volatile ("sync" : : : "memory"); |
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for (p = start; p < stop; p += MIN_CACHE_LINE_SIZE) {
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asm volatile ("icbi 0,%0" : : "r"(p) : "memory"); |
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} |
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asm volatile ("sync" : : : "memory"); |
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asm volatile ("isync" : : : "memory"); |
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} |
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#elif defined(__alpha__)
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static inline void flush_icache_range(unsigned long start, unsigned long stop) |
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{ |
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asm ("imb"); |
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} |
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#elif defined(__sparc__)
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static inline void flush_icache_range(unsigned long start, unsigned long stop) |
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{ |
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unsigned long p; |
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p = start & ~(8UL - 1UL); |
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stop = (stop + (8UL - 1UL)) & ~(8UL - 1UL); |
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for (; p < stop; p += 8) |
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__asm__ __volatile__("flush\t%0" : : "r" (p)); |
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} |
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#elif defined(__arm__)
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static inline void flush_icache_range(unsigned long start, unsigned long stop) |
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{ |
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register unsigned long _beg __asm ("a1") = start; |
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register unsigned long _end __asm ("a2") = stop; |
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register unsigned long _flg __asm ("a3") = 0; |
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__asm __volatile__ ("swi 0x9f0002" : : "r" (_beg), "r" (_end), "r" (_flg)); |
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} |
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#elif defined(__mc68000)
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# include <asm/cachectl.h> |
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static inline void flush_icache_range(unsigned long start, unsigned long stop) |
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{ |
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cacheflush(start,FLUSH_SCOPE_LINE,FLUSH_CACHE_BOTH,stop-start+16);
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} |
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#elif defined(__mips__)
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#include <sys/cachectl.h> |
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static inline void flush_icache_range(unsigned long start, unsigned long stop) |
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{ |
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_flush_cache ((void *)start, stop - start, BCACHE);
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} |
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#else
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#error unsupported CPU
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#endif
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#ifdef __alpha__
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register int gp asm("$29"); |
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static inline void immediate_ldah(void *p, int val) { |
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uint32_t *dest = p; |
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long high = ((val >> 16) + ((val >> 15) & 1)) & 0xffff; |
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*dest &= ~0xffff;
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*dest |= high; |
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*dest |= 31 << 16; |
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} |
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static inline void immediate_lda(void *dest, int val) { |
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*(uint16_t *) dest = val; |
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} |
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void fix_bsr(void *p, int offset) { |
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uint32_t *dest = p; |
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*dest &= ~((1 << 21) - 1); |
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*dest |= (offset >> 2) & ((1 << 21) - 1); |
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} |
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#endif /* __alpha__ */ |
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#ifdef __arm__
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#define ARM_LDR_TABLE_SIZE 1024 |
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typedef struct LDREntry { |
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uint8_t *ptr; |
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uint32_t *data_ptr; |
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unsigned type:2; |
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} LDREntry; |
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static LDREntry arm_ldr_table[1024]; |
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static uint32_t arm_data_table[ARM_LDR_TABLE_SIZE];
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extern char exec_loop; |
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static inline void arm_reloc_pc24(uint32_t *ptr, uint32_t insn, int val) |
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{ |
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*ptr = (insn & ~0xffffff) | ((insn + ((val - (int)ptr) >> 2)) & 0xffffff); |
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} |
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static uint8_t *arm_flush_ldr(uint8_t *gen_code_ptr,
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LDREntry *ldr_start, LDREntry *ldr_end, |
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uint32_t *data_start, uint32_t *data_end, |
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int gen_jmp)
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{ |
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LDREntry *le; |
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uint32_t *ptr; |
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int offset, data_size, target;
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uint8_t *data_ptr; |
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uint32_t insn; |
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uint32_t mask; |
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data_size = (data_end - data_start) << 2;
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if (gen_jmp) {
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/* generate branch to skip the data */
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if (data_size == 0) |
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return gen_code_ptr;
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target = (long)gen_code_ptr + data_size + 4; |
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arm_reloc_pc24((uint32_t *)gen_code_ptr, 0xeafffffe, target);
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gen_code_ptr += 4;
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} |
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/* copy the data */
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data_ptr = gen_code_ptr; |
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memcpy(gen_code_ptr, data_start, data_size); |
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gen_code_ptr += data_size; |
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/* patch the ldr to point to the data */
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for(le = ldr_start; le < ldr_end; le++) {
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ptr = (uint32_t *)le->ptr; |
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offset = ((unsigned long)(le->data_ptr) - (unsigned long)data_start) + |
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(unsigned long)data_ptr - |
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(unsigned long)ptr - 8; |
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if (offset < 0) { |
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fprintf(stderr, "Negative constant pool offset\n");
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tcg_abort(); |
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} |
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switch (le->type) {
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case 0: /* ldr */ |
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mask = ~0x00800fff;
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if (offset >= 4096) { |
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fprintf(stderr, "Bad ldr offset\n");
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tcg_abort(); |
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} |
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break;
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case 1: /* ldc */ |
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mask = ~0x008000ff;
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if (offset >= 1024 ) { |
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fprintf(stderr, "Bad ldc offset\n");
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tcg_abort(); |
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} |
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break;
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case 2: /* add */ |
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mask = ~0xfff;
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if (offset >= 1024 ) { |
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fprintf(stderr, "Bad add offset\n");
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tcg_abort(); |
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} |
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break;
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default:
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fprintf(stderr, "Bad pc relative fixup\n");
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tcg_abort(); |
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} |
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insn = *ptr & mask; |
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switch (le->type) {
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case 0: /* ldr */ |
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insn |= offset | 0x00800000;
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break;
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case 1: /* ldc */ |
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insn |= (offset >> 2) | 0x00800000; |
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break;
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case 2: /* add */ |
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insn |= (offset >> 2) | 0xf00; |
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break;
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} |
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*ptr = insn; |
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} |
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return gen_code_ptr;
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} |
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#endif /* __arm__ */ |
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#ifdef __ia64
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/* Patch instruction with "val" where "mask" has 1 bits. */
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static inline void ia64_patch (uint64_t insn_addr, uint64_t mask, uint64_t val) |
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{ |
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uint64_t m0, m1, v0, v1, b0, b1, *b = (uint64_t *) (insn_addr & -16);
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# define insn_mask ((1UL << 41) - 1) |
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unsigned long shift; |
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b0 = b[0]; b1 = b[1]; |
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shift = 5 + 41 * (insn_addr % 16); /* 5 template, 3 x 41-bit insns */ |
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if (shift >= 64) { |
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m1 = mask << (shift - 64);
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v1 = val << (shift - 64);
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} else {
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m0 = mask << shift; m1 = mask >> (64 - shift);
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v0 = val << shift; v1 = val >> (64 - shift);
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b[0] = (b0 & ~m0) | (v0 & m0);
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} |
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b[1] = (b1 & ~m1) | (v1 & m1);
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} |
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static inline void ia64_patch_imm60 (uint64_t insn_addr, uint64_t val) |
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{ |
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ia64_patch(insn_addr, |
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0x011ffffe000UL,
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( ((val & 0x0800000000000000UL) >> 23) /* bit 59 -> 36 */ |
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| ((val & 0x00000000000fffffUL) << 13) /* bit 0 -> 13 */)); |
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ia64_patch(insn_addr - 1, 0x1fffffffffcUL, val >> 18); |
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} |
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static inline void ia64_imm64 (void *insn, uint64_t val) |
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{ |
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/* Ignore the slot number of the relocation; GCC and Intel
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toolchains differed for some time on whether IMM64 relocs are
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against slot 1 (Intel) or slot 2 (GCC). */
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uint64_t insn_addr = (uint64_t) insn & ~3UL;
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ia64_patch(insn_addr + 2,
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0x01fffefe000UL,
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( ((val & 0x8000000000000000UL) >> 27) /* bit 63 -> 36 */ |
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| ((val & 0x0000000000200000UL) << 0) /* bit 21 -> 21 */ |
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| ((val & 0x00000000001f0000UL) << 6) /* bit 16 -> 22 */ |
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| ((val & 0x000000000000ff80UL) << 20) /* bit 7 -> 27 */ |
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| ((val & 0x000000000000007fUL) << 13) /* bit 0 -> 13 */) |
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); |
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ia64_patch(insn_addr + 1, 0x1ffffffffffUL, val >> 22); |
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} |
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static inline void ia64_imm60b (void *insn, uint64_t val) |
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{ |
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/* Ignore the slot number of the relocation; GCC and Intel
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toolchains differed for some time on whether IMM64 relocs are
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against slot 1 (Intel) or slot 2 (GCC). */
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uint64_t insn_addr = (uint64_t) insn & ~3UL;
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if (val + ((uint64_t) 1 << 59) >= (1UL << 60)) |
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fprintf(stderr, "%s: value %ld out of IMM60 range\n",
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__FUNCTION__, (int64_t) val); |
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ia64_patch_imm60(insn_addr + 2, val);
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} |
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static inline void ia64_imm22 (void *insn, uint64_t val) |
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{ |
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if (val + (1 << 21) >= (1 << 22)) |
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fprintf(stderr, "%s: value %li out of IMM22 range\n",
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__FUNCTION__, (int64_t)val); |
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ia64_patch((uint64_t) insn, 0x01fffcfe000UL,
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( ((val & 0x200000UL) << 15) /* bit 21 -> 36 */ |
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| ((val & 0x1f0000UL) << 6) /* bit 16 -> 22 */ |
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| ((val & 0x00ff80UL) << 20) /* bit 7 -> 27 */ |
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| ((val & 0x00007fUL) << 13) /* bit 0 -> 13 */)); |
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} |
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/* Like ia64_imm22(), but also clear bits 20-21. For addl, this has
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the effect of turning "addl rX=imm22,rY" into "addl
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rX=imm22,r0". */
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static inline void ia64_imm22_r0 (void *insn, uint64_t val) |
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{ |
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if (val + (1 << 21) >= (1 << 22)) |
329 |
fprintf(stderr, "%s: value %li out of IMM22 range\n",
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__FUNCTION__, (int64_t)val); |
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ia64_patch((uint64_t) insn, 0x01fffcfe000UL | (0x3UL << 20), |
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( ((val & 0x200000UL) << 15) /* bit 21 -> 36 */ |
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| ((val & 0x1f0000UL) << 6) /* bit 16 -> 22 */ |
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| ((val & 0x00ff80UL) << 20) /* bit 7 -> 27 */ |
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| ((val & 0x00007fUL) << 13) /* bit 0 -> 13 */)); |
336 |
} |
337 |
|
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static inline void ia64_imm21b (void *insn, uint64_t val) |
339 |
{ |
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if (val + (1 << 20) >= (1 << 21)) |
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fprintf(stderr, "%s: value %li out of IMM21b range\n",
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__FUNCTION__, (int64_t)val); |
343 |
ia64_patch((uint64_t) insn, 0x11ffffe000UL,
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( ((val & 0x100000UL) << 16) /* bit 20 -> 36 */ |
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| ((val & 0x0fffffUL) << 13) /* bit 0 -> 13 */)); |
346 |
} |
347 |
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348 |
static inline void ia64_nop_b (void *insn) |
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{ |
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ia64_patch((uint64_t) insn, (1UL << 41) - 1, 2UL << 37); |
351 |
} |
352 |
|
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static inline void ia64_ldxmov(void *insn, uint64_t val) |
354 |
{ |
355 |
if (val + (1 << 21) < (1 << 22)) |
356 |
ia64_patch((uint64_t) insn, 0x1fff80fe000UL, 8UL << 37); |
357 |
} |
358 |
|
359 |
static inline int ia64_patch_ltoff(void *insn, uint64_t val, |
360 |
int relaxable)
|
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{ |
362 |
if (relaxable && (val + (1 << 21) < (1 << 22))) { |
363 |
ia64_imm22_r0(insn, val); |
364 |
return 0; |
365 |
} |
366 |
return 1; |
367 |
} |
368 |
|
369 |
struct ia64_fixup {
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370 |
struct ia64_fixup *next;
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371 |
void *addr; /* address that needs to be patched */ |
372 |
long value;
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}; |
374 |
|
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#define IA64_PLT(insn, plt_index) \
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376 |
do { \
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struct ia64_fixup *fixup = alloca(sizeof(*fixup)); \ |
378 |
fixup->next = plt_fixes; \ |
379 |
plt_fixes = fixup; \ |
380 |
fixup->addr = (insn); \ |
381 |
fixup->value = (plt_index); \ |
382 |
plt_offset[(plt_index)] = 1; \
|
383 |
} while (0) |
384 |
|
385 |
#define IA64_LTOFF(insn, val, relaxable) \
|
386 |
do { \
|
387 |
if (ia64_patch_ltoff(insn, val, relaxable)) { \
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388 |
struct ia64_fixup *fixup = alloca(sizeof(*fixup)); \ |
389 |
fixup->next = ltoff_fixes; \ |
390 |
ltoff_fixes = fixup; \ |
391 |
fixup->addr = (insn); \ |
392 |
fixup->value = (val); \ |
393 |
} \ |
394 |
} while (0) |
395 |
|
396 |
static inline void ia64_apply_fixes (uint8_t **gen_code_pp, |
397 |
struct ia64_fixup *ltoff_fixes,
|
398 |
uint64_t gp, |
399 |
struct ia64_fixup *plt_fixes,
|
400 |
int num_plts,
|
401 |
unsigned long *plt_target, |
402 |
unsigned int *plt_offset) |
403 |
{ |
404 |
static const uint8_t plt_bundle[] = { |
405 |
0x04, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, /* nop 0; movl r1=GP */ |
406 |
0x00, 0x00, 0x00, 0x20, 0x00, 0x00, 0x00, 0x60, |
407 |
|
408 |
0x05, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, /* nop 0; brl IP */ |
409 |
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0 |
410 |
}; |
411 |
uint8_t *gen_code_ptr = *gen_code_pp, *plt_start, *got_start; |
412 |
uint64_t *vp; |
413 |
struct ia64_fixup *fixup;
|
414 |
unsigned int offset = 0; |
415 |
struct fdesc {
|
416 |
long ip;
|
417 |
long gp;
|
418 |
} *fdesc; |
419 |
int i;
|
420 |
|
421 |
if (plt_fixes) {
|
422 |
plt_start = gen_code_ptr; |
423 |
|
424 |
for (i = 0; i < num_plts; ++i) { |
425 |
if (plt_offset[i]) {
|
426 |
plt_offset[i] = offset; |
427 |
offset += sizeof(plt_bundle);
|
428 |
|
429 |
fdesc = (struct fdesc *) plt_target[i];
|
430 |
memcpy(gen_code_ptr, plt_bundle, sizeof(plt_bundle));
|
431 |
ia64_imm64 (gen_code_ptr + 0x02, fdesc->gp);
|
432 |
ia64_imm60b(gen_code_ptr + 0x12,
|
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(fdesc->ip - (long) (gen_code_ptr + 0x10)) >> 4); |
434 |
gen_code_ptr += sizeof(plt_bundle);
|
435 |
} |
436 |
} |
437 |
|
438 |
for (fixup = plt_fixes; fixup; fixup = fixup->next)
|
439 |
ia64_imm21b(fixup->addr, |
440 |
((long) plt_start + plt_offset[fixup->value]
|
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- ((long) fixup->addr & ~0xf)) >> 4); |
442 |
} |
443 |
|
444 |
got_start = gen_code_ptr; |
445 |
|
446 |
/* First, create the GOT: */
|
447 |
for (fixup = ltoff_fixes; fixup; fixup = fixup->next) {
|
448 |
/* first check if we already have this value in the GOT: */
|
449 |
for (vp = (uint64_t *) got_start; vp < (uint64_t *) gen_code_ptr; ++vp)
|
450 |
if (*vp == fixup->value)
|
451 |
break;
|
452 |
if (vp == (uint64_t *) gen_code_ptr) {
|
453 |
/* Nope, we need to put the value in the GOT: */
|
454 |
*vp = fixup->value; |
455 |
gen_code_ptr += 8;
|
456 |
} |
457 |
ia64_imm22(fixup->addr, (long) vp - gp);
|
458 |
} |
459 |
/* Keep code ptr aligned. */
|
460 |
if ((long) gen_code_ptr & 15) |
461 |
gen_code_ptr += 8;
|
462 |
*gen_code_pp = gen_code_ptr; |
463 |
} |
464 |
#endif
|
465 |
#endif
|
466 |
|
467 |
#ifdef CONFIG_DYNGEN_OP
|
468 |
|
469 |
#if defined __hppa__
|
470 |
struct hppa_branch_stub {
|
471 |
uint32_t *location; |
472 |
long target;
|
473 |
struct hppa_branch_stub *next;
|
474 |
}; |
475 |
|
476 |
#define HPPA_RECORD_BRANCH(LIST, LOC, TARGET) \
|
477 |
do { \
|
478 |
struct hppa_branch_stub *stub = alloca(sizeof(struct hppa_branch_stub)); \ |
479 |
stub->location = LOC; \ |
480 |
stub->target = TARGET; \ |
481 |
stub->next = LIST; \ |
482 |
LIST = stub; \ |
483 |
} while (0) |
484 |
|
485 |
static inline void hppa_process_stubs(struct hppa_branch_stub *stub, |
486 |
uint8_t **gen_code_pp) |
487 |
{ |
488 |
uint32_t *s = (uint32_t *)*gen_code_pp; |
489 |
uint32_t *p = s + 1;
|
490 |
|
491 |
if (!stub) return; |
492 |
|
493 |
for (; stub != NULL; stub = stub->next) { |
494 |
unsigned long l = (unsigned long)p; |
495 |
/* stub:
|
496 |
* ldil L'target, %r1
|
497 |
* be,n R'target(%sr4,%r1)
|
498 |
*/
|
499 |
*p++ = 0x20200000 | reassemble_21(lrsel(stub->target, 0)); |
500 |
*p++ = 0xe0202002 | (reassemble_17(rrsel(stub->target, 0) >> 2)); |
501 |
hppa_patch17f(stub->location, l, 0);
|
502 |
} |
503 |
/* b,l,n stub,%r0 */
|
504 |
*s = 0xe8000002 | reassemble_17((p - s) - 2); |
505 |
*gen_code_pp = (uint8_t *)p; |
506 |
} |
507 |
#endif /* __hppa__ */ |
508 |
|
509 |
const TCGArg *dyngen_op(TCGContext *s, int opc, const TCGArg *opparam_ptr) |
510 |
{ |
511 |
uint8_t *gen_code_ptr; |
512 |
|
513 |
#ifdef __hppa__
|
514 |
struct hppa_branch_stub *hppa_stubs = NULL; |
515 |
#endif
|
516 |
|
517 |
gen_code_ptr = s->code_ptr; |
518 |
switch(opc) {
|
519 |
|
520 |
/* op.h is dynamically generated by dyngen.c from op.c */
|
521 |
#include "op.h" |
522 |
|
523 |
default:
|
524 |
tcg_abort(); |
525 |
} |
526 |
|
527 |
#ifdef __hppa__
|
528 |
hppa_process_stubs(hppa_stubs, &gen_code_ptr); |
529 |
#endif
|
530 |
|
531 |
s->code_ptr = gen_code_ptr; |
532 |
return opparam_ptr;
|
533 |
} |
534 |
#endif
|