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1 | dbda808a | bellard | /*
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2 | dbda808a | bellard | * OpenPIC emulation
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3 | 5fafdf24 | ths | *
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4 | dbda808a | bellard | * Copyright (c) 2004 Jocelyn Mayer
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5 | 5fafdf24 | ths | *
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6 | dbda808a | bellard | * Permission is hereby granted, free of charge, to any person obtaining a copy
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7 | dbda808a | bellard | * of this software and associated documentation files (the "Software"), to deal
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8 | dbda808a | bellard | * in the Software without restriction, including without limitation the rights
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9 | dbda808a | bellard | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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10 | dbda808a | bellard | * copies of the Software, and to permit persons to whom the Software is
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11 | dbda808a | bellard | * furnished to do so, subject to the following conditions:
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12 | dbda808a | bellard | *
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13 | dbda808a | bellard | * The above copyright notice and this permission notice shall be included in
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14 | dbda808a | bellard | * all copies or substantial portions of the Software.
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15 | dbda808a | bellard | *
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16 | dbda808a | bellard | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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17 | dbda808a | bellard | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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18 | dbda808a | bellard | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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19 | dbda808a | bellard | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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20 | dbda808a | bellard | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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21 | dbda808a | bellard | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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22 | dbda808a | bellard | * THE SOFTWARE.
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23 | dbda808a | bellard | */
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24 | dbda808a | bellard | /*
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25 | dbda808a | bellard | *
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26 | dbda808a | bellard | * Based on OpenPic implementations:
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27 | 67b55785 | blueswir1 | * - Intel GW80314 I/O companion chip developer's manual
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28 | dbda808a | bellard | * - Motorola MPC8245 & MPC8540 user manuals.
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29 | dbda808a | bellard | * - Motorola MCP750 (aka Raven) programmer manual.
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30 | dbda808a | bellard | * - Motorola Harrier programmer manuel
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31 | dbda808a | bellard | *
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32 | dbda808a | bellard | * Serial interrupts, as implemented in Raven chipset are not supported yet.
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33 | 5fafdf24 | ths | *
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34 | dbda808a | bellard | */
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35 | 87ecb68b | pbrook | #include "hw.h" |
36 | 87ecb68b | pbrook | #include "ppc_mac.h" |
37 | 87ecb68b | pbrook | #include "pci.h" |
38 | b7169916 | aurel32 | #include "openpic.h" |
39 | dbda808a | bellard | |
40 | 611493d9 | bellard | //#define DEBUG_OPENPIC
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41 | dbda808a | bellard | |
42 | dbda808a | bellard | #ifdef DEBUG_OPENPIC
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43 | 001faf32 | Blue Swirl | #define DPRINTF(fmt, ...) do { printf(fmt , ## __VA_ARGS__); } while (0) |
44 | dbda808a | bellard | #else
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45 | 001faf32 | Blue Swirl | #define DPRINTF(fmt, ...) do { } while (0) |
46 | dbda808a | bellard | #endif
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47 | dbda808a | bellard | |
48 | dbda808a | bellard | #define USE_MPCxxx /* Intel model is broken, for now */ |
49 | dbda808a | bellard | |
50 | dbda808a | bellard | #if defined (USE_INTEL_GW80314)
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51 | dbda808a | bellard | /* Intel GW80314 I/O Companion chip */
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52 | dbda808a | bellard | |
53 | dbda808a | bellard | #define MAX_CPU 4 |
54 | dbda808a | bellard | #define MAX_IRQ 32 |
55 | dbda808a | bellard | #define MAX_DBL 4 |
56 | dbda808a | bellard | #define MAX_MBX 4 |
57 | dbda808a | bellard | #define MAX_TMR 4 |
58 | dbda808a | bellard | #define VECTOR_BITS 8 |
59 | dbda808a | bellard | #define MAX_IPI 0 |
60 | dbda808a | bellard | |
61 | dbda808a | bellard | #define VID (0x00000000) |
62 | dbda808a | bellard | |
63 | dbda808a | bellard | #elif defined(USE_MPCxxx)
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64 | dbda808a | bellard | |
65 | dbda808a | bellard | #define MAX_CPU 2 |
66 | b7169916 | aurel32 | #define MAX_IRQ 128 |
67 | dbda808a | bellard | #define MAX_DBL 0 |
68 | dbda808a | bellard | #define MAX_MBX 0 |
69 | dbda808a | bellard | #define MAX_TMR 4 |
70 | dbda808a | bellard | #define VECTOR_BITS 8 |
71 | dbda808a | bellard | #define MAX_IPI 4 |
72 | dbda808a | bellard | #define VID 0x03 /* MPIC version ID */ |
73 | dbda808a | bellard | #define VENI 0x00000000 /* Vendor ID */ |
74 | dbda808a | bellard | |
75 | dbda808a | bellard | enum {
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76 | dbda808a | bellard | IRQ_IPVP = 0,
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77 | dbda808a | bellard | IRQ_IDE, |
78 | dbda808a | bellard | }; |
79 | dbda808a | bellard | |
80 | b7169916 | aurel32 | /* OpenPIC */
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81 | b7169916 | aurel32 | #define OPENPIC_MAX_CPU 2 |
82 | b7169916 | aurel32 | #define OPENPIC_MAX_IRQ 64 |
83 | b7169916 | aurel32 | #define OPENPIC_EXT_IRQ 48 |
84 | b7169916 | aurel32 | #define OPENPIC_MAX_TMR MAX_TMR
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85 | b7169916 | aurel32 | #define OPENPIC_MAX_IPI MAX_IPI
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86 | dbda808a | bellard | |
87 | b7169916 | aurel32 | /* Interrupt definitions */
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88 | b7169916 | aurel32 | #define OPENPIC_IRQ_FE (OPENPIC_EXT_IRQ) /* Internal functional IRQ */ |
89 | b7169916 | aurel32 | #define OPENPIC_IRQ_ERR (OPENPIC_EXT_IRQ + 1) /* Error IRQ */ |
90 | b7169916 | aurel32 | #define OPENPIC_IRQ_TIM0 (OPENPIC_EXT_IRQ + 2) /* First timer IRQ */ |
91 | b7169916 | aurel32 | #if OPENPIC_MAX_IPI > 0 |
92 | b7169916 | aurel32 | #define OPENPIC_IRQ_IPI0 (OPENPIC_IRQ_TIM0 + OPENPIC_MAX_TMR) /* First IPI IRQ */ |
93 | b7169916 | aurel32 | #define OPENPIC_IRQ_DBL0 (OPENPIC_IRQ_IPI0 + (OPENPIC_MAX_CPU * OPENPIC_MAX_IPI)) /* First doorbell IRQ */ |
94 | dbda808a | bellard | #else
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95 | b7169916 | aurel32 | #define OPENPIC_IRQ_DBL0 (OPENPIC_IRQ_TIM0 + OPENPIC_MAX_TMR) /* First doorbell IRQ */ |
96 | b7169916 | aurel32 | #define OPENPIC_IRQ_MBX0 (OPENPIC_IRQ_DBL0 + OPENPIC_MAX_DBL) /* First mailbox IRQ */ |
97 | dbda808a | bellard | #endif
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98 | dbda808a | bellard | |
99 | b7169916 | aurel32 | /* MPIC */
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100 | b7169916 | aurel32 | #define MPIC_MAX_CPU 1 |
101 | b7169916 | aurel32 | #define MPIC_MAX_EXT 12 |
102 | b7169916 | aurel32 | #define MPIC_MAX_INT 64 |
103 | b7169916 | aurel32 | #define MPIC_MAX_MSG 4 |
104 | b7169916 | aurel32 | #define MPIC_MAX_MSI 8 |
105 | b7169916 | aurel32 | #define MPIC_MAX_TMR MAX_TMR
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106 | b7169916 | aurel32 | #define MPIC_MAX_IPI MAX_IPI
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107 | b7169916 | aurel32 | #define MPIC_MAX_IRQ (MPIC_MAX_EXT + MPIC_MAX_INT + MPIC_MAX_TMR + MPIC_MAX_MSG + MPIC_MAX_MSI + (MPIC_MAX_IPI * MPIC_MAX_CPU))
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108 | dbda808a | bellard | |
109 | dbda808a | bellard | /* Interrupt definitions */
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110 | b7169916 | aurel32 | #define MPIC_EXT_IRQ 0 |
111 | b7169916 | aurel32 | #define MPIC_INT_IRQ (MPIC_EXT_IRQ + MPIC_MAX_EXT)
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112 | b7169916 | aurel32 | #define MPIC_TMR_IRQ (MPIC_INT_IRQ + MPIC_MAX_INT)
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113 | b7169916 | aurel32 | #define MPIC_MSG_IRQ (MPIC_TMR_IRQ + MPIC_MAX_TMR)
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114 | b7169916 | aurel32 | #define MPIC_MSI_IRQ (MPIC_MSG_IRQ + MPIC_MAX_MSG)
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115 | b7169916 | aurel32 | #define MPIC_IPI_IRQ (MPIC_MSI_IRQ + MPIC_MAX_MSI)
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116 | b7169916 | aurel32 | |
117 | b7169916 | aurel32 | #define MPIC_GLB_REG_START 0x0 |
118 | b7169916 | aurel32 | #define MPIC_GLB_REG_SIZE 0x10F0 |
119 | b7169916 | aurel32 | #define MPIC_TMR_REG_START 0x10F0 |
120 | b7169916 | aurel32 | #define MPIC_TMR_REG_SIZE 0x220 |
121 | b7169916 | aurel32 | #define MPIC_EXT_REG_START 0x10000 |
122 | b7169916 | aurel32 | #define MPIC_EXT_REG_SIZE 0x180 |
123 | b7169916 | aurel32 | #define MPIC_INT_REG_START 0x10200 |
124 | b7169916 | aurel32 | #define MPIC_INT_REG_SIZE 0x800 |
125 | b7169916 | aurel32 | #define MPIC_MSG_REG_START 0x11600 |
126 | b7169916 | aurel32 | #define MPIC_MSG_REG_SIZE 0x100 |
127 | b7169916 | aurel32 | #define MPIC_MSI_REG_START 0x11C00 |
128 | b7169916 | aurel32 | #define MPIC_MSI_REG_SIZE 0x100 |
129 | b7169916 | aurel32 | #define MPIC_CPU_REG_START 0x20000 |
130 | b7169916 | aurel32 | #define MPIC_CPU_REG_SIZE 0x100 |
131 | b7169916 | aurel32 | |
132 | b7169916 | aurel32 | enum mpic_ide_bits {
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133 | b7169916 | aurel32 | IDR_EP = 0,
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134 | b7169916 | aurel32 | IDR_CI0 = 1,
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135 | b7169916 | aurel32 | IDR_CI1 = 2,
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136 | b7169916 | aurel32 | IDR_P1 = 30,
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137 | b7169916 | aurel32 | IDR_P0 = 31,
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138 | b7169916 | aurel32 | }; |
139 | b7169916 | aurel32 | |
140 | dbda808a | bellard | #else
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141 | b7169916 | aurel32 | #error "Please select which OpenPic implementation is to be emulated" |
142 | dbda808a | bellard | #endif
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143 | dbda808a | bellard | |
144 | dbda808a | bellard | #define BF_WIDTH(_bits_) \
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145 | dbda808a | bellard | (((_bits_) + (sizeof(uint32_t) * 8) - 1) / (sizeof(uint32_t) * 8)) |
146 | dbda808a | bellard | |
147 | dbda808a | bellard | static inline void set_bit (uint32_t *field, int bit) |
148 | dbda808a | bellard | { |
149 | dbda808a | bellard | field[bit >> 5] |= 1 << (bit & 0x1F); |
150 | dbda808a | bellard | } |
151 | dbda808a | bellard | |
152 | dbda808a | bellard | static inline void reset_bit (uint32_t *field, int bit) |
153 | dbda808a | bellard | { |
154 | dbda808a | bellard | field[bit >> 5] &= ~(1 << (bit & 0x1F)); |
155 | dbda808a | bellard | } |
156 | dbda808a | bellard | |
157 | dbda808a | bellard | static inline int test_bit (uint32_t *field, int bit) |
158 | dbda808a | bellard | { |
159 | dbda808a | bellard | return (field[bit >> 5] & 1 << (bit & 0x1F)) != 0; |
160 | dbda808a | bellard | } |
161 | dbda808a | bellard | |
162 | dbda808a | bellard | enum {
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163 | dbda808a | bellard | IRQ_EXTERNAL = 0x01,
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164 | dbda808a | bellard | IRQ_INTERNAL = 0x02,
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165 | dbda808a | bellard | IRQ_TIMER = 0x04,
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166 | dbda808a | bellard | IRQ_SPECIAL = 0x08,
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167 | b1d8e52e | blueswir1 | }; |
168 | dbda808a | bellard | |
169 | dbda808a | bellard | typedef struct IRQ_queue_t { |
170 | dbda808a | bellard | uint32_t queue[BF_WIDTH(MAX_IRQ)]; |
171 | dbda808a | bellard | int next;
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172 | dbda808a | bellard | int priority;
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173 | dbda808a | bellard | } IRQ_queue_t; |
174 | dbda808a | bellard | |
175 | dbda808a | bellard | typedef struct IRQ_src_t { |
176 | dbda808a | bellard | uint32_t ipvp; /* IRQ vector/priority register */
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177 | dbda808a | bellard | uint32_t ide; /* IRQ destination register */
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178 | dbda808a | bellard | int type;
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179 | dbda808a | bellard | int last_cpu;
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180 | 611493d9 | bellard | int pending; /* TRUE if IRQ is pending */ |
181 | dbda808a | bellard | } IRQ_src_t; |
182 | dbda808a | bellard | |
183 | dbda808a | bellard | enum IPVP_bits {
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184 | dbda808a | bellard | IPVP_MASK = 31,
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185 | dbda808a | bellard | IPVP_ACTIVITY = 30,
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186 | dbda808a | bellard | IPVP_MODE = 29,
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187 | dbda808a | bellard | IPVP_POLARITY = 23,
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188 | dbda808a | bellard | IPVP_SENSE = 22,
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189 | dbda808a | bellard | }; |
190 | dbda808a | bellard | #define IPVP_PRIORITY_MASK (0x1F << 16) |
191 | 611493d9 | bellard | #define IPVP_PRIORITY(_ipvpr_) ((int)(((_ipvpr_) & IPVP_PRIORITY_MASK) >> 16)) |
192 | dbda808a | bellard | #define IPVP_VECTOR_MASK ((1 << VECTOR_BITS) - 1) |
193 | dbda808a | bellard | #define IPVP_VECTOR(_ipvpr_) ((_ipvpr_) & IPVP_VECTOR_MASK)
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194 | dbda808a | bellard | |
195 | dbda808a | bellard | typedef struct IRQ_dst_t { |
196 | b7169916 | aurel32 | uint32_t tfrr; |
197 | dbda808a | bellard | uint32_t pctp; /* CPU current task priority */
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198 | dbda808a | bellard | uint32_t pcsr; /* CPU sensitivity register */
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199 | dbda808a | bellard | IRQ_queue_t raised; |
200 | dbda808a | bellard | IRQ_queue_t servicing; |
201 | e9df014c | j_mayer | qemu_irq *irqs; |
202 | dbda808a | bellard | } IRQ_dst_t; |
203 | dbda808a | bellard | |
204 | d537cf6c | pbrook | typedef struct openpic_t { |
205 | dbda808a | bellard | PCIDevice pci_dev; |
206 | 91d848eb | bellard | int mem_index;
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207 | dbda808a | bellard | /* Global registers */
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208 | dbda808a | bellard | uint32_t frep; /* Feature reporting register */
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209 | dbda808a | bellard | uint32_t glbc; /* Global configuration register */
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210 | dbda808a | bellard | uint32_t micr; /* MPIC interrupt configuration register */
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211 | dbda808a | bellard | uint32_t veni; /* Vendor identification register */
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212 | e9df014c | j_mayer | uint32_t pint; /* Processor initialization register */
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213 | dbda808a | bellard | uint32_t spve; /* Spurious vector register */
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214 | dbda808a | bellard | uint32_t tifr; /* Timer frequency reporting register */
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215 | dbda808a | bellard | /* Source registers */
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216 | dbda808a | bellard | IRQ_src_t src[MAX_IRQ]; |
217 | dbda808a | bellard | /* Local registers per output pin */
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218 | dbda808a | bellard | IRQ_dst_t dst[MAX_CPU]; |
219 | dbda808a | bellard | int nb_cpus;
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220 | dbda808a | bellard | /* Timer registers */
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221 | dbda808a | bellard | struct {
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222 | dbda808a | bellard | uint32_t ticc; /* Global timer current count register */
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223 | dbda808a | bellard | uint32_t tibc; /* Global timer base count register */
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224 | dbda808a | bellard | } timers[MAX_TMR]; |
225 | dbda808a | bellard | #if MAX_DBL > 0 |
226 | dbda808a | bellard | /* Doorbell registers */
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227 | dbda808a | bellard | uint32_t dar; /* Doorbell activate register */
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228 | dbda808a | bellard | struct {
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229 | dbda808a | bellard | uint32_t dmr; /* Doorbell messaging register */
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230 | dbda808a | bellard | } doorbells[MAX_DBL]; |
231 | dbda808a | bellard | #endif
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232 | dbda808a | bellard | #if MAX_MBX > 0 |
233 | dbda808a | bellard | /* Mailbox registers */
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234 | dbda808a | bellard | struct {
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235 | dbda808a | bellard | uint32_t mbr; /* Mailbox register */
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236 | dbda808a | bellard | } mailboxes[MAX_MAILBOXES]; |
237 | dbda808a | bellard | #endif
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238 | e9df014c | j_mayer | /* IRQ out is used when in bypass mode (not implemented) */
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239 | e9df014c | j_mayer | qemu_irq irq_out; |
240 | b7169916 | aurel32 | int max_irq;
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241 | b7169916 | aurel32 | int irq_ipi0;
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242 | b7169916 | aurel32 | int irq_tim0;
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243 | b7169916 | aurel32 | int need_swap;
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244 | b7169916 | aurel32 | void (*reset) (void *); |
245 | b7169916 | aurel32 | void (*irq_raise) (struct openpic_t *, int, IRQ_src_t *); |
246 | d537cf6c | pbrook | } openpic_t; |
247 | dbda808a | bellard | |
248 | b7169916 | aurel32 | static inline uint32_t openpic_swap32(openpic_t *opp, uint32_t val) |
249 | b7169916 | aurel32 | { |
250 | b7169916 | aurel32 | if (opp->need_swap)
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251 | b7169916 | aurel32 | return bswap32(val);
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252 | b7169916 | aurel32 | |
253 | b7169916 | aurel32 | return val;
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254 | b7169916 | aurel32 | } |
255 | b7169916 | aurel32 | |
256 | dbda808a | bellard | static inline void IRQ_setbit (IRQ_queue_t *q, int n_IRQ) |
257 | dbda808a | bellard | { |
258 | dbda808a | bellard | set_bit(q->queue, n_IRQ); |
259 | dbda808a | bellard | } |
260 | dbda808a | bellard | |
261 | dbda808a | bellard | static inline void IRQ_resetbit (IRQ_queue_t *q, int n_IRQ) |
262 | dbda808a | bellard | { |
263 | dbda808a | bellard | reset_bit(q->queue, n_IRQ); |
264 | dbda808a | bellard | } |
265 | dbda808a | bellard | |
266 | dbda808a | bellard | static inline int IRQ_testbit (IRQ_queue_t *q, int n_IRQ) |
267 | dbda808a | bellard | { |
268 | dbda808a | bellard | return test_bit(q->queue, n_IRQ);
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269 | dbda808a | bellard | } |
270 | dbda808a | bellard | |
271 | dbda808a | bellard | static void IRQ_check (openpic_t *opp, IRQ_queue_t *q) |
272 | dbda808a | bellard | { |
273 | dbda808a | bellard | int next, i;
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274 | dbda808a | bellard | int priority;
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275 | dbda808a | bellard | |
276 | dbda808a | bellard | next = -1;
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277 | dbda808a | bellard | priority = -1;
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278 | b7169916 | aurel32 | for (i = 0; i < opp->max_irq; i++) { |
279 | dbda808a | bellard | if (IRQ_testbit(q, i)) {
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280 | 5fafdf24 | ths | DPRINTF("IRQ_check: irq %d set ipvp_pr=%d pr=%d\n",
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281 | 611493d9 | bellard | i, IPVP_PRIORITY(opp->src[i].ipvp), priority); |
282 | dbda808a | bellard | if (IPVP_PRIORITY(opp->src[i].ipvp) > priority) {
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283 | dbda808a | bellard | next = i; |
284 | dbda808a | bellard | priority = IPVP_PRIORITY(opp->src[i].ipvp); |
285 | dbda808a | bellard | } |
286 | dbda808a | bellard | } |
287 | dbda808a | bellard | } |
288 | dbda808a | bellard | q->next = next; |
289 | dbda808a | bellard | q->priority = priority; |
290 | dbda808a | bellard | } |
291 | dbda808a | bellard | |
292 | dbda808a | bellard | static int IRQ_get_next (openpic_t *opp, IRQ_queue_t *q) |
293 | dbda808a | bellard | { |
294 | dbda808a | bellard | if (q->next == -1) { |
295 | 611493d9 | bellard | /* XXX: optimize */
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296 | dbda808a | bellard | IRQ_check(opp, q); |
297 | dbda808a | bellard | } |
298 | dbda808a | bellard | |
299 | dbda808a | bellard | return q->next;
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300 | dbda808a | bellard | } |
301 | dbda808a | bellard | |
302 | dbda808a | bellard | static void IRQ_local_pipe (openpic_t *opp, int n_CPU, int n_IRQ) |
303 | dbda808a | bellard | { |
304 | dbda808a | bellard | IRQ_dst_t *dst; |
305 | dbda808a | bellard | IRQ_src_t *src; |
306 | dbda808a | bellard | int priority;
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307 | dbda808a | bellard | |
308 | dbda808a | bellard | dst = &opp->dst[n_CPU]; |
309 | dbda808a | bellard | src = &opp->src[n_IRQ]; |
310 | dbda808a | bellard | priority = IPVP_PRIORITY(src->ipvp); |
311 | dbda808a | bellard | if (priority <= dst->pctp) {
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312 | dbda808a | bellard | /* Too low priority */
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313 | e9df014c | j_mayer | DPRINTF("%s: IRQ %d has too low priority on CPU %d\n",
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314 | e9df014c | j_mayer | __func__, n_IRQ, n_CPU); |
315 | dbda808a | bellard | return;
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316 | dbda808a | bellard | } |
317 | dbda808a | bellard | if (IRQ_testbit(&dst->raised, n_IRQ)) {
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318 | dbda808a | bellard | /* Interrupt miss */
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319 | e9df014c | j_mayer | DPRINTF("%s: IRQ %d was missed on CPU %d\n",
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320 | e9df014c | j_mayer | __func__, n_IRQ, n_CPU); |
321 | dbda808a | bellard | return;
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322 | dbda808a | bellard | } |
323 | dbda808a | bellard | set_bit(&src->ipvp, IPVP_ACTIVITY); |
324 | dbda808a | bellard | IRQ_setbit(&dst->raised, n_IRQ); |
325 | e9df014c | j_mayer | if (priority < dst->raised.priority) {
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326 | e9df014c | j_mayer | /* An higher priority IRQ is already raised */
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327 | e9df014c | j_mayer | DPRINTF("%s: IRQ %d is hidden by raised IRQ %d on CPU %d\n",
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328 | e9df014c | j_mayer | __func__, n_IRQ, dst->raised.next, n_CPU); |
329 | e9df014c | j_mayer | return;
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330 | e9df014c | j_mayer | } |
331 | e9df014c | j_mayer | IRQ_get_next(opp, &dst->raised); |
332 | e9df014c | j_mayer | if (IRQ_get_next(opp, &dst->servicing) != -1 && |
333 | 24865167 | aliguori | priority <= dst->servicing.priority) { |
334 | e9df014c | j_mayer | DPRINTF("%s: IRQ %d is hidden by servicing IRQ %d on CPU %d\n",
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335 | e9df014c | j_mayer | __func__, n_IRQ, dst->servicing.next, n_CPU); |
336 | e9df014c | j_mayer | /* Already servicing a higher priority IRQ */
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337 | e9df014c | j_mayer | return;
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338 | dbda808a | bellard | } |
339 | e9df014c | j_mayer | DPRINTF("Raise OpenPIC INT output cpu %d irq %d\n", n_CPU, n_IRQ);
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340 | b7169916 | aurel32 | opp->irq_raise(opp, n_CPU, src); |
341 | dbda808a | bellard | } |
342 | dbda808a | bellard | |
343 | 611493d9 | bellard | /* update pic state because registers for n_IRQ have changed value */
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344 | 611493d9 | bellard | static void openpic_update_irq(openpic_t *opp, int n_IRQ) |
345 | dbda808a | bellard | { |
346 | dbda808a | bellard | IRQ_src_t *src; |
347 | dbda808a | bellard | int i;
|
348 | dbda808a | bellard | |
349 | dbda808a | bellard | src = &opp->src[n_IRQ]; |
350 | 611493d9 | bellard | |
351 | 611493d9 | bellard | if (!src->pending) {
|
352 | 611493d9 | bellard | /* no irq pending */
|
353 | e9df014c | j_mayer | DPRINTF("%s: IRQ %d is not pending\n", __func__, n_IRQ);
|
354 | 611493d9 | bellard | return;
|
355 | 611493d9 | bellard | } |
356 | 611493d9 | bellard | if (test_bit(&src->ipvp, IPVP_MASK)) {
|
357 | dbda808a | bellard | /* Interrupt source is disabled */
|
358 | e9df014c | j_mayer | DPRINTF("%s: IRQ %d is disabled\n", __func__, n_IRQ);
|
359 | dbda808a | bellard | return;
|
360 | dbda808a | bellard | } |
361 | dbda808a | bellard | if (IPVP_PRIORITY(src->ipvp) == 0) { |
362 | dbda808a | bellard | /* Priority set to zero */
|
363 | e9df014c | j_mayer | DPRINTF("%s: IRQ %d has 0 priority\n", __func__, n_IRQ);
|
364 | dbda808a | bellard | return;
|
365 | dbda808a | bellard | } |
366 | 611493d9 | bellard | if (test_bit(&src->ipvp, IPVP_ACTIVITY)) {
|
367 | 611493d9 | bellard | /* IRQ already active */
|
368 | e9df014c | j_mayer | DPRINTF("%s: IRQ %d is already active\n", __func__, n_IRQ);
|
369 | 611493d9 | bellard | return;
|
370 | 611493d9 | bellard | } |
371 | dbda808a | bellard | if (src->ide == 0x00000000) { |
372 | dbda808a | bellard | /* No target */
|
373 | e9df014c | j_mayer | DPRINTF("%s: IRQ %d has no target\n", __func__, n_IRQ);
|
374 | dbda808a | bellard | return;
|
375 | dbda808a | bellard | } |
376 | 611493d9 | bellard | |
377 | e9df014c | j_mayer | if (src->ide == (1 << src->last_cpu)) { |
378 | e9df014c | j_mayer | /* Only one CPU is allowed to receive this IRQ */
|
379 | e9df014c | j_mayer | IRQ_local_pipe(opp, src->last_cpu, n_IRQ); |
380 | e9df014c | j_mayer | } else if (!test_bit(&src->ipvp, IPVP_MODE)) { |
381 | 611493d9 | bellard | /* Directed delivery mode */
|
382 | 611493d9 | bellard | for (i = 0; i < opp->nb_cpus; i++) { |
383 | 611493d9 | bellard | if (test_bit(&src->ide, i))
|
384 | 611493d9 | bellard | IRQ_local_pipe(opp, i, n_IRQ); |
385 | 611493d9 | bellard | } |
386 | dbda808a | bellard | } else {
|
387 | 611493d9 | bellard | /* Distributed delivery mode */
|
388 | e9df014c | j_mayer | for (i = src->last_cpu + 1; i != src->last_cpu; i++) { |
389 | e9df014c | j_mayer | if (i == opp->nb_cpus)
|
390 | 611493d9 | bellard | i = 0;
|
391 | 611493d9 | bellard | if (test_bit(&src->ide, i)) {
|
392 | 611493d9 | bellard | IRQ_local_pipe(opp, i, n_IRQ); |
393 | 611493d9 | bellard | src->last_cpu = i; |
394 | 611493d9 | bellard | break;
|
395 | 611493d9 | bellard | } |
396 | 611493d9 | bellard | } |
397 | 611493d9 | bellard | } |
398 | 611493d9 | bellard | } |
399 | 611493d9 | bellard | |
400 | d537cf6c | pbrook | static void openpic_set_irq(void *opaque, int n_IRQ, int level) |
401 | 611493d9 | bellard | { |
402 | 54fa5af5 | bellard | openpic_t *opp = opaque; |
403 | 611493d9 | bellard | IRQ_src_t *src; |
404 | 611493d9 | bellard | |
405 | 611493d9 | bellard | src = &opp->src[n_IRQ]; |
406 | 5fafdf24 | ths | DPRINTF("openpic: set irq %d = %d ipvp=%08x\n",
|
407 | 611493d9 | bellard | n_IRQ, level, src->ipvp); |
408 | 611493d9 | bellard | if (test_bit(&src->ipvp, IPVP_SENSE)) {
|
409 | 611493d9 | bellard | /* level-sensitive irq */
|
410 | 611493d9 | bellard | src->pending = level; |
411 | 611493d9 | bellard | if (!level)
|
412 | 611493d9 | bellard | reset_bit(&src->ipvp, IPVP_ACTIVITY); |
413 | 611493d9 | bellard | } else {
|
414 | 611493d9 | bellard | /* edge-sensitive irq */
|
415 | 611493d9 | bellard | if (level)
|
416 | 611493d9 | bellard | src->pending = 1;
|
417 | dbda808a | bellard | } |
418 | 611493d9 | bellard | openpic_update_irq(opp, n_IRQ); |
419 | dbda808a | bellard | } |
420 | dbda808a | bellard | |
421 | 67b55785 | blueswir1 | static void openpic_reset (void *opaque) |
422 | dbda808a | bellard | { |
423 | 67b55785 | blueswir1 | openpic_t *opp = (openpic_t *)opaque; |
424 | dbda808a | bellard | int i;
|
425 | dbda808a | bellard | |
426 | dbda808a | bellard | opp->glbc = 0x80000000;
|
427 | f8407028 | bellard | /* Initialise controller registers */
|
428 | b7169916 | aurel32 | opp->frep = ((OPENPIC_EXT_IRQ - 1) << 16) | ((MAX_CPU - 1) << 8) | VID; |
429 | dbda808a | bellard | opp->veni = VENI; |
430 | e9df014c | j_mayer | opp->pint = 0x00000000;
|
431 | dbda808a | bellard | opp->spve = 0x000000FF;
|
432 | dbda808a | bellard | opp->tifr = 0x003F7A00;
|
433 | dbda808a | bellard | /* ? */
|
434 | dbda808a | bellard | opp->micr = 0x00000000;
|
435 | dbda808a | bellard | /* Initialise IRQ sources */
|
436 | b7169916 | aurel32 | for (i = 0; i < opp->max_irq; i++) { |
437 | dbda808a | bellard | opp->src[i].ipvp = 0xA0000000;
|
438 | dbda808a | bellard | opp->src[i].ide = 0x00000000;
|
439 | dbda808a | bellard | } |
440 | dbda808a | bellard | /* Initialise IRQ destinations */
|
441 | e9df014c | j_mayer | for (i = 0; i < MAX_CPU; i++) { |
442 | dbda808a | bellard | opp->dst[i].pctp = 0x0000000F;
|
443 | dbda808a | bellard | opp->dst[i].pcsr = 0x00000000;
|
444 | dbda808a | bellard | memset(&opp->dst[i].raised, 0, sizeof(IRQ_queue_t)); |
445 | dbda808a | bellard | memset(&opp->dst[i].servicing, 0, sizeof(IRQ_queue_t)); |
446 | dbda808a | bellard | } |
447 | dbda808a | bellard | /* Initialise timers */
|
448 | dbda808a | bellard | for (i = 0; i < MAX_TMR; i++) { |
449 | dbda808a | bellard | opp->timers[i].ticc = 0x00000000;
|
450 | dbda808a | bellard | opp->timers[i].tibc = 0x80000000;
|
451 | dbda808a | bellard | } |
452 | dbda808a | bellard | /* Initialise doorbells */
|
453 | dbda808a | bellard | #if MAX_DBL > 0 |
454 | dbda808a | bellard | opp->dar = 0x00000000;
|
455 | dbda808a | bellard | for (i = 0; i < MAX_DBL; i++) { |
456 | dbda808a | bellard | opp->doorbells[i].dmr = 0x00000000;
|
457 | dbda808a | bellard | } |
458 | dbda808a | bellard | #endif
|
459 | dbda808a | bellard | /* Initialise mailboxes */
|
460 | dbda808a | bellard | #if MAX_MBX > 0 |
461 | dbda808a | bellard | for (i = 0; i < MAX_MBX; i++) { /* ? */ |
462 | dbda808a | bellard | opp->mailboxes[i].mbr = 0x00000000;
|
463 | dbda808a | bellard | } |
464 | dbda808a | bellard | #endif
|
465 | dbda808a | bellard | /* Go out of RESET state */
|
466 | dbda808a | bellard | opp->glbc = 0x00000000;
|
467 | dbda808a | bellard | } |
468 | dbda808a | bellard | |
469 | dbda808a | bellard | static inline uint32_t read_IRQreg (openpic_t *opp, int n_IRQ, uint32_t reg) |
470 | dbda808a | bellard | { |
471 | dbda808a | bellard | uint32_t retval; |
472 | dbda808a | bellard | |
473 | dbda808a | bellard | switch (reg) {
|
474 | dbda808a | bellard | case IRQ_IPVP:
|
475 | dbda808a | bellard | retval = opp->src[n_IRQ].ipvp; |
476 | dbda808a | bellard | break;
|
477 | dbda808a | bellard | case IRQ_IDE:
|
478 | dbda808a | bellard | retval = opp->src[n_IRQ].ide; |
479 | dbda808a | bellard | break;
|
480 | dbda808a | bellard | } |
481 | dbda808a | bellard | |
482 | dbda808a | bellard | return retval;
|
483 | dbda808a | bellard | } |
484 | dbda808a | bellard | |
485 | dbda808a | bellard | static inline void write_IRQreg (openpic_t *opp, int n_IRQ, |
486 | dbda808a | bellard | uint32_t reg, uint32_t val) |
487 | dbda808a | bellard | { |
488 | dbda808a | bellard | uint32_t tmp; |
489 | dbda808a | bellard | |
490 | dbda808a | bellard | switch (reg) {
|
491 | dbda808a | bellard | case IRQ_IPVP:
|
492 | 611493d9 | bellard | /* NOTE: not fully accurate for special IRQs, but simple and
|
493 | 611493d9 | bellard | sufficient */
|
494 | 611493d9 | bellard | /* ACTIVITY bit is read-only */
|
495 | 5fafdf24 | ths | opp->src[n_IRQ].ipvp = |
496 | 611493d9 | bellard | (opp->src[n_IRQ].ipvp & 0x40000000) |
|
497 | 611493d9 | bellard | (val & 0x800F00FF);
|
498 | 611493d9 | bellard | openpic_update_irq(opp, n_IRQ); |
499 | 5fafdf24 | ths | DPRINTF("Set IPVP %d to 0x%08x -> 0x%08x\n",
|
500 | 611493d9 | bellard | n_IRQ, val, opp->src[n_IRQ].ipvp); |
501 | dbda808a | bellard | break;
|
502 | dbda808a | bellard | case IRQ_IDE:
|
503 | dbda808a | bellard | tmp = val & 0xC0000000;
|
504 | dbda808a | bellard | tmp |= val & ((1 << MAX_CPU) - 1); |
505 | dbda808a | bellard | opp->src[n_IRQ].ide = tmp; |
506 | dbda808a | bellard | DPRINTF("Set IDE %d to 0x%08x\n", n_IRQ, opp->src[n_IRQ].ide);
|
507 | dbda808a | bellard | break;
|
508 | dbda808a | bellard | } |
509 | dbda808a | bellard | } |
510 | dbda808a | bellard | |
511 | dbda808a | bellard | #if 0 // Code provision for Intel model
|
512 | dbda808a | bellard | #if MAX_DBL > 0
|
513 | dbda808a | bellard | static uint32_t read_doorbell_register (openpic_t *opp,
|
514 | dbda808a | bellard | int n_dbl, uint32_t offset)
|
515 | dbda808a | bellard | {
|
516 | dbda808a | bellard | uint32_t retval;
|
517 | dbda808a | bellard | |
518 | dbda808a | bellard | switch (offset) {
|
519 | dbda808a | bellard | case DBL_IPVP_OFFSET:
|
520 | dbda808a | bellard | retval = read_IRQreg(opp, IRQ_DBL0 + n_dbl, IRQ_IPVP);
|
521 | dbda808a | bellard | break;
|
522 | dbda808a | bellard | case DBL_IDE_OFFSET:
|
523 | dbda808a | bellard | retval = read_IRQreg(opp, IRQ_DBL0 + n_dbl, IRQ_IDE);
|
524 | dbda808a | bellard | break;
|
525 | dbda808a | bellard | case DBL_DMR_OFFSET:
|
526 | dbda808a | bellard | retval = opp->doorbells[n_dbl].dmr;
|
527 | dbda808a | bellard | break;
|
528 | dbda808a | bellard | }
|
529 | dbda808a | bellard | |
530 | dbda808a | bellard | return retval;
|
531 | dbda808a | bellard | }
|
532 | 3b46e624 | ths | |
533 | dbda808a | bellard | static void write_doorbell_register (penpic_t *opp, int n_dbl,
|
534 | dbda808a | bellard | uint32_t offset, uint32_t value)
|
535 | dbda808a | bellard | {
|
536 | dbda808a | bellard | switch (offset) {
|
537 | dbda808a | bellard | case DBL_IVPR_OFFSET:
|
538 | dbda808a | bellard | write_IRQreg(opp, IRQ_DBL0 + n_dbl, IRQ_IPVP, value);
|
539 | dbda808a | bellard | break;
|
540 | dbda808a | bellard | case DBL_IDE_OFFSET:
|
541 | dbda808a | bellard | write_IRQreg(opp, IRQ_DBL0 + n_dbl, IRQ_IDE, value);
|
542 | dbda808a | bellard | break;
|
543 | dbda808a | bellard | case DBL_DMR_OFFSET:
|
544 | dbda808a | bellard | opp->doorbells[n_dbl].dmr = value;
|
545 | dbda808a | bellard | break;
|
546 | dbda808a | bellard | }
|
547 | dbda808a | bellard | }
|
548 | dbda808a | bellard | #endif
|
549 | dbda808a | bellard | |
550 | dbda808a | bellard | #if MAX_MBX > 0 |
551 | dbda808a | bellard | static uint32_t read_mailbox_register (openpic_t *opp,
|
552 | dbda808a | bellard | int n_mbx, uint32_t offset)
|
553 | dbda808a | bellard | { |
554 | dbda808a | bellard | uint32_t retval; |
555 | dbda808a | bellard | |
556 | dbda808a | bellard | switch (offset) {
|
557 | dbda808a | bellard | case MBX_MBR_OFFSET:
|
558 | dbda808a | bellard | retval = opp->mailboxes[n_mbx].mbr; |
559 | dbda808a | bellard | break;
|
560 | dbda808a | bellard | case MBX_IVPR_OFFSET:
|
561 | dbda808a | bellard | retval = read_IRQreg(opp, IRQ_MBX0 + n_mbx, IRQ_IPVP); |
562 | dbda808a | bellard | break;
|
563 | dbda808a | bellard | case MBX_DMR_OFFSET:
|
564 | dbda808a | bellard | retval = read_IRQreg(opp, IRQ_MBX0 + n_mbx, IRQ_IDE); |
565 | dbda808a | bellard | break;
|
566 | dbda808a | bellard | } |
567 | dbda808a | bellard | |
568 | dbda808a | bellard | return retval;
|
569 | dbda808a | bellard | } |
570 | dbda808a | bellard | |
571 | dbda808a | bellard | static void write_mailbox_register (openpic_t *opp, int n_mbx, |
572 | dbda808a | bellard | uint32_t address, uint32_t value) |
573 | dbda808a | bellard | { |
574 | dbda808a | bellard | switch (offset) {
|
575 | dbda808a | bellard | case MBX_MBR_OFFSET:
|
576 | dbda808a | bellard | opp->mailboxes[n_mbx].mbr = value; |
577 | dbda808a | bellard | break;
|
578 | dbda808a | bellard | case MBX_IVPR_OFFSET:
|
579 | dbda808a | bellard | write_IRQreg(opp, IRQ_MBX0 + n_mbx, IRQ_IPVP, value); |
580 | dbda808a | bellard | break;
|
581 | dbda808a | bellard | case MBX_DMR_OFFSET:
|
582 | dbda808a | bellard | write_IRQreg(opp, IRQ_MBX0 + n_mbx, IRQ_IDE, value); |
583 | dbda808a | bellard | break;
|
584 | dbda808a | bellard | } |
585 | dbda808a | bellard | } |
586 | dbda808a | bellard | #endif
|
587 | dbda808a | bellard | #endif /* 0 : Code provision for Intel model */ |
588 | dbda808a | bellard | |
589 | b7169916 | aurel32 | static void openpic_gbl_write (void *opaque, target_phys_addr_t addr, uint32_t val) |
590 | dbda808a | bellard | { |
591 | dbda808a | bellard | openpic_t *opp = opaque; |
592 | e9df014c | j_mayer | IRQ_dst_t *dst; |
593 | e9df014c | j_mayer | int idx;
|
594 | dbda808a | bellard | |
595 | 0bf9e31a | Blue Swirl | DPRINTF("%s: addr " TARGET_FMT_plx " <= %08x\n", __func__, addr, val); |
596 | dbda808a | bellard | if (addr & 0xF) |
597 | dbda808a | bellard | return;
|
598 | b7169916 | aurel32 | #if defined TARGET_WORDS_BIGENDIAN
|
599 | b7169916 | aurel32 | val = openpic_swap32(opp, val); |
600 | dbda808a | bellard | #endif
|
601 | dbda808a | bellard | addr &= 0xFF;
|
602 | dbda808a | bellard | switch (addr) {
|
603 | dbda808a | bellard | case 0x00: /* FREP */ |
604 | dbda808a | bellard | break;
|
605 | dbda808a | bellard | case 0x20: /* GLBC */ |
606 | b7169916 | aurel32 | if (val & 0x80000000 && opp->reset) |
607 | b7169916 | aurel32 | opp->reset(opp); |
608 | dbda808a | bellard | opp->glbc = val & ~0x80000000;
|
609 | dbda808a | bellard | break;
|
610 | dbda808a | bellard | case 0x80: /* VENI */ |
611 | dbda808a | bellard | break;
|
612 | dbda808a | bellard | case 0x90: /* PINT */ |
613 | e9df014c | j_mayer | for (idx = 0; idx < opp->nb_cpus; idx++) { |
614 | e9df014c | j_mayer | if ((val & (1 << idx)) && !(opp->pint & (1 << idx))) { |
615 | e9df014c | j_mayer | DPRINTF("Raise OpenPIC RESET output for CPU %d\n", idx);
|
616 | e9df014c | j_mayer | dst = &opp->dst[idx]; |
617 | e9df014c | j_mayer | qemu_irq_raise(dst->irqs[OPENPIC_OUTPUT_RESET]); |
618 | e9df014c | j_mayer | } else if (!(val & (1 << idx)) && (opp->pint & (1 << idx))) { |
619 | e9df014c | j_mayer | DPRINTF("Lower OpenPIC RESET output for CPU %d\n", idx);
|
620 | e9df014c | j_mayer | dst = &opp->dst[idx]; |
621 | e9df014c | j_mayer | qemu_irq_lower(dst->irqs[OPENPIC_OUTPUT_RESET]); |
622 | e9df014c | j_mayer | } |
623 | dbda808a | bellard | } |
624 | e9df014c | j_mayer | opp->pint = val; |
625 | dbda808a | bellard | break;
|
626 | dbda808a | bellard | #if MAX_IPI > 0 |
627 | dbda808a | bellard | case 0xA0: /* IPI_IPVP */ |
628 | dbda808a | bellard | case 0xB0: |
629 | dbda808a | bellard | case 0xC0: |
630 | dbda808a | bellard | case 0xD0: |
631 | dbda808a | bellard | { |
632 | dbda808a | bellard | int idx;
|
633 | dbda808a | bellard | idx = (addr - 0xA0) >> 4; |
634 | b7169916 | aurel32 | write_IRQreg(opp, opp->irq_ipi0 + idx, IRQ_IPVP, val); |
635 | dbda808a | bellard | } |
636 | dbda808a | bellard | break;
|
637 | dbda808a | bellard | #endif
|
638 | dbda808a | bellard | case 0xE0: /* SPVE */ |
639 | dbda808a | bellard | opp->spve = val & 0x000000FF;
|
640 | dbda808a | bellard | break;
|
641 | dbda808a | bellard | case 0xF0: /* TIFR */ |
642 | dbda808a | bellard | opp->tifr = val; |
643 | dbda808a | bellard | break;
|
644 | dbda808a | bellard | default:
|
645 | dbda808a | bellard | break;
|
646 | dbda808a | bellard | } |
647 | dbda808a | bellard | } |
648 | dbda808a | bellard | |
649 | b7169916 | aurel32 | static uint32_t openpic_gbl_read (void *opaque, target_phys_addr_t addr) |
650 | dbda808a | bellard | { |
651 | dbda808a | bellard | openpic_t *opp = opaque; |
652 | dbda808a | bellard | uint32_t retval; |
653 | dbda808a | bellard | |
654 | 0bf9e31a | Blue Swirl | DPRINTF("%s: addr " TARGET_FMT_plx "\n", __func__, addr); |
655 | dbda808a | bellard | retval = 0xFFFFFFFF;
|
656 | dbda808a | bellard | if (addr & 0xF) |
657 | dbda808a | bellard | return retval;
|
658 | dbda808a | bellard | addr &= 0xFF;
|
659 | dbda808a | bellard | switch (addr) {
|
660 | dbda808a | bellard | case 0x00: /* FREP */ |
661 | dbda808a | bellard | retval = opp->frep; |
662 | dbda808a | bellard | break;
|
663 | dbda808a | bellard | case 0x20: /* GLBC */ |
664 | dbda808a | bellard | retval = opp->glbc; |
665 | dbda808a | bellard | break;
|
666 | dbda808a | bellard | case 0x80: /* VENI */ |
667 | dbda808a | bellard | retval = opp->veni; |
668 | dbda808a | bellard | break;
|
669 | dbda808a | bellard | case 0x90: /* PINT */ |
670 | dbda808a | bellard | retval = 0x00000000;
|
671 | dbda808a | bellard | break;
|
672 | dbda808a | bellard | #if MAX_IPI > 0 |
673 | dbda808a | bellard | case 0xA0: /* IPI_IPVP */ |
674 | dbda808a | bellard | case 0xB0: |
675 | dbda808a | bellard | case 0xC0: |
676 | dbda808a | bellard | case 0xD0: |
677 | dbda808a | bellard | { |
678 | dbda808a | bellard | int idx;
|
679 | dbda808a | bellard | idx = (addr - 0xA0) >> 4; |
680 | b7169916 | aurel32 | retval = read_IRQreg(opp, opp->irq_ipi0 + idx, IRQ_IPVP); |
681 | dbda808a | bellard | } |
682 | dbda808a | bellard | break;
|
683 | dbda808a | bellard | #endif
|
684 | dbda808a | bellard | case 0xE0: /* SPVE */ |
685 | dbda808a | bellard | retval = opp->spve; |
686 | dbda808a | bellard | break;
|
687 | dbda808a | bellard | case 0xF0: /* TIFR */ |
688 | dbda808a | bellard | retval = opp->tifr; |
689 | dbda808a | bellard | break;
|
690 | dbda808a | bellard | default:
|
691 | dbda808a | bellard | break;
|
692 | dbda808a | bellard | } |
693 | dbda808a | bellard | DPRINTF("%s: => %08x\n", __func__, retval);
|
694 | b7169916 | aurel32 | #if defined TARGET_WORDS_BIGENDIAN
|
695 | b7169916 | aurel32 | retval = openpic_swap32(opp, retval); |
696 | dbda808a | bellard | #endif
|
697 | dbda808a | bellard | |
698 | dbda808a | bellard | return retval;
|
699 | dbda808a | bellard | } |
700 | dbda808a | bellard | |
701 | dbda808a | bellard | static void openpic_timer_write (void *opaque, uint32_t addr, uint32_t val) |
702 | dbda808a | bellard | { |
703 | dbda808a | bellard | openpic_t *opp = opaque; |
704 | dbda808a | bellard | int idx;
|
705 | dbda808a | bellard | |
706 | dbda808a | bellard | DPRINTF("%s: addr %08x <= %08x\n", __func__, addr, val);
|
707 | dbda808a | bellard | if (addr & 0xF) |
708 | dbda808a | bellard | return;
|
709 | b7169916 | aurel32 | #if defined TARGET_WORDS_BIGENDIAN
|
710 | b7169916 | aurel32 | val = openpic_swap32(opp, val); |
711 | dbda808a | bellard | #endif
|
712 | dbda808a | bellard | addr -= 0x1100;
|
713 | dbda808a | bellard | addr &= 0xFFFF;
|
714 | dbda808a | bellard | idx = (addr & 0xFFF0) >> 6; |
715 | dbda808a | bellard | addr = addr & 0x30;
|
716 | dbda808a | bellard | switch (addr) {
|
717 | dbda808a | bellard | case 0x00: /* TICC */ |
718 | dbda808a | bellard | break;
|
719 | dbda808a | bellard | case 0x10: /* TIBC */ |
720 | dbda808a | bellard | if ((opp->timers[idx].ticc & 0x80000000) != 0 && |
721 | 8adbc566 | bellard | (val & 0x80000000) == 0 && |
722 | dbda808a | bellard | (opp->timers[idx].tibc & 0x80000000) != 0) |
723 | dbda808a | bellard | opp->timers[idx].ticc &= ~0x80000000;
|
724 | dbda808a | bellard | opp->timers[idx].tibc = val; |
725 | dbda808a | bellard | break;
|
726 | dbda808a | bellard | case 0x20: /* TIVP */ |
727 | b7169916 | aurel32 | write_IRQreg(opp, opp->irq_tim0 + idx, IRQ_IPVP, val); |
728 | dbda808a | bellard | break;
|
729 | dbda808a | bellard | case 0x30: /* TIDE */ |
730 | b7169916 | aurel32 | write_IRQreg(opp, opp->irq_tim0 + idx, IRQ_IDE, val); |
731 | dbda808a | bellard | break;
|
732 | dbda808a | bellard | } |
733 | dbda808a | bellard | } |
734 | dbda808a | bellard | |
735 | dbda808a | bellard | static uint32_t openpic_timer_read (void *opaque, uint32_t addr) |
736 | dbda808a | bellard | { |
737 | dbda808a | bellard | openpic_t *opp = opaque; |
738 | dbda808a | bellard | uint32_t retval; |
739 | dbda808a | bellard | int idx;
|
740 | dbda808a | bellard | |
741 | dbda808a | bellard | DPRINTF("%s: addr %08x\n", __func__, addr);
|
742 | dbda808a | bellard | retval = 0xFFFFFFFF;
|
743 | dbda808a | bellard | if (addr & 0xF) |
744 | dbda808a | bellard | return retval;
|
745 | dbda808a | bellard | addr -= 0x1100;
|
746 | dbda808a | bellard | addr &= 0xFFFF;
|
747 | dbda808a | bellard | idx = (addr & 0xFFF0) >> 6; |
748 | dbda808a | bellard | addr = addr & 0x30;
|
749 | dbda808a | bellard | switch (addr) {
|
750 | dbda808a | bellard | case 0x00: /* TICC */ |
751 | dbda808a | bellard | retval = opp->timers[idx].ticc; |
752 | dbda808a | bellard | break;
|
753 | dbda808a | bellard | case 0x10: /* TIBC */ |
754 | dbda808a | bellard | retval = opp->timers[idx].tibc; |
755 | dbda808a | bellard | break;
|
756 | dbda808a | bellard | case 0x20: /* TIPV */ |
757 | b7169916 | aurel32 | retval = read_IRQreg(opp, opp->irq_tim0 + idx, IRQ_IPVP); |
758 | dbda808a | bellard | break;
|
759 | dbda808a | bellard | case 0x30: /* TIDE */ |
760 | b7169916 | aurel32 | retval = read_IRQreg(opp, opp->irq_tim0 + idx, IRQ_IDE); |
761 | dbda808a | bellard | break;
|
762 | dbda808a | bellard | } |
763 | dbda808a | bellard | DPRINTF("%s: => %08x\n", __func__, retval);
|
764 | b7169916 | aurel32 | #if defined TARGET_WORDS_BIGENDIAN
|
765 | b7169916 | aurel32 | retval = openpic_swap32(opp, retval); |
766 | dbda808a | bellard | #endif
|
767 | dbda808a | bellard | |
768 | dbda808a | bellard | return retval;
|
769 | dbda808a | bellard | } |
770 | dbda808a | bellard | |
771 | dbda808a | bellard | static void openpic_src_write (void *opaque, uint32_t addr, uint32_t val) |
772 | dbda808a | bellard | { |
773 | dbda808a | bellard | openpic_t *opp = opaque; |
774 | dbda808a | bellard | int idx;
|
775 | dbda808a | bellard | |
776 | dbda808a | bellard | DPRINTF("%s: addr %08x <= %08x\n", __func__, addr, val);
|
777 | dbda808a | bellard | if (addr & 0xF) |
778 | dbda808a | bellard | return;
|
779 | b7169916 | aurel32 | #if defined TARGET_WORDS_BIGENDIAN
|
780 | b7169916 | aurel32 | val = openpic_swap32(opp, val); |
781 | dbda808a | bellard | #endif
|
782 | dbda808a | bellard | addr = addr & 0xFFF0;
|
783 | dbda808a | bellard | idx = addr >> 5;
|
784 | dbda808a | bellard | if (addr & 0x10) { |
785 | dbda808a | bellard | /* EXDE / IFEDE / IEEDE */
|
786 | dbda808a | bellard | write_IRQreg(opp, idx, IRQ_IDE, val); |
787 | dbda808a | bellard | } else {
|
788 | dbda808a | bellard | /* EXVP / IFEVP / IEEVP */
|
789 | dbda808a | bellard | write_IRQreg(opp, idx, IRQ_IPVP, val); |
790 | dbda808a | bellard | } |
791 | dbda808a | bellard | } |
792 | dbda808a | bellard | |
793 | dbda808a | bellard | static uint32_t openpic_src_read (void *opaque, uint32_t addr) |
794 | dbda808a | bellard | { |
795 | dbda808a | bellard | openpic_t *opp = opaque; |
796 | dbda808a | bellard | uint32_t retval; |
797 | dbda808a | bellard | int idx;
|
798 | dbda808a | bellard | |
799 | dbda808a | bellard | DPRINTF("%s: addr %08x\n", __func__, addr);
|
800 | dbda808a | bellard | retval = 0xFFFFFFFF;
|
801 | dbda808a | bellard | if (addr & 0xF) |
802 | dbda808a | bellard | return retval;
|
803 | dbda808a | bellard | addr = addr & 0xFFF0;
|
804 | dbda808a | bellard | idx = addr >> 5;
|
805 | dbda808a | bellard | if (addr & 0x10) { |
806 | dbda808a | bellard | /* EXDE / IFEDE / IEEDE */
|
807 | dbda808a | bellard | retval = read_IRQreg(opp, idx, IRQ_IDE); |
808 | dbda808a | bellard | } else {
|
809 | dbda808a | bellard | /* EXVP / IFEVP / IEEVP */
|
810 | dbda808a | bellard | retval = read_IRQreg(opp, idx, IRQ_IPVP); |
811 | dbda808a | bellard | } |
812 | dbda808a | bellard | DPRINTF("%s: => %08x\n", __func__, retval);
|
813 | b7169916 | aurel32 | #if defined TARGET_WORDS_BIGENDIAN
|
814 | b7169916 | aurel32 | retval = openpic_swap32(opp, retval); |
815 | dbda808a | bellard | #endif
|
816 | dbda808a | bellard | |
817 | dbda808a | bellard | return retval;
|
818 | dbda808a | bellard | } |
819 | dbda808a | bellard | |
820 | b7169916 | aurel32 | static void openpic_cpu_write (void *opaque, target_phys_addr_t addr, uint32_t val) |
821 | dbda808a | bellard | { |
822 | dbda808a | bellard | openpic_t *opp = opaque; |
823 | dbda808a | bellard | IRQ_src_t *src; |
824 | dbda808a | bellard | IRQ_dst_t *dst; |
825 | e9df014c | j_mayer | int idx, s_IRQ, n_IRQ;
|
826 | dbda808a | bellard | |
827 | 0bf9e31a | Blue Swirl | DPRINTF("%s: addr " TARGET_FMT_plx " <= %08x\n", __func__, addr, val); |
828 | dbda808a | bellard | if (addr & 0xF) |
829 | dbda808a | bellard | return;
|
830 | b7169916 | aurel32 | #if defined TARGET_WORDS_BIGENDIAN
|
831 | b7169916 | aurel32 | val = openpic_swap32(opp, val); |
832 | dbda808a | bellard | #endif
|
833 | dbda808a | bellard | addr &= 0x1FFF0;
|
834 | dbda808a | bellard | idx = addr / 0x1000;
|
835 | dbda808a | bellard | dst = &opp->dst[idx]; |
836 | dbda808a | bellard | addr &= 0xFF0;
|
837 | dbda808a | bellard | switch (addr) {
|
838 | dbda808a | bellard | #if MAX_IPI > 0 |
839 | dbda808a | bellard | case 0x40: /* PIPD */ |
840 | dbda808a | bellard | case 0x50: |
841 | dbda808a | bellard | case 0x60: |
842 | dbda808a | bellard | case 0x70: |
843 | dbda808a | bellard | idx = (addr - 0x40) >> 4; |
844 | b7169916 | aurel32 | write_IRQreg(opp, opp->irq_ipi0 + idx, IRQ_IDE, val); |
845 | b7169916 | aurel32 | openpic_set_irq(opp, opp->irq_ipi0 + idx, 1);
|
846 | b7169916 | aurel32 | openpic_set_irq(opp, opp->irq_ipi0 + idx, 0);
|
847 | dbda808a | bellard | break;
|
848 | dbda808a | bellard | #endif
|
849 | dbda808a | bellard | case 0x80: /* PCTP */ |
850 | dbda808a | bellard | dst->pctp = val & 0x0000000F;
|
851 | dbda808a | bellard | break;
|
852 | dbda808a | bellard | case 0x90: /* WHOAMI */ |
853 | dbda808a | bellard | /* Read-only register */
|
854 | dbda808a | bellard | break;
|
855 | dbda808a | bellard | case 0xA0: /* PIAC */ |
856 | dbda808a | bellard | /* Read-only register */
|
857 | dbda808a | bellard | break;
|
858 | dbda808a | bellard | case 0xB0: /* PEOI */ |
859 | dbda808a | bellard | DPRINTF("PEOI\n");
|
860 | e9df014c | j_mayer | s_IRQ = IRQ_get_next(opp, &dst->servicing); |
861 | e9df014c | j_mayer | IRQ_resetbit(&dst->servicing, s_IRQ); |
862 | dbda808a | bellard | dst->servicing.next = -1;
|
863 | dbda808a | bellard | /* Set up next servicing IRQ */
|
864 | e9df014c | j_mayer | s_IRQ = IRQ_get_next(opp, &dst->servicing); |
865 | e9df014c | j_mayer | /* Check queued interrupts. */
|
866 | e9df014c | j_mayer | n_IRQ = IRQ_get_next(opp, &dst->raised); |
867 | e9df014c | j_mayer | src = &opp->src[n_IRQ]; |
868 | e9df014c | j_mayer | if (n_IRQ != -1 && |
869 | e9df014c | j_mayer | (s_IRQ == -1 ||
|
870 | e9df014c | j_mayer | IPVP_PRIORITY(src->ipvp) > dst->servicing.priority)) { |
871 | e9df014c | j_mayer | DPRINTF("Raise OpenPIC INT output cpu %d irq %d\n",
|
872 | e9df014c | j_mayer | idx, n_IRQ); |
873 | b7169916 | aurel32 | opp->irq_raise(opp, idx, src); |
874 | e9df014c | j_mayer | } |
875 | dbda808a | bellard | break;
|
876 | dbda808a | bellard | default:
|
877 | dbda808a | bellard | break;
|
878 | dbda808a | bellard | } |
879 | dbda808a | bellard | } |
880 | dbda808a | bellard | |
881 | b7169916 | aurel32 | static uint32_t openpic_cpu_read (void *opaque, target_phys_addr_t addr) |
882 | dbda808a | bellard | { |
883 | dbda808a | bellard | openpic_t *opp = opaque; |
884 | dbda808a | bellard | IRQ_src_t *src; |
885 | dbda808a | bellard | IRQ_dst_t *dst; |
886 | dbda808a | bellard | uint32_t retval; |
887 | dbda808a | bellard | int idx, n_IRQ;
|
888 | 3b46e624 | ths | |
889 | 0bf9e31a | Blue Swirl | DPRINTF("%s: addr " TARGET_FMT_plx "\n", __func__, addr); |
890 | dbda808a | bellard | retval = 0xFFFFFFFF;
|
891 | dbda808a | bellard | if (addr & 0xF) |
892 | dbda808a | bellard | return retval;
|
893 | dbda808a | bellard | addr &= 0x1FFF0;
|
894 | dbda808a | bellard | idx = addr / 0x1000;
|
895 | dbda808a | bellard | dst = &opp->dst[idx]; |
896 | dbda808a | bellard | addr &= 0xFF0;
|
897 | dbda808a | bellard | switch (addr) {
|
898 | dbda808a | bellard | case 0x80: /* PCTP */ |
899 | dbda808a | bellard | retval = dst->pctp; |
900 | dbda808a | bellard | break;
|
901 | dbda808a | bellard | case 0x90: /* WHOAMI */ |
902 | dbda808a | bellard | retval = idx; |
903 | dbda808a | bellard | break;
|
904 | dbda808a | bellard | case 0xA0: /* PIAC */ |
905 | e9df014c | j_mayer | DPRINTF("Lower OpenPIC INT output\n");
|
906 | e9df014c | j_mayer | qemu_irq_lower(dst->irqs[OPENPIC_OUTPUT_INT]); |
907 | dbda808a | bellard | n_IRQ = IRQ_get_next(opp, &dst->raised); |
908 | dbda808a | bellard | DPRINTF("PIAC: irq=%d\n", n_IRQ);
|
909 | dbda808a | bellard | if (n_IRQ == -1) { |
910 | dbda808a | bellard | /* No more interrupt pending */
|
911 | e9df014c | j_mayer | retval = IPVP_VECTOR(opp->spve); |
912 | dbda808a | bellard | } else {
|
913 | dbda808a | bellard | src = &opp->src[n_IRQ]; |
914 | dbda808a | bellard | if (!test_bit(&src->ipvp, IPVP_ACTIVITY) ||
|
915 | dbda808a | bellard | !(IPVP_PRIORITY(src->ipvp) > dst->pctp)) { |
916 | dbda808a | bellard | /* - Spurious level-sensitive IRQ
|
917 | dbda808a | bellard | * - Priorities has been changed
|
918 | dbda808a | bellard | * and the pending IRQ isn't allowed anymore
|
919 | dbda808a | bellard | */
|
920 | dbda808a | bellard | reset_bit(&src->ipvp, IPVP_ACTIVITY); |
921 | dbda808a | bellard | retval = IPVP_VECTOR(opp->spve); |
922 | dbda808a | bellard | } else {
|
923 | dbda808a | bellard | /* IRQ enter servicing state */
|
924 | dbda808a | bellard | IRQ_setbit(&dst->servicing, n_IRQ); |
925 | dbda808a | bellard | retval = IPVP_VECTOR(src->ipvp); |
926 | dbda808a | bellard | } |
927 | dbda808a | bellard | IRQ_resetbit(&dst->raised, n_IRQ); |
928 | dbda808a | bellard | dst->raised.next = -1;
|
929 | 611493d9 | bellard | if (!test_bit(&src->ipvp, IPVP_SENSE)) {
|
930 | 611493d9 | bellard | /* edge-sensitive IRQ */
|
931 | dbda808a | bellard | reset_bit(&src->ipvp, IPVP_ACTIVITY); |
932 | 611493d9 | bellard | src->pending = 0;
|
933 | 611493d9 | bellard | } |
934 | dbda808a | bellard | } |
935 | dbda808a | bellard | break;
|
936 | dbda808a | bellard | case 0xB0: /* PEOI */ |
937 | dbda808a | bellard | retval = 0;
|
938 | dbda808a | bellard | break;
|
939 | dbda808a | bellard | #if MAX_IPI > 0 |
940 | dbda808a | bellard | case 0x40: /* IDE */ |
941 | dbda808a | bellard | case 0x50: |
942 | dbda808a | bellard | idx = (addr - 0x40) >> 4; |
943 | b7169916 | aurel32 | retval = read_IRQreg(opp, opp->irq_ipi0 + idx, IRQ_IDE); |
944 | dbda808a | bellard | break;
|
945 | dbda808a | bellard | #endif
|
946 | dbda808a | bellard | default:
|
947 | dbda808a | bellard | break;
|
948 | dbda808a | bellard | } |
949 | dbda808a | bellard | DPRINTF("%s: => %08x\n", __func__, retval);
|
950 | b7169916 | aurel32 | #if defined TARGET_WORDS_BIGENDIAN
|
951 | b7169916 | aurel32 | retval = openpic_swap32(opp, retval); |
952 | dbda808a | bellard | #endif
|
953 | dbda808a | bellard | |
954 | dbda808a | bellard | return retval;
|
955 | dbda808a | bellard | } |
956 | dbda808a | bellard | |
957 | dbda808a | bellard | static void openpic_buggy_write (void *opaque, |
958 | dbda808a | bellard | target_phys_addr_t addr, uint32_t val) |
959 | dbda808a | bellard | { |
960 | dbda808a | bellard | printf("Invalid OPENPIC write access !\n");
|
961 | dbda808a | bellard | } |
962 | dbda808a | bellard | |
963 | dbda808a | bellard | static uint32_t openpic_buggy_read (void *opaque, target_phys_addr_t addr) |
964 | dbda808a | bellard | { |
965 | dbda808a | bellard | printf("Invalid OPENPIC read access !\n");
|
966 | dbda808a | bellard | |
967 | dbda808a | bellard | return -1; |
968 | dbda808a | bellard | } |
969 | dbda808a | bellard | |
970 | dbda808a | bellard | static void openpic_writel (void *opaque, |
971 | dbda808a | bellard | target_phys_addr_t addr, uint32_t val) |
972 | dbda808a | bellard | { |
973 | dbda808a | bellard | openpic_t *opp = opaque; |
974 | dbda808a | bellard | |
975 | dbda808a | bellard | addr &= 0x3FFFF;
|
976 | 611493d9 | bellard | DPRINTF("%s: offset %08x val: %08x\n", __func__, (int)addr, val); |
977 | dbda808a | bellard | if (addr < 0x1100) { |
978 | dbda808a | bellard | /* Global registers */
|
979 | dbda808a | bellard | openpic_gbl_write(opp, addr, val); |
980 | dbda808a | bellard | } else if (addr < 0x10000) { |
981 | dbda808a | bellard | /* Timers registers */
|
982 | dbda808a | bellard | openpic_timer_write(opp, addr, val); |
983 | dbda808a | bellard | } else if (addr < 0x20000) { |
984 | dbda808a | bellard | /* Source registers */
|
985 | dbda808a | bellard | openpic_src_write(opp, addr, val); |
986 | dbda808a | bellard | } else {
|
987 | dbda808a | bellard | /* CPU registers */
|
988 | dbda808a | bellard | openpic_cpu_write(opp, addr, val); |
989 | dbda808a | bellard | } |
990 | dbda808a | bellard | } |
991 | dbda808a | bellard | |
992 | dbda808a | bellard | static uint32_t openpic_readl (void *opaque,target_phys_addr_t addr) |
993 | dbda808a | bellard | { |
994 | dbda808a | bellard | openpic_t *opp = opaque; |
995 | dbda808a | bellard | uint32_t retval; |
996 | dbda808a | bellard | |
997 | dbda808a | bellard | addr &= 0x3FFFF;
|
998 | 611493d9 | bellard | DPRINTF("%s: offset %08x\n", __func__, (int)addr); |
999 | dbda808a | bellard | if (addr < 0x1100) { |
1000 | dbda808a | bellard | /* Global registers */
|
1001 | dbda808a | bellard | retval = openpic_gbl_read(opp, addr); |
1002 | dbda808a | bellard | } else if (addr < 0x10000) { |
1003 | dbda808a | bellard | /* Timers registers */
|
1004 | dbda808a | bellard | retval = openpic_timer_read(opp, addr); |
1005 | dbda808a | bellard | } else if (addr < 0x20000) { |
1006 | dbda808a | bellard | /* Source registers */
|
1007 | dbda808a | bellard | retval = openpic_src_read(opp, addr); |
1008 | dbda808a | bellard | } else {
|
1009 | dbda808a | bellard | /* CPU registers */
|
1010 | dbda808a | bellard | retval = openpic_cpu_read(opp, addr); |
1011 | dbda808a | bellard | } |
1012 | dbda808a | bellard | |
1013 | dbda808a | bellard | return retval;
|
1014 | dbda808a | bellard | } |
1015 | dbda808a | bellard | |
1016 | d60efc6b | Blue Swirl | static CPUWriteMemoryFunc * const openpic_write[] = { |
1017 | dbda808a | bellard | &openpic_buggy_write, |
1018 | dbda808a | bellard | &openpic_buggy_write, |
1019 | dbda808a | bellard | &openpic_writel, |
1020 | dbda808a | bellard | }; |
1021 | dbda808a | bellard | |
1022 | d60efc6b | Blue Swirl | static CPUReadMemoryFunc * const openpic_read[] = { |
1023 | dbda808a | bellard | &openpic_buggy_read, |
1024 | dbda808a | bellard | &openpic_buggy_read, |
1025 | dbda808a | bellard | &openpic_readl, |
1026 | dbda808a | bellard | }; |
1027 | dbda808a | bellard | |
1028 | 5fafdf24 | ths | static void openpic_map(PCIDevice *pci_dev, int region_num, |
1029 | dbda808a | bellard | uint32_t addr, uint32_t size, int type)
|
1030 | dbda808a | bellard | { |
1031 | dbda808a | bellard | openpic_t *opp; |
1032 | dbda808a | bellard | |
1033 | dbda808a | bellard | DPRINTF("Map OpenPIC\n");
|
1034 | dbda808a | bellard | opp = (openpic_t *)pci_dev; |
1035 | dbda808a | bellard | /* Global registers */
|
1036 | dbda808a | bellard | DPRINTF("Register OPENPIC gbl %08x => %08x\n",
|
1037 | dbda808a | bellard | addr + 0x1000, addr + 0x1000 + 0x100); |
1038 | dbda808a | bellard | /* Timer registers */
|
1039 | dbda808a | bellard | DPRINTF("Register OPENPIC timer %08x => %08x\n",
|
1040 | dbda808a | bellard | addr + 0x1100, addr + 0x1100 + 0x40 * MAX_TMR); |
1041 | dbda808a | bellard | /* Interrupt source registers */
|
1042 | dbda808a | bellard | DPRINTF("Register OPENPIC src %08x => %08x\n",
|
1043 | b7169916 | aurel32 | addr + 0x10000, addr + 0x10000 + 0x20 * (OPENPIC_EXT_IRQ + 2)); |
1044 | dbda808a | bellard | /* Per CPU registers */
|
1045 | dbda808a | bellard | DPRINTF("Register OPENPIC dst %08x => %08x\n",
|
1046 | dbda808a | bellard | addr + 0x20000, addr + 0x20000 + 0x1000 * MAX_CPU); |
1047 | 91d848eb | bellard | cpu_register_physical_memory(addr, 0x40000, opp->mem_index);
|
1048 | dbda808a | bellard | #if 0 // Don't implement ISU for now
|
1049 | 1eed09cb | Avi Kivity | opp_io_memory = cpu_register_io_memory(openpic_src_read,
|
1050 | dbda808a | bellard | openpic_src_write);
|
1051 | dbda808a | bellard | cpu_register_physical_memory(isu_base, 0x20 * (EXT_IRQ + 2),
|
1052 | dbda808a | bellard | opp_io_memory);
|
1053 | dbda808a | bellard | #endif
|
1054 | dbda808a | bellard | } |
1055 | dbda808a | bellard | |
1056 | 67b55785 | blueswir1 | static void openpic_save_IRQ_queue(QEMUFile* f, IRQ_queue_t *q) |
1057 | 67b55785 | blueswir1 | { |
1058 | 67b55785 | blueswir1 | unsigned int i; |
1059 | 67b55785 | blueswir1 | |
1060 | 67b55785 | blueswir1 | for (i = 0; i < BF_WIDTH(MAX_IRQ); i++) |
1061 | 67b55785 | blueswir1 | qemu_put_be32s(f, &q->queue[i]); |
1062 | 67b55785 | blueswir1 | |
1063 | 67b55785 | blueswir1 | qemu_put_sbe32s(f, &q->next); |
1064 | 67b55785 | blueswir1 | qemu_put_sbe32s(f, &q->priority); |
1065 | 67b55785 | blueswir1 | } |
1066 | 67b55785 | blueswir1 | |
1067 | 67b55785 | blueswir1 | static void openpic_save(QEMUFile* f, void *opaque) |
1068 | 67b55785 | blueswir1 | { |
1069 | 67b55785 | blueswir1 | openpic_t *opp = (openpic_t *)opaque; |
1070 | 67b55785 | blueswir1 | unsigned int i; |
1071 | 67b55785 | blueswir1 | |
1072 | 67b55785 | blueswir1 | qemu_put_be32s(f, &opp->frep); |
1073 | 67b55785 | blueswir1 | qemu_put_be32s(f, &opp->glbc); |
1074 | 67b55785 | blueswir1 | qemu_put_be32s(f, &opp->micr); |
1075 | 67b55785 | blueswir1 | qemu_put_be32s(f, &opp->veni); |
1076 | 67b55785 | blueswir1 | qemu_put_be32s(f, &opp->pint); |
1077 | 67b55785 | blueswir1 | qemu_put_be32s(f, &opp->spve); |
1078 | 67b55785 | blueswir1 | qemu_put_be32s(f, &opp->tifr); |
1079 | 67b55785 | blueswir1 | |
1080 | b7169916 | aurel32 | for (i = 0; i < opp->max_irq; i++) { |
1081 | 67b55785 | blueswir1 | qemu_put_be32s(f, &opp->src[i].ipvp); |
1082 | 67b55785 | blueswir1 | qemu_put_be32s(f, &opp->src[i].ide); |
1083 | 67b55785 | blueswir1 | qemu_put_sbe32s(f, &opp->src[i].type); |
1084 | 67b55785 | blueswir1 | qemu_put_sbe32s(f, &opp->src[i].last_cpu); |
1085 | 67b55785 | blueswir1 | qemu_put_sbe32s(f, &opp->src[i].pending); |
1086 | 67b55785 | blueswir1 | } |
1087 | 67b55785 | blueswir1 | |
1088 | b7169916 | aurel32 | qemu_put_sbe32s(f, &opp->nb_cpus); |
1089 | b7169916 | aurel32 | |
1090 | b7169916 | aurel32 | for (i = 0; i < opp->nb_cpus; i++) { |
1091 | b7169916 | aurel32 | qemu_put_be32s(f, &opp->dst[i].tfrr); |
1092 | 67b55785 | blueswir1 | qemu_put_be32s(f, &opp->dst[i].pctp); |
1093 | 67b55785 | blueswir1 | qemu_put_be32s(f, &opp->dst[i].pcsr); |
1094 | 67b55785 | blueswir1 | openpic_save_IRQ_queue(f, &opp->dst[i].raised); |
1095 | 67b55785 | blueswir1 | openpic_save_IRQ_queue(f, &opp->dst[i].servicing); |
1096 | 67b55785 | blueswir1 | } |
1097 | 67b55785 | blueswir1 | |
1098 | 67b55785 | blueswir1 | for (i = 0; i < MAX_TMR; i++) { |
1099 | 67b55785 | blueswir1 | qemu_put_be32s(f, &opp->timers[i].ticc); |
1100 | 67b55785 | blueswir1 | qemu_put_be32s(f, &opp->timers[i].tibc); |
1101 | 67b55785 | blueswir1 | } |
1102 | 67b55785 | blueswir1 | |
1103 | 67b55785 | blueswir1 | #if MAX_DBL > 0 |
1104 | 67b55785 | blueswir1 | qemu_put_be32s(f, &opp->dar); |
1105 | 67b55785 | blueswir1 | |
1106 | 67b55785 | blueswir1 | for (i = 0; i < MAX_DBL; i++) { |
1107 | 67b55785 | blueswir1 | qemu_put_be32s(f, &opp->doorbells[i].dmr); |
1108 | 67b55785 | blueswir1 | } |
1109 | 67b55785 | blueswir1 | #endif
|
1110 | 67b55785 | blueswir1 | |
1111 | 67b55785 | blueswir1 | #if MAX_MBX > 0 |
1112 | 67b55785 | blueswir1 | for (i = 0; i < MAX_MAILBOXES; i++) { |
1113 | 67b55785 | blueswir1 | qemu_put_be32s(f, &opp->mailboxes[i].mbr); |
1114 | 67b55785 | blueswir1 | } |
1115 | 67b55785 | blueswir1 | #endif
|
1116 | 67b55785 | blueswir1 | |
1117 | 67b55785 | blueswir1 | pci_device_save(&opp->pci_dev, f); |
1118 | 67b55785 | blueswir1 | } |
1119 | 67b55785 | blueswir1 | |
1120 | 67b55785 | blueswir1 | static void openpic_load_IRQ_queue(QEMUFile* f, IRQ_queue_t *q) |
1121 | 67b55785 | blueswir1 | { |
1122 | 67b55785 | blueswir1 | unsigned int i; |
1123 | 67b55785 | blueswir1 | |
1124 | 67b55785 | blueswir1 | for (i = 0; i < BF_WIDTH(MAX_IRQ); i++) |
1125 | 67b55785 | blueswir1 | qemu_get_be32s(f, &q->queue[i]); |
1126 | 67b55785 | blueswir1 | |
1127 | 67b55785 | blueswir1 | qemu_get_sbe32s(f, &q->next); |
1128 | 67b55785 | blueswir1 | qemu_get_sbe32s(f, &q->priority); |
1129 | 67b55785 | blueswir1 | } |
1130 | 67b55785 | blueswir1 | |
1131 | 67b55785 | blueswir1 | static int openpic_load(QEMUFile* f, void *opaque, int version_id) |
1132 | 67b55785 | blueswir1 | { |
1133 | 67b55785 | blueswir1 | openpic_t *opp = (openpic_t *)opaque; |
1134 | 67b55785 | blueswir1 | unsigned int i; |
1135 | 67b55785 | blueswir1 | |
1136 | 67b55785 | blueswir1 | if (version_id != 1) |
1137 | 67b55785 | blueswir1 | return -EINVAL;
|
1138 | 67b55785 | blueswir1 | |
1139 | 67b55785 | blueswir1 | qemu_get_be32s(f, &opp->frep); |
1140 | 67b55785 | blueswir1 | qemu_get_be32s(f, &opp->glbc); |
1141 | 67b55785 | blueswir1 | qemu_get_be32s(f, &opp->micr); |
1142 | 67b55785 | blueswir1 | qemu_get_be32s(f, &opp->veni); |
1143 | 67b55785 | blueswir1 | qemu_get_be32s(f, &opp->pint); |
1144 | 67b55785 | blueswir1 | qemu_get_be32s(f, &opp->spve); |
1145 | 67b55785 | blueswir1 | qemu_get_be32s(f, &opp->tifr); |
1146 | 67b55785 | blueswir1 | |
1147 | b7169916 | aurel32 | for (i = 0; i < opp->max_irq; i++) { |
1148 | 67b55785 | blueswir1 | qemu_get_be32s(f, &opp->src[i].ipvp); |
1149 | 67b55785 | blueswir1 | qemu_get_be32s(f, &opp->src[i].ide); |
1150 | 67b55785 | blueswir1 | qemu_get_sbe32s(f, &opp->src[i].type); |
1151 | 67b55785 | blueswir1 | qemu_get_sbe32s(f, &opp->src[i].last_cpu); |
1152 | 67b55785 | blueswir1 | qemu_get_sbe32s(f, &opp->src[i].pending); |
1153 | 67b55785 | blueswir1 | } |
1154 | 67b55785 | blueswir1 | |
1155 | b7169916 | aurel32 | qemu_get_sbe32s(f, &opp->nb_cpus); |
1156 | b7169916 | aurel32 | |
1157 | b7169916 | aurel32 | for (i = 0; i < opp->nb_cpus; i++) { |
1158 | b7169916 | aurel32 | qemu_get_be32s(f, &opp->dst[i].tfrr); |
1159 | 67b55785 | blueswir1 | qemu_get_be32s(f, &opp->dst[i].pctp); |
1160 | 67b55785 | blueswir1 | qemu_get_be32s(f, &opp->dst[i].pcsr); |
1161 | 67b55785 | blueswir1 | openpic_load_IRQ_queue(f, &opp->dst[i].raised); |
1162 | 67b55785 | blueswir1 | openpic_load_IRQ_queue(f, &opp->dst[i].servicing); |
1163 | 67b55785 | blueswir1 | } |
1164 | 67b55785 | blueswir1 | |
1165 | 67b55785 | blueswir1 | for (i = 0; i < MAX_TMR; i++) { |
1166 | 67b55785 | blueswir1 | qemu_get_be32s(f, &opp->timers[i].ticc); |
1167 | 67b55785 | blueswir1 | qemu_get_be32s(f, &opp->timers[i].tibc); |
1168 | 67b55785 | blueswir1 | } |
1169 | 67b55785 | blueswir1 | |
1170 | 67b55785 | blueswir1 | #if MAX_DBL > 0 |
1171 | 67b55785 | blueswir1 | qemu_get_be32s(f, &opp->dar); |
1172 | 67b55785 | blueswir1 | |
1173 | 67b55785 | blueswir1 | for (i = 0; i < MAX_DBL; i++) { |
1174 | 67b55785 | blueswir1 | qemu_get_be32s(f, &opp->doorbells[i].dmr); |
1175 | 67b55785 | blueswir1 | } |
1176 | 67b55785 | blueswir1 | #endif
|
1177 | 67b55785 | blueswir1 | |
1178 | 67b55785 | blueswir1 | #if MAX_MBX > 0 |
1179 | 67b55785 | blueswir1 | for (i = 0; i < MAX_MAILBOXES; i++) { |
1180 | 67b55785 | blueswir1 | qemu_get_be32s(f, &opp->mailboxes[i].mbr); |
1181 | 67b55785 | blueswir1 | } |
1182 | 67b55785 | blueswir1 | #endif
|
1183 | 67b55785 | blueswir1 | |
1184 | 67b55785 | blueswir1 | return pci_device_load(&opp->pci_dev, f);
|
1185 | 67b55785 | blueswir1 | } |
1186 | 67b55785 | blueswir1 | |
1187 | b7169916 | aurel32 | static void openpic_irq_raise(openpic_t *opp, int n_CPU, IRQ_src_t *src) |
1188 | b7169916 | aurel32 | { |
1189 | b7169916 | aurel32 | qemu_irq_raise(opp->dst[n_CPU].irqs[OPENPIC_OUTPUT_INT]); |
1190 | b7169916 | aurel32 | } |
1191 | b7169916 | aurel32 | |
1192 | e9df014c | j_mayer | qemu_irq *openpic_init (PCIBus *bus, int *pmem_index, int nb_cpus, |
1193 | e9df014c | j_mayer | qemu_irq **irqs, qemu_irq irq_out) |
1194 | dbda808a | bellard | { |
1195 | dbda808a | bellard | openpic_t *opp; |
1196 | dbda808a | bellard | uint8_t *pci_conf; |
1197 | dbda808a | bellard | int i, m;
|
1198 | 3b46e624 | ths | |
1199 | dbda808a | bellard | /* XXX: for now, only one CPU is supported */
|
1200 | dbda808a | bellard | if (nb_cpus != 1) |
1201 | dbda808a | bellard | return NULL; |
1202 | 91d848eb | bellard | if (bus) {
|
1203 | 91d848eb | bellard | opp = (openpic_t *)pci_register_device(bus, "OpenPIC", sizeof(openpic_t), |
1204 | 91d848eb | bellard | -1, NULL, NULL); |
1205 | 91d848eb | bellard | if (opp == NULL) |
1206 | 91d848eb | bellard | return NULL; |
1207 | 91d848eb | bellard | pci_conf = opp->pci_dev.config; |
1208 | deb54399 | aliguori | pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_IBM); |
1209 | 4ebcf884 | blueswir1 | pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_IBM_OPENPIC2); |
1210 | 173a543b | blueswir1 | pci_config_set_class(pci_conf, PCI_CLASS_SYSTEM_OTHER); // FIXME?
|
1211 | 6407f373 | Isaku Yamahata | pci_conf[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_NORMAL; // header_type
|
1212 | 91d848eb | bellard | pci_conf[0x3d] = 0x00; // no interrupt pin |
1213 | 3b46e624 | ths | |
1214 | 91d848eb | bellard | /* Register I/O spaces */
|
1215 | 28c2c264 | Avi Kivity | pci_register_bar((PCIDevice *)opp, 0, 0x40000, |
1216 | 91d848eb | bellard | PCI_ADDRESS_SPACE_MEM, &openpic_map); |
1217 | 91d848eb | bellard | } else {
|
1218 | 91d848eb | bellard | opp = qemu_mallocz(sizeof(openpic_t));
|
1219 | 91d848eb | bellard | } |
1220 | 1eed09cb | Avi Kivity | opp->mem_index = cpu_register_io_memory(openpic_read, |
1221 | 91d848eb | bellard | openpic_write, opp); |
1222 | 3b46e624 | ths | |
1223 | 91d848eb | bellard | // isu_base &= 0xFFFC0000;
|
1224 | dbda808a | bellard | opp->nb_cpus = nb_cpus; |
1225 | b7169916 | aurel32 | opp->max_irq = OPENPIC_MAX_IRQ; |
1226 | b7169916 | aurel32 | opp->irq_ipi0 = OPENPIC_IRQ_IPI0; |
1227 | b7169916 | aurel32 | opp->irq_tim0 = OPENPIC_IRQ_TIM0; |
1228 | dbda808a | bellard | /* Set IRQ types */
|
1229 | b7169916 | aurel32 | for (i = 0; i < OPENPIC_EXT_IRQ; i++) { |
1230 | dbda808a | bellard | opp->src[i].type = IRQ_EXTERNAL; |
1231 | dbda808a | bellard | } |
1232 | b7169916 | aurel32 | for (; i < OPENPIC_IRQ_TIM0; i++) {
|
1233 | dbda808a | bellard | opp->src[i].type = IRQ_SPECIAL; |
1234 | dbda808a | bellard | } |
1235 | dbda808a | bellard | #if MAX_IPI > 0 |
1236 | b7169916 | aurel32 | m = OPENPIC_IRQ_IPI0; |
1237 | dbda808a | bellard | #else
|
1238 | b7169916 | aurel32 | m = OPENPIC_IRQ_DBL0; |
1239 | dbda808a | bellard | #endif
|
1240 | dbda808a | bellard | for (; i < m; i++) {
|
1241 | dbda808a | bellard | opp->src[i].type = IRQ_TIMER; |
1242 | dbda808a | bellard | } |
1243 | b7169916 | aurel32 | for (; i < OPENPIC_MAX_IRQ; i++) {
|
1244 | dbda808a | bellard | opp->src[i].type = IRQ_INTERNAL; |
1245 | dbda808a | bellard | } |
1246 | 7668a27f | bellard | for (i = 0; i < nb_cpus; i++) |
1247 | e9df014c | j_mayer | opp->dst[i].irqs = irqs[i]; |
1248 | e9df014c | j_mayer | opp->irq_out = irq_out; |
1249 | b7169916 | aurel32 | opp->need_swap = 1;
|
1250 | 67b55785 | blueswir1 | |
1251 | b7169916 | aurel32 | register_savevm("openpic", 0, 2, openpic_save, openpic_load, opp); |
1252 | a08d4367 | Jan Kiszka | qemu_register_reset(openpic_reset, opp); |
1253 | b7169916 | aurel32 | |
1254 | b7169916 | aurel32 | opp->irq_raise = openpic_irq_raise; |
1255 | b7169916 | aurel32 | opp->reset = openpic_reset; |
1256 | b7169916 | aurel32 | |
1257 | b7169916 | aurel32 | opp->reset(opp); |
1258 | 91d848eb | bellard | if (pmem_index)
|
1259 | 91d848eb | bellard | *pmem_index = opp->mem_index; |
1260 | e9df014c | j_mayer | |
1261 | b7169916 | aurel32 | return qemu_allocate_irqs(openpic_set_irq, opp, opp->max_irq);
|
1262 | b7169916 | aurel32 | } |
1263 | b7169916 | aurel32 | |
1264 | b7169916 | aurel32 | static void mpic_irq_raise(openpic_t *mpp, int n_CPU, IRQ_src_t *src) |
1265 | b7169916 | aurel32 | { |
1266 | b7169916 | aurel32 | int n_ci = IDR_CI0 - n_CPU;
|
1267 | 0bf9e31a | Blue Swirl | |
1268 | b7169916 | aurel32 | if(test_bit(&src->ide, n_ci)) {
|
1269 | b7169916 | aurel32 | qemu_irq_raise(mpp->dst[n_CPU].irqs[OPENPIC_OUTPUT_CINT]); |
1270 | b7169916 | aurel32 | } |
1271 | b7169916 | aurel32 | else {
|
1272 | b7169916 | aurel32 | qemu_irq_raise(mpp->dst[n_CPU].irqs[OPENPIC_OUTPUT_INT]); |
1273 | b7169916 | aurel32 | } |
1274 | b7169916 | aurel32 | } |
1275 | b7169916 | aurel32 | |
1276 | b7169916 | aurel32 | static void mpic_reset (void *opaque) |
1277 | b7169916 | aurel32 | { |
1278 | b7169916 | aurel32 | openpic_t *mpp = (openpic_t *)opaque; |
1279 | b7169916 | aurel32 | int i;
|
1280 | b7169916 | aurel32 | |
1281 | b7169916 | aurel32 | mpp->glbc = 0x80000000;
|
1282 | b7169916 | aurel32 | /* Initialise controller registers */
|
1283 | b7169916 | aurel32 | mpp->frep = 0x004f0002;
|
1284 | b7169916 | aurel32 | mpp->veni = VENI; |
1285 | b7169916 | aurel32 | mpp->pint = 0x00000000;
|
1286 | b7169916 | aurel32 | mpp->spve = 0x0000FFFF;
|
1287 | b7169916 | aurel32 | /* Initialise IRQ sources */
|
1288 | b7169916 | aurel32 | for (i = 0; i < mpp->max_irq; i++) { |
1289 | b7169916 | aurel32 | mpp->src[i].ipvp = 0x80800000;
|
1290 | b7169916 | aurel32 | mpp->src[i].ide = 0x00000001;
|
1291 | b7169916 | aurel32 | } |
1292 | b7169916 | aurel32 | /* Initialise IRQ destinations */
|
1293 | b7169916 | aurel32 | for (i = 0; i < MAX_CPU; i++) { |
1294 | b7169916 | aurel32 | mpp->dst[i].pctp = 0x0000000F;
|
1295 | b7169916 | aurel32 | mpp->dst[i].tfrr = 0x00000000;
|
1296 | b7169916 | aurel32 | memset(&mpp->dst[i].raised, 0, sizeof(IRQ_queue_t)); |
1297 | b7169916 | aurel32 | mpp->dst[i].raised.next = -1;
|
1298 | b7169916 | aurel32 | memset(&mpp->dst[i].servicing, 0, sizeof(IRQ_queue_t)); |
1299 | b7169916 | aurel32 | mpp->dst[i].servicing.next = -1;
|
1300 | b7169916 | aurel32 | } |
1301 | b7169916 | aurel32 | /* Initialise timers */
|
1302 | b7169916 | aurel32 | for (i = 0; i < MAX_TMR; i++) { |
1303 | b7169916 | aurel32 | mpp->timers[i].ticc = 0x00000000;
|
1304 | b7169916 | aurel32 | mpp->timers[i].tibc = 0x80000000;
|
1305 | b7169916 | aurel32 | } |
1306 | b7169916 | aurel32 | /* Go out of RESET state */
|
1307 | b7169916 | aurel32 | mpp->glbc = 0x00000000;
|
1308 | b7169916 | aurel32 | } |
1309 | b7169916 | aurel32 | |
1310 | b7169916 | aurel32 | static void mpic_timer_write (void *opaque, target_phys_addr_t addr, uint32_t val) |
1311 | b7169916 | aurel32 | { |
1312 | b7169916 | aurel32 | openpic_t *mpp = opaque; |
1313 | b7169916 | aurel32 | int idx, cpu;
|
1314 | b7169916 | aurel32 | |
1315 | 0bf9e31a | Blue Swirl | DPRINTF("%s: addr " TARGET_FMT_plx " <= %08x\n", __func__, addr, val); |
1316 | b7169916 | aurel32 | if (addr & 0xF) |
1317 | b7169916 | aurel32 | return;
|
1318 | b7169916 | aurel32 | addr &= 0xFFFF;
|
1319 | b7169916 | aurel32 | cpu = addr >> 12;
|
1320 | b7169916 | aurel32 | idx = (addr >> 6) & 0x3; |
1321 | b7169916 | aurel32 | switch (addr & 0x30) { |
1322 | b7169916 | aurel32 | case 0x00: /* gtccr */ |
1323 | b7169916 | aurel32 | break;
|
1324 | b7169916 | aurel32 | case 0x10: /* gtbcr */ |
1325 | b7169916 | aurel32 | if ((mpp->timers[idx].ticc & 0x80000000) != 0 && |
1326 | b7169916 | aurel32 | (val & 0x80000000) == 0 && |
1327 | b7169916 | aurel32 | (mpp->timers[idx].tibc & 0x80000000) != 0) |
1328 | b7169916 | aurel32 | mpp->timers[idx].ticc &= ~0x80000000;
|
1329 | b7169916 | aurel32 | mpp->timers[idx].tibc = val; |
1330 | b7169916 | aurel32 | break;
|
1331 | b7169916 | aurel32 | case 0x20: /* GTIVPR */ |
1332 | b7169916 | aurel32 | write_IRQreg(mpp, MPIC_TMR_IRQ + idx, IRQ_IPVP, val); |
1333 | b7169916 | aurel32 | break;
|
1334 | b7169916 | aurel32 | case 0x30: /* GTIDR & TFRR */ |
1335 | b7169916 | aurel32 | if ((addr & 0xF0) == 0xF0) |
1336 | b7169916 | aurel32 | mpp->dst[cpu].tfrr = val; |
1337 | b7169916 | aurel32 | else
|
1338 | b7169916 | aurel32 | write_IRQreg(mpp, MPIC_TMR_IRQ + idx, IRQ_IDE, val); |
1339 | b7169916 | aurel32 | break;
|
1340 | b7169916 | aurel32 | } |
1341 | b7169916 | aurel32 | } |
1342 | b7169916 | aurel32 | |
1343 | b7169916 | aurel32 | static uint32_t mpic_timer_read (void *opaque, target_phys_addr_t addr) |
1344 | b7169916 | aurel32 | { |
1345 | b7169916 | aurel32 | openpic_t *mpp = opaque; |
1346 | b7169916 | aurel32 | uint32_t retval; |
1347 | b7169916 | aurel32 | int idx, cpu;
|
1348 | b7169916 | aurel32 | |
1349 | 0bf9e31a | Blue Swirl | DPRINTF("%s: addr " TARGET_FMT_plx "\n", __func__, addr); |
1350 | b7169916 | aurel32 | retval = 0xFFFFFFFF;
|
1351 | b7169916 | aurel32 | if (addr & 0xF) |
1352 | b7169916 | aurel32 | return retval;
|
1353 | b7169916 | aurel32 | addr &= 0xFFFF;
|
1354 | b7169916 | aurel32 | cpu = addr >> 12;
|
1355 | b7169916 | aurel32 | idx = (addr >> 6) & 0x3; |
1356 | b7169916 | aurel32 | switch (addr & 0x30) { |
1357 | b7169916 | aurel32 | case 0x00: /* gtccr */ |
1358 | b7169916 | aurel32 | retval = mpp->timers[idx].ticc; |
1359 | b7169916 | aurel32 | break;
|
1360 | b7169916 | aurel32 | case 0x10: /* gtbcr */ |
1361 | b7169916 | aurel32 | retval = mpp->timers[idx].tibc; |
1362 | b7169916 | aurel32 | break;
|
1363 | b7169916 | aurel32 | case 0x20: /* TIPV */ |
1364 | b7169916 | aurel32 | retval = read_IRQreg(mpp, MPIC_TMR_IRQ + idx, IRQ_IPVP); |
1365 | b7169916 | aurel32 | break;
|
1366 | b7169916 | aurel32 | case 0x30: /* TIDR */ |
1367 | b7169916 | aurel32 | if ((addr &0xF0) == 0XF0) |
1368 | b7169916 | aurel32 | retval = mpp->dst[cpu].tfrr; |
1369 | b7169916 | aurel32 | else
|
1370 | b7169916 | aurel32 | retval = read_IRQreg(mpp, MPIC_TMR_IRQ + idx, IRQ_IDE); |
1371 | b7169916 | aurel32 | break;
|
1372 | b7169916 | aurel32 | } |
1373 | b7169916 | aurel32 | DPRINTF("%s: => %08x\n", __func__, retval);
|
1374 | b7169916 | aurel32 | |
1375 | b7169916 | aurel32 | return retval;
|
1376 | b7169916 | aurel32 | } |
1377 | b7169916 | aurel32 | |
1378 | b7169916 | aurel32 | static void mpic_src_ext_write (void *opaque, target_phys_addr_t addr, |
1379 | b7169916 | aurel32 | uint32_t val) |
1380 | b7169916 | aurel32 | { |
1381 | b7169916 | aurel32 | openpic_t *mpp = opaque; |
1382 | b7169916 | aurel32 | int idx = MPIC_EXT_IRQ;
|
1383 | b7169916 | aurel32 | |
1384 | 0bf9e31a | Blue Swirl | DPRINTF("%s: addr " TARGET_FMT_plx " <= %08x\n", __func__, addr, val); |
1385 | b7169916 | aurel32 | if (addr & 0xF) |
1386 | b7169916 | aurel32 | return;
|
1387 | b7169916 | aurel32 | |
1388 | b7169916 | aurel32 | addr -= MPIC_EXT_REG_START & (TARGET_PAGE_SIZE - 1);
|
1389 | b7169916 | aurel32 | if (addr < MPIC_EXT_REG_SIZE) {
|
1390 | b7169916 | aurel32 | idx += (addr & 0xFFF0) >> 5; |
1391 | b7169916 | aurel32 | if (addr & 0x10) { |
1392 | b7169916 | aurel32 | /* EXDE / IFEDE / IEEDE */
|
1393 | b7169916 | aurel32 | write_IRQreg(mpp, idx, IRQ_IDE, val); |
1394 | b7169916 | aurel32 | } else {
|
1395 | b7169916 | aurel32 | /* EXVP / IFEVP / IEEVP */
|
1396 | b7169916 | aurel32 | write_IRQreg(mpp, idx, IRQ_IPVP, val); |
1397 | b7169916 | aurel32 | } |
1398 | b7169916 | aurel32 | } |
1399 | b7169916 | aurel32 | } |
1400 | b7169916 | aurel32 | |
1401 | b7169916 | aurel32 | static uint32_t mpic_src_ext_read (void *opaque, target_phys_addr_t addr) |
1402 | b7169916 | aurel32 | { |
1403 | b7169916 | aurel32 | openpic_t *mpp = opaque; |
1404 | b7169916 | aurel32 | uint32_t retval; |
1405 | b7169916 | aurel32 | int idx = MPIC_EXT_IRQ;
|
1406 | b7169916 | aurel32 | |
1407 | 0bf9e31a | Blue Swirl | DPRINTF("%s: addr " TARGET_FMT_plx "\n", __func__, addr); |
1408 | b7169916 | aurel32 | retval = 0xFFFFFFFF;
|
1409 | b7169916 | aurel32 | if (addr & 0xF) |
1410 | b7169916 | aurel32 | return retval;
|
1411 | b7169916 | aurel32 | |
1412 | b7169916 | aurel32 | addr -= MPIC_EXT_REG_START & (TARGET_PAGE_SIZE - 1);
|
1413 | b7169916 | aurel32 | if (addr < MPIC_EXT_REG_SIZE) {
|
1414 | b7169916 | aurel32 | idx += (addr & 0xFFF0) >> 5; |
1415 | b7169916 | aurel32 | if (addr & 0x10) { |
1416 | b7169916 | aurel32 | /* EXDE / IFEDE / IEEDE */
|
1417 | b7169916 | aurel32 | retval = read_IRQreg(mpp, idx, IRQ_IDE); |
1418 | b7169916 | aurel32 | } else {
|
1419 | b7169916 | aurel32 | /* EXVP / IFEVP / IEEVP */
|
1420 | b7169916 | aurel32 | retval = read_IRQreg(mpp, idx, IRQ_IPVP); |
1421 | b7169916 | aurel32 | } |
1422 | b7169916 | aurel32 | DPRINTF("%s: => %08x\n", __func__, retval);
|
1423 | b7169916 | aurel32 | } |
1424 | b7169916 | aurel32 | |
1425 | b7169916 | aurel32 | return retval;
|
1426 | b7169916 | aurel32 | } |
1427 | b7169916 | aurel32 | |
1428 | b7169916 | aurel32 | static void mpic_src_int_write (void *opaque, target_phys_addr_t addr, |
1429 | b7169916 | aurel32 | uint32_t val) |
1430 | b7169916 | aurel32 | { |
1431 | b7169916 | aurel32 | openpic_t *mpp = opaque; |
1432 | b7169916 | aurel32 | int idx = MPIC_INT_IRQ;
|
1433 | b7169916 | aurel32 | |
1434 | 0bf9e31a | Blue Swirl | DPRINTF("%s: addr " TARGET_FMT_plx " <= %08x\n", __func__, addr, val); |
1435 | b7169916 | aurel32 | if (addr & 0xF) |
1436 | b7169916 | aurel32 | return;
|
1437 | b7169916 | aurel32 | |
1438 | b7169916 | aurel32 | addr -= MPIC_INT_REG_START & (TARGET_PAGE_SIZE - 1);
|
1439 | b7169916 | aurel32 | if (addr < MPIC_INT_REG_SIZE) {
|
1440 | b7169916 | aurel32 | idx += (addr & 0xFFF0) >> 5; |
1441 | b7169916 | aurel32 | if (addr & 0x10) { |
1442 | b7169916 | aurel32 | /* EXDE / IFEDE / IEEDE */
|
1443 | b7169916 | aurel32 | write_IRQreg(mpp, idx, IRQ_IDE, val); |
1444 | b7169916 | aurel32 | } else {
|
1445 | b7169916 | aurel32 | /* EXVP / IFEVP / IEEVP */
|
1446 | b7169916 | aurel32 | write_IRQreg(mpp, idx, IRQ_IPVP, val); |
1447 | b7169916 | aurel32 | } |
1448 | b7169916 | aurel32 | } |
1449 | b7169916 | aurel32 | } |
1450 | b7169916 | aurel32 | |
1451 | b7169916 | aurel32 | static uint32_t mpic_src_int_read (void *opaque, target_phys_addr_t addr) |
1452 | b7169916 | aurel32 | { |
1453 | b7169916 | aurel32 | openpic_t *mpp = opaque; |
1454 | b7169916 | aurel32 | uint32_t retval; |
1455 | b7169916 | aurel32 | int idx = MPIC_INT_IRQ;
|
1456 | b7169916 | aurel32 | |
1457 | 0bf9e31a | Blue Swirl | DPRINTF("%s: addr " TARGET_FMT_plx "\n", __func__, addr); |
1458 | b7169916 | aurel32 | retval = 0xFFFFFFFF;
|
1459 | b7169916 | aurel32 | if (addr & 0xF) |
1460 | b7169916 | aurel32 | return retval;
|
1461 | b7169916 | aurel32 | |
1462 | b7169916 | aurel32 | addr -= MPIC_INT_REG_START & (TARGET_PAGE_SIZE - 1);
|
1463 | b7169916 | aurel32 | if (addr < MPIC_INT_REG_SIZE) {
|
1464 | b7169916 | aurel32 | idx += (addr & 0xFFF0) >> 5; |
1465 | b7169916 | aurel32 | if (addr & 0x10) { |
1466 | b7169916 | aurel32 | /* EXDE / IFEDE / IEEDE */
|
1467 | b7169916 | aurel32 | retval = read_IRQreg(mpp, idx, IRQ_IDE); |
1468 | b7169916 | aurel32 | } else {
|
1469 | b7169916 | aurel32 | /* EXVP / IFEVP / IEEVP */
|
1470 | b7169916 | aurel32 | retval = read_IRQreg(mpp, idx, IRQ_IPVP); |
1471 | b7169916 | aurel32 | } |
1472 | b7169916 | aurel32 | DPRINTF("%s: => %08x\n", __func__, retval);
|
1473 | b7169916 | aurel32 | } |
1474 | b7169916 | aurel32 | |
1475 | b7169916 | aurel32 | return retval;
|
1476 | b7169916 | aurel32 | } |
1477 | b7169916 | aurel32 | |
1478 | b7169916 | aurel32 | static void mpic_src_msg_write (void *opaque, target_phys_addr_t addr, |
1479 | b7169916 | aurel32 | uint32_t val) |
1480 | b7169916 | aurel32 | { |
1481 | b7169916 | aurel32 | openpic_t *mpp = opaque; |
1482 | b7169916 | aurel32 | int idx = MPIC_MSG_IRQ;
|
1483 | b7169916 | aurel32 | |
1484 | 0bf9e31a | Blue Swirl | DPRINTF("%s: addr " TARGET_FMT_plx " <= %08x\n", __func__, addr, val); |
1485 | b7169916 | aurel32 | if (addr & 0xF) |
1486 | b7169916 | aurel32 | return;
|
1487 | b7169916 | aurel32 | |
1488 | b7169916 | aurel32 | addr -= MPIC_MSG_REG_START & (TARGET_PAGE_SIZE - 1);
|
1489 | b7169916 | aurel32 | if (addr < MPIC_MSG_REG_SIZE) {
|
1490 | b7169916 | aurel32 | idx += (addr & 0xFFF0) >> 5; |
1491 | b7169916 | aurel32 | if (addr & 0x10) { |
1492 | b7169916 | aurel32 | /* EXDE / IFEDE / IEEDE */
|
1493 | b7169916 | aurel32 | write_IRQreg(mpp, idx, IRQ_IDE, val); |
1494 | b7169916 | aurel32 | } else {
|
1495 | b7169916 | aurel32 | /* EXVP / IFEVP / IEEVP */
|
1496 | b7169916 | aurel32 | write_IRQreg(mpp, idx, IRQ_IPVP, val); |
1497 | b7169916 | aurel32 | } |
1498 | b7169916 | aurel32 | } |
1499 | b7169916 | aurel32 | } |
1500 | b7169916 | aurel32 | |
1501 | b7169916 | aurel32 | static uint32_t mpic_src_msg_read (void *opaque, target_phys_addr_t addr) |
1502 | b7169916 | aurel32 | { |
1503 | b7169916 | aurel32 | openpic_t *mpp = opaque; |
1504 | b7169916 | aurel32 | uint32_t retval; |
1505 | b7169916 | aurel32 | int idx = MPIC_MSG_IRQ;
|
1506 | b7169916 | aurel32 | |
1507 | 0bf9e31a | Blue Swirl | DPRINTF("%s: addr " TARGET_FMT_plx "\n", __func__, addr); |
1508 | b7169916 | aurel32 | retval = 0xFFFFFFFF;
|
1509 | b7169916 | aurel32 | if (addr & 0xF) |
1510 | b7169916 | aurel32 | return retval;
|
1511 | b7169916 | aurel32 | |
1512 | b7169916 | aurel32 | addr -= MPIC_MSG_REG_START & (TARGET_PAGE_SIZE - 1);
|
1513 | b7169916 | aurel32 | if (addr < MPIC_MSG_REG_SIZE) {
|
1514 | b7169916 | aurel32 | idx += (addr & 0xFFF0) >> 5; |
1515 | b7169916 | aurel32 | if (addr & 0x10) { |
1516 | b7169916 | aurel32 | /* EXDE / IFEDE / IEEDE */
|
1517 | b7169916 | aurel32 | retval = read_IRQreg(mpp, idx, IRQ_IDE); |
1518 | b7169916 | aurel32 | } else {
|
1519 | b7169916 | aurel32 | /* EXVP / IFEVP / IEEVP */
|
1520 | b7169916 | aurel32 | retval = read_IRQreg(mpp, idx, IRQ_IPVP); |
1521 | b7169916 | aurel32 | } |
1522 | b7169916 | aurel32 | DPRINTF("%s: => %08x\n", __func__, retval);
|
1523 | b7169916 | aurel32 | } |
1524 | b7169916 | aurel32 | |
1525 | b7169916 | aurel32 | return retval;
|
1526 | b7169916 | aurel32 | } |
1527 | b7169916 | aurel32 | |
1528 | b7169916 | aurel32 | static void mpic_src_msi_write (void *opaque, target_phys_addr_t addr, |
1529 | b7169916 | aurel32 | uint32_t val) |
1530 | b7169916 | aurel32 | { |
1531 | b7169916 | aurel32 | openpic_t *mpp = opaque; |
1532 | b7169916 | aurel32 | int idx = MPIC_MSI_IRQ;
|
1533 | b7169916 | aurel32 | |
1534 | 0bf9e31a | Blue Swirl | DPRINTF("%s: addr " TARGET_FMT_plx " <= %08x\n", __func__, addr, val); |
1535 | b7169916 | aurel32 | if (addr & 0xF) |
1536 | b7169916 | aurel32 | return;
|
1537 | b7169916 | aurel32 | |
1538 | b7169916 | aurel32 | addr -= MPIC_MSI_REG_START & (TARGET_PAGE_SIZE - 1);
|
1539 | b7169916 | aurel32 | if (addr < MPIC_MSI_REG_SIZE) {
|
1540 | b7169916 | aurel32 | idx += (addr & 0xFFF0) >> 5; |
1541 | b7169916 | aurel32 | if (addr & 0x10) { |
1542 | b7169916 | aurel32 | /* EXDE / IFEDE / IEEDE */
|
1543 | b7169916 | aurel32 | write_IRQreg(mpp, idx, IRQ_IDE, val); |
1544 | b7169916 | aurel32 | } else {
|
1545 | b7169916 | aurel32 | /* EXVP / IFEVP / IEEVP */
|
1546 | b7169916 | aurel32 | write_IRQreg(mpp, idx, IRQ_IPVP, val); |
1547 | b7169916 | aurel32 | } |
1548 | b7169916 | aurel32 | } |
1549 | b7169916 | aurel32 | } |
1550 | b7169916 | aurel32 | static uint32_t mpic_src_msi_read (void *opaque, target_phys_addr_t addr) |
1551 | b7169916 | aurel32 | { |
1552 | b7169916 | aurel32 | openpic_t *mpp = opaque; |
1553 | b7169916 | aurel32 | uint32_t retval; |
1554 | b7169916 | aurel32 | int idx = MPIC_MSI_IRQ;
|
1555 | b7169916 | aurel32 | |
1556 | 0bf9e31a | Blue Swirl | DPRINTF("%s: addr " TARGET_FMT_plx "\n", __func__, addr); |
1557 | b7169916 | aurel32 | retval = 0xFFFFFFFF;
|
1558 | b7169916 | aurel32 | if (addr & 0xF) |
1559 | b7169916 | aurel32 | return retval;
|
1560 | b7169916 | aurel32 | |
1561 | b7169916 | aurel32 | addr -= MPIC_MSI_REG_START & (TARGET_PAGE_SIZE - 1);
|
1562 | b7169916 | aurel32 | if (addr < MPIC_MSI_REG_SIZE) {
|
1563 | b7169916 | aurel32 | idx += (addr & 0xFFF0) >> 5; |
1564 | b7169916 | aurel32 | if (addr & 0x10) { |
1565 | b7169916 | aurel32 | /* EXDE / IFEDE / IEEDE */
|
1566 | b7169916 | aurel32 | retval = read_IRQreg(mpp, idx, IRQ_IDE); |
1567 | b7169916 | aurel32 | } else {
|
1568 | b7169916 | aurel32 | /* EXVP / IFEVP / IEEVP */
|
1569 | b7169916 | aurel32 | retval = read_IRQreg(mpp, idx, IRQ_IPVP); |
1570 | b7169916 | aurel32 | } |
1571 | b7169916 | aurel32 | DPRINTF("%s: => %08x\n", __func__, retval);
|
1572 | b7169916 | aurel32 | } |
1573 | b7169916 | aurel32 | |
1574 | b7169916 | aurel32 | return retval;
|
1575 | b7169916 | aurel32 | } |
1576 | b7169916 | aurel32 | |
1577 | d60efc6b | Blue Swirl | static CPUWriteMemoryFunc * const mpic_glb_write[] = { |
1578 | b7169916 | aurel32 | &openpic_buggy_write, |
1579 | b7169916 | aurel32 | &openpic_buggy_write, |
1580 | b7169916 | aurel32 | &openpic_gbl_write, |
1581 | b7169916 | aurel32 | }; |
1582 | b7169916 | aurel32 | |
1583 | d60efc6b | Blue Swirl | static CPUReadMemoryFunc * const mpic_glb_read[] = { |
1584 | b7169916 | aurel32 | &openpic_buggy_read, |
1585 | b7169916 | aurel32 | &openpic_buggy_read, |
1586 | b7169916 | aurel32 | &openpic_gbl_read, |
1587 | b7169916 | aurel32 | }; |
1588 | b7169916 | aurel32 | |
1589 | d60efc6b | Blue Swirl | static CPUWriteMemoryFunc * const mpic_tmr_write[] = { |
1590 | b7169916 | aurel32 | &openpic_buggy_write, |
1591 | b7169916 | aurel32 | &openpic_buggy_write, |
1592 | b7169916 | aurel32 | &mpic_timer_write, |
1593 | b7169916 | aurel32 | }; |
1594 | b7169916 | aurel32 | |
1595 | d60efc6b | Blue Swirl | static CPUReadMemoryFunc * const mpic_tmr_read[] = { |
1596 | b7169916 | aurel32 | &openpic_buggy_read, |
1597 | b7169916 | aurel32 | &openpic_buggy_read, |
1598 | b7169916 | aurel32 | &mpic_timer_read, |
1599 | b7169916 | aurel32 | }; |
1600 | b7169916 | aurel32 | |
1601 | d60efc6b | Blue Swirl | static CPUWriteMemoryFunc * const mpic_cpu_write[] = { |
1602 | b7169916 | aurel32 | &openpic_buggy_write, |
1603 | b7169916 | aurel32 | &openpic_buggy_write, |
1604 | b7169916 | aurel32 | &openpic_cpu_write, |
1605 | b7169916 | aurel32 | }; |
1606 | b7169916 | aurel32 | |
1607 | d60efc6b | Blue Swirl | static CPUReadMemoryFunc * const mpic_cpu_read[] = { |
1608 | b7169916 | aurel32 | &openpic_buggy_read, |
1609 | b7169916 | aurel32 | &openpic_buggy_read, |
1610 | b7169916 | aurel32 | &openpic_cpu_read, |
1611 | b7169916 | aurel32 | }; |
1612 | b7169916 | aurel32 | |
1613 | d60efc6b | Blue Swirl | static CPUWriteMemoryFunc * const mpic_ext_write[] = { |
1614 | b7169916 | aurel32 | &openpic_buggy_write, |
1615 | b7169916 | aurel32 | &openpic_buggy_write, |
1616 | b7169916 | aurel32 | &mpic_src_ext_write, |
1617 | b7169916 | aurel32 | }; |
1618 | b7169916 | aurel32 | |
1619 | d60efc6b | Blue Swirl | static CPUReadMemoryFunc * const mpic_ext_read[] = { |
1620 | b7169916 | aurel32 | &openpic_buggy_read, |
1621 | b7169916 | aurel32 | &openpic_buggy_read, |
1622 | b7169916 | aurel32 | &mpic_src_ext_read, |
1623 | b7169916 | aurel32 | }; |
1624 | b7169916 | aurel32 | |
1625 | d60efc6b | Blue Swirl | static CPUWriteMemoryFunc * const mpic_int_write[] = { |
1626 | b7169916 | aurel32 | &openpic_buggy_write, |
1627 | b7169916 | aurel32 | &openpic_buggy_write, |
1628 | b7169916 | aurel32 | &mpic_src_int_write, |
1629 | b7169916 | aurel32 | }; |
1630 | b7169916 | aurel32 | |
1631 | d60efc6b | Blue Swirl | static CPUReadMemoryFunc * const mpic_int_read[] = { |
1632 | b7169916 | aurel32 | &openpic_buggy_read, |
1633 | b7169916 | aurel32 | &openpic_buggy_read, |
1634 | b7169916 | aurel32 | &mpic_src_int_read, |
1635 | b7169916 | aurel32 | }; |
1636 | b7169916 | aurel32 | |
1637 | d60efc6b | Blue Swirl | static CPUWriteMemoryFunc * const mpic_msg_write[] = { |
1638 | b7169916 | aurel32 | &openpic_buggy_write, |
1639 | b7169916 | aurel32 | &openpic_buggy_write, |
1640 | b7169916 | aurel32 | &mpic_src_msg_write, |
1641 | b7169916 | aurel32 | }; |
1642 | b7169916 | aurel32 | |
1643 | d60efc6b | Blue Swirl | static CPUReadMemoryFunc * const mpic_msg_read[] = { |
1644 | b7169916 | aurel32 | &openpic_buggy_read, |
1645 | b7169916 | aurel32 | &openpic_buggy_read, |
1646 | b7169916 | aurel32 | &mpic_src_msg_read, |
1647 | b7169916 | aurel32 | }; |
1648 | d60efc6b | Blue Swirl | static CPUWriteMemoryFunc * const mpic_msi_write[] = { |
1649 | b7169916 | aurel32 | &openpic_buggy_write, |
1650 | b7169916 | aurel32 | &openpic_buggy_write, |
1651 | b7169916 | aurel32 | &mpic_src_msi_write, |
1652 | b7169916 | aurel32 | }; |
1653 | b7169916 | aurel32 | |
1654 | d60efc6b | Blue Swirl | static CPUReadMemoryFunc * const mpic_msi_read[] = { |
1655 | b7169916 | aurel32 | &openpic_buggy_read, |
1656 | b7169916 | aurel32 | &openpic_buggy_read, |
1657 | b7169916 | aurel32 | &mpic_src_msi_read, |
1658 | b7169916 | aurel32 | }; |
1659 | b7169916 | aurel32 | |
1660 | b7169916 | aurel32 | qemu_irq *mpic_init (target_phys_addr_t base, int nb_cpus,
|
1661 | b7169916 | aurel32 | qemu_irq **irqs, qemu_irq irq_out) |
1662 | b7169916 | aurel32 | { |
1663 | b7169916 | aurel32 | openpic_t *mpp; |
1664 | b7169916 | aurel32 | int i;
|
1665 | b7169916 | aurel32 | struct {
|
1666 | d60efc6b | Blue Swirl | CPUReadMemoryFunc * const *read;
|
1667 | d60efc6b | Blue Swirl | CPUWriteMemoryFunc * const *write;
|
1668 | b7169916 | aurel32 | target_phys_addr_t start_addr; |
1669 | b7169916 | aurel32 | ram_addr_t size; |
1670 | dfebf62b | aurel32 | } const list[] = {
|
1671 | b7169916 | aurel32 | {mpic_glb_read, mpic_glb_write, MPIC_GLB_REG_START, MPIC_GLB_REG_SIZE}, |
1672 | b7169916 | aurel32 | {mpic_tmr_read, mpic_tmr_write, MPIC_TMR_REG_START, MPIC_TMR_REG_SIZE}, |
1673 | b7169916 | aurel32 | {mpic_ext_read, mpic_ext_write, MPIC_EXT_REG_START, MPIC_EXT_REG_SIZE}, |
1674 | b7169916 | aurel32 | {mpic_int_read, mpic_int_write, MPIC_INT_REG_START, MPIC_INT_REG_SIZE}, |
1675 | b7169916 | aurel32 | {mpic_msg_read, mpic_msg_write, MPIC_MSG_REG_START, MPIC_MSG_REG_SIZE}, |
1676 | b7169916 | aurel32 | {mpic_msi_read, mpic_msi_write, MPIC_MSI_REG_START, MPIC_MSI_REG_SIZE}, |
1677 | b7169916 | aurel32 | {mpic_cpu_read, mpic_cpu_write, MPIC_CPU_REG_START, MPIC_CPU_REG_SIZE}, |
1678 | b7169916 | aurel32 | }; |
1679 | b7169916 | aurel32 | |
1680 | b7169916 | aurel32 | /* XXX: for now, only one CPU is supported */
|
1681 | b7169916 | aurel32 | if (nb_cpus != 1) |
1682 | b7169916 | aurel32 | return NULL; |
1683 | b7169916 | aurel32 | |
1684 | b7169916 | aurel32 | mpp = qemu_mallocz(sizeof(openpic_t));
|
1685 | b7169916 | aurel32 | |
1686 | b7169916 | aurel32 | for (i = 0; i < sizeof(list)/sizeof(list[0]); i++) { |
1687 | b7169916 | aurel32 | int mem_index;
|
1688 | b7169916 | aurel32 | |
1689 | 1eed09cb | Avi Kivity | mem_index = cpu_register_io_memory(list[i].read, list[i].write, mpp); |
1690 | b7169916 | aurel32 | if (mem_index < 0) { |
1691 | b7169916 | aurel32 | goto free;
|
1692 | b7169916 | aurel32 | } |
1693 | b7169916 | aurel32 | cpu_register_physical_memory(base + list[i].start_addr, |
1694 | b7169916 | aurel32 | list[i].size, mem_index); |
1695 | b7169916 | aurel32 | } |
1696 | b7169916 | aurel32 | |
1697 | b7169916 | aurel32 | mpp->nb_cpus = nb_cpus; |
1698 | b7169916 | aurel32 | mpp->max_irq = MPIC_MAX_IRQ; |
1699 | b7169916 | aurel32 | mpp->irq_ipi0 = MPIC_IPI_IRQ; |
1700 | b7169916 | aurel32 | mpp->irq_tim0 = MPIC_TMR_IRQ; |
1701 | b7169916 | aurel32 | |
1702 | b7169916 | aurel32 | for (i = 0; i < nb_cpus; i++) |
1703 | b7169916 | aurel32 | mpp->dst[i].irqs = irqs[i]; |
1704 | b7169916 | aurel32 | mpp->irq_out = irq_out; |
1705 | b7169916 | aurel32 | mpp->need_swap = 0; /* MPIC has the same endian as target */ |
1706 | b7169916 | aurel32 | |
1707 | b7169916 | aurel32 | mpp->irq_raise = mpic_irq_raise; |
1708 | b7169916 | aurel32 | mpp->reset = mpic_reset; |
1709 | b7169916 | aurel32 | |
1710 | b7169916 | aurel32 | register_savevm("mpic", 0, 2, openpic_save, openpic_load, mpp); |
1711 | a08d4367 | Jan Kiszka | qemu_register_reset(mpic_reset, mpp); |
1712 | b7169916 | aurel32 | mpp->reset(mpp); |
1713 | b7169916 | aurel32 | |
1714 | b7169916 | aurel32 | return qemu_allocate_irqs(openpic_set_irq, mpp, mpp->max_irq);
|
1715 | b7169916 | aurel32 | |
1716 | b7169916 | aurel32 | free:
|
1717 | b7169916 | aurel32 | qemu_free(mpp); |
1718 | b7169916 | aurel32 | return NULL; |
1719 | dbda808a | bellard | } |