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1
/*
2
 *  PowerPC emulation for qemu: main translation routines.
3
 *
4
 *  Copyright (c) 2003-2007 Jocelyn Mayer
5
 *
6
 * This library is free software; you can redistribute it and/or
7
 * modify it under the terms of the GNU Lesser General Public
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 * License as published by the Free Software Foundation; either
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 * version 2 of the License, or (at your option) any later version.
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 *
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 * This library is distributed in the hope that it will be useful,
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 * but WITHOUT ANY WARRANTY; without even the implied warranty of
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 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
14
 * Lesser General Public License for more details.
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 *
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 * You should have received a copy of the GNU Lesser General Public
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 * License along with this library; if not, write to the Free Software
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 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
19
 */
20
#include <stdarg.h>
21
#include <stdlib.h>
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#include <stdio.h>
23
#include <string.h>
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#include <inttypes.h>
25

    
26
#include "cpu.h"
27
#include "exec-all.h"
28
#include "disas.h"
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#include "helper.h"
30
#include "tcg-op.h"
31
#include "qemu-common.h"
32

    
33
#define CPU_SINGLE_STEP 0x1
34
#define CPU_BRANCH_STEP 0x2
35
#define GDBSTUB_SINGLE_STEP 0x4
36

    
37
/* Include definitions for instructions classes and implementations flags */
38
//#define DO_SINGLE_STEP
39
//#define PPC_DEBUG_DISAS
40
//#define DEBUG_MEMORY_ACCESSES
41
//#define DO_PPC_STATISTICS
42
//#define OPTIMIZE_FPRF_UPDATE
43

    
44
/*****************************************************************************/
45
/* Code translation helpers                                                  */
46

    
47
static TCGv cpu_env, cpu_T[3];
48

    
49
#include "gen-icount.h"
50

    
51
void ppc_translate_init(void)
52
{
53
    static int done_init = 0;
54
    if (done_init)
55
        return;
56
    cpu_env = tcg_global_reg_new(TCG_TYPE_PTR, TCG_AREG0, "env");
57
#if TARGET_LONG_BITS > HOST_LONG_BITS
58
    cpu_T[0] = tcg_global_mem_new(TCG_TYPE_TL,
59
                                  TCG_AREG0, offsetof(CPUState, t0), "T0");
60
    cpu_T[1] = tcg_global_mem_new(TCG_TYPE_TL,
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                                  TCG_AREG0, offsetof(CPUState, t1), "T1");
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    cpu_T[2] = tcg_global_mem_new(TCG_TYPE_TL,
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                                  TCG_AREG0, offsetof(CPUState, t2), "T2");
64
#else
65
    cpu_T[0] = tcg_global_reg_new(TCG_TYPE_TL, TCG_AREG1, "T0");
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    cpu_T[1] = tcg_global_reg_new(TCG_TYPE_TL, TCG_AREG2, "T1");
67
    cpu_T[2] = tcg_global_reg_new(TCG_TYPE_TL, TCG_AREG3, "T2");
68
#endif
69

    
70
    /* register helpers */
71
#undef DEF_HELPER
72
#define DEF_HELPER(ret, name, params) tcg_register_helper(name, #name);
73
#include "helper.h"
74

    
75
    done_init = 1;
76
}
77

    
78
#if defined(OPTIMIZE_FPRF_UPDATE)
79
static uint16_t *gen_fprf_buf[OPC_BUF_SIZE];
80
static uint16_t **gen_fprf_ptr;
81
#endif
82

    
83
#define GEN8(func, NAME)                                                      \
84
static GenOpFunc *NAME ## _table [8] = {                                      \
85
NAME ## 0, NAME ## 1, NAME ## 2, NAME ## 3,                                   \
86
NAME ## 4, NAME ## 5, NAME ## 6, NAME ## 7,                                   \
87
};                                                                            \
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static always_inline void func (int n)                                        \
89
{                                                                             \
90
    NAME ## _table[n]();                                                      \
91
}
92

    
93
#define GEN16(func, NAME)                                                     \
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static GenOpFunc *NAME ## _table [16] = {                                     \
95
NAME ## 0, NAME ## 1, NAME ## 2, NAME ## 3,                                   \
96
NAME ## 4, NAME ## 5, NAME ## 6, NAME ## 7,                                   \
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NAME ## 8, NAME ## 9, NAME ## 10, NAME ## 11,                                 \
98
NAME ## 12, NAME ## 13, NAME ## 14, NAME ## 15,                               \
99
};                                                                            \
100
static always_inline void func (int n)                                        \
101
{                                                                             \
102
    NAME ## _table[n]();                                                      \
103
}
104

    
105
#define GEN32(func, NAME)                                                     \
106
static GenOpFunc *NAME ## _table [32] = {                                     \
107
NAME ## 0, NAME ## 1, NAME ## 2, NAME ## 3,                                   \
108
NAME ## 4, NAME ## 5, NAME ## 6, NAME ## 7,                                   \
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NAME ## 8, NAME ## 9, NAME ## 10, NAME ## 11,                                 \
110
NAME ## 12, NAME ## 13, NAME ## 14, NAME ## 15,                               \
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NAME ## 16, NAME ## 17, NAME ## 18, NAME ## 19,                               \
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NAME ## 20, NAME ## 21, NAME ## 22, NAME ## 23,                               \
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NAME ## 24, NAME ## 25, NAME ## 26, NAME ## 27,                               \
114
NAME ## 28, NAME ## 29, NAME ## 30, NAME ## 31,                               \
115
};                                                                            \
116
static always_inline void func (int n)                                        \
117
{                                                                             \
118
    NAME ## _table[n]();                                                      \
119
}
120

    
121
/* Condition register moves */
122
GEN8(gen_op_load_crf_T0, gen_op_load_crf_T0_crf);
123
GEN8(gen_op_load_crf_T1, gen_op_load_crf_T1_crf);
124
GEN8(gen_op_store_T0_crf, gen_op_store_T0_crf_crf);
125
#if 0 // Unused
126
GEN8(gen_op_store_T1_crf, gen_op_store_T1_crf_crf);
127
#endif
128

    
129
/* General purpose registers moves */
130
GEN32(gen_op_load_gpr_T0, gen_op_load_gpr_T0_gpr);
131
GEN32(gen_op_load_gpr_T1, gen_op_load_gpr_T1_gpr);
132
GEN32(gen_op_load_gpr_T2, gen_op_load_gpr_T2_gpr);
133

    
134
GEN32(gen_op_store_T0_gpr, gen_op_store_T0_gpr_gpr);
135
GEN32(gen_op_store_T1_gpr, gen_op_store_T1_gpr_gpr);
136
#if 0 // unused
137
GEN32(gen_op_store_T2_gpr, gen_op_store_T2_gpr_gpr);
138
#endif
139

    
140
/* floating point registers moves */
141
GEN32(gen_op_load_fpr_FT0, gen_op_load_fpr_FT0_fpr);
142
GEN32(gen_op_load_fpr_FT1, gen_op_load_fpr_FT1_fpr);
143
GEN32(gen_op_load_fpr_FT2, gen_op_load_fpr_FT2_fpr);
144
GEN32(gen_op_store_FT0_fpr, gen_op_store_FT0_fpr_fpr);
145
GEN32(gen_op_store_FT1_fpr, gen_op_store_FT1_fpr_fpr);
146
#if 0 // unused
147
GEN32(gen_op_store_FT2_fpr, gen_op_store_FT2_fpr_fpr);
148
#endif
149

    
150
/* internal defines */
151
typedef struct DisasContext {
152
    struct TranslationBlock *tb;
153
    target_ulong nip;
154
    uint32_t opcode;
155
    uint32_t exception;
156
    /* Routine used to access memory */
157
    int mem_idx;
158
    /* Translation flags */
159
#if !defined(CONFIG_USER_ONLY)
160
    int supervisor;
161
#endif
162
#if defined(TARGET_PPC64)
163
    int sf_mode;
164
#endif
165
    int fpu_enabled;
166
    int altivec_enabled;
167
    int spe_enabled;
168
    ppc_spr_t *spr_cb; /* Needed to check rights for mfspr/mtspr */
169
    int singlestep_enabled;
170
    int dcache_line_size;
171
} DisasContext;
172

    
173
struct opc_handler_t {
174
    /* invalid bits */
175
    uint32_t inval;
176
    /* instruction type */
177
    uint64_t type;
178
    /* handler */
179
    void (*handler)(DisasContext *ctx);
180
#if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
181
    const unsigned char *oname;
182
#endif
183
#if defined(DO_PPC_STATISTICS)
184
    uint64_t count;
185
#endif
186
};
187

    
188
static always_inline void gen_set_Rc0 (DisasContext *ctx)
189
{
190
#if defined(TARGET_PPC64)
191
    if (ctx->sf_mode)
192
        gen_op_cmpi_64(0);
193
    else
194
#endif
195
        gen_op_cmpi(0);
196
    gen_op_set_Rc0();
197
}
198

    
199
static always_inline void gen_reset_fpstatus (void)
200
{
201
#ifdef CONFIG_SOFTFLOAT
202
    gen_op_reset_fpstatus();
203
#endif
204
}
205

    
206
static always_inline void gen_compute_fprf (int set_fprf, int set_rc)
207
{
208
    if (set_fprf != 0) {
209
        /* This case might be optimized later */
210
#if defined(OPTIMIZE_FPRF_UPDATE)
211
        *gen_fprf_ptr++ = gen_opc_ptr;
212
#endif
213
        gen_op_compute_fprf(1);
214
        if (unlikely(set_rc))
215
            gen_op_store_T0_crf(1);
216
        gen_op_float_check_status();
217
    } else if (unlikely(set_rc)) {
218
        /* We always need to compute fpcc */
219
        gen_op_compute_fprf(0);
220
        gen_op_store_T0_crf(1);
221
        if (set_fprf)
222
            gen_op_float_check_status();
223
    }
224
}
225

    
226
static always_inline void gen_optimize_fprf (void)
227
{
228
#if defined(OPTIMIZE_FPRF_UPDATE)
229
    uint16_t **ptr;
230

    
231
    for (ptr = gen_fprf_buf; ptr != (gen_fprf_ptr - 1); ptr++)
232
        *ptr = INDEX_op_nop1;
233
    gen_fprf_ptr = gen_fprf_buf;
234
#endif
235
}
236

    
237
static always_inline void gen_update_nip (DisasContext *ctx, target_ulong nip)
238
{
239
#if defined(TARGET_PPC64)
240
    if (ctx->sf_mode)
241
        gen_op_update_nip_64(nip >> 32, nip);
242
    else
243
#endif
244
        gen_op_update_nip(nip);
245
}
246

    
247
#define GEN_EXCP(ctx, excp, error)                                            \
248
do {                                                                          \
249
    if ((ctx)->exception == POWERPC_EXCP_NONE) {                              \
250
        gen_update_nip(ctx, (ctx)->nip);                                      \
251
    }                                                                         \
252
    gen_op_raise_exception_err((excp), (error));                              \
253
    ctx->exception = (excp);                                                  \
254
} while (0)
255

    
256
#define GEN_EXCP_INVAL(ctx)                                                   \
257
GEN_EXCP((ctx), POWERPC_EXCP_PROGRAM,                                         \
258
         POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_INVAL)
259

    
260
#define GEN_EXCP_PRIVOPC(ctx)                                                 \
261
GEN_EXCP((ctx), POWERPC_EXCP_PROGRAM,                                         \
262
         POWERPC_EXCP_INVAL | POWERPC_EXCP_PRIV_OPC)
263

    
264
#define GEN_EXCP_PRIVREG(ctx)                                                 \
265
GEN_EXCP((ctx), POWERPC_EXCP_PROGRAM,                                         \
266
         POWERPC_EXCP_INVAL | POWERPC_EXCP_PRIV_REG)
267

    
268
#define GEN_EXCP_NO_FP(ctx)                                                   \
269
GEN_EXCP(ctx, POWERPC_EXCP_FPU, 0)
270

    
271
#define GEN_EXCP_NO_AP(ctx)                                                   \
272
GEN_EXCP(ctx, POWERPC_EXCP_APU, 0)
273

    
274
#define GEN_EXCP_NO_VR(ctx)                                                   \
275
GEN_EXCP(ctx, POWERPC_EXCP_VPU, 0)
276

    
277
/* Stop translation */
278
static always_inline void GEN_STOP (DisasContext *ctx)
279
{
280
    gen_update_nip(ctx, ctx->nip);
281
    ctx->exception = POWERPC_EXCP_STOP;
282
}
283

    
284
/* No need to update nip here, as execution flow will change */
285
static always_inline void GEN_SYNC (DisasContext *ctx)
286
{
287
    ctx->exception = POWERPC_EXCP_SYNC;
288
}
289

    
290
#define GEN_HANDLER(name, opc1, opc2, opc3, inval, type)                      \
291
static void gen_##name (DisasContext *ctx);                                   \
292
GEN_OPCODE(name, opc1, opc2, opc3, inval, type);                              \
293
static void gen_##name (DisasContext *ctx)
294

    
295
#define GEN_HANDLER2(name, onam, opc1, opc2, opc3, inval, type)               \
296
static void gen_##name (DisasContext *ctx);                                   \
297
GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type);                       \
298
static void gen_##name (DisasContext *ctx)
299

    
300
typedef struct opcode_t {
301
    unsigned char opc1, opc2, opc3;
302
#if HOST_LONG_BITS == 64 /* Explicitly align to 64 bits */
303
    unsigned char pad[5];
304
#else
305
    unsigned char pad[1];
306
#endif
307
    opc_handler_t handler;
308
    const unsigned char *oname;
309
} opcode_t;
310

    
311
/*****************************************************************************/
312
/***                           Instruction decoding                        ***/
313
#define EXTRACT_HELPER(name, shift, nb)                                       \
314
static always_inline uint32_t name (uint32_t opcode)                          \
315
{                                                                             \
316
    return (opcode >> (shift)) & ((1 << (nb)) - 1);                           \
317
}
318

    
319
#define EXTRACT_SHELPER(name, shift, nb)                                      \
320
static always_inline int32_t name (uint32_t opcode)                           \
321
{                                                                             \
322
    return (int16_t)((opcode >> (shift)) & ((1 << (nb)) - 1));                \
323
}
324

    
325
/* Opcode part 1 */
326
EXTRACT_HELPER(opc1, 26, 6);
327
/* Opcode part 2 */
328
EXTRACT_HELPER(opc2, 1, 5);
329
/* Opcode part 3 */
330
EXTRACT_HELPER(opc3, 6, 5);
331
/* Update Cr0 flags */
332
EXTRACT_HELPER(Rc, 0, 1);
333
/* Destination */
334
EXTRACT_HELPER(rD, 21, 5);
335
/* Source */
336
EXTRACT_HELPER(rS, 21, 5);
337
/* First operand */
338
EXTRACT_HELPER(rA, 16, 5);
339
/* Second operand */
340
EXTRACT_HELPER(rB, 11, 5);
341
/* Third operand */
342
EXTRACT_HELPER(rC, 6, 5);
343
/***                               Get CRn                                 ***/
344
EXTRACT_HELPER(crfD, 23, 3);
345
EXTRACT_HELPER(crfS, 18, 3);
346
EXTRACT_HELPER(crbD, 21, 5);
347
EXTRACT_HELPER(crbA, 16, 5);
348
EXTRACT_HELPER(crbB, 11, 5);
349
/* SPR / TBL */
350
EXTRACT_HELPER(_SPR, 11, 10);
351
static always_inline uint32_t SPR (uint32_t opcode)
352
{
353
    uint32_t sprn = _SPR(opcode);
354

    
355
    return ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5);
356
}
357
/***                              Get constants                            ***/
358
EXTRACT_HELPER(IMM, 12, 8);
359
/* 16 bits signed immediate value */
360
EXTRACT_SHELPER(SIMM, 0, 16);
361
/* 16 bits unsigned immediate value */
362
EXTRACT_HELPER(UIMM, 0, 16);
363
/* Bit count */
364
EXTRACT_HELPER(NB, 11, 5);
365
/* Shift count */
366
EXTRACT_HELPER(SH, 11, 5);
367
/* Mask start */
368
EXTRACT_HELPER(MB, 6, 5);
369
/* Mask end */
370
EXTRACT_HELPER(ME, 1, 5);
371
/* Trap operand */
372
EXTRACT_HELPER(TO, 21, 5);
373

    
374
EXTRACT_HELPER(CRM, 12, 8);
375
EXTRACT_HELPER(FM, 17, 8);
376
EXTRACT_HELPER(SR, 16, 4);
377
EXTRACT_HELPER(FPIMM, 12, 4);
378

    
379
/***                            Jump target decoding                       ***/
380
/* Displacement */
381
EXTRACT_SHELPER(d, 0, 16);
382
/* Immediate address */
383
static always_inline target_ulong LI (uint32_t opcode)
384
{
385
    return (opcode >> 0) & 0x03FFFFFC;
386
}
387

    
388
static always_inline uint32_t BD (uint32_t opcode)
389
{
390
    return (opcode >> 0) & 0xFFFC;
391
}
392

    
393
EXTRACT_HELPER(BO, 21, 5);
394
EXTRACT_HELPER(BI, 16, 5);
395
/* Absolute/relative address */
396
EXTRACT_HELPER(AA, 1, 1);
397
/* Link */
398
EXTRACT_HELPER(LK, 0, 1);
399

    
400
/* Create a mask between <start> and <end> bits */
401
static always_inline target_ulong MASK (uint32_t start, uint32_t end)
402
{
403
    target_ulong ret;
404

    
405
#if defined(TARGET_PPC64)
406
    if (likely(start == 0)) {
407
        ret = UINT64_MAX << (63 - end);
408
    } else if (likely(end == 63)) {
409
        ret = UINT64_MAX >> start;
410
    }
411
#else
412
    if (likely(start == 0)) {
413
        ret = UINT32_MAX << (31  - end);
414
    } else if (likely(end == 31)) {
415
        ret = UINT32_MAX >> start;
416
    }
417
#endif
418
    else {
419
        ret = (((target_ulong)(-1ULL)) >> (start)) ^
420
            (((target_ulong)(-1ULL) >> (end)) >> 1);
421
        if (unlikely(start > end))
422
            return ~ret;
423
    }
424

    
425
    return ret;
426
}
427

    
428
/*****************************************************************************/
429
/* PowerPC Instructions types definitions                                    */
430
enum {
431
    PPC_NONE           = 0x0000000000000000ULL,
432
    /* PowerPC base instructions set                                         */
433
    PPC_INSNS_BASE     = 0x0000000000000001ULL,
434
    /*   integer operations instructions                                     */
435
#define PPC_INTEGER PPC_INSNS_BASE
436
    /*   flow control instructions                                           */
437
#define PPC_FLOW    PPC_INSNS_BASE
438
    /*   virtual memory instructions                                         */
439
#define PPC_MEM     PPC_INSNS_BASE
440
    /*   ld/st with reservation instructions                                 */
441
#define PPC_RES     PPC_INSNS_BASE
442
    /*   spr/msr access instructions                                         */
443
#define PPC_MISC    PPC_INSNS_BASE
444
    /* Deprecated instruction sets                                           */
445
    /*   Original POWER instruction set                                      */
446
    PPC_POWER          = 0x0000000000000002ULL,
447
    /*   POWER2 instruction set extension                                    */
448
    PPC_POWER2         = 0x0000000000000004ULL,
449
    /*   Power RTC support                                                   */
450
    PPC_POWER_RTC      = 0x0000000000000008ULL,
451
    /*   Power-to-PowerPC bridge (601)                                       */
452
    PPC_POWER_BR       = 0x0000000000000010ULL,
453
    /* 64 bits PowerPC instruction set                                       */
454
    PPC_64B            = 0x0000000000000020ULL,
455
    /*   New 64 bits extensions (PowerPC 2.0x)                               */
456
    PPC_64BX           = 0x0000000000000040ULL,
457
    /*   64 bits hypervisor extensions                                       */
458
    PPC_64H            = 0x0000000000000080ULL,
459
    /*   New wait instruction (PowerPC 2.0x)                                 */
460
    PPC_WAIT           = 0x0000000000000100ULL,
461
    /*   Time base mftb instruction                                          */
462
    PPC_MFTB           = 0x0000000000000200ULL,
463

    
464
    /* Fixed-point unit extensions                                           */
465
    /*   PowerPC 602 specific                                                */
466
    PPC_602_SPEC       = 0x0000000000000400ULL,
467
    /*   isel instruction                                                    */
468
    PPC_ISEL           = 0x0000000000000800ULL,
469
    /*   popcntb instruction                                                 */
470
    PPC_POPCNTB        = 0x0000000000001000ULL,
471
    /*   string load / store                                                 */
472
    PPC_STRING         = 0x0000000000002000ULL,
473

    
474
    /* Floating-point unit extensions                                        */
475
    /*   Optional floating point instructions                                */
476
    PPC_FLOAT          = 0x0000000000010000ULL,
477
    /* New floating-point extensions (PowerPC 2.0x)                          */
478
    PPC_FLOAT_EXT      = 0x0000000000020000ULL,
479
    PPC_FLOAT_FSQRT    = 0x0000000000040000ULL,
480
    PPC_FLOAT_FRES     = 0x0000000000080000ULL,
481
    PPC_FLOAT_FRSQRTE  = 0x0000000000100000ULL,
482
    PPC_FLOAT_FRSQRTES = 0x0000000000200000ULL,
483
    PPC_FLOAT_FSEL     = 0x0000000000400000ULL,
484
    PPC_FLOAT_STFIWX   = 0x0000000000800000ULL,
485

    
486
    /* Vector/SIMD extensions                                                */
487
    /*   Altivec support                                                     */
488
    PPC_ALTIVEC        = 0x0000000001000000ULL,
489
    /*   PowerPC 2.03 SPE extension                                          */
490
    PPC_SPE            = 0x0000000002000000ULL,
491
    /*   PowerPC 2.03 SPE floating-point extension                           */
492
    PPC_SPEFPU         = 0x0000000004000000ULL,
493

    
494
    /* Optional memory control instructions                                  */
495
    PPC_MEM_TLBIA      = 0x0000000010000000ULL,
496
    PPC_MEM_TLBIE      = 0x0000000020000000ULL,
497
    PPC_MEM_TLBSYNC    = 0x0000000040000000ULL,
498
    /*   sync instruction                                                    */
499
    PPC_MEM_SYNC       = 0x0000000080000000ULL,
500
    /*   eieio instruction                                                   */
501
    PPC_MEM_EIEIO      = 0x0000000100000000ULL,
502

    
503
    /* Cache control instructions                                            */
504
    PPC_CACHE          = 0x0000000200000000ULL,
505
    /*   icbi instruction                                                    */
506
    PPC_CACHE_ICBI     = 0x0000000400000000ULL,
507
    /*   dcbz instruction with fixed cache line size                         */
508
    PPC_CACHE_DCBZ     = 0x0000000800000000ULL,
509
    /*   dcbz instruction with tunable cache line size                       */
510
    PPC_CACHE_DCBZT    = 0x0000001000000000ULL,
511
    /*   dcba instruction                                                    */
512
    PPC_CACHE_DCBA     = 0x0000002000000000ULL,
513
    /*   Freescale cache locking instructions                                */
514
    PPC_CACHE_LOCK     = 0x0000004000000000ULL,
515

    
516
    /* MMU related extensions                                                */
517
    /*   external control instructions                                       */
518
    PPC_EXTERN         = 0x0000010000000000ULL,
519
    /*   segment register access instructions                                */
520
    PPC_SEGMENT        = 0x0000020000000000ULL,
521
    /*   PowerPC 6xx TLB management instructions                             */
522
    PPC_6xx_TLB        = 0x0000040000000000ULL,
523
    /* PowerPC 74xx TLB management instructions                              */
524
    PPC_74xx_TLB       = 0x0000080000000000ULL,
525
    /*   PowerPC 40x TLB management instructions                             */
526
    PPC_40x_TLB        = 0x0000100000000000ULL,
527
    /*   segment register access instructions for PowerPC 64 "bridge"        */
528
    PPC_SEGMENT_64B    = 0x0000200000000000ULL,
529
    /*   SLB management                                                      */
530
    PPC_SLBI           = 0x0000400000000000ULL,
531

    
532
    /* Embedded PowerPC dedicated instructions                               */
533
    PPC_WRTEE          = 0x0001000000000000ULL,
534
    /* PowerPC 40x exception model                                           */
535
    PPC_40x_EXCP       = 0x0002000000000000ULL,
536
    /* PowerPC 405 Mac instructions                                          */
537
    PPC_405_MAC        = 0x0004000000000000ULL,
538
    /* PowerPC 440 specific instructions                                     */
539
    PPC_440_SPEC       = 0x0008000000000000ULL,
540
    /* BookE (embedded) PowerPC specification                                */
541
    PPC_BOOKE          = 0x0010000000000000ULL,
542
    /* mfapidi instruction                                                   */
543
    PPC_MFAPIDI        = 0x0020000000000000ULL,
544
    /* tlbiva instruction                                                    */
545
    PPC_TLBIVA         = 0x0040000000000000ULL,
546
    /* tlbivax instruction                                                   */
547
    PPC_TLBIVAX        = 0x0080000000000000ULL,
548
    /* PowerPC 4xx dedicated instructions                                    */
549
    PPC_4xx_COMMON     = 0x0100000000000000ULL,
550
    /* PowerPC 40x ibct instructions                                         */
551
    PPC_40x_ICBT       = 0x0200000000000000ULL,
552
    /* rfmci is not implemented in all BookE PowerPC                         */
553
    PPC_RFMCI          = 0x0400000000000000ULL,
554
    /* rfdi instruction                                                      */
555
    PPC_RFDI           = 0x0800000000000000ULL,
556
    /* DCR accesses                                                          */
557
    PPC_DCR            = 0x1000000000000000ULL,
558
    /* DCR extended accesse                                                  */
559
    PPC_DCRX           = 0x2000000000000000ULL,
560
    /* user-mode DCR access, implemented in PowerPC 460                      */
561
    PPC_DCRUX          = 0x4000000000000000ULL,
562
};
563

    
564
/*****************************************************************************/
565
/* PowerPC instructions table                                                */
566
#if HOST_LONG_BITS == 64
567
#define OPC_ALIGN 8
568
#else
569
#define OPC_ALIGN 4
570
#endif
571
#if defined(__APPLE__)
572
#define OPCODES_SECTION                                                       \
573
    __attribute__ ((section("__TEXT,__opcodes"), unused, aligned (OPC_ALIGN) ))
574
#else
575
#define OPCODES_SECTION                                                       \
576
    __attribute__ ((section(".opcodes"), unused, aligned (OPC_ALIGN) ))
577
#endif
578

    
579
#if defined(DO_PPC_STATISTICS)
580
#define GEN_OPCODE(name, op1, op2, op3, invl, _typ)                           \
581
OPCODES_SECTION opcode_t opc_##name = {                                       \
582
    .opc1 = op1,                                                              \
583
    .opc2 = op2,                                                              \
584
    .opc3 = op3,                                                              \
585
    .pad  = { 0, },                                                           \
586
    .handler = {                                                              \
587
        .inval   = invl,                                                      \
588
        .type = _typ,                                                         \
589
        .handler = &gen_##name,                                               \
590
        .oname = stringify(name),                                             \
591
    },                                                                        \
592
    .oname = stringify(name),                                                 \
593
}
594
#define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ)                    \
595
OPCODES_SECTION opcode_t opc_##name = {                                       \
596
    .opc1 = op1,                                                              \
597
    .opc2 = op2,                                                              \
598
    .opc3 = op3,                                                              \
599
    .pad  = { 0, },                                                           \
600
    .handler = {                                                              \
601
        .inval   = invl,                                                      \
602
        .type = _typ,                                                         \
603
        .handler = &gen_##name,                                               \
604
        .oname = onam,                                                        \
605
    },                                                                        \
606
    .oname = onam,                                                            \
607
}
608
#else
609
#define GEN_OPCODE(name, op1, op2, op3, invl, _typ)                           \
610
OPCODES_SECTION opcode_t opc_##name = {                                       \
611
    .opc1 = op1,                                                              \
612
    .opc2 = op2,                                                              \
613
    .opc3 = op3,                                                              \
614
    .pad  = { 0, },                                                           \
615
    .handler = {                                                              \
616
        .inval   = invl,                                                      \
617
        .type = _typ,                                                         \
618
        .handler = &gen_##name,                                               \
619
    },                                                                        \
620
    .oname = stringify(name),                                                 \
621
}
622
#define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ)                    \
623
OPCODES_SECTION opcode_t opc_##name = {                                       \
624
    .opc1 = op1,                                                              \
625
    .opc2 = op2,                                                              \
626
    .opc3 = op3,                                                              \
627
    .pad  = { 0, },                                                           \
628
    .handler = {                                                              \
629
        .inval   = invl,                                                      \
630
        .type = _typ,                                                         \
631
        .handler = &gen_##name,                                               \
632
    },                                                                        \
633
    .oname = onam,                                                            \
634
}
635
#endif
636

    
637
#define GEN_OPCODE_MARK(name)                                                 \
638
OPCODES_SECTION opcode_t opc_##name = {                                       \
639
    .opc1 = 0xFF,                                                             \
640
    .opc2 = 0xFF,                                                             \
641
    .opc3 = 0xFF,                                                             \
642
    .pad  = { 0, },                                                           \
643
    .handler = {                                                              \
644
        .inval   = 0x00000000,                                                \
645
        .type = 0x00,                                                         \
646
        .handler = NULL,                                                      \
647
    },                                                                        \
648
    .oname = stringify(name),                                                 \
649
}
650

    
651
/* Start opcode list */
652
GEN_OPCODE_MARK(start);
653

    
654
/* Invalid instruction */
655
GEN_HANDLER(invalid, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE)
656
{
657
    GEN_EXCP_INVAL(ctx);
658
}
659

    
660
static opc_handler_t invalid_handler = {
661
    .inval   = 0xFFFFFFFF,
662
    .type    = PPC_NONE,
663
    .handler = gen_invalid,
664
};
665

    
666
/***                           Integer arithmetic                          ***/
667
#define __GEN_INT_ARITH2(name, opc1, opc2, opc3, inval, type)                 \
668
GEN_HANDLER(name, opc1, opc2, opc3, inval, type)                              \
669
{                                                                             \
670
    gen_op_load_gpr_T0(rA(ctx->opcode));                                      \
671
    gen_op_load_gpr_T1(rB(ctx->opcode));                                      \
672
    gen_op_##name();                                                          \
673
    gen_op_store_T0_gpr(rD(ctx->opcode));                                     \
674
    if (unlikely(Rc(ctx->opcode) != 0))                                       \
675
        gen_set_Rc0(ctx);                                                     \
676
}
677

    
678
#define __GEN_INT_ARITH2_O(name, opc1, opc2, opc3, inval, type)               \
679
GEN_HANDLER(name, opc1, opc2, opc3, inval, type)                              \
680
{                                                                             \
681
    gen_op_load_gpr_T0(rA(ctx->opcode));                                      \
682
    gen_op_load_gpr_T1(rB(ctx->opcode));                                      \
683
    gen_op_##name();                                                          \
684
    gen_op_store_T0_gpr(rD(ctx->opcode));                                     \
685
    if (unlikely(Rc(ctx->opcode) != 0))                                       \
686
        gen_set_Rc0(ctx);                                                     \
687
}
688

    
689
#define __GEN_INT_ARITH1(name, opc1, opc2, opc3, type)                        \
690
GEN_HANDLER(name, opc1, opc2, opc3, 0x0000F800, type)                         \
691
{                                                                             \
692
    gen_op_load_gpr_T0(rA(ctx->opcode));                                      \
693
    gen_op_##name();                                                          \
694
    gen_op_store_T0_gpr(rD(ctx->opcode));                                     \
695
    if (unlikely(Rc(ctx->opcode) != 0))                                       \
696
        gen_set_Rc0(ctx);                                                     \
697
}
698
#define __GEN_INT_ARITH1_O(name, opc1, opc2, opc3, type)                      \
699
GEN_HANDLER(name, opc1, opc2, opc3, 0x0000F800, type)                         \
700
{                                                                             \
701
    gen_op_load_gpr_T0(rA(ctx->opcode));                                      \
702
    gen_op_##name();                                                          \
703
    gen_op_store_T0_gpr(rD(ctx->opcode));                                     \
704
    if (unlikely(Rc(ctx->opcode) != 0))                                       \
705
        gen_set_Rc0(ctx);                                                     \
706
}
707

    
708
/* Two operands arithmetic functions */
709
#define GEN_INT_ARITH2(name, opc1, opc2, opc3, type)                          \
710
__GEN_INT_ARITH2(name, opc1, opc2, opc3, 0x00000000, type)                    \
711
__GEN_INT_ARITH2_O(name##o, opc1, opc2, opc3 | 0x10, 0x00000000, type)
712

    
713
/* Two operands arithmetic functions with no overflow allowed */
714
#define GEN_INT_ARITHN(name, opc1, opc2, opc3, type)                          \
715
__GEN_INT_ARITH2(name, opc1, opc2, opc3, 0x00000400, type)
716

    
717
/* One operand arithmetic functions */
718
#define GEN_INT_ARITH1(name, opc1, opc2, opc3, type)                          \
719
__GEN_INT_ARITH1(name, opc1, opc2, opc3, type)                                \
720
__GEN_INT_ARITH1_O(name##o, opc1, opc2, opc3 | 0x10, type)
721

    
722
#if defined(TARGET_PPC64)
723
#define __GEN_INT_ARITH2_64(name, opc1, opc2, opc3, inval, type)              \
724
GEN_HANDLER(name, opc1, opc2, opc3, inval, type)                              \
725
{                                                                             \
726
    gen_op_load_gpr_T0(rA(ctx->opcode));                                      \
727
    gen_op_load_gpr_T1(rB(ctx->opcode));                                      \
728
    if (ctx->sf_mode)                                                         \
729
        gen_op_##name##_64();                                                 \
730
    else                                                                      \
731
        gen_op_##name();                                                      \
732
    gen_op_store_T0_gpr(rD(ctx->opcode));                                     \
733
    if (unlikely(Rc(ctx->opcode) != 0))                                       \
734
        gen_set_Rc0(ctx);                                                     \
735
}
736

    
737
#define __GEN_INT_ARITH2_O_64(name, opc1, opc2, opc3, inval, type)            \
738
GEN_HANDLER(name, opc1, opc2, opc3, inval, type)                              \
739
{                                                                             \
740
    gen_op_load_gpr_T0(rA(ctx->opcode));                                      \
741
    gen_op_load_gpr_T1(rB(ctx->opcode));                                      \
742
    if (ctx->sf_mode)                                                         \
743
        gen_op_##name##_64();                                                 \
744
    else                                                                      \
745
        gen_op_##name();                                                      \
746
    gen_op_store_T0_gpr(rD(ctx->opcode));                                     \
747
    if (unlikely(Rc(ctx->opcode) != 0))                                       \
748
        gen_set_Rc0(ctx);                                                     \
749
}
750

    
751
#define __GEN_INT_ARITH1_64(name, opc1, opc2, opc3, type)                     \
752
GEN_HANDLER(name, opc1, opc2, opc3, 0x0000F800, type)                         \
753
{                                                                             \
754
    gen_op_load_gpr_T0(rA(ctx->opcode));                                      \
755
    if (ctx->sf_mode)                                                         \
756
        gen_op_##name##_64();                                                 \
757
    else                                                                      \
758
        gen_op_##name();                                                      \
759
    gen_op_store_T0_gpr(rD(ctx->opcode));                                     \
760
    if (unlikely(Rc(ctx->opcode) != 0))                                       \
761
        gen_set_Rc0(ctx);                                                     \
762
}
763
#define __GEN_INT_ARITH1_O_64(name, opc1, opc2, opc3, type)                   \
764
GEN_HANDLER(name, opc1, opc2, opc3, 0x0000F800, type)                         \
765
{                                                                             \
766
    gen_op_load_gpr_T0(rA(ctx->opcode));                                      \
767
    if (ctx->sf_mode)                                                         \
768
        gen_op_##name##_64();                                                 \
769
    else                                                                      \
770
        gen_op_##name();                                                      \
771
    gen_op_store_T0_gpr(rD(ctx->opcode));                                     \
772
    if (unlikely(Rc(ctx->opcode) != 0))                                       \
773
        gen_set_Rc0(ctx);                                                     \
774
}
775

    
776
/* Two operands arithmetic functions */
777
#define GEN_INT_ARITH2_64(name, opc1, opc2, opc3, type)                       \
778
__GEN_INT_ARITH2_64(name, opc1, opc2, opc3, 0x00000000, type)                 \
779
__GEN_INT_ARITH2_O_64(name##o, opc1, opc2, opc3 | 0x10, 0x00000000, type)
780

    
781
/* Two operands arithmetic functions with no overflow allowed */
782
#define GEN_INT_ARITHN_64(name, opc1, opc2, opc3, type)                       \
783
__GEN_INT_ARITH2_64(name, opc1, opc2, opc3, 0x00000400, type)
784

    
785
/* One operand arithmetic functions */
786
#define GEN_INT_ARITH1_64(name, opc1, opc2, opc3, type)                       \
787
__GEN_INT_ARITH1_64(name, opc1, opc2, opc3, type)                             \
788
__GEN_INT_ARITH1_O_64(name##o, opc1, opc2, opc3 | 0x10, type)
789
#else
790
#define GEN_INT_ARITH2_64 GEN_INT_ARITH2
791
#define GEN_INT_ARITHN_64 GEN_INT_ARITHN
792
#define GEN_INT_ARITH1_64 GEN_INT_ARITH1
793
#endif
794

    
795
/* add    add.    addo    addo.    */
796
static always_inline void gen_op_addo (void)
797
{
798
    tcg_gen_mov_tl(cpu_T[2], cpu_T[0]);
799
    gen_op_add();
800
    gen_op_check_addo();
801
}
802
#if defined(TARGET_PPC64)
803
#define gen_op_add_64 gen_op_add
804
static always_inline void gen_op_addo_64 (void)
805
{
806
    tcg_gen_mov_tl(cpu_T[2], cpu_T[0]);
807
    gen_op_add();
808
    gen_op_check_addo_64();
809
}
810
#endif
811
GEN_INT_ARITH2_64 (add,    0x1F, 0x0A, 0x08, PPC_INTEGER);
812
/* addc   addc.   addco   addco.   */
813
static always_inline void gen_op_addc (void)
814
{
815
    tcg_gen_mov_tl(cpu_T[2], cpu_T[0]);
816
    gen_op_add();
817
    gen_op_check_addc();
818
}
819
static always_inline void gen_op_addco (void)
820
{
821
    tcg_gen_mov_tl(cpu_T[2], cpu_T[0]);
822
    gen_op_add();
823
    gen_op_check_addc();
824
    gen_op_check_addo();
825
}
826
#if defined(TARGET_PPC64)
827
static always_inline void gen_op_addc_64 (void)
828
{
829
    tcg_gen_mov_tl(cpu_T[2], cpu_T[0]);
830
    gen_op_add();
831
    gen_op_check_addc_64();
832
}
833
static always_inline void gen_op_addco_64 (void)
834
{
835
    tcg_gen_mov_tl(cpu_T[2], cpu_T[0]);
836
    gen_op_add();
837
    gen_op_check_addc_64();
838
    gen_op_check_addo_64();
839
}
840
#endif
841
GEN_INT_ARITH2_64 (addc,   0x1F, 0x0A, 0x00, PPC_INTEGER);
842
/* adde   adde.   addeo   addeo.   */
843
static always_inline void gen_op_addeo (void)
844
{
845
    tcg_gen_mov_tl(cpu_T[2], cpu_T[0]);
846
    gen_op_adde();
847
    gen_op_check_addo();
848
}
849
#if defined(TARGET_PPC64)
850
static always_inline void gen_op_addeo_64 (void)
851
{
852
    tcg_gen_mov_tl(cpu_T[2], cpu_T[0]);
853
    gen_op_adde_64();
854
    gen_op_check_addo_64();
855
}
856
#endif
857
GEN_INT_ARITH2_64 (adde,   0x1F, 0x0A, 0x04, PPC_INTEGER);
858
/* addme  addme.  addmeo  addmeo.  */
859
static always_inline void gen_op_addme (void)
860
{
861
    tcg_gen_mov_tl(cpu_T[1], cpu_T[0]);
862
    gen_op_add_me();
863
}
864
#if defined(TARGET_PPC64)
865
static always_inline void gen_op_addme_64 (void)
866
{
867
    tcg_gen_mov_tl(cpu_T[1], cpu_T[0]);
868
    gen_op_add_me_64();
869
}
870
#endif
871
GEN_INT_ARITH1_64 (addme,  0x1F, 0x0A, 0x07, PPC_INTEGER);
872
/* addze  addze.  addzeo  addzeo.  */
873
static always_inline void gen_op_addze (void)
874
{
875
    tcg_gen_mov_tl(cpu_T[2], cpu_T[0]);
876
    gen_op_add_ze();
877
    gen_op_check_addc();
878
}
879
static always_inline void gen_op_addzeo (void)
880
{
881
    tcg_gen_mov_tl(cpu_T[2], cpu_T[0]);
882
    gen_op_add_ze();
883
    gen_op_check_addc();
884
    gen_op_check_addo();
885
}
886
#if defined(TARGET_PPC64)
887
static always_inline void gen_op_addze_64 (void)
888
{
889
    tcg_gen_mov_tl(cpu_T[2], cpu_T[0]);
890
    gen_op_add_ze();
891
    gen_op_check_addc_64();
892
}
893
static always_inline void gen_op_addzeo_64 (void)
894
{
895
    tcg_gen_mov_tl(cpu_T[2], cpu_T[0]);
896
    gen_op_add_ze();
897
    gen_op_check_addc_64();
898
    gen_op_check_addo_64();
899
}
900
#endif
901
GEN_INT_ARITH1_64 (addze,  0x1F, 0x0A, 0x06, PPC_INTEGER);
902
/* divw   divw.   divwo   divwo.   */
903
GEN_INT_ARITH2 (divw,   0x1F, 0x0B, 0x0F, PPC_INTEGER);
904
/* divwu  divwu.  divwuo  divwuo.  */
905
GEN_INT_ARITH2 (divwu,  0x1F, 0x0B, 0x0E, PPC_INTEGER);
906
/* mulhw  mulhw.                   */
907
GEN_INT_ARITHN (mulhw,  0x1F, 0x0B, 0x02, PPC_INTEGER);
908
/* mulhwu mulhwu.                  */
909
GEN_INT_ARITHN (mulhwu, 0x1F, 0x0B, 0x00, PPC_INTEGER);
910
/* mullw  mullw.  mullwo  mullwo.  */
911
GEN_INT_ARITH2 (mullw,  0x1F, 0x0B, 0x07, PPC_INTEGER);
912
/* neg    neg.    nego    nego.    */
913
GEN_INT_ARITH1_64 (neg,    0x1F, 0x08, 0x03, PPC_INTEGER);
914
/* subf   subf.   subfo   subfo.   */
915
static always_inline void gen_op_subfo (void)
916
{
917
    gen_op_moven_T2_T0();
918
    gen_op_subf();
919
    gen_op_check_addo();
920
}
921
#if defined(TARGET_PPC64)
922
#define gen_op_subf_64 gen_op_subf
923
static always_inline void gen_op_subfo_64 (void)
924
{
925
    gen_op_moven_T2_T0();
926
    gen_op_subf();
927
    gen_op_check_addo_64();
928
}
929
#endif
930
GEN_INT_ARITH2_64 (subf,   0x1F, 0x08, 0x01, PPC_INTEGER);
931
/* subfc  subfc.  subfco  subfco.  */
932
static always_inline void gen_op_subfc (void)
933
{
934
    gen_op_subf();
935
    gen_op_check_subfc();
936
}
937
static always_inline void gen_op_subfco (void)
938
{
939
    gen_op_moven_T2_T0();
940
    gen_op_subf();
941
    gen_op_check_subfc();
942
    gen_op_check_addo();
943
}
944
#if defined(TARGET_PPC64)
945
static always_inline void gen_op_subfc_64 (void)
946
{
947
    gen_op_subf();
948
    gen_op_check_subfc_64();
949
}
950
static always_inline void gen_op_subfco_64 (void)
951
{
952
    gen_op_moven_T2_T0();
953
    gen_op_subf();
954
    gen_op_check_subfc_64();
955
    gen_op_check_addo_64();
956
}
957
#endif
958
GEN_INT_ARITH2_64 (subfc,  0x1F, 0x08, 0x00, PPC_INTEGER);
959
/* subfe  subfe.  subfeo  subfeo.  */
960
static always_inline void gen_op_subfeo (void)
961
{
962
    gen_op_moven_T2_T0();
963
    gen_op_subfe();
964
    gen_op_check_addo();
965
}
966
#if defined(TARGET_PPC64)
967
#define gen_op_subfe_64 gen_op_subfe
968
static always_inline void gen_op_subfeo_64 (void)
969
{
970
    gen_op_moven_T2_T0();
971
    gen_op_subfe_64();
972
    gen_op_check_addo_64();
973
}
974
#endif
975
GEN_INT_ARITH2_64 (subfe,  0x1F, 0x08, 0x04, PPC_INTEGER);
976
/* subfme subfme. subfmeo subfmeo. */
977
GEN_INT_ARITH1_64 (subfme, 0x1F, 0x08, 0x07, PPC_INTEGER);
978
/* subfze subfze. subfzeo subfzeo. */
979
GEN_INT_ARITH1_64 (subfze, 0x1F, 0x08, 0x06, PPC_INTEGER);
980
/* addi */
981
GEN_HANDLER(addi, 0x0E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
982
{
983
    target_long simm = SIMM(ctx->opcode);
984

    
985
    if (rA(ctx->opcode) == 0) {
986
        /* li case */
987
        tcg_gen_movi_tl(cpu_T[0], simm);
988
    } else {
989
        gen_op_load_gpr_T0(rA(ctx->opcode));
990
        if (likely(simm != 0))
991
            gen_op_addi(simm);
992
    }
993
    gen_op_store_T0_gpr(rD(ctx->opcode));
994
}
995
/* addic */
996
GEN_HANDLER(addic, 0x0C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
997
{
998
    target_long simm = SIMM(ctx->opcode);
999

    
1000
    gen_op_load_gpr_T0(rA(ctx->opcode));
1001
    if (likely(simm != 0)) {
1002
        tcg_gen_mov_tl(cpu_T[2], cpu_T[0]);
1003
        gen_op_addi(simm);
1004
#if defined(TARGET_PPC64)
1005
        if (ctx->sf_mode)
1006
            gen_op_check_addc_64();
1007
        else
1008
#endif
1009
            gen_op_check_addc();
1010
    } else {
1011
        gen_op_clear_xer_ca();
1012
    }
1013
    gen_op_store_T0_gpr(rD(ctx->opcode));
1014
}
1015
/* addic. */
1016
GEN_HANDLER2(addic_, "addic.", 0x0D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1017
{
1018
    target_long simm = SIMM(ctx->opcode);
1019

    
1020
    gen_op_load_gpr_T0(rA(ctx->opcode));
1021
    if (likely(simm != 0)) {
1022
        tcg_gen_mov_tl(cpu_T[2], cpu_T[0]);
1023
        gen_op_addi(simm);
1024
#if defined(TARGET_PPC64)
1025
        if (ctx->sf_mode)
1026
            gen_op_check_addc_64();
1027
        else
1028
#endif
1029
            gen_op_check_addc();
1030
    } else {
1031
        gen_op_clear_xer_ca();
1032
    }
1033
    gen_op_store_T0_gpr(rD(ctx->opcode));
1034
    gen_set_Rc0(ctx);
1035
}
1036
/* addis */
1037
GEN_HANDLER(addis, 0x0F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1038
{
1039
    target_long simm = SIMM(ctx->opcode);
1040

    
1041
    if (rA(ctx->opcode) == 0) {
1042
        /* lis case */
1043
        tcg_gen_movi_tl(cpu_T[0], simm << 16);
1044
    } else {
1045
        gen_op_load_gpr_T0(rA(ctx->opcode));
1046
        if (likely(simm != 0))
1047
            gen_op_addi(simm << 16);
1048
    }
1049
    gen_op_store_T0_gpr(rD(ctx->opcode));
1050
}
1051
/* mulli */
1052
GEN_HANDLER(mulli, 0x07, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1053
{
1054
    gen_op_load_gpr_T0(rA(ctx->opcode));
1055
    gen_op_mulli(SIMM(ctx->opcode));
1056
    gen_op_store_T0_gpr(rD(ctx->opcode));
1057
}
1058
/* subfic */
1059
GEN_HANDLER(subfic, 0x08, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1060
{
1061
    gen_op_load_gpr_T0(rA(ctx->opcode));
1062
#if defined(TARGET_PPC64)
1063
    if (ctx->sf_mode)
1064
        gen_op_subfic_64(SIMM(ctx->opcode));
1065
    else
1066
#endif
1067
        gen_op_subfic(SIMM(ctx->opcode));
1068
    gen_op_store_T0_gpr(rD(ctx->opcode));
1069
}
1070

    
1071
#if defined(TARGET_PPC64)
1072
/* mulhd  mulhd.                   */
1073
GEN_INT_ARITHN (mulhd,  0x1F, 0x09, 0x02, PPC_64B);
1074
/* mulhdu mulhdu.                  */
1075
GEN_INT_ARITHN (mulhdu, 0x1F, 0x09, 0x00, PPC_64B);
1076
/* mulld  mulld.  mulldo  mulldo.  */
1077
GEN_INT_ARITH2 (mulld,  0x1F, 0x09, 0x07, PPC_64B);
1078
/* divd   divd.   divdo   divdo.   */
1079
GEN_INT_ARITH2 (divd,   0x1F, 0x09, 0x0F, PPC_64B);
1080
/* divdu  divdu.  divduo  divduo.  */
1081
GEN_INT_ARITH2 (divdu,  0x1F, 0x09, 0x0E, PPC_64B);
1082
#endif
1083

    
1084
/***                           Integer comparison                          ***/
1085
#if defined(TARGET_PPC64)
1086
#define GEN_CMP(name, opc, type)                                              \
1087
GEN_HANDLER(name, 0x1F, 0x00, opc, 0x00400000, type)                          \
1088
{                                                                             \
1089
    gen_op_load_gpr_T0(rA(ctx->opcode));                                      \
1090
    gen_op_load_gpr_T1(rB(ctx->opcode));                                      \
1091
    if (ctx->sf_mode && (ctx->opcode & 0x00200000))                           \
1092
        gen_op_##name##_64();                                                 \
1093
    else                                                                      \
1094
        gen_op_##name();                                                      \
1095
    gen_op_store_T0_crf(crfD(ctx->opcode));                                   \
1096
}
1097
#else
1098
#define GEN_CMP(name, opc, type)                                              \
1099
GEN_HANDLER(name, 0x1F, 0x00, opc, 0x00400000, type)                          \
1100
{                                                                             \
1101
    gen_op_load_gpr_T0(rA(ctx->opcode));                                      \
1102
    gen_op_load_gpr_T1(rB(ctx->opcode));                                      \
1103
    gen_op_##name();                                                          \
1104
    gen_op_store_T0_crf(crfD(ctx->opcode));                                   \
1105
}
1106
#endif
1107

    
1108
/* cmp */
1109
GEN_CMP(cmp, 0x00, PPC_INTEGER);
1110
/* cmpi */
1111
GEN_HANDLER(cmpi, 0x0B, 0xFF, 0xFF, 0x00400000, PPC_INTEGER)
1112
{
1113
    gen_op_load_gpr_T0(rA(ctx->opcode));
1114
#if defined(TARGET_PPC64)
1115
    if (ctx->sf_mode && (ctx->opcode & 0x00200000))
1116
        gen_op_cmpi_64(SIMM(ctx->opcode));
1117
    else
1118
#endif
1119
        gen_op_cmpi(SIMM(ctx->opcode));
1120
    gen_op_store_T0_crf(crfD(ctx->opcode));
1121
}
1122
/* cmpl */
1123
GEN_CMP(cmpl, 0x01, PPC_INTEGER);
1124
/* cmpli */
1125
GEN_HANDLER(cmpli, 0x0A, 0xFF, 0xFF, 0x00400000, PPC_INTEGER)
1126
{
1127
    gen_op_load_gpr_T0(rA(ctx->opcode));
1128
#if defined(TARGET_PPC64)
1129
    if (ctx->sf_mode && (ctx->opcode & 0x00200000))
1130
        gen_op_cmpli_64(UIMM(ctx->opcode));
1131
    else
1132
#endif
1133
        gen_op_cmpli(UIMM(ctx->opcode));
1134
    gen_op_store_T0_crf(crfD(ctx->opcode));
1135
}
1136

    
1137
/* isel (PowerPC 2.03 specification) */
1138
GEN_HANDLER(isel, 0x1F, 0x0F, 0xFF, 0x00000001, PPC_ISEL)
1139
{
1140
    uint32_t bi = rC(ctx->opcode);
1141
    uint32_t mask;
1142

    
1143
    if (rA(ctx->opcode) == 0) {
1144
        tcg_gen_movi_tl(cpu_T[0], 0);
1145
    } else {
1146
        gen_op_load_gpr_T1(rA(ctx->opcode));
1147
    }
1148
    gen_op_load_gpr_T2(rB(ctx->opcode));
1149
    mask = 1 << (3 - (bi & 0x03));
1150
    gen_op_load_crf_T0(bi >> 2);
1151
    gen_op_test_true(mask);
1152
    gen_op_isel();
1153
    gen_op_store_T0_gpr(rD(ctx->opcode));
1154
}
1155

    
1156
/***                            Integer logical                            ***/
1157
#define __GEN_LOGICAL2(name, opc2, opc3, type)                                \
1158
GEN_HANDLER(name, 0x1F, opc2, opc3, 0x00000000, type)                         \
1159
{                                                                             \
1160
    gen_op_load_gpr_T0(rS(ctx->opcode));                                      \
1161
    gen_op_load_gpr_T1(rB(ctx->opcode));                                      \
1162
    gen_op_##name();                                                          \
1163
    gen_op_store_T0_gpr(rA(ctx->opcode));                                     \
1164
    if (unlikely(Rc(ctx->opcode) != 0))                                       \
1165
        gen_set_Rc0(ctx);                                                     \
1166
}
1167
#define GEN_LOGICAL2(name, opc, type)                                         \
1168
__GEN_LOGICAL2(name, 0x1C, opc, type)
1169

    
1170
#define GEN_LOGICAL1(name, opc, type)                                         \
1171
GEN_HANDLER(name, 0x1F, 0x1A, opc, 0x00000000, type)                          \
1172
{                                                                             \
1173
    gen_op_load_gpr_T0(rS(ctx->opcode));                                      \
1174
    gen_op_##name();                                                          \
1175
    gen_op_store_T0_gpr(rA(ctx->opcode));                                     \
1176
    if (unlikely(Rc(ctx->opcode) != 0))                                       \
1177
        gen_set_Rc0(ctx);                                                     \
1178
}
1179

    
1180
/* and & and. */
1181
GEN_LOGICAL2(and, 0x00, PPC_INTEGER);
1182
/* andc & andc. */
1183
GEN_LOGICAL2(andc, 0x01, PPC_INTEGER);
1184
/* andi. */
1185
GEN_HANDLER2(andi_, "andi.", 0x1C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1186
{
1187
    gen_op_load_gpr_T0(rS(ctx->opcode));
1188
    gen_op_andi_T0(UIMM(ctx->opcode));
1189
    gen_op_store_T0_gpr(rA(ctx->opcode));
1190
    gen_set_Rc0(ctx);
1191
}
1192
/* andis. */
1193
GEN_HANDLER2(andis_, "andis.", 0x1D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1194
{
1195
    gen_op_load_gpr_T0(rS(ctx->opcode));
1196
    gen_op_andi_T0(UIMM(ctx->opcode) << 16);
1197
    gen_op_store_T0_gpr(rA(ctx->opcode));
1198
    gen_set_Rc0(ctx);
1199
}
1200

    
1201
/* cntlzw */
1202
GEN_LOGICAL1(cntlzw, 0x00, PPC_INTEGER);
1203
/* eqv & eqv. */
1204
GEN_LOGICAL2(eqv, 0x08, PPC_INTEGER);
1205
/* extsb & extsb. */
1206
GEN_LOGICAL1(extsb, 0x1D, PPC_INTEGER);
1207
/* extsh & extsh. */
1208
GEN_LOGICAL1(extsh, 0x1C, PPC_INTEGER);
1209
/* nand & nand. */
1210
GEN_LOGICAL2(nand, 0x0E, PPC_INTEGER);
1211
/* nor & nor. */
1212
GEN_LOGICAL2(nor, 0x03, PPC_INTEGER);
1213

    
1214
/* or & or. */
1215
GEN_HANDLER(or, 0x1F, 0x1C, 0x0D, 0x00000000, PPC_INTEGER)
1216
{
1217
    int rs, ra, rb;
1218

    
1219
    rs = rS(ctx->opcode);
1220
    ra = rA(ctx->opcode);
1221
    rb = rB(ctx->opcode);
1222
    /* Optimisation for mr. ri case */
1223
    if (rs != ra || rs != rb) {
1224
        gen_op_load_gpr_T0(rs);
1225
        if (rs != rb) {
1226
            gen_op_load_gpr_T1(rb);
1227
            gen_op_or();
1228
        }
1229
        gen_op_store_T0_gpr(ra);
1230
        if (unlikely(Rc(ctx->opcode) != 0))
1231
            gen_set_Rc0(ctx);
1232
    } else if (unlikely(Rc(ctx->opcode) != 0)) {
1233
        gen_op_load_gpr_T0(rs);
1234
        gen_set_Rc0(ctx);
1235
#if defined(TARGET_PPC64)
1236
    } else {
1237
        switch (rs) {
1238
        case 1:
1239
            /* Set process priority to low */
1240
            gen_op_store_pri(2);
1241
            break;
1242
        case 6:
1243
            /* Set process priority to medium-low */
1244
            gen_op_store_pri(3);
1245
            break;
1246
        case 2:
1247
            /* Set process priority to normal */
1248
            gen_op_store_pri(4);
1249
            break;
1250
#if !defined(CONFIG_USER_ONLY)
1251
        case 31:
1252
            if (ctx->supervisor > 0) {
1253
                /* Set process priority to very low */
1254
                gen_op_store_pri(1);
1255
            }
1256
            break;
1257
        case 5:
1258
            if (ctx->supervisor > 0) {
1259
                /* Set process priority to medium-hight */
1260
                gen_op_store_pri(5);
1261
            }
1262
            break;
1263
        case 3:
1264
            if (ctx->supervisor > 0) {
1265
                /* Set process priority to high */
1266
                gen_op_store_pri(6);
1267
            }
1268
            break;
1269
        case 7:
1270
            if (ctx->supervisor > 1) {
1271
                /* Set process priority to very high */
1272
                gen_op_store_pri(7);
1273
            }
1274
            break;
1275
#endif
1276
        default:
1277
            /* nop */
1278
            break;
1279
        }
1280
#endif
1281
    }
1282
}
1283

    
1284
/* orc & orc. */
1285
GEN_LOGICAL2(orc, 0x0C, PPC_INTEGER);
1286
/* xor & xor. */
1287
GEN_HANDLER(xor, 0x1F, 0x1C, 0x09, 0x00000000, PPC_INTEGER)
1288
{
1289
    gen_op_load_gpr_T0(rS(ctx->opcode));
1290
    /* Optimisation for "set to zero" case */
1291
    if (rS(ctx->opcode) != rB(ctx->opcode)) {
1292
        gen_op_load_gpr_T1(rB(ctx->opcode));
1293
        gen_op_xor();
1294
    } else {
1295
        tcg_gen_movi_tl(cpu_T[0], 0);
1296
    }
1297
    gen_op_store_T0_gpr(rA(ctx->opcode));
1298
    if (unlikely(Rc(ctx->opcode) != 0))
1299
        gen_set_Rc0(ctx);
1300
}
1301
/* ori */
1302
GEN_HANDLER(ori, 0x18, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1303
{
1304
    target_ulong uimm = UIMM(ctx->opcode);
1305

    
1306
    if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1307
        /* NOP */
1308
        /* XXX: should handle special NOPs for POWER series */
1309
        return;
1310
    }
1311
    gen_op_load_gpr_T0(rS(ctx->opcode));
1312
    if (likely(uimm != 0))
1313
        gen_op_ori(uimm);
1314
    gen_op_store_T0_gpr(rA(ctx->opcode));
1315
}
1316
/* oris */
1317
GEN_HANDLER(oris, 0x19, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1318
{
1319
    target_ulong uimm = UIMM(ctx->opcode);
1320

    
1321
    if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1322
        /* NOP */
1323
        return;
1324
    }
1325
    gen_op_load_gpr_T0(rS(ctx->opcode));
1326
    if (likely(uimm != 0))
1327
        gen_op_ori(uimm << 16);
1328
    gen_op_store_T0_gpr(rA(ctx->opcode));
1329
}
1330
/* xori */
1331
GEN_HANDLER(xori, 0x1A, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1332
{
1333
    target_ulong uimm = UIMM(ctx->opcode);
1334

    
1335
    if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1336
        /* NOP */
1337
        return;
1338
    }
1339
    gen_op_load_gpr_T0(rS(ctx->opcode));
1340
    if (likely(uimm != 0))
1341
        gen_op_xori(uimm);
1342
    gen_op_store_T0_gpr(rA(ctx->opcode));
1343
}
1344

    
1345
/* xoris */
1346
GEN_HANDLER(xoris, 0x1B, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1347
{
1348
    target_ulong uimm = UIMM(ctx->opcode);
1349

    
1350
    if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1351
        /* NOP */
1352
        return;
1353
    }
1354
    gen_op_load_gpr_T0(rS(ctx->opcode));
1355
    if (likely(uimm != 0))
1356
        gen_op_xori(uimm << 16);
1357
    gen_op_store_T0_gpr(rA(ctx->opcode));
1358
}
1359

    
1360
/* popcntb : PowerPC 2.03 specification */
1361
GEN_HANDLER(popcntb, 0x1F, 0x03, 0x03, 0x0000F801, PPC_POPCNTB)
1362
{
1363
    gen_op_load_gpr_T0(rS(ctx->opcode));
1364
#if defined(TARGET_PPC64)
1365
    if (ctx->sf_mode)
1366
        gen_op_popcntb_64();
1367
    else
1368
#endif
1369
        gen_op_popcntb();
1370
    gen_op_store_T0_gpr(rA(ctx->opcode));
1371
}
1372

    
1373
#if defined(TARGET_PPC64)
1374
/* extsw & extsw. */
1375
GEN_LOGICAL1(extsw, 0x1E, PPC_64B);
1376
/* cntlzd */
1377
GEN_LOGICAL1(cntlzd, 0x01, PPC_64B);
1378
#endif
1379

    
1380
/***                             Integer rotate                            ***/
1381
/* rlwimi & rlwimi. */
1382
GEN_HANDLER(rlwimi, 0x14, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1383
{
1384
    target_ulong mask;
1385
    uint32_t mb, me, sh;
1386

    
1387
    mb = MB(ctx->opcode);
1388
    me = ME(ctx->opcode);
1389
    sh = SH(ctx->opcode);
1390
    if (likely(sh == 0)) {
1391
        if (likely(mb == 0 && me == 31)) {
1392
            gen_op_load_gpr_T0(rS(ctx->opcode));
1393
            goto do_store;
1394
        } else if (likely(mb == 31 && me == 0)) {
1395
            gen_op_load_gpr_T0(rA(ctx->opcode));
1396
            goto do_store;
1397
        }
1398
        gen_op_load_gpr_T0(rS(ctx->opcode));
1399
        gen_op_load_gpr_T1(rA(ctx->opcode));
1400
        goto do_mask;
1401
    }
1402
    gen_op_load_gpr_T0(rS(ctx->opcode));
1403
    gen_op_load_gpr_T1(rA(ctx->opcode));
1404
    gen_op_rotli32_T0(SH(ctx->opcode));
1405
 do_mask:
1406
#if defined(TARGET_PPC64)
1407
    mb += 32;
1408
    me += 32;
1409
#endif
1410
    mask = MASK(mb, me);
1411
    gen_op_andi_T0(mask);
1412
    gen_op_andi_T1(~mask);
1413
    gen_op_or();
1414
 do_store:
1415
    gen_op_store_T0_gpr(rA(ctx->opcode));
1416
    if (unlikely(Rc(ctx->opcode) != 0))
1417
        gen_set_Rc0(ctx);
1418
}
1419
/* rlwinm & rlwinm. */
1420
GEN_HANDLER(rlwinm, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1421
{
1422
    uint32_t mb, me, sh;
1423

    
1424
    sh = SH(ctx->opcode);
1425
    mb = MB(ctx->opcode);
1426
    me = ME(ctx->opcode);
1427
    gen_op_load_gpr_T0(rS(ctx->opcode));
1428
    if (likely(sh == 0)) {
1429
        goto do_mask;
1430
    }
1431
    if (likely(mb == 0)) {
1432
        if (likely(me == 31)) {
1433
            gen_op_rotli32_T0(sh);
1434
            goto do_store;
1435
        } else if (likely(me == (31 - sh))) {
1436
            gen_op_sli_T0(sh);
1437
            goto do_store;
1438
        }
1439
    } else if (likely(me == 31)) {
1440
        if (likely(sh == (32 - mb))) {
1441
            gen_op_srli_T0(mb);
1442
            goto do_store;
1443
        }
1444
    }
1445
    gen_op_rotli32_T0(sh);
1446
 do_mask:
1447
#if defined(TARGET_PPC64)
1448
    mb += 32;
1449
    me += 32;
1450
#endif
1451
    gen_op_andi_T0(MASK(mb, me));
1452
 do_store:
1453
    gen_op_store_T0_gpr(rA(ctx->opcode));
1454
    if (unlikely(Rc(ctx->opcode) != 0))
1455
        gen_set_Rc0(ctx);
1456
}
1457
/* rlwnm & rlwnm. */
1458
GEN_HANDLER(rlwnm, 0x17, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1459
{
1460
    uint32_t mb, me;
1461

    
1462
    mb = MB(ctx->opcode);
1463
    me = ME(ctx->opcode);
1464
    gen_op_load_gpr_T0(rS(ctx->opcode));
1465
    gen_op_load_gpr_T1(rB(ctx->opcode));
1466
    gen_op_rotl32_T0_T1();
1467
    if (unlikely(mb != 0 || me != 31)) {
1468
#if defined(TARGET_PPC64)
1469
        mb += 32;
1470
        me += 32;
1471
#endif
1472
        gen_op_andi_T0(MASK(mb, me));
1473
    }
1474
    gen_op_store_T0_gpr(rA(ctx->opcode));
1475
    if (unlikely(Rc(ctx->opcode) != 0))
1476
        gen_set_Rc0(ctx);
1477
}
1478

    
1479
#if defined(TARGET_PPC64)
1480
#define GEN_PPC64_R2(name, opc1, opc2)                                        \
1481
GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B) \
1482
{                                                                             \
1483
    gen_##name(ctx, 0);                                                       \
1484
}                                                                             \
1485
GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000,   \
1486
             PPC_64B)                                                         \
1487
{                                                                             \
1488
    gen_##name(ctx, 1);                                                       \
1489
}
1490
#define GEN_PPC64_R4(name, opc1, opc2)                                        \
1491
GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B) \
1492
{                                                                             \
1493
    gen_##name(ctx, 0, 0);                                                    \
1494
}                                                                             \
1495
GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x01, 0xFF, 0x00000000,   \
1496
             PPC_64B)                                                         \
1497
{                                                                             \
1498
    gen_##name(ctx, 0, 1);                                                    \
1499
}                                                                             \
1500
GEN_HANDLER2(name##2, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000,   \
1501
             PPC_64B)                                                         \
1502
{                                                                             \
1503
    gen_##name(ctx, 1, 0);                                                    \
1504
}                                                                             \
1505
GEN_HANDLER2(name##3, stringify(name), opc1, opc2 | 0x11, 0xFF, 0x00000000,   \
1506
             PPC_64B)                                                         \
1507
{                                                                             \
1508
    gen_##name(ctx, 1, 1);                                                    \
1509
}
1510

    
1511
static always_inline void gen_andi_T0_64 (DisasContext *ctx, uint64_t mask)
1512
{
1513
    if (mask >> 32)
1514
        gen_op_andi_T0_64(mask >> 32, mask & 0xFFFFFFFF);
1515
    else
1516
        gen_op_andi_T0(mask);
1517
}
1518

    
1519
static always_inline void gen_andi_T1_64 (DisasContext *ctx, uint64_t mask)
1520
{
1521
    if (mask >> 32)
1522
        gen_op_andi_T1_64(mask >> 32, mask & 0xFFFFFFFF);
1523
    else
1524
        gen_op_andi_T1(mask);
1525
}
1526

    
1527
static always_inline void gen_rldinm (DisasContext *ctx, uint32_t mb,
1528
                                      uint32_t me, uint32_t sh)
1529
{
1530
    gen_op_load_gpr_T0(rS(ctx->opcode));
1531
    if (likely(sh == 0)) {
1532
        goto do_mask;
1533
    }
1534
    if (likely(mb == 0)) {
1535
        if (likely(me == 63)) {
1536
            gen_op_rotli64_T0(sh);
1537
            goto do_store;
1538
        } else if (likely(me == (63 - sh))) {
1539
            gen_op_sli_T0(sh);
1540
            goto do_store;
1541
        }
1542
    } else if (likely(me == 63)) {
1543
        if (likely(sh == (64 - mb))) {
1544
            gen_op_srli_T0_64(mb);
1545
            goto do_store;
1546
        }
1547
    }
1548
    gen_op_rotli64_T0(sh);
1549
 do_mask:
1550
    gen_andi_T0_64(ctx, MASK(mb, me));
1551
 do_store:
1552
    gen_op_store_T0_gpr(rA(ctx->opcode));
1553
    if (unlikely(Rc(ctx->opcode) != 0))
1554
        gen_set_Rc0(ctx);
1555
}
1556
/* rldicl - rldicl. */
1557
static always_inline void gen_rldicl (DisasContext *ctx, int mbn, int shn)
1558
{
1559
    uint32_t sh, mb;
1560

    
1561
    sh = SH(ctx->opcode) | (shn << 5);
1562
    mb = MB(ctx->opcode) | (mbn << 5);
1563
    gen_rldinm(ctx, mb, 63, sh);
1564
}
1565
GEN_PPC64_R4(rldicl, 0x1E, 0x00);
1566
/* rldicr - rldicr. */
1567
static always_inline void gen_rldicr (DisasContext *ctx, int men, int shn)
1568
{
1569
    uint32_t sh, me;
1570

    
1571
    sh = SH(ctx->opcode) | (shn << 5);
1572
    me = MB(ctx->opcode) | (men << 5);
1573
    gen_rldinm(ctx, 0, me, sh);
1574
}
1575
GEN_PPC64_R4(rldicr, 0x1E, 0x02);
1576
/* rldic - rldic. */
1577
static always_inline void gen_rldic (DisasContext *ctx, int mbn, int shn)
1578
{
1579
    uint32_t sh, mb;
1580

    
1581
    sh = SH(ctx->opcode) | (shn << 5);
1582
    mb = MB(ctx->opcode) | (mbn << 5);
1583
    gen_rldinm(ctx, mb, 63 - sh, sh);
1584
}
1585
GEN_PPC64_R4(rldic, 0x1E, 0x04);
1586

    
1587
static always_inline void gen_rldnm (DisasContext *ctx, uint32_t mb,
1588
                                     uint32_t me)
1589
{
1590
    gen_op_load_gpr_T0(rS(ctx->opcode));
1591
    gen_op_load_gpr_T1(rB(ctx->opcode));
1592
    gen_op_rotl64_T0_T1();
1593
    if (unlikely(mb != 0 || me != 63)) {
1594
        gen_andi_T0_64(ctx, MASK(mb, me));
1595
    }
1596
    gen_op_store_T0_gpr(rA(ctx->opcode));
1597
    if (unlikely(Rc(ctx->opcode) != 0))
1598
        gen_set_Rc0(ctx);
1599
}
1600

    
1601
/* rldcl - rldcl. */
1602
static always_inline void gen_rldcl (DisasContext *ctx, int mbn)
1603
{
1604
    uint32_t mb;
1605

    
1606
    mb = MB(ctx->opcode) | (mbn << 5);
1607
    gen_rldnm(ctx, mb, 63);
1608
}
1609
GEN_PPC64_R2(rldcl, 0x1E, 0x08);
1610
/* rldcr - rldcr. */
1611
static always_inline void gen_rldcr (DisasContext *ctx, int men)
1612
{
1613
    uint32_t me;
1614

    
1615
    me = MB(ctx->opcode) | (men << 5);
1616
    gen_rldnm(ctx, 0, me);
1617
}
1618
GEN_PPC64_R2(rldcr, 0x1E, 0x09);
1619
/* rldimi - rldimi. */
1620
static always_inline void gen_rldimi (DisasContext *ctx, int mbn, int shn)
1621
{
1622
    uint64_t mask;
1623
    uint32_t sh, mb, me;
1624

    
1625
    sh = SH(ctx->opcode) | (shn << 5);
1626
    mb = MB(ctx->opcode) | (mbn << 5);
1627
    me = 63 - sh;
1628
    if (likely(sh == 0)) {
1629
        if (likely(mb == 0)) {
1630
            gen_op_load_gpr_T0(rS(ctx->opcode));
1631
            goto do_store;
1632
        }
1633
        gen_op_load_gpr_T0(rS(ctx->opcode));
1634
        gen_op_load_gpr_T1(rA(ctx->opcode));
1635
        goto do_mask;
1636
    }
1637
    gen_op_load_gpr_T0(rS(ctx->opcode));
1638
    gen_op_load_gpr_T1(rA(ctx->opcode));
1639
    gen_op_rotli64_T0(sh);
1640
 do_mask:
1641
    mask = MASK(mb, me);
1642
    gen_andi_T0_64(ctx, mask);
1643
    gen_andi_T1_64(ctx, ~mask);
1644
    gen_op_or();
1645
 do_store:
1646
    gen_op_store_T0_gpr(rA(ctx->opcode));
1647
    if (unlikely(Rc(ctx->opcode) != 0))
1648
        gen_set_Rc0(ctx);
1649
}
1650
GEN_PPC64_R4(rldimi, 0x1E, 0x06);
1651
#endif
1652

    
1653
/***                             Integer shift                             ***/
1654
/* slw & slw. */
1655
__GEN_LOGICAL2(slw, 0x18, 0x00, PPC_INTEGER);
1656
/* sraw & sraw. */
1657
__GEN_LOGICAL2(sraw, 0x18, 0x18, PPC_INTEGER);
1658
/* srawi & srawi. */
1659
GEN_HANDLER(srawi, 0x1F, 0x18, 0x19, 0x00000000, PPC_INTEGER)
1660
{
1661
    int mb, me;
1662
    gen_op_load_gpr_T0(rS(ctx->opcode));
1663
    if (SH(ctx->opcode) != 0) {
1664
        tcg_gen_mov_tl(cpu_T[1], cpu_T[0]);
1665
        mb = 32 - SH(ctx->opcode);
1666
        me = 31;
1667
#if defined(TARGET_PPC64)
1668
        mb += 32;
1669
        me += 32;
1670
#endif
1671
        gen_op_srawi(SH(ctx->opcode), MASK(mb, me));
1672
    }
1673
    gen_op_store_T0_gpr(rA(ctx->opcode));
1674
    if (unlikely(Rc(ctx->opcode) != 0))
1675
        gen_set_Rc0(ctx);
1676
}
1677
/* srw & srw. */
1678
__GEN_LOGICAL2(srw, 0x18, 0x10, PPC_INTEGER);
1679

    
1680
#if defined(TARGET_PPC64)
1681
/* sld & sld. */
1682
__GEN_LOGICAL2(sld, 0x1B, 0x00, PPC_64B);
1683
/* srad & srad. */
1684
__GEN_LOGICAL2(srad, 0x1A, 0x18, PPC_64B);
1685
/* sradi & sradi. */
1686
static always_inline void gen_sradi (DisasContext *ctx, int n)
1687
{
1688
    uint64_t mask;
1689
    int sh, mb, me;
1690

    
1691
    gen_op_load_gpr_T0(rS(ctx->opcode));
1692
    sh = SH(ctx->opcode) + (n << 5);
1693
    if (sh != 0) {
1694
        tcg_gen_mov_tl(cpu_T[1], cpu_T[0]);
1695
        mb = 64 - SH(ctx->opcode);
1696
        me = 63;
1697
        mask = MASK(mb, me);
1698
        gen_op_sradi(sh, mask >> 32, mask);
1699
    }
1700
    gen_op_store_T0_gpr(rA(ctx->opcode));
1701
    if (unlikely(Rc(ctx->opcode) != 0))
1702
        gen_set_Rc0(ctx);
1703
}
1704
GEN_HANDLER2(sradi0, "sradi", 0x1F, 0x1A, 0x19, 0x00000000, PPC_64B)
1705
{
1706
    gen_sradi(ctx, 0);
1707
}
1708
GEN_HANDLER2(sradi1, "sradi", 0x1F, 0x1B, 0x19, 0x00000000, PPC_64B)
1709
{
1710
    gen_sradi(ctx, 1);
1711
}
1712
/* srd & srd. */
1713
__GEN_LOGICAL2(srd, 0x1B, 0x10, PPC_64B);
1714
#endif
1715

    
1716
/***                       Floating-Point arithmetic                       ***/
1717
#define _GEN_FLOAT_ACB(name, op, op1, op2, isfloat, set_fprf, type)           \
1718
GEN_HANDLER(f##name, op1, op2, 0xFF, 0x00000000, type)                        \
1719
{                                                                             \
1720
    if (unlikely(!ctx->fpu_enabled)) {                                        \
1721
        GEN_EXCP_NO_FP(ctx);                                                  \
1722
        return;                                                               \
1723
    }                                                                         \
1724
    gen_op_load_fpr_FT0(rA(ctx->opcode));                                     \
1725
    gen_op_load_fpr_FT1(rC(ctx->opcode));                                     \
1726
    gen_op_load_fpr_FT2(rB(ctx->opcode));                                     \
1727
    gen_reset_fpstatus();                                                     \
1728
    gen_op_f##op();                                                           \
1729
    if (isfloat) {                                                            \
1730
        gen_op_frsp();                                                        \
1731
    }                                                                         \
1732
    gen_op_store_FT0_fpr(rD(ctx->opcode));                                    \
1733
    gen_compute_fprf(set_fprf, Rc(ctx->opcode) != 0);                         \
1734
}
1735

    
1736
#define GEN_FLOAT_ACB(name, op2, set_fprf, type)                              \
1737
_GEN_FLOAT_ACB(name, name, 0x3F, op2, 0, set_fprf, type);                     \
1738
_GEN_FLOAT_ACB(name##s, name, 0x3B, op2, 1, set_fprf, type);
1739

    
1740
#define _GEN_FLOAT_AB(name, op, op1, op2, inval, isfloat, set_fprf, type)     \
1741
GEN_HANDLER(f##name, op1, op2, 0xFF, inval, type)                             \
1742
{                                                                             \
1743
    if (unlikely(!ctx->fpu_enabled)) {                                        \
1744
        GEN_EXCP_NO_FP(ctx);                                                  \
1745
        return;                                                               \
1746
    }                                                                         \
1747
    gen_op_load_fpr_FT0(rA(ctx->opcode));                                     \
1748
    gen_op_load_fpr_FT1(rB(ctx->opcode));                                     \
1749
    gen_reset_fpstatus();                                                     \
1750
    gen_op_f##op();                                                           \
1751
    if (isfloat) {                                                            \
1752
        gen_op_frsp();                                                        \
1753
    }                                                                         \
1754
    gen_op_store_FT0_fpr(rD(ctx->opcode));                                    \
1755
    gen_compute_fprf(set_fprf, Rc(ctx->opcode) != 0);                         \
1756
}
1757
#define GEN_FLOAT_AB(name, op2, inval, set_fprf, type)                        \
1758
_GEN_FLOAT_AB(name, name, 0x3F, op2, inval, 0, set_fprf, type);               \
1759
_GEN_FLOAT_AB(name##s, name, 0x3B, op2, inval, 1, set_fprf, type);
1760

    
1761
#define _GEN_FLOAT_AC(name, op, op1, op2, inval, isfloat, set_fprf, type)     \
1762
GEN_HANDLER(f##name, op1, op2, 0xFF, inval, type)                             \
1763
{                                                                             \
1764
    if (unlikely(!ctx->fpu_enabled)) {                                        \
1765
        GEN_EXCP_NO_FP(ctx);                                                  \
1766
        return;                                                               \
1767
    }                                                                         \
1768
    gen_op_load_fpr_FT0(rA(ctx->opcode));                                     \
1769
    gen_op_load_fpr_FT1(rC(ctx->opcode));                                     \
1770
    gen_reset_fpstatus();                                                     \
1771
    gen_op_f##op();                                                           \
1772
    if (isfloat) {                                                            \
1773
        gen_op_frsp();                                                        \
1774
    }                                                                         \
1775
    gen_op_store_FT0_fpr(rD(ctx->opcode));                                    \
1776
    gen_compute_fprf(set_fprf, Rc(ctx->opcode) != 0);                         \
1777
}
1778
#define GEN_FLOAT_AC(name, op2, inval, set_fprf, type)                        \
1779
_GEN_FLOAT_AC(name, name, 0x3F, op2, inval, 0, set_fprf, type);               \
1780
_GEN_FLOAT_AC(name##s, name, 0x3B, op2, inval, 1, set_fprf, type);
1781

    
1782
#define GEN_FLOAT_B(name, op2, op3, set_fprf, type)                           \
1783
GEN_HANDLER(f##name, 0x3F, op2, op3, 0x001F0000, type)                        \
1784
{                                                                             \
1785
    if (unlikely(!ctx->fpu_enabled)) {                                        \
1786
        GEN_EXCP_NO_FP(ctx);                                                  \
1787
        return;                                                               \
1788
    }                                                                         \
1789
    gen_op_load_fpr_FT0(rB(ctx->opcode));                                     \
1790
    gen_reset_fpstatus();                                                     \
1791
    gen_op_f##name();                                                         \
1792
    gen_op_store_FT0_fpr(rD(ctx->opcode));                                    \
1793
    gen_compute_fprf(set_fprf, Rc(ctx->opcode) != 0);                         \
1794
}
1795

    
1796
#define GEN_FLOAT_BS(name, op1, op2, set_fprf, type)                          \
1797
GEN_HANDLER(f##name, op1, op2, 0xFF, 0x001F07C0, type)                        \
1798
{                                                                             \
1799
    if (unlikely(!ctx->fpu_enabled)) {                                        \
1800
        GEN_EXCP_NO_FP(ctx);                                                  \
1801
        return;                                                               \
1802
    }                                                                         \
1803
    gen_op_load_fpr_FT0(rB(ctx->opcode));                                     \
1804
    gen_reset_fpstatus();                                                     \
1805
    gen_op_f##name();                                                         \
1806
    gen_op_store_FT0_fpr(rD(ctx->opcode));                                    \
1807
    gen_compute_fprf(set_fprf, Rc(ctx->opcode) != 0);                         \
1808
}
1809

    
1810
/* fadd - fadds */
1811
GEN_FLOAT_AB(add, 0x15, 0x000007C0, 1, PPC_FLOAT);
1812
/* fdiv - fdivs */
1813
GEN_FLOAT_AB(div, 0x12, 0x000007C0, 1, PPC_FLOAT);
1814
/* fmul - fmuls */
1815
GEN_FLOAT_AC(mul, 0x19, 0x0000F800, 1, PPC_FLOAT);
1816

    
1817
/* fre */
1818
GEN_FLOAT_BS(re, 0x3F, 0x18, 1, PPC_FLOAT_EXT);
1819

    
1820
/* fres */
1821
GEN_FLOAT_BS(res, 0x3B, 0x18, 1, PPC_FLOAT_FRES);
1822

    
1823
/* frsqrte */
1824
GEN_FLOAT_BS(rsqrte, 0x3F, 0x1A, 1, PPC_FLOAT_FRSQRTE);
1825

    
1826
/* frsqrtes */
1827
static always_inline void gen_op_frsqrtes (void)
1828
{
1829
    gen_op_frsqrte();
1830
    gen_op_frsp();
1831
}
1832
GEN_FLOAT_BS(rsqrtes, 0x3B, 0x1A, 1, PPC_FLOAT_FRSQRTES);
1833

    
1834
/* fsel */
1835
_GEN_FLOAT_ACB(sel, sel, 0x3F, 0x17, 0, 0, PPC_FLOAT_FSEL);
1836
/* fsub - fsubs */
1837
GEN_FLOAT_AB(sub, 0x14, 0x000007C0, 1, PPC_FLOAT);
1838
/* Optional: */
1839
/* fsqrt */
1840
GEN_HANDLER(fsqrt, 0x3F, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT)
1841
{
1842
    if (unlikely(!ctx->fpu_enabled)) {
1843
        GEN_EXCP_NO_FP(ctx);
1844
        return;
1845
    }
1846
    gen_op_load_fpr_FT0(rB(ctx->opcode));
1847
    gen_reset_fpstatus();
1848
    gen_op_fsqrt();
1849
    gen_op_store_FT0_fpr(rD(ctx->opcode));
1850
    gen_compute_fprf(1, Rc(ctx->opcode) != 0);
1851
}
1852

    
1853
GEN_HANDLER(fsqrts, 0x3B, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT)
1854
{
1855
    if (unlikely(!ctx->fpu_enabled)) {
1856
        GEN_EXCP_NO_FP(ctx);
1857
        return;
1858
    }
1859
    gen_op_load_fpr_FT0(rB(ctx->opcode));
1860
    gen_reset_fpstatus();
1861
    gen_op_fsqrt();
1862
    gen_op_frsp();
1863
    gen_op_store_FT0_fpr(rD(ctx->opcode));
1864
    gen_compute_fprf(1, Rc(ctx->opcode) != 0);
1865
}
1866

    
1867
/***                     Floating-Point multiply-and-add                   ***/
1868
/* fmadd - fmadds */
1869
GEN_FLOAT_ACB(madd, 0x1D, 1, PPC_FLOAT);
1870
/* fmsub - fmsubs */
1871
GEN_FLOAT_ACB(msub, 0x1C, 1, PPC_FLOAT);
1872
/* fnmadd - fnmadds */
1873
GEN_FLOAT_ACB(nmadd, 0x1F, 1, PPC_FLOAT);
1874
/* fnmsub - fnmsubs */
1875
GEN_FLOAT_ACB(nmsub, 0x1E, 1, PPC_FLOAT);
1876

    
1877
/***                     Floating-Point round & convert                    ***/
1878
/* fctiw */
1879
GEN_FLOAT_B(ctiw, 0x0E, 0x00, 0, PPC_FLOAT);
1880
/* fctiwz */
1881
GEN_FLOAT_B(ctiwz, 0x0F, 0x00, 0, PPC_FLOAT);
1882
/* frsp */
1883
GEN_FLOAT_B(rsp, 0x0C, 0x00, 1, PPC_FLOAT);
1884
#if defined(TARGET_PPC64)
1885
/* fcfid */
1886
GEN_FLOAT_B(cfid, 0x0E, 0x1A, 1, PPC_64B);
1887
/* fctid */
1888
GEN_FLOAT_B(ctid, 0x0E, 0x19, 0, PPC_64B);
1889
/* fctidz */
1890
GEN_FLOAT_B(ctidz, 0x0F, 0x19, 0, PPC_64B);
1891
#endif
1892

    
1893
/* frin */
1894
GEN_FLOAT_B(rin, 0x08, 0x0C, 1, PPC_FLOAT_EXT);
1895
/* friz */
1896
GEN_FLOAT_B(riz, 0x08, 0x0D, 1, PPC_FLOAT_EXT);
1897
/* frip */
1898
GEN_FLOAT_B(rip, 0x08, 0x0E, 1, PPC_FLOAT_EXT);
1899
/* frim */
1900
GEN_FLOAT_B(rim, 0x08, 0x0F, 1, PPC_FLOAT_EXT);
1901

    
1902
/***                         Floating-Point compare                        ***/
1903
/* fcmpo */
1904
GEN_HANDLER(fcmpo, 0x3F, 0x00, 0x01, 0x00600001, PPC_FLOAT)
1905
{
1906
    if (unlikely(!ctx->fpu_enabled)) {
1907
        GEN_EXCP_NO_FP(ctx);
1908
        return;
1909
    }
1910
    gen_op_load_fpr_FT0(rA(ctx->opcode));
1911
    gen_op_load_fpr_FT1(rB(ctx->opcode));
1912
    gen_reset_fpstatus();
1913
    gen_op_fcmpo();
1914
    gen_op_store_T0_crf(crfD(ctx->opcode));
1915
    gen_op_float_check_status();
1916
}
1917

    
1918
/* fcmpu */
1919
GEN_HANDLER(fcmpu, 0x3F, 0x00, 0x00, 0x00600001, PPC_FLOAT)
1920
{
1921
    if (unlikely(!ctx->fpu_enabled)) {
1922
        GEN_EXCP_NO_FP(ctx);
1923
        return;
1924
    }
1925
    gen_op_load_fpr_FT0(rA(ctx->opcode));
1926
    gen_op_load_fpr_FT1(rB(ctx->opcode));
1927
    gen_reset_fpstatus();
1928
    gen_op_fcmpu();
1929
    gen_op_store_T0_crf(crfD(ctx->opcode));
1930
    gen_op_float_check_status();
1931
}
1932

    
1933
/***                         Floating-point move                           ***/
1934
/* fabs */
1935
/* XXX: beware that fabs never checks for NaNs nor update FPSCR */
1936
GEN_FLOAT_B(abs, 0x08, 0x08, 0, PPC_FLOAT);
1937

    
1938
/* fmr  - fmr. */
1939
/* XXX: beware that fmr never checks for NaNs nor update FPSCR */
1940
GEN_HANDLER(fmr, 0x3F, 0x08, 0x02, 0x001F0000, PPC_FLOAT)
1941
{
1942
    if (unlikely(!ctx->fpu_enabled)) {
1943
        GEN_EXCP_NO_FP(ctx);
1944
        return;
1945
    }
1946
    gen_op_load_fpr_FT0(rB(ctx->opcode));
1947
    gen_op_store_FT0_fpr(rD(ctx->opcode));
1948
    gen_compute_fprf(0, Rc(ctx->opcode) != 0);
1949
}
1950

    
1951
/* fnabs */
1952
/* XXX: beware that fnabs never checks for NaNs nor update FPSCR */
1953
GEN_FLOAT_B(nabs, 0x08, 0x04, 0, PPC_FLOAT);
1954
/* fneg */
1955
/* XXX: beware that fneg never checks for NaNs nor update FPSCR */
1956
GEN_FLOAT_B(neg, 0x08, 0x01, 0, PPC_FLOAT);
1957

    
1958
/***                  Floating-Point status & ctrl register                ***/
1959
/* mcrfs */
1960
GEN_HANDLER(mcrfs, 0x3F, 0x00, 0x02, 0x0063F801, PPC_FLOAT)
1961
{
1962
    int bfa;
1963

    
1964
    if (unlikely(!ctx->fpu_enabled)) {
1965
        GEN_EXCP_NO_FP(ctx);
1966
        return;
1967
    }
1968
    gen_optimize_fprf();
1969
    bfa = 4 * (7 - crfS(ctx->opcode));
1970
    gen_op_load_fpscr_T0(bfa);
1971
    gen_op_store_T0_crf(crfD(ctx->opcode));
1972
    gen_op_fpscr_resetbit(~(0xF << bfa));
1973
}
1974

    
1975
/* mffs */
1976
GEN_HANDLER(mffs, 0x3F, 0x07, 0x12, 0x001FF800, PPC_FLOAT)
1977
{
1978
    if (unlikely(!ctx->fpu_enabled)) {
1979
        GEN_EXCP_NO_FP(ctx);
1980
        return;
1981
    }
1982
    gen_optimize_fprf();
1983
    gen_reset_fpstatus();
1984
    gen_op_load_fpscr_FT0();
1985
    gen_op_store_FT0_fpr(rD(ctx->opcode));
1986
    gen_compute_fprf(0, Rc(ctx->opcode) != 0);
1987
}
1988

    
1989
/* mtfsb0 */
1990
GEN_HANDLER(mtfsb0, 0x3F, 0x06, 0x02, 0x001FF800, PPC_FLOAT)
1991
{
1992
    uint8_t crb;
1993

    
1994
    if (unlikely(!ctx->fpu_enabled)) {
1995
        GEN_EXCP_NO_FP(ctx);
1996
        return;
1997
    }
1998
    crb = 32 - (crbD(ctx->opcode) >> 2);
1999
    gen_optimize_fprf();
2000
    gen_reset_fpstatus();
2001
    if (likely(crb != 30 && crb != 29))
2002
        gen_op_fpscr_resetbit(~(1 << crb));
2003
    if (unlikely(Rc(ctx->opcode) != 0)) {
2004
        gen_op_load_fpcc();
2005
        gen_op_set_Rc0();
2006
    }
2007
}
2008

    
2009
/* mtfsb1 */
2010
GEN_HANDLER(mtfsb1, 0x3F, 0x06, 0x01, 0x001FF800, PPC_FLOAT)
2011
{
2012
    uint8_t crb;
2013

    
2014
    if (unlikely(!ctx->fpu_enabled)) {
2015
        GEN_EXCP_NO_FP(ctx);
2016
        return;
2017
    }
2018
    crb = 32 - (crbD(ctx->opcode) >> 2);
2019
    gen_optimize_fprf();
2020
    gen_reset_fpstatus();
2021
    /* XXX: we pretend we can only do IEEE floating-point computations */
2022
    if (likely(crb != FPSCR_FEX && crb != FPSCR_VX && crb != FPSCR_NI))
2023
        gen_op_fpscr_setbit(crb);
2024
    if (unlikely(Rc(ctx->opcode) != 0)) {
2025
        gen_op_load_fpcc();
2026
        gen_op_set_Rc0();
2027
    }
2028
    /* We can raise a differed exception */
2029
    gen_op_float_check_status();
2030
}
2031

    
2032
/* mtfsf */
2033
GEN_HANDLER(mtfsf, 0x3F, 0x07, 0x16, 0x02010000, PPC_FLOAT)
2034
{
2035
    if (unlikely(!ctx->fpu_enabled)) {
2036
        GEN_EXCP_NO_FP(ctx);
2037
        return;
2038
    }
2039
    gen_optimize_fprf();
2040
    gen_op_load_fpr_FT0(rB(ctx->opcode));
2041
    gen_reset_fpstatus();
2042
    gen_op_store_fpscr(FM(ctx->opcode));
2043
    if (unlikely(Rc(ctx->opcode) != 0)) {
2044
        gen_op_load_fpcc();
2045
        gen_op_set_Rc0();
2046
    }
2047
    /* We can raise a differed exception */
2048
    gen_op_float_check_status();
2049
}
2050

    
2051
/* mtfsfi */
2052
GEN_HANDLER(mtfsfi, 0x3F, 0x06, 0x04, 0x006f0800, PPC_FLOAT)
2053
{
2054
    int bf, sh;
2055

    
2056
    if (unlikely(!ctx->fpu_enabled)) {
2057
        GEN_EXCP_NO_FP(ctx);
2058
        return;
2059
    }
2060
    bf = crbD(ctx->opcode) >> 2;
2061
    sh = 7 - bf;
2062
    gen_optimize_fprf();
2063
    gen_op_set_FT0(FPIMM(ctx->opcode) << (4 * sh));
2064
    gen_reset_fpstatus();
2065
    gen_op_store_fpscr(1 << sh);
2066
    if (unlikely(Rc(ctx->opcode) != 0)) {
2067
        gen_op_load_fpcc();
2068
        gen_op_set_Rc0();
2069
    }
2070
    /* We can raise a differed exception */
2071
    gen_op_float_check_status();
2072
}
2073

    
2074
/***                           Addressing modes                            ***/
2075
/* Register indirect with immediate index : EA = (rA|0) + SIMM */
2076
static always_inline void gen_addr_imm_index (DisasContext *ctx,
2077
                                              target_long maskl)
2078
{
2079
    target_long simm = SIMM(ctx->opcode);
2080

    
2081
    simm &= ~maskl;
2082
    if (rA(ctx->opcode) == 0) {
2083
        tcg_gen_movi_tl(cpu_T[0], simm);
2084
    } else {
2085
        gen_op_load_gpr_T0(rA(ctx->opcode));
2086
        if (likely(simm != 0))
2087
            gen_op_addi(simm);
2088
    }
2089
#ifdef DEBUG_MEMORY_ACCESSES
2090
    gen_op_print_mem_EA();
2091
#endif
2092
}
2093

    
2094
static always_inline void gen_addr_reg_index (DisasContext *ctx)
2095
{
2096
    if (rA(ctx->opcode) == 0) {
2097
        gen_op_load_gpr_T0(rB(ctx->opcode));
2098
    } else {
2099
        gen_op_load_gpr_T0(rA(ctx->opcode));
2100
        gen_op_load_gpr_T1(rB(ctx->opcode));
2101
        gen_op_add();
2102
    }
2103
#ifdef DEBUG_MEMORY_ACCESSES
2104
    gen_op_print_mem_EA();
2105
#endif
2106
}
2107

    
2108
static always_inline void gen_addr_register (DisasContext *ctx)
2109
{
2110
    if (rA(ctx->opcode) == 0) {
2111
        tcg_gen_movi_tl(cpu_T[0], 0);
2112
    } else {
2113
        gen_op_load_gpr_T0(rA(ctx->opcode));
2114
    }
2115
#ifdef DEBUG_MEMORY_ACCESSES
2116
    gen_op_print_mem_EA();
2117
#endif
2118
}
2119

    
2120
#if defined(TARGET_PPC64)
2121
#define _GEN_MEM_FUNCS(name, mode)                                            \
2122
    &gen_op_##name##_##mode,                                                  \
2123
    &gen_op_##name##_le_##mode,                                               \
2124
    &gen_op_##name##_64_##mode,                                               \
2125
    &gen_op_##name##_le_64_##mode
2126
#else
2127
#define _GEN_MEM_FUNCS(name, mode)                                            \
2128
    &gen_op_##name##_##mode,                                                  \
2129
    &gen_op_##name##_le_##mode
2130
#endif
2131
#if defined(CONFIG_USER_ONLY)
2132
#if defined(TARGET_PPC64)
2133
#define NB_MEM_FUNCS 4
2134
#else
2135
#define NB_MEM_FUNCS 2
2136
#endif
2137
#define GEN_MEM_FUNCS(name)                                                   \
2138
    _GEN_MEM_FUNCS(name, raw)
2139
#else
2140
#if defined(TARGET_PPC64)
2141
#define NB_MEM_FUNCS 12
2142
#else
2143
#define NB_MEM_FUNCS 6
2144
#endif
2145
#define GEN_MEM_FUNCS(name)                                                   \
2146
    _GEN_MEM_FUNCS(name, user),                                               \
2147
    _GEN_MEM_FUNCS(name, kernel),                                             \
2148
    _GEN_MEM_FUNCS(name, hypv)
2149
#endif
2150

    
2151
/***                             Integer load                              ***/
2152
#define op_ldst(name)        (*gen_op_##name[ctx->mem_idx])()
2153
/* Byte access routine are endian safe */
2154
#define gen_op_lbz_le_raw       gen_op_lbz_raw
2155
#define gen_op_lbz_le_user      gen_op_lbz_user
2156
#define gen_op_lbz_le_kernel    gen_op_lbz_kernel
2157
#define gen_op_lbz_le_hypv      gen_op_lbz_hypv
2158
#define gen_op_lbz_le_64_raw    gen_op_lbz_64_raw
2159
#define gen_op_lbz_le_64_user   gen_op_lbz_64_user
2160
#define gen_op_lbz_le_64_kernel gen_op_lbz_64_kernel
2161
#define gen_op_lbz_le_64_hypv   gen_op_lbz_64_hypv
2162
#define gen_op_stb_le_raw       gen_op_stb_raw
2163
#define gen_op_stb_le_user      gen_op_stb_user
2164
#define gen_op_stb_le_kernel    gen_op_stb_kernel
2165
#define gen_op_stb_le_hypv      gen_op_stb_hypv
2166
#define gen_op_stb_le_64_raw    gen_op_stb_64_raw
2167
#define gen_op_stb_le_64_user   gen_op_stb_64_user
2168
#define gen_op_stb_le_64_kernel gen_op_stb_64_kernel
2169
#define gen_op_stb_le_64_hypv   gen_op_stb_64_hypv
2170
#define OP_LD_TABLE(width)                                                    \
2171
static GenOpFunc *gen_op_l##width[NB_MEM_FUNCS] = {                           \
2172
    GEN_MEM_FUNCS(l##width),                                                  \
2173
};
2174
#define OP_ST_TABLE(width)                                                    \
2175
static GenOpFunc *gen_op_st##width[NB_MEM_FUNCS] = {                          \
2176
    GEN_MEM_FUNCS(st##width),                                                 \
2177
};
2178

    
2179
#define GEN_LD(width, opc, type)                                              \
2180
GEN_HANDLER(l##width, opc, 0xFF, 0xFF, 0x00000000, type)                      \
2181
{                                                                             \
2182
    gen_addr_imm_index(ctx, 0);                                               \
2183
    op_ldst(l##width);                                                        \
2184
    gen_op_store_T1_gpr(rD(ctx->opcode));                                     \
2185
}
2186

    
2187
#define GEN_LDU(width, opc, type)                                             \
2188
GEN_HANDLER(l##width##u, opc, 0xFF, 0xFF, 0x00000000, type)                   \
2189
{                                                                             \
2190
    if (unlikely(rA(ctx->opcode) == 0 ||                                      \
2191
                 rA(ctx->opcode) == rD(ctx->opcode))) {                       \
2192
        GEN_EXCP_INVAL(ctx);                                                  \
2193
        return;                                                               \
2194
    }                                                                         \
2195
    if (type == PPC_64B)                                                      \
2196
        gen_addr_imm_index(ctx, 0x03);                                        \
2197
    else                                                                      \
2198
        gen_addr_imm_index(ctx, 0);                                           \
2199
    op_ldst(l##width);                                                        \
2200
    gen_op_store_T1_gpr(rD(ctx->opcode));                                     \
2201
    gen_op_store_T0_gpr(rA(ctx->opcode));                                     \
2202
}
2203

    
2204
#define GEN_LDUX(width, opc2, opc3, type)                                     \
2205
GEN_HANDLER(l##width##ux, 0x1F, opc2, opc3, 0x00000001, type)                 \
2206
{                                                                             \
2207
    if (unlikely(rA(ctx->opcode) == 0 ||                                      \
2208
                 rA(ctx->opcode) == rD(ctx->opcode))) {                       \
2209
        GEN_EXCP_INVAL(ctx);                                                  \
2210
        return;                                                               \
2211
    }                                                                         \
2212
    gen_addr_reg_index(ctx);                                                  \
2213
    op_ldst(l##width);                                                        \
2214
    gen_op_store_T1_gpr(rD(ctx->opcode));                                     \
2215
    gen_op_store_T0_gpr(rA(ctx->opcode));                                     \
2216
}
2217

    
2218
#define GEN_LDX(width, opc2, opc3, type)                                      \
2219
GEN_HANDLER(l##width##x, 0x1F, opc2, opc3, 0x00000001, type)                  \
2220
{                                                                             \
2221
    gen_addr_reg_index(ctx);                                                  \
2222
    op_ldst(l##width);                                                        \
2223
    gen_op_store_T1_gpr(rD(ctx->opcode));                                     \
2224
}
2225

    
2226
#define GEN_LDS(width, op, type)                                              \
2227
OP_LD_TABLE(width);                                                           \
2228
GEN_LD(width, op | 0x20, type);                                               \
2229
GEN_LDU(width, op | 0x21, type);                                              \
2230
GEN_LDUX(width, 0x17, op | 0x01, type);                                       \
2231
GEN_LDX(width, 0x17, op | 0x00, type)
2232

    
2233
/* lbz lbzu lbzux lbzx */
2234
GEN_LDS(bz, 0x02, PPC_INTEGER);
2235
/* lha lhau lhaux lhax */
2236
GEN_LDS(ha, 0x0A, PPC_INTEGER);
2237
/* lhz lhzu lhzux lhzx */
2238
GEN_LDS(hz, 0x08, PPC_INTEGER);
2239
/* lwz lwzu lwzux lwzx */
2240
GEN_LDS(wz, 0x00, PPC_INTEGER);
2241
#if defined(TARGET_PPC64)
2242
OP_LD_TABLE(wa);
2243
OP_LD_TABLE(d);
2244
/* lwaux */
2245
GEN_LDUX(wa, 0x15, 0x0B, PPC_64B);
2246
/* lwax */
2247
GEN_LDX(wa, 0x15, 0x0A, PPC_64B);
2248
/* ldux */
2249
GEN_LDUX(d, 0x15, 0x01, PPC_64B);
2250
/* ldx */
2251
GEN_LDX(d, 0x15, 0x00, PPC_64B);
2252
GEN_HANDLER(ld, 0x3A, 0xFF, 0xFF, 0x00000000, PPC_64B)
2253
{
2254
    if (Rc(ctx->opcode)) {
2255
        if (unlikely(rA(ctx->opcode) == 0 ||
2256
                     rA(ctx->opcode) == rD(ctx->opcode))) {
2257
            GEN_EXCP_INVAL(ctx);
2258
            return;
2259
        }
2260
    }
2261
    gen_addr_imm_index(ctx, 0x03);
2262
    if (ctx->opcode & 0x02) {
2263
        /* lwa (lwau is undefined) */
2264
        op_ldst(lwa);
2265
    } else {
2266
        /* ld - ldu */
2267
        op_ldst(ld);
2268
    }
2269
    gen_op_store_T1_gpr(rD(ctx->opcode));
2270
    if (Rc(ctx->opcode))
2271
        gen_op_store_T0_gpr(rA(ctx->opcode));
2272
}
2273
/* lq */
2274
GEN_HANDLER(lq, 0x38, 0xFF, 0xFF, 0x00000000, PPC_64BX)
2275
{
2276
#if defined(CONFIG_USER_ONLY)
2277
    GEN_EXCP_PRIVOPC(ctx);
2278
#else
2279
    int ra, rd;
2280

    
2281
    /* Restore CPU state */
2282
    if (unlikely(ctx->supervisor == 0)) {
2283
        GEN_EXCP_PRIVOPC(ctx);
2284
        return;
2285
    }
2286
    ra = rA(ctx->opcode);
2287
    rd = rD(ctx->opcode);
2288
    if (unlikely((rd & 1) || rd == ra)) {
2289
        GEN_EXCP_INVAL(ctx);
2290
        return;
2291
    }
2292
    if (unlikely(ctx->mem_idx & 1)) {
2293
        /* Little-endian mode is not handled */
2294
        GEN_EXCP(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_LE);
2295
        return;
2296
    }
2297
    gen_addr_imm_index(ctx, 0x0F);
2298
    op_ldst(ld);
2299
    gen_op_store_T1_gpr(rd);
2300
    gen_op_addi(8);
2301
    op_ldst(ld);
2302
    gen_op_store_T1_gpr(rd + 1);
2303
#endif
2304
}
2305
#endif
2306

    
2307
/***                              Integer store                            ***/
2308
#define GEN_ST(width, opc, type)                                              \
2309
GEN_HANDLER(st##width, opc, 0xFF, 0xFF, 0x00000000, type)                     \
2310
{                                                                             \
2311
    gen_addr_imm_index(ctx, 0);                                               \
2312
    gen_op_load_gpr_T1(rS(ctx->opcode));                                      \
2313
    op_ldst(st##width);                                                       \
2314
}
2315

    
2316
#define GEN_STU(width, opc, type)                                             \
2317
GEN_HANDLER(st##width##u, opc, 0xFF, 0xFF, 0x00000000, type)                  \
2318
{                                                                             \
2319
    if (unlikely(rA(ctx->opcode) == 0)) {                                     \
2320
        GEN_EXCP_INVAL(ctx);                                                  \
2321
        return;                                                               \
2322
    }                                                                         \
2323
    if (type == PPC_64B)                                                      \
2324
        gen_addr_imm_index(ctx, 0x03);                                        \
2325
    else                                                                      \
2326
        gen_addr_imm_index(ctx, 0);                                           \
2327
    gen_op_load_gpr_T1(rS(ctx->opcode));                                      \
2328
    op_ldst(st##width);                                                       \
2329
    gen_op_store_T0_gpr(rA(ctx->opcode));                                     \
2330
}
2331

    
2332
#define GEN_STUX(width, opc2, opc3, type)                                     \
2333
GEN_HANDLER(st##width##ux, 0x1F, opc2, opc3, 0x00000001, type)                \
2334
{                                                                             \
2335
    if (unlikely(rA(ctx->opcode) == 0)) {                                     \
2336
        GEN_EXCP_INVAL(ctx);                                                  \
2337
        return;                                                               \
2338
    }                                                                         \
2339
    gen_addr_reg_index(ctx);                                                  \
2340
    gen_op_load_gpr_T1(rS(ctx->opcode));                                      \
2341
    op_ldst(st##width);                                                       \
2342
    gen_op_store_T0_gpr(rA(ctx->opcode));                                     \
2343
}
2344

    
2345
#define GEN_STX(width, opc2, opc3, type)                                      \
2346
GEN_HANDLER(st##width##x, 0x1F, opc2, opc3, 0x00000001, type)                 \
2347
{                                                                             \
2348
    gen_addr_reg_index(ctx);                                                  \
2349
    gen_op_load_gpr_T1(rS(ctx->opcode));                                      \
2350
    op_ldst(st##width);                                                       \
2351
}
2352

    
2353
#define GEN_STS(width, op, type)                                              \
2354
OP_ST_TABLE(width);                                                           \
2355
GEN_ST(width, op | 0x20, type);                                               \
2356
GEN_STU(width, op | 0x21, type);                                              \
2357
GEN_STUX(width, 0x17, op | 0x01, type);                                       \
2358
GEN_STX(width, 0x17, op | 0x00, type)
2359

    
2360
/* stb stbu stbux stbx */
2361
GEN_STS(b, 0x06, PPC_INTEGER);
2362
/* sth sthu sthux sthx */
2363
GEN_STS(h, 0x0C, PPC_INTEGER);
2364
/* stw stwu stwux stwx */
2365
GEN_STS(w, 0x04, PPC_INTEGER);
2366
#if defined(TARGET_PPC64)
2367
OP_ST_TABLE(d);
2368
GEN_STUX(d, 0x15, 0x05, PPC_64B);
2369
GEN_STX(d, 0x15, 0x04, PPC_64B);
2370
GEN_HANDLER(std, 0x3E, 0xFF, 0xFF, 0x00000000, PPC_64B)
2371
{
2372
    int rs;
2373

    
2374
    rs = rS(ctx->opcode);
2375
    if ((ctx->opcode & 0x3) == 0x2) {
2376
#if defined(CONFIG_USER_ONLY)
2377
        GEN_EXCP_PRIVOPC(ctx);
2378
#else
2379
        /* stq */
2380
        if (unlikely(ctx->supervisor == 0)) {
2381
            GEN_EXCP_PRIVOPC(ctx);
2382
            return;
2383
        }
2384
        if (unlikely(rs & 1)) {
2385
            GEN_EXCP_INVAL(ctx);
2386
            return;
2387
        }
2388
        if (unlikely(ctx->mem_idx & 1)) {
2389
            /* Little-endian mode is not handled */
2390
            GEN_EXCP(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_LE);
2391
            return;
2392
        }
2393
        gen_addr_imm_index(ctx, 0x03);
2394
        gen_op_load_gpr_T1(rs);
2395
        op_ldst(std);
2396
        gen_op_addi(8);
2397
        gen_op_load_gpr_T1(rs + 1);
2398
        op_ldst(std);
2399
#endif
2400
    } else {
2401
        /* std / stdu */
2402
        if (Rc(ctx->opcode)) {
2403
            if (unlikely(rA(ctx->opcode) == 0)) {
2404
                GEN_EXCP_INVAL(ctx);
2405
                return;
2406
            }
2407
        }
2408
        gen_addr_imm_index(ctx, 0x03);
2409
        gen_op_load_gpr_T1(rs);
2410
        op_ldst(std);
2411
        if (Rc(ctx->opcode))
2412
            gen_op_store_T0_gpr(rA(ctx->opcode));
2413
    }
2414
}
2415
#endif
2416
/***                Integer load and store with byte reverse               ***/
2417
/* lhbrx */
2418
OP_LD_TABLE(hbr);
2419
GEN_LDX(hbr, 0x16, 0x18, PPC_INTEGER);
2420
/* lwbrx */
2421
OP_LD_TABLE(wbr);
2422
GEN_LDX(wbr, 0x16, 0x10, PPC_INTEGER);
2423
/* sthbrx */
2424
OP_ST_TABLE(hbr);
2425
GEN_STX(hbr, 0x16, 0x1C, PPC_INTEGER);
2426
/* stwbrx */
2427
OP_ST_TABLE(wbr);
2428
GEN_STX(wbr, 0x16, 0x14, PPC_INTEGER);
2429

    
2430
/***                    Integer load and store multiple                    ***/
2431
#define op_ldstm(name, reg) (*gen_op_##name[ctx->mem_idx])(reg)
2432
static GenOpFunc1 *gen_op_lmw[NB_MEM_FUNCS] = {
2433
    GEN_MEM_FUNCS(lmw),
2434
};
2435
static GenOpFunc1 *gen_op_stmw[NB_MEM_FUNCS] = {
2436
    GEN_MEM_FUNCS(stmw),
2437
};
2438

    
2439
/* lmw */
2440
GEN_HANDLER(lmw, 0x2E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
2441
{
2442
    /* NIP cannot be restored if the memory exception comes from an helper */
2443
    gen_update_nip(ctx, ctx->nip - 4);
2444
    gen_addr_imm_index(ctx, 0);
2445
    op_ldstm(lmw, rD(ctx->opcode));
2446
}
2447

    
2448
/* stmw */
2449
GEN_HANDLER(stmw, 0x2F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
2450
{
2451
    /* NIP cannot be restored if the memory exception comes from an helper */
2452
    gen_update_nip(ctx, ctx->nip - 4);
2453
    gen_addr_imm_index(ctx, 0);
2454
    op_ldstm(stmw, rS(ctx->opcode));
2455
}
2456

    
2457
/***                    Integer load and store strings                     ***/
2458
#define op_ldsts(name, start) (*gen_op_##name[ctx->mem_idx])(start)
2459
#define op_ldstsx(name, rd, ra, rb) (*gen_op_##name[ctx->mem_idx])(rd, ra, rb)
2460
/* string load & stores are by definition endian-safe */
2461
#define gen_op_lswi_le_raw       gen_op_lswi_raw
2462
#define gen_op_lswi_le_user      gen_op_lswi_user
2463
#define gen_op_lswi_le_kernel    gen_op_lswi_kernel
2464
#define gen_op_lswi_le_hypv      gen_op_lswi_hypv
2465
#define gen_op_lswi_le_64_raw    gen_op_lswi_raw
2466
#define gen_op_lswi_le_64_user   gen_op_lswi_user
2467
#define gen_op_lswi_le_64_kernel gen_op_lswi_kernel
2468
#define gen_op_lswi_le_64_hypv   gen_op_lswi_hypv
2469
static GenOpFunc1 *gen_op_lswi[NB_MEM_FUNCS] = {
2470
    GEN_MEM_FUNCS(lswi),
2471
};
2472
#define gen_op_lswx_le_raw       gen_op_lswx_raw
2473
#define gen_op_lswx_le_user      gen_op_lswx_user
2474
#define gen_op_lswx_le_kernel    gen_op_lswx_kernel
2475
#define gen_op_lswx_le_hypv      gen_op_lswx_hypv
2476
#define gen_op_lswx_le_64_raw    gen_op_lswx_raw
2477
#define gen_op_lswx_le_64_user   gen_op_lswx_user
2478
#define gen_op_lswx_le_64_kernel gen_op_lswx_kernel
2479
#define gen_op_lswx_le_64_hypv   gen_op_lswx_hypv
2480
static GenOpFunc3 *gen_op_lswx[NB_MEM_FUNCS] = {
2481
    GEN_MEM_FUNCS(lswx),
2482
};
2483
#define gen_op_stsw_le_raw       gen_op_stsw_raw
2484
#define gen_op_stsw_le_user      gen_op_stsw_user
2485
#define gen_op_stsw_le_kernel    gen_op_stsw_kernel
2486
#define gen_op_stsw_le_hypv      gen_op_stsw_hypv
2487
#define gen_op_stsw_le_64_raw    gen_op_stsw_raw
2488
#define gen_op_stsw_le_64_user   gen_op_stsw_user
2489
#define gen_op_stsw_le_64_kernel gen_op_stsw_kernel
2490
#define gen_op_stsw_le_64_hypv   gen_op_stsw_hypv
2491
static GenOpFunc1 *gen_op_stsw[NB_MEM_FUNCS] = {
2492
    GEN_MEM_FUNCS(stsw),
2493
};
2494

    
2495
/* lswi */
2496
/* PowerPC32 specification says we must generate an exception if
2497
 * rA is in the range of registers to be loaded.
2498
 * In an other hand, IBM says this is valid, but rA won't be loaded.
2499
 * For now, I'll follow the spec...
2500
 */
2501
GEN_HANDLER(lswi, 0x1F, 0x15, 0x12, 0x00000001, PPC_STRING)
2502
{
2503
    int nb = NB(ctx->opcode);
2504
    int start = rD(ctx->opcode);
2505
    int ra = rA(ctx->opcode);
2506
    int nr;
2507

    
2508
    if (nb == 0)
2509
        nb = 32;
2510
    nr = nb / 4;
2511
    if (unlikely(((start + nr) > 32  &&
2512
                  start <= ra && (start + nr - 32) > ra) ||
2513
                 ((start + nr) <= 32 && start <= ra && (start + nr) > ra))) {
2514
        GEN_EXCP(ctx, POWERPC_EXCP_PROGRAM,
2515
                 POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_LSWX);
2516
        return;
2517
    }
2518
    /* NIP cannot be restored if the memory exception comes from an helper */
2519
    gen_update_nip(ctx, ctx->nip - 4);
2520
    gen_addr_register(ctx);
2521
    tcg_gen_movi_tl(cpu_T[1], nb);
2522
    op_ldsts(lswi, start);
2523
}
2524

    
2525
/* lswx */
2526
GEN_HANDLER(lswx, 0x1F, 0x15, 0x10, 0x00000001, PPC_STRING)
2527
{
2528
    int ra = rA(ctx->opcode);
2529
    int rb = rB(ctx->opcode);
2530

    
2531
    /* NIP cannot be restored if the memory exception comes from an helper */
2532
    gen_update_nip(ctx, ctx->nip - 4);
2533
    gen_addr_reg_index(ctx);
2534
    if (ra == 0) {
2535
        ra = rb;
2536
    }
2537
    gen_op_load_xer_bc();
2538
    op_ldstsx(lswx, rD(ctx->opcode), ra, rb);
2539
}
2540

    
2541
/* stswi */
2542
GEN_HANDLER(stswi, 0x1F, 0x15, 0x16, 0x00000001, PPC_STRING)
2543
{
2544
    int nb = NB(ctx->opcode);
2545

    
2546
    /* NIP cannot be restored if the memory exception comes from an helper */
2547
    gen_update_nip(ctx, ctx->nip - 4);
2548
    gen_addr_register(ctx);
2549
    if (nb == 0)
2550
        nb = 32;
2551
    tcg_gen_movi_tl(cpu_T[1], nb);
2552
    op_ldsts(stsw, rS(ctx->opcode));
2553
}
2554

    
2555
/* stswx */
2556
GEN_HANDLER(stswx, 0x1F, 0x15, 0x14, 0x00000001, PPC_STRING)
2557
{
2558
    /* NIP cannot be restored if the memory exception comes from an helper */
2559
    gen_update_nip(ctx, ctx->nip - 4);
2560
    gen_addr_reg_index(ctx);
2561
    gen_op_load_xer_bc();
2562
    op_ldsts(stsw, rS(ctx->opcode));
2563
}
2564

    
2565
/***                        Memory synchronisation                         ***/
2566
/* eieio */
2567
GEN_HANDLER(eieio, 0x1F, 0x16, 0x1A, 0x03FFF801, PPC_MEM_EIEIO)
2568
{
2569
}
2570

    
2571
/* isync */
2572
GEN_HANDLER(isync, 0x13, 0x16, 0x04, 0x03FFF801, PPC_MEM)
2573
{
2574
    GEN_STOP(ctx);
2575
}
2576

    
2577
#define op_lwarx() (*gen_op_lwarx[ctx->mem_idx])()
2578
#define op_stwcx() (*gen_op_stwcx[ctx->mem_idx])()
2579
static GenOpFunc *gen_op_lwarx[NB_MEM_FUNCS] = {
2580
    GEN_MEM_FUNCS(lwarx),
2581
};
2582
static GenOpFunc *gen_op_stwcx[NB_MEM_FUNCS] = {
2583
    GEN_MEM_FUNCS(stwcx),
2584
};
2585

    
2586
/* lwarx */
2587
GEN_HANDLER(lwarx, 0x1F, 0x14, 0x00, 0x00000001, PPC_RES)
2588
{
2589
    /* NIP cannot be restored if the memory exception comes from an helper */
2590
    gen_update_nip(ctx, ctx->nip - 4);
2591
    gen_addr_reg_index(ctx);
2592
    op_lwarx();
2593
    gen_op_store_T1_gpr(rD(ctx->opcode));
2594
}
2595

    
2596
/* stwcx. */
2597
GEN_HANDLER2(stwcx_, "stwcx.", 0x1F, 0x16, 0x04, 0x00000000, PPC_RES)
2598
{
2599
    /* NIP cannot be restored if the memory exception comes from an helper */
2600
    gen_update_nip(ctx, ctx->nip - 4);
2601
    gen_addr_reg_index(ctx);
2602
    gen_op_load_gpr_T1(rS(ctx->opcode));
2603
    op_stwcx();
2604
}
2605

    
2606
#if defined(TARGET_PPC64)
2607
#define op_ldarx() (*gen_op_ldarx[ctx->mem_idx])()
2608
#define op_stdcx() (*gen_op_stdcx[ctx->mem_idx])()
2609
static GenOpFunc *gen_op_ldarx[NB_MEM_FUNCS] = {
2610
    GEN_MEM_FUNCS(ldarx),
2611
};
2612
static GenOpFunc *gen_op_stdcx[NB_MEM_FUNCS] = {
2613
    GEN_MEM_FUNCS(stdcx),
2614
};
2615

    
2616
/* ldarx */
2617
GEN_HANDLER(ldarx, 0x1F, 0x14, 0x02, 0x00000001, PPC_64B)
2618
{
2619
    /* NIP cannot be restored if the memory exception comes from an helper */
2620
    gen_update_nip(ctx, ctx->nip - 4);
2621
    gen_addr_reg_index(ctx);
2622
    op_ldarx();
2623
    gen_op_store_T1_gpr(rD(ctx->opcode));
2624
}
2625

    
2626
/* stdcx. */
2627
GEN_HANDLER2(stdcx_, "stdcx.", 0x1F, 0x16, 0x06, 0x00000000, PPC_64B)
2628
{
2629
    /* NIP cannot be restored if the memory exception comes from an helper */
2630
    gen_update_nip(ctx, ctx->nip - 4);
2631
    gen_addr_reg_index(ctx);
2632
    gen_op_load_gpr_T1(rS(ctx->opcode));
2633
    op_stdcx();
2634
}
2635
#endif /* defined(TARGET_PPC64) */
2636

    
2637
/* sync */
2638
GEN_HANDLER(sync, 0x1F, 0x16, 0x12, 0x039FF801, PPC_MEM_SYNC)
2639
{
2640
}
2641

    
2642
/* wait */
2643
GEN_HANDLER(wait, 0x1F, 0x1E, 0x01, 0x03FFF801, PPC_WAIT)
2644
{
2645
    /* Stop translation, as the CPU is supposed to sleep from now */
2646
    gen_op_wait();
2647
    GEN_EXCP(ctx, EXCP_HLT, 1);
2648
}
2649

    
2650
/***                         Floating-point load                           ***/
2651
#define GEN_LDF(width, opc, type)                                             \
2652
GEN_HANDLER(l##width, opc, 0xFF, 0xFF, 0x00000000, type)                      \
2653
{                                                                             \
2654
    if (unlikely(!ctx->fpu_enabled)) {                                        \
2655
        GEN_EXCP_NO_FP(ctx);                                                  \
2656
        return;                                                               \
2657
    }                                                                         \
2658
    gen_addr_imm_index(ctx, 0);                                               \
2659
    op_ldst(l##width);                                                        \
2660
    gen_op_store_FT0_fpr(rD(ctx->opcode));                                    \
2661
}
2662

    
2663
#define GEN_LDUF(width, opc, type)                                            \
2664
GEN_HANDLER(l##width##u, opc, 0xFF, 0xFF, 0x00000000, type)                   \
2665
{                                                                             \
2666
    if (unlikely(!ctx->fpu_enabled)) {                                        \
2667
        GEN_EXCP_NO_FP(ctx);                                                  \
2668
        return;                                                               \
2669
    }                                                                         \
2670
    if (unlikely(rA(ctx->opcode) == 0)) {                                     \
2671
        GEN_EXCP_INVAL(ctx);                                                  \
2672
        return;                                                               \
2673
    }                                                                         \
2674
    gen_addr_imm_index(ctx, 0);                                               \
2675
    op_ldst(l##width);                                                        \
2676
    gen_op_store_FT0_fpr(rD(ctx->opcode));                                    \
2677
    gen_op_store_T0_gpr(rA(ctx->opcode));                                     \
2678
}
2679

    
2680
#define GEN_LDUXF(width, opc, type)                                           \
2681
GEN_HANDLER(l##width##ux, 0x1F, 0x17, opc, 0x00000001, type)                  \
2682
{                                                                             \
2683
    if (unlikely(!ctx->fpu_enabled)) {                                        \
2684
        GEN_EXCP_NO_FP(ctx);                                                  \
2685
        return;                                                               \
2686
    }                                                                         \
2687
    if (unlikely(rA(ctx->opcode) == 0)) {                                     \
2688
        GEN_EXCP_INVAL(ctx);                                                  \
2689
        return;                                                               \
2690
    }                                                                         \
2691
    gen_addr_reg_index(ctx);                                                  \
2692
    op_ldst(l##width);                                                        \
2693
    gen_op_store_FT0_fpr(rD(ctx->opcode));                                    \
2694
    gen_op_store_T0_gpr(rA(ctx->opcode));                                     \
2695
}
2696

    
2697
#define GEN_LDXF(width, opc2, opc3, type)                                     \
2698
GEN_HANDLER(l##width##x, 0x1F, opc2, opc3, 0x00000001, type)                  \
2699
{                                                                             \
2700
    if (unlikely(!ctx->fpu_enabled)) {                                        \
2701
        GEN_EXCP_NO_FP(ctx);                                                  \
2702
        return;                                                               \
2703
    }                                                                         \
2704
    gen_addr_reg_index(ctx);                                                  \
2705
    op_ldst(l##width);                                                        \
2706
    gen_op_store_FT0_fpr(rD(ctx->opcode));                                    \
2707
}
2708

    
2709
#define GEN_LDFS(width, op, type)                                             \
2710
OP_LD_TABLE(width);                                                           \
2711
GEN_LDF(width, op | 0x20, type);                                              \
2712
GEN_LDUF(width, op | 0x21, type);                                             \
2713
GEN_LDUXF(width, op | 0x01, type);                                            \
2714
GEN_LDXF(width, 0x17, op | 0x00, type)
2715

    
2716
/* lfd lfdu lfdux lfdx */
2717
GEN_LDFS(fd, 0x12, PPC_FLOAT);
2718
/* lfs lfsu lfsux lfsx */
2719
GEN_LDFS(fs, 0x10, PPC_FLOAT);
2720

    
2721
/***                         Floating-point store                          ***/
2722
#define GEN_STF(width, opc, type)                                             \
2723
GEN_HANDLER(st##width, opc, 0xFF, 0xFF, 0x00000000, type)                     \
2724
{                                                                             \
2725
    if (unlikely(!ctx->fpu_enabled)) {                                        \
2726
        GEN_EXCP_NO_FP(ctx);                                                  \
2727
        return;                                                               \
2728
    }                                                                         \
2729
    gen_addr_imm_index(ctx, 0);                                               \
2730
    gen_op_load_fpr_FT0(rS(ctx->opcode));                                     \
2731
    op_ldst(st##width);                                                       \
2732
}
2733

    
2734
#define GEN_STUF(width, opc, type)                                            \
2735
GEN_HANDLER(st##width##u, opc, 0xFF, 0xFF, 0x00000000, type)                  \
2736
{                                                                             \
2737
    if (unlikely(!ctx->fpu_enabled)) {                                        \
2738
        GEN_EXCP_NO_FP(ctx);                                                  \
2739
        return;                                                               \
2740
    }                                                                         \
2741
    if (unlikely(rA(ctx->opcode) == 0)) {                                     \
2742
        GEN_EXCP_INVAL(ctx);                                                  \
2743
        return;                                                               \
2744
    }                                                                         \
2745
    gen_addr_imm_index(ctx, 0);                                               \
2746
    gen_op_load_fpr_FT0(rS(ctx->opcode));                                     \
2747
    op_ldst(st##width);                                                       \
2748
    gen_op_store_T0_gpr(rA(ctx->opcode));                                     \
2749
}
2750

    
2751
#define GEN_STUXF(width, opc, type)                                           \
2752
GEN_HANDLER(st##width##ux, 0x1F, 0x17, opc, 0x00000001, type)                 \
2753
{                                                                             \
2754
    if (unlikely(!ctx->fpu_enabled)) {                                        \
2755
        GEN_EXCP_NO_FP(ctx);                                                  \
2756
        return;                                                               \
2757
    }                                                                         \
2758
    if (unlikely(rA(ctx->opcode) == 0)) {                                     \
2759
        GEN_EXCP_INVAL(ctx);                                                  \
2760
        return;                                                               \
2761
    }                                                                         \
2762
    gen_addr_reg_index(ctx);                                                  \
2763
    gen_op_load_fpr_FT0(rS(ctx->opcode));                                     \
2764
    op_ldst(st##width);                                                       \
2765
    gen_op_store_T0_gpr(rA(ctx->opcode));                                     \
2766
}
2767

    
2768
#define GEN_STXF(width, opc2, opc3, type)                                     \
2769
GEN_HANDLER(st##width##x, 0x1F, opc2, opc3, 0x00000001, type)                 \
2770
{                                                                             \
2771
    if (unlikely(!ctx->fpu_enabled)) {                                        \
2772
        GEN_EXCP_NO_FP(ctx);                                                  \
2773
        return;                                                               \
2774
    }                                                                         \
2775
    gen_addr_reg_index(ctx);                                                  \
2776
    gen_op_load_fpr_FT0(rS(ctx->opcode));                                     \
2777
    op_ldst(st##width);                                                       \
2778
}
2779

    
2780
#define GEN_STFS(width, op, type)                                             \
2781
OP_ST_TABLE(width);                                                           \
2782
GEN_STF(width, op | 0x20, type);                                              \
2783
GEN_STUF(width, op | 0x21, type);                                             \
2784
GEN_STUXF(width, op | 0x01, type);                                            \
2785
GEN_STXF(width, 0x17, op | 0x00, type)
2786

    
2787
/* stfd stfdu stfdux stfdx */
2788
GEN_STFS(fd, 0x16, PPC_FLOAT);
2789
/* stfs stfsu stfsux stfsx */
2790
GEN_STFS(fs, 0x14, PPC_FLOAT);
2791

    
2792
/* Optional: */
2793
/* stfiwx */
2794
OP_ST_TABLE(fiw);
2795
GEN_STXF(fiw, 0x17, 0x1E, PPC_FLOAT_STFIWX);
2796

    
2797
/***                                Branch                                 ***/
2798
static always_inline void gen_goto_tb (DisasContext *ctx, int n,
2799
                                       target_ulong dest)
2800
{
2801
    TranslationBlock *tb;
2802
    tb = ctx->tb;
2803
    if ((tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK) &&
2804
        likely(!ctx->singlestep_enabled)) {
2805
        tcg_gen_goto_tb(n);
2806
        tcg_gen_movi_tl(cpu_T[1], dest);
2807
#if defined(TARGET_PPC64)
2808
        if (ctx->sf_mode)
2809
            gen_op_b_T1_64();
2810
        else
2811
#endif
2812
            gen_op_b_T1();
2813
        tcg_gen_exit_tb((long)tb + n);
2814
    } else {
2815
        tcg_gen_movi_tl(cpu_T[1], dest);
2816
#if defined(TARGET_PPC64)
2817
        if (ctx->sf_mode)
2818
            gen_op_b_T1_64();
2819
        else
2820
#endif
2821
            gen_op_b_T1();
2822
        if (unlikely(ctx->singlestep_enabled)) {
2823
            if ((ctx->singlestep_enabled &
2824
                 (CPU_BRANCH_STEP | CPU_SINGLE_STEP)) &&
2825
                ctx->exception == POWERPC_EXCP_BRANCH) {
2826
                target_ulong tmp = ctx->nip;
2827
                ctx->nip = dest;
2828
                GEN_EXCP(ctx, POWERPC_EXCP_TRACE, 0);
2829
                ctx->nip = tmp;
2830
            }
2831
            if (ctx->singlestep_enabled & GDBSTUB_SINGLE_STEP) {
2832
                gen_update_nip(ctx, dest);
2833
                gen_op_debug();
2834
            }
2835
        }
2836
        tcg_gen_exit_tb(0);
2837
    }
2838
}
2839

    
2840
static always_inline void gen_setlr (DisasContext *ctx, target_ulong nip)
2841
{
2842
#if defined(TARGET_PPC64)
2843
    if (ctx->sf_mode != 0 && (nip >> 32))
2844
        gen_op_setlr_64(ctx->nip >> 32, ctx->nip);
2845
    else
2846
#endif
2847
        gen_op_setlr(ctx->nip);
2848
}
2849

    
2850
/* b ba bl bla */
2851
GEN_HANDLER(b, 0x12, 0xFF, 0xFF, 0x00000000, PPC_FLOW)
2852
{
2853
    target_ulong li, target;
2854

    
2855
    ctx->exception = POWERPC_EXCP_BRANCH;
2856
    /* sign extend LI */
2857
#if defined(TARGET_PPC64)
2858
    if (ctx->sf_mode)
2859
        li = ((int64_t)LI(ctx->opcode) << 38) >> 38;
2860
    else
2861
#endif
2862
        li = ((int32_t)LI(ctx->opcode) << 6) >> 6;
2863
    if (likely(AA(ctx->opcode) == 0))
2864
        target = ctx->nip + li - 4;
2865
    else
2866
        target = li;
2867
#if defined(TARGET_PPC64)
2868
    if (!ctx->sf_mode)
2869
        target = (uint32_t)target;
2870
#endif
2871
    if (LK(ctx->opcode))
2872
        gen_setlr(ctx, ctx->nip);
2873
    gen_goto_tb(ctx, 0, target);
2874
}
2875

    
2876
#define BCOND_IM  0
2877
#define BCOND_LR  1
2878
#define BCOND_CTR 2
2879

    
2880
static always_inline void gen_bcond (DisasContext *ctx, int type)
2881
{
2882
    target_ulong target = 0;
2883
    target_ulong li;
2884
    uint32_t bo = BO(ctx->opcode);
2885
    uint32_t bi = BI(ctx->opcode);
2886
    uint32_t mask;
2887

    
2888
    ctx->exception = POWERPC_EXCP_BRANCH;
2889
    if ((bo & 0x4) == 0)
2890
        gen_op_dec_ctr();
2891
    switch(type) {
2892
    case BCOND_IM:
2893
        li = (target_long)((int16_t)(BD(ctx->opcode)));
2894
        if (likely(AA(ctx->opcode) == 0)) {
2895
            target = ctx->nip + li - 4;
2896
        } else {
2897
            target = li;
2898
        }
2899
#if defined(TARGET_PPC64)
2900
        if (!ctx->sf_mode)
2901
            target = (uint32_t)target;
2902
#endif
2903
        break;
2904
    case BCOND_CTR:
2905
        gen_op_movl_T1_ctr();
2906
        break;
2907
    default:
2908
    case BCOND_LR:
2909
        gen_op_movl_T1_lr();
2910
        break;
2911
    }
2912
    if (LK(ctx->opcode))
2913
        gen_setlr(ctx, ctx->nip);
2914
    if (bo & 0x10) {
2915
        /* No CR condition */
2916
        switch (bo & 0x6) {
2917
        case 0:
2918
#if defined(TARGET_PPC64)
2919
            if (ctx->sf_mode)
2920
                gen_op_test_ctr_64();
2921
            else
2922
#endif
2923
                gen_op_test_ctr();
2924
            break;
2925
        case 2:
2926
#if defined(TARGET_PPC64)
2927
            if (ctx->sf_mode)
2928
                gen_op_test_ctrz_64();
2929
            else
2930
#endif
2931
                gen_op_test_ctrz();
2932
            break;
2933
        default:
2934
        case 4:
2935
        case 6:
2936
            if (type == BCOND_IM) {
2937
                gen_goto_tb(ctx, 0, target);
2938
                return;
2939
            } else {
2940
#if defined(TARGET_PPC64)
2941
                if (ctx->sf_mode)
2942
                    gen_op_b_T1_64();
2943
                else
2944
#endif
2945
                    gen_op_b_T1();
2946
                goto no_test;
2947
            }
2948
            break;
2949
        }
2950
    } else {
2951
        mask = 1 << (3 - (bi & 0x03));
2952
        gen_op_load_crf_T0(bi >> 2);
2953
        if (bo & 0x8) {
2954
            switch (bo & 0x6) {
2955
            case 0:
2956
#if defined(TARGET_PPC64)
2957
                if (ctx->sf_mode)
2958
                    gen_op_test_ctr_true_64(mask);
2959
                else
2960
#endif
2961
                    gen_op_test_ctr_true(mask);
2962
                break;
2963
            case 2:
2964
#if defined(TARGET_PPC64)
2965
                if (ctx->sf_mode)
2966
                    gen_op_test_ctrz_true_64(mask);
2967
                else
2968
#endif
2969
                    gen_op_test_ctrz_true(mask);
2970
                break;
2971
            default:
2972
            case 4:
2973
            case 6:
2974
                gen_op_test_true(mask);
2975
                break;
2976
            }
2977
        } else {
2978
            switch (bo & 0x6) {
2979
            case 0:
2980
#if defined(TARGET_PPC64)
2981
                if (ctx->sf_mode)
2982
                    gen_op_test_ctr_false_64(mask);
2983
                else
2984
#endif
2985
                    gen_op_test_ctr_false(mask);
2986
                break;
2987
            case 2:
2988
#if defined(TARGET_PPC64)
2989
                if (ctx->sf_mode)
2990
                    gen_op_test_ctrz_false_64(mask);
2991
                else
2992
#endif
2993
                    gen_op_test_ctrz_false(mask);
2994
                break;
2995
            default:
2996
            case 4:
2997
            case 6:
2998
                gen_op_test_false(mask);
2999
                break;
3000
            }
3001
        }
3002
    }
3003
    if (type == BCOND_IM) {
3004
        int l1 = gen_new_label();
3005
        gen_op_jz_T0(l1);
3006
        gen_goto_tb(ctx, 0, target);
3007
        gen_set_label(l1);
3008
        gen_goto_tb(ctx, 1, ctx->nip);
3009
    } else {
3010
#if defined(TARGET_PPC64)
3011
        if (ctx->sf_mode)
3012
            gen_op_btest_T1_64(ctx->nip >> 32, ctx->nip);
3013
        else
3014
#endif
3015
            gen_op_btest_T1(ctx->nip);
3016
    no_test:
3017
        if (ctx->singlestep_enabled & GDBSTUB_SINGLE_STEP) {
3018
            gen_update_nip(ctx, ctx->nip);
3019
            gen_op_debug();
3020
        }
3021
        tcg_gen_exit_tb(0);
3022
    }
3023
}
3024

    
3025
GEN_HANDLER(bc, 0x10, 0xFF, 0xFF, 0x00000000, PPC_FLOW)
3026
{
3027
    gen_bcond(ctx, BCOND_IM);
3028
}
3029

    
3030
GEN_HANDLER(bcctr, 0x13, 0x10, 0x10, 0x00000000, PPC_FLOW)
3031
{
3032
    gen_bcond(ctx, BCOND_CTR);
3033
}
3034

    
3035
GEN_HANDLER(bclr, 0x13, 0x10, 0x00, 0x00000000, PPC_FLOW)
3036
{
3037
    gen_bcond(ctx, BCOND_LR);
3038
}
3039

    
3040
/***                      Condition register logical                       ***/
3041
#define GEN_CRLOGIC(op, opc)                                                  \
3042
GEN_HANDLER(cr##op, 0x13, 0x01, opc, 0x00000001, PPC_INTEGER)                 \
3043
{                                                                             \
3044
    uint8_t bitmask;                                                          \
3045
    int sh;                                                                   \
3046
    gen_op_load_crf_T0(crbA(ctx->opcode) >> 2);                               \
3047
    sh = (crbD(ctx->opcode) & 0x03) - (crbA(ctx->opcode) & 0x03);             \
3048
    if (sh > 0)                                                               \
3049
        gen_op_srli_T0(sh);                                                   \
3050
    else if (sh < 0)                                                          \
3051
        gen_op_sli_T0(-sh);                                                   \
3052
    gen_op_load_crf_T1(crbB(ctx->opcode) >> 2);                               \
3053
    sh = (crbD(ctx->opcode) & 0x03) - (crbB(ctx->opcode) & 0x03);             \
3054
    if (sh > 0)                                                               \
3055
        gen_op_srli_T1(sh);                                                   \
3056
    else if (sh < 0)                                                          \
3057
        gen_op_sli_T1(-sh);                                                   \
3058
    gen_op_##op();                                                            \
3059
    bitmask = 1 << (3 - (crbD(ctx->opcode) & 0x03));                          \
3060
    gen_op_andi_T0(bitmask);                                                  \
3061
    gen_op_load_crf_T1(crbD(ctx->opcode) >> 2);                               \
3062
    gen_op_andi_T1(~bitmask);                                                 \
3063
    gen_op_or();                                                              \
3064
    gen_op_store_T0_crf(crbD(ctx->opcode) >> 2);                              \
3065
}
3066

    
3067
/* crand */
3068
GEN_CRLOGIC(and, 0x08);
3069
/* crandc */
3070
GEN_CRLOGIC(andc, 0x04);
3071
/* creqv */
3072
GEN_CRLOGIC(eqv, 0x09);
3073
/* crnand */
3074
GEN_CRLOGIC(nand, 0x07);
3075
/* crnor */
3076
GEN_CRLOGIC(nor, 0x01);
3077
/* cror */
3078
GEN_CRLOGIC(or, 0x0E);
3079
/* crorc */
3080
GEN_CRLOGIC(orc, 0x0D);
3081
/* crxor */
3082
GEN_CRLOGIC(xor, 0x06);
3083
/* mcrf */
3084
GEN_HANDLER(mcrf, 0x13, 0x00, 0xFF, 0x00000001, PPC_INTEGER)
3085
{
3086
    gen_op_load_crf_T0(crfS(ctx->opcode));
3087
    gen_op_store_T0_crf(crfD(ctx->opcode));
3088
}
3089

    
3090
/***                           System linkage                              ***/
3091
/* rfi (supervisor only) */
3092
GEN_HANDLER(rfi, 0x13, 0x12, 0x01, 0x03FF8001, PPC_FLOW)
3093
{
3094
#if defined(CONFIG_USER_ONLY)
3095
    GEN_EXCP_PRIVOPC(ctx);
3096
#else
3097
    /* Restore CPU state */
3098
    if (unlikely(!ctx->supervisor)) {
3099
        GEN_EXCP_PRIVOPC(ctx);
3100
        return;
3101
    }
3102
    gen_op_rfi();
3103
    GEN_SYNC(ctx);
3104
#endif
3105
}
3106

    
3107
#if defined(TARGET_PPC64)
3108
GEN_HANDLER(rfid, 0x13, 0x12, 0x00, 0x03FF8001, PPC_64B)
3109
{
3110
#if defined(CONFIG_USER_ONLY)
3111
    GEN_EXCP_PRIVOPC(ctx);
3112
#else
3113
    /* Restore CPU state */
3114
    if (unlikely(!ctx->supervisor)) {
3115
        GEN_EXCP_PRIVOPC(ctx);
3116
        return;
3117
    }
3118
    gen_op_rfid();
3119
    GEN_SYNC(ctx);
3120
#endif
3121
}
3122

    
3123
GEN_HANDLER(hrfid, 0x13, 0x12, 0x08, 0x03FF8001, PPC_64H)
3124
{
3125
#if defined(CONFIG_USER_ONLY)
3126
    GEN_EXCP_PRIVOPC(ctx);
3127
#else
3128
    /* Restore CPU state */
3129
    if (unlikely(ctx->supervisor <= 1)) {
3130
        GEN_EXCP_PRIVOPC(ctx);
3131
        return;
3132
    }
3133
    gen_op_hrfid();
3134
    GEN_SYNC(ctx);
3135
#endif
3136
}
3137
#endif
3138

    
3139
/* sc */
3140
#if defined(CONFIG_USER_ONLY)
3141
#define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL_USER
3142
#else
3143
#define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL
3144
#endif
3145
GEN_HANDLER(sc, 0x11, 0xFF, 0xFF, 0x03FFF01D, PPC_FLOW)
3146
{
3147
    uint32_t lev;
3148

    
3149
    lev = (ctx->opcode >> 5) & 0x7F;
3150
    GEN_EXCP(ctx, POWERPC_SYSCALL, lev);
3151
}
3152

    
3153
/***                                Trap                                   ***/
3154
/* tw */
3155
GEN_HANDLER(tw, 0x1F, 0x04, 0x00, 0x00000001, PPC_FLOW)
3156
{
3157
    gen_op_load_gpr_T0(rA(ctx->opcode));
3158
    gen_op_load_gpr_T1(rB(ctx->opcode));
3159
    /* Update the nip since this might generate a trap exception */
3160
    gen_update_nip(ctx, ctx->nip);
3161
    gen_op_tw(TO(ctx->opcode));
3162
}
3163

    
3164
/* twi */
3165
GEN_HANDLER(twi, 0x03, 0xFF, 0xFF, 0x00000000, PPC_FLOW)
3166
{
3167
    gen_op_load_gpr_T0(rA(ctx->opcode));
3168
    tcg_gen_movi_tl(cpu_T[1], SIMM(ctx->opcode));
3169
    /* Update the nip since this might generate a trap exception */
3170
    gen_update_nip(ctx, ctx->nip);
3171
    gen_op_tw(TO(ctx->opcode));
3172
}
3173

    
3174
#if defined(TARGET_PPC64)
3175
/* td */
3176
GEN_HANDLER(td, 0x1F, 0x04, 0x02, 0x00000001, PPC_64B)
3177
{
3178
    gen_op_load_gpr_T0(rA(ctx->opcode));
3179
    gen_op_load_gpr_T1(rB(ctx->opcode));
3180
    /* Update the nip since this might generate a trap exception */
3181
    gen_update_nip(ctx, ctx->nip);
3182
    gen_op_td(TO(ctx->opcode));
3183
}
3184

    
3185
/* tdi */
3186
GEN_HANDLER(tdi, 0x02, 0xFF, 0xFF, 0x00000000, PPC_64B)
3187
{
3188
    gen_op_load_gpr_T0(rA(ctx->opcode));
3189
    tcg_gen_movi_tl(cpu_T[1], SIMM(ctx->opcode));
3190
    /* Update the nip since this might generate a trap exception */
3191
    gen_update_nip(ctx, ctx->nip);
3192
    gen_op_td(TO(ctx->opcode));
3193
}
3194
#endif
3195

    
3196
/***                          Processor control                            ***/
3197
/* mcrxr */
3198
GEN_HANDLER(mcrxr, 0x1F, 0x00, 0x10, 0x007FF801, PPC_MISC)
3199
{
3200
    gen_op_load_xer_cr();
3201
    gen_op_store_T0_crf(crfD(ctx->opcode));
3202
    gen_op_clear_xer_ov();
3203
    gen_op_clear_xer_ca();
3204
}
3205

    
3206
/* mfcr */
3207
GEN_HANDLER(mfcr, 0x1F, 0x13, 0x00, 0x00000801, PPC_MISC)
3208
{
3209
    uint32_t crm, crn;
3210

    
3211
    if (likely(ctx->opcode & 0x00100000)) {
3212
        crm = CRM(ctx->opcode);
3213
        if (likely((crm ^ (crm - 1)) == 0)) {
3214
            crn = ffs(crm);
3215
            gen_op_load_cro(7 - crn);
3216
        }
3217
    } else {
3218
        gen_op_load_cr();
3219
    }
3220
    gen_op_store_T0_gpr(rD(ctx->opcode));
3221
}
3222

    
3223
/* mfmsr */
3224
GEN_HANDLER(mfmsr, 0x1F, 0x13, 0x02, 0x001FF801, PPC_MISC)
3225
{
3226
#if defined(CONFIG_USER_ONLY)
3227
    GEN_EXCP_PRIVREG(ctx);
3228
#else
3229
    if (unlikely(!ctx->supervisor)) {
3230
        GEN_EXCP_PRIVREG(ctx);
3231
        return;
3232
    }
3233
    gen_op_load_msr();
3234
    gen_op_store_T0_gpr(rD(ctx->opcode));
3235
#endif
3236
}
3237

    
3238
#if 1
3239
#define SPR_NOACCESS ((void *)(-1UL))
3240
#else
3241
static void spr_noaccess (void *opaque, int sprn)
3242
{
3243
    sprn = ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5);
3244
    printf("ERROR: try to access SPR %d !\n", sprn);
3245
}
3246
#define SPR_NOACCESS (&spr_noaccess)
3247
#endif
3248

    
3249
/* mfspr */
3250
static always_inline void gen_op_mfspr (DisasContext *ctx)
3251
{
3252
    void (*read_cb)(void *opaque, int sprn);
3253
    uint32_t sprn = SPR(ctx->opcode);
3254

    
3255
#if !defined(CONFIG_USER_ONLY)
3256
    if (ctx->supervisor == 2)
3257
        read_cb = ctx->spr_cb[sprn].hea_read;
3258
    else if (ctx->supervisor)
3259
        read_cb = ctx->spr_cb[sprn].oea_read;
3260
    else
3261
#endif
3262
        read_cb = ctx->spr_cb[sprn].uea_read;
3263
    if (likely(read_cb != NULL)) {
3264
        if (likely(read_cb != SPR_NOACCESS)) {
3265
            (*read_cb)(ctx, sprn);
3266
            gen_op_store_T0_gpr(rD(ctx->opcode));
3267
        } else {
3268
            /* Privilege exception */
3269
            /* This is a hack to avoid warnings when running Linux:
3270
             * this OS breaks the PowerPC virtualisation model,
3271
             * allowing userland application to read the PVR
3272
             */
3273
            if (sprn != SPR_PVR) {
3274
                if (loglevel != 0) {
3275
                    fprintf(logfile, "Trying to read privileged spr %d %03x at "
3276
                            ADDRX "\n", sprn, sprn, ctx->nip);
3277
                }
3278
                printf("Trying to read privileged spr %d %03x at " ADDRX "\n",
3279
                       sprn, sprn, ctx->nip);
3280
            }
3281
            GEN_EXCP_PRIVREG(ctx);
3282
        }
3283
    } else {
3284
        /* Not defined */
3285
        if (loglevel != 0) {
3286
            fprintf(logfile, "Trying to read invalid spr %d %03x at "
3287
                    ADDRX "\n", sprn, sprn, ctx->nip);
3288
        }
3289
        printf("Trying to read invalid spr %d %03x at " ADDRX "\n",
3290
               sprn, sprn, ctx->nip);
3291
        GEN_EXCP(ctx, POWERPC_EXCP_PROGRAM,
3292
                 POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_SPR);
3293
    }
3294
}
3295

    
3296
GEN_HANDLER(mfspr, 0x1F, 0x13, 0x0A, 0x00000001, PPC_MISC)
3297
{
3298
    gen_op_mfspr(ctx);
3299
}
3300

    
3301
/* mftb */
3302
GEN_HANDLER(mftb, 0x1F, 0x13, 0x0B, 0x00000001, PPC_MFTB)
3303
{
3304
    gen_op_mfspr(ctx);
3305
}
3306

    
3307
/* mtcrf */
3308
GEN_HANDLER(mtcrf, 0x1F, 0x10, 0x04, 0x00000801, PPC_MISC)
3309
{
3310
    uint32_t crm, crn;
3311

    
3312
    gen_op_load_gpr_T0(rS(ctx->opcode));
3313
    crm = CRM(ctx->opcode);
3314
    if (likely((ctx->opcode & 0x00100000) || (crm ^ (crm - 1)) == 0)) {
3315
        crn = ffs(crm);
3316
        gen_op_srli_T0(crn * 4);
3317
        gen_op_andi_T0(0xF);
3318
        gen_op_store_cro(7 - crn);
3319
    } else {
3320
        gen_op_store_cr(crm);
3321
    }
3322
}
3323

    
3324
/* mtmsr */
3325
#if defined(TARGET_PPC64)
3326
GEN_HANDLER(mtmsrd, 0x1F, 0x12, 0x05, 0x001EF801, PPC_64B)
3327
{
3328
#if defined(CONFIG_USER_ONLY)
3329
    GEN_EXCP_PRIVREG(ctx);
3330
#else
3331
    if (unlikely(!ctx->supervisor)) {
3332
        GEN_EXCP_PRIVREG(ctx);
3333
        return;
3334
    }
3335
    gen_op_load_gpr_T0(rS(ctx->opcode));
3336
    if (ctx->opcode & 0x00010000) {
3337
        /* Special form that does not need any synchronisation */
3338
        gen_op_update_riee();
3339
    } else {
3340
        /* XXX: we need to update nip before the store
3341
         *      if we enter power saving mode, we will exit the loop
3342
         *      directly from ppc_store_msr
3343
         */
3344
        gen_update_nip(ctx, ctx->nip);
3345
        gen_op_store_msr();
3346
        /* Must stop the translation as machine state (may have) changed */
3347
        /* Note that mtmsr is not always defined as context-synchronizing */
3348
        ctx->exception = POWERPC_EXCP_STOP;
3349
    }
3350
#endif
3351
}
3352
#endif
3353

    
3354
GEN_HANDLER(mtmsr, 0x1F, 0x12, 0x04, 0x001FF801, PPC_MISC)
3355
{
3356
#if defined(CONFIG_USER_ONLY)
3357
    GEN_EXCP_PRIVREG(ctx);
3358
#else
3359
    if (unlikely(!ctx->supervisor)) {
3360
        GEN_EXCP_PRIVREG(ctx);
3361
        return;
3362
    }
3363
    gen_op_load_gpr_T0(rS(ctx->opcode));
3364
    if (ctx->opcode & 0x00010000) {
3365
        /* Special form that does not need any synchronisation */
3366
        gen_op_update_riee();
3367
    } else {
3368
        /* XXX: we need to update nip before the store
3369
         *      if we enter power saving mode, we will exit the loop
3370
         *      directly from ppc_store_msr
3371
         */
3372
        gen_update_nip(ctx, ctx->nip);
3373
#if defined(TARGET_PPC64)
3374
        if (!ctx->sf_mode)
3375
            gen_op_store_msr_32();
3376
        else
3377
#endif
3378
            gen_op_store_msr();
3379
        /* Must stop the translation as machine state (may have) changed */
3380
        /* Note that mtmsrd is not always defined as context-synchronizing */
3381
        ctx->exception = POWERPC_EXCP_STOP;
3382
    }
3383
#endif
3384
}
3385

    
3386
/* mtspr */
3387
GEN_HANDLER(mtspr, 0x1F, 0x13, 0x0E, 0x00000001, PPC_MISC)
3388
{
3389
    void (*write_cb)(void *opaque, int sprn);
3390
    uint32_t sprn = SPR(ctx->opcode);
3391

    
3392
#if !defined(CONFIG_USER_ONLY)
3393
    if (ctx->supervisor == 2)
3394
        write_cb = ctx->spr_cb[sprn].hea_write;
3395
    else if (ctx->supervisor)
3396
        write_cb = ctx->spr_cb[sprn].oea_write;
3397
    else
3398
#endif
3399
        write_cb = ctx->spr_cb[sprn].uea_write;
3400
    if (likely(write_cb != NULL)) {
3401
        if (likely(write_cb != SPR_NOACCESS)) {
3402
            gen_op_load_gpr_T0(rS(ctx->opcode));
3403
            (*write_cb)(ctx, sprn);
3404
        } else {
3405
            /* Privilege exception */
3406
            if (loglevel != 0) {
3407
                fprintf(logfile, "Trying to write privileged spr %d %03x at "
3408
                        ADDRX "\n", sprn, sprn, ctx->nip);
3409
            }
3410
            printf("Trying to write privileged spr %d %03x at " ADDRX "\n",
3411
                   sprn, sprn, ctx->nip);
3412
            GEN_EXCP_PRIVREG(ctx);
3413
        }
3414
    } else {
3415
        /* Not defined */
3416
        if (loglevel != 0) {
3417
            fprintf(logfile, "Trying to write invalid spr %d %03x at "
3418
                    ADDRX "\n", sprn, sprn, ctx->nip);
3419
        }
3420
        printf("Trying to write invalid spr %d %03x at " ADDRX "\n",
3421
               sprn, sprn, ctx->nip);
3422
        GEN_EXCP(ctx, POWERPC_EXCP_PROGRAM,
3423
                 POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_SPR);
3424
    }
3425
}
3426

    
3427
/***                         Cache management                              ***/
3428
/* dcbf */
3429
GEN_HANDLER(dcbf, 0x1F, 0x16, 0x02, 0x03C00001, PPC_CACHE)
3430
{
3431
    /* XXX: specification says this is treated as a load by the MMU */
3432
    gen_addr_reg_index(ctx);
3433
    op_ldst(lbz);
3434
}
3435

    
3436
/* dcbi (Supervisor only) */
3437
GEN_HANDLER(dcbi, 0x1F, 0x16, 0x0E, 0x03E00001, PPC_CACHE)
3438
{
3439
#if defined(CONFIG_USER_ONLY)
3440
    GEN_EXCP_PRIVOPC(ctx);
3441
#else
3442
    if (unlikely(!ctx->supervisor)) {
3443
        GEN_EXCP_PRIVOPC(ctx);
3444
        return;
3445
    }
3446
    gen_addr_reg_index(ctx);
3447
    /* XXX: specification says this should be treated as a store by the MMU */
3448
    op_ldst(lbz);
3449
    op_ldst(stb);
3450
#endif
3451
}
3452

    
3453
/* dcdst */
3454
GEN_HANDLER(dcbst, 0x1F, 0x16, 0x01, 0x03E00001, PPC_CACHE)
3455
{
3456
    /* XXX: specification say this is treated as a load by the MMU */
3457
    gen_addr_reg_index(ctx);
3458
    op_ldst(lbz);
3459
}
3460

    
3461
/* dcbt */
3462
GEN_HANDLER(dcbt, 0x1F, 0x16, 0x08, 0x02000001, PPC_CACHE)
3463
{
3464
    /* interpreted as no-op */
3465
    /* XXX: specification say this is treated as a load by the MMU
3466
     *      but does not generate any exception
3467
     */
3468
}
3469

    
3470
/* dcbtst */
3471
GEN_HANDLER(dcbtst, 0x1F, 0x16, 0x07, 0x02000001, PPC_CACHE)
3472
{
3473
    /* interpreted as no-op */
3474
    /* XXX: specification say this is treated as a load by the MMU
3475
     *      but does not generate any exception
3476
     */
3477
}
3478

    
3479
/* dcbz */
3480
#define op_dcbz(n) (*gen_op_dcbz[n][ctx->mem_idx])()
3481
static GenOpFunc *gen_op_dcbz[4][NB_MEM_FUNCS] = {
3482
    /* 32 bytes cache line size */
3483
    {
3484
#define gen_op_dcbz_l32_le_raw        gen_op_dcbz_l32_raw
3485
#define gen_op_dcbz_l32_le_user       gen_op_dcbz_l32_user
3486
#define gen_op_dcbz_l32_le_kernel     gen_op_dcbz_l32_kernel
3487
#define gen_op_dcbz_l32_le_hypv       gen_op_dcbz_l32_hypv
3488
#define gen_op_dcbz_l32_le_64_raw     gen_op_dcbz_l32_64_raw
3489
#define gen_op_dcbz_l32_le_64_user    gen_op_dcbz_l32_64_user
3490
#define gen_op_dcbz_l32_le_64_kernel  gen_op_dcbz_l32_64_kernel
3491
#define gen_op_dcbz_l32_le_64_hypv    gen_op_dcbz_l32_64_hypv
3492
        GEN_MEM_FUNCS(dcbz_l32),
3493
    },
3494
    /* 64 bytes cache line size */
3495
    {
3496
#define gen_op_dcbz_l64_le_raw        gen_op_dcbz_l64_raw
3497
#define gen_op_dcbz_l64_le_user       gen_op_dcbz_l64_user
3498
#define gen_op_dcbz_l64_le_kernel     gen_op_dcbz_l64_kernel
3499
#define gen_op_dcbz_l64_le_hypv       gen_op_dcbz_l64_hypv
3500
#define gen_op_dcbz_l64_le_64_raw     gen_op_dcbz_l64_64_raw
3501
#define gen_op_dcbz_l64_le_64_user    gen_op_dcbz_l64_64_user
3502
#define gen_op_dcbz_l64_le_64_kernel  gen_op_dcbz_l64_64_kernel
3503
#define gen_op_dcbz_l64_le_64_hypv    gen_op_dcbz_l64_64_hypv
3504
        GEN_MEM_FUNCS(dcbz_l64),
3505
    },
3506
    /* 128 bytes cache line size */
3507
    {
3508
#define gen_op_dcbz_l128_le_raw       gen_op_dcbz_l128_raw
3509
#define gen_op_dcbz_l128_le_user      gen_op_dcbz_l128_user
3510
#define gen_op_dcbz_l128_le_kernel    gen_op_dcbz_l128_kernel
3511
#define gen_op_dcbz_l128_le_hypv      gen_op_dcbz_l128_hypv
3512
#define gen_op_dcbz_l128_le_64_raw    gen_op_dcbz_l128_64_raw
3513
#define gen_op_dcbz_l128_le_64_user   gen_op_dcbz_l128_64_user
3514
#define gen_op_dcbz_l128_le_64_kernel gen_op_dcbz_l128_64_kernel
3515
#define gen_op_dcbz_l128_le_64_hypv   gen_op_dcbz_l128_64_hypv
3516
        GEN_MEM_FUNCS(dcbz_l128),
3517
    },
3518
    /* tunable cache line size */
3519
    {
3520
#define gen_op_dcbz_le_raw            gen_op_dcbz_raw
3521
#define gen_op_dcbz_le_user           gen_op_dcbz_user
3522
#define gen_op_dcbz_le_kernel         gen_op_dcbz_kernel
3523
#define gen_op_dcbz_le_hypv           gen_op_dcbz_hypv
3524
#define gen_op_dcbz_le_64_raw         gen_op_dcbz_64_raw
3525
#define gen_op_dcbz_le_64_user        gen_op_dcbz_64_user
3526
#define gen_op_dcbz_le_64_kernel      gen_op_dcbz_64_kernel
3527
#define gen_op_dcbz_le_64_hypv        gen_op_dcbz_64_hypv
3528
        GEN_MEM_FUNCS(dcbz),
3529
    },
3530
};
3531

    
3532
static always_inline void handler_dcbz (DisasContext *ctx,
3533
                                        int dcache_line_size)
3534
{
3535
    int n;
3536

    
3537
    switch (dcache_line_size) {
3538
    case 32:
3539
        n = 0;
3540
        break;
3541
    case 64:
3542
        n = 1;
3543
        break;
3544
    case 128:
3545
        n = 2;
3546
        break;
3547
    default:
3548
        n = 3;
3549
        break;
3550
    }
3551
    op_dcbz(n);
3552
}
3553

    
3554
GEN_HANDLER(dcbz, 0x1F, 0x16, 0x1F, 0x03E00001, PPC_CACHE_DCBZ)
3555
{
3556
    gen_addr_reg_index(ctx);
3557
    handler_dcbz(ctx, ctx->dcache_line_size);
3558
    gen_op_check_reservation();
3559
}
3560

    
3561
GEN_HANDLER2(dcbz_970, "dcbz", 0x1F, 0x16, 0x1F, 0x03C00001, PPC_CACHE_DCBZT)
3562
{
3563
    gen_addr_reg_index(ctx);
3564
    if (ctx->opcode & 0x00200000)
3565
        handler_dcbz(ctx, ctx->dcache_line_size);
3566
    else
3567
        handler_dcbz(ctx, -1);
3568
    gen_op_check_reservation();
3569
}
3570

    
3571
/* icbi */
3572
#define op_icbi() (*gen_op_icbi[ctx->mem_idx])()
3573
#define gen_op_icbi_le_raw       gen_op_icbi_raw
3574
#define gen_op_icbi_le_user      gen_op_icbi_user
3575
#define gen_op_icbi_le_kernel    gen_op_icbi_kernel
3576
#define gen_op_icbi_le_hypv      gen_op_icbi_hypv
3577
#define gen_op_icbi_le_64_raw    gen_op_icbi_64_raw
3578
#define gen_op_icbi_le_64_user   gen_op_icbi_64_user
3579
#define gen_op_icbi_le_64_kernel gen_op_icbi_64_kernel
3580
#define gen_op_icbi_le_64_hypv   gen_op_icbi_64_hypv
3581
static GenOpFunc *gen_op_icbi[NB_MEM_FUNCS] = {
3582
    GEN_MEM_FUNCS(icbi),
3583
};
3584

    
3585
GEN_HANDLER(icbi, 0x1F, 0x16, 0x1E, 0x03E00001, PPC_CACHE_ICBI)
3586
{
3587
    /* NIP cannot be restored if the memory exception comes from an helper */
3588
    gen_update_nip(ctx, ctx->nip - 4);
3589
    gen_addr_reg_index(ctx);
3590
    op_icbi();
3591
}
3592

    
3593
/* Optional: */
3594
/* dcba */
3595
GEN_HANDLER(dcba, 0x1F, 0x16, 0x17, 0x03E00001, PPC_CACHE_DCBA)
3596
{
3597
    /* interpreted as no-op */
3598
    /* XXX: specification say this is treated as a store by the MMU
3599
     *      but does not generate any exception
3600
     */
3601
}
3602

    
3603
/***                    Segment register manipulation                      ***/
3604
/* Supervisor only: */
3605
/* mfsr */
3606
GEN_HANDLER(mfsr, 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT)
3607
{
3608
#if defined(CONFIG_USER_ONLY)
3609
    GEN_EXCP_PRIVREG(ctx);
3610
#else
3611
    if (unlikely(!ctx->supervisor)) {
3612
        GEN_EXCP_PRIVREG(ctx);
3613
        return;
3614
    }
3615
    tcg_gen_movi_tl(cpu_T[1], SR(ctx->opcode));
3616
    gen_op_load_sr();
3617
    gen_op_store_T0_gpr(rD(ctx->opcode));
3618
#endif
3619
}
3620

    
3621
/* mfsrin */
3622
GEN_HANDLER(mfsrin, 0x1F, 0x13, 0x14, 0x001F0001, PPC_SEGMENT)
3623
{
3624
#if defined(CONFIG_USER_ONLY)
3625
    GEN_EXCP_PRIVREG(ctx);
3626
#else
3627
    if (unlikely(!ctx->supervisor)) {
3628
        GEN_EXCP_PRIVREG(ctx);
3629
        return;
3630
    }
3631
    gen_op_load_gpr_T1(rB(ctx->opcode));
3632
    gen_op_srli_T1(28);
3633
    gen_op_load_sr();
3634
    gen_op_store_T0_gpr(rD(ctx->opcode));
3635
#endif
3636
}
3637

    
3638
/* mtsr */
3639
GEN_HANDLER(mtsr, 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT)
3640
{
3641
#if defined(CONFIG_USER_ONLY)
3642
    GEN_EXCP_PRIVREG(ctx);
3643
#else
3644
    if (unlikely(!ctx->supervisor)) {
3645
        GEN_EXCP_PRIVREG(ctx);
3646
        return;
3647
    }
3648
    gen_op_load_gpr_T0(rS(ctx->opcode));
3649
    tcg_gen_movi_tl(cpu_T[1], SR(ctx->opcode));
3650
    gen_op_store_sr();
3651
#endif
3652
}
3653

    
3654
/* mtsrin */
3655
GEN_HANDLER(mtsrin, 0x1F, 0x12, 0x07, 0x001F0001, PPC_SEGMENT)
3656
{
3657
#if defined(CONFIG_USER_ONLY)
3658
    GEN_EXCP_PRIVREG(ctx);
3659
#else
3660
    if (unlikely(!ctx->supervisor)) {
3661
        GEN_EXCP_PRIVREG(ctx);
3662
        return;
3663
    }
3664
    gen_op_load_gpr_T0(rS(ctx->opcode));
3665
    gen_op_load_gpr_T1(rB(ctx->opcode));
3666
    gen_op_srli_T1(28);
3667
    gen_op_store_sr();
3668
#endif
3669
}
3670

    
3671
#if defined(TARGET_PPC64)
3672
/* Specific implementation for PowerPC 64 "bridge" emulation using SLB */
3673
/* mfsr */
3674
GEN_HANDLER2(mfsr_64b, "mfsr", 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT_64B)
3675
{
3676
#if defined(CONFIG_USER_ONLY)
3677
    GEN_EXCP_PRIVREG(ctx);
3678
#else
3679
    if (unlikely(!ctx->supervisor)) {
3680
        GEN_EXCP_PRIVREG(ctx);
3681
        return;
3682
    }
3683
    tcg_gen_movi_tl(cpu_T[1], SR(ctx->opcode));
3684
    gen_op_load_slb();
3685
    gen_op_store_T0_gpr(rD(ctx->opcode));
3686
#endif
3687
}
3688

    
3689
/* mfsrin */
3690
GEN_HANDLER2(mfsrin_64b, "mfsrin", 0x1F, 0x13, 0x14, 0x001F0001,
3691
             PPC_SEGMENT_64B)
3692
{
3693
#if defined(CONFIG_USER_ONLY)
3694
    GEN_EXCP_PRIVREG(ctx);
3695
#else
3696
    if (unlikely(!ctx->supervisor)) {
3697
        GEN_EXCP_PRIVREG(ctx);
3698
        return;
3699
    }
3700
    gen_op_load_gpr_T1(rB(ctx->opcode));
3701
    gen_op_srli_T1(28);
3702
    gen_op_load_slb();
3703
    gen_op_store_T0_gpr(rD(ctx->opcode));
3704
#endif
3705
}
3706

    
3707
/* mtsr */
3708
GEN_HANDLER2(mtsr_64b, "mtsr", 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT_64B)
3709
{
3710
#if defined(CONFIG_USER_ONLY)
3711
    GEN_EXCP_PRIVREG(ctx);
3712
#else
3713
    if (unlikely(!ctx->supervisor)) {
3714
        GEN_EXCP_PRIVREG(ctx);
3715
        return;
3716
    }
3717
    gen_op_load_gpr_T0(rS(ctx->opcode));
3718
    tcg_gen_movi_tl(cpu_T[1], SR(ctx->opcode));
3719
    gen_op_store_slb();
3720
#endif
3721
}
3722

    
3723
/* mtsrin */
3724
GEN_HANDLER2(mtsrin_64b, "mtsrin", 0x1F, 0x12, 0x07, 0x001F0001,
3725
             PPC_SEGMENT_64B)
3726
{
3727
#if defined(CONFIG_USER_ONLY)
3728
    GEN_EXCP_PRIVREG(ctx);
3729
#else
3730
    if (unlikely(!ctx->supervisor)) {
3731
        GEN_EXCP_PRIVREG(ctx);
3732
        return;
3733
    }
3734
    gen_op_load_gpr_T0(rS(ctx->opcode));
3735
    gen_op_load_gpr_T1(rB(ctx->opcode));
3736
    gen_op_srli_T1(28);
3737
    gen_op_store_slb();
3738
#endif
3739
}
3740
#endif /* defined(TARGET_PPC64) */
3741

    
3742
/***                      Lookaside buffer management                      ***/
3743
/* Optional & supervisor only: */
3744
/* tlbia */
3745
GEN_HANDLER(tlbia, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_TLBIA)
3746
{
3747
#if defined(CONFIG_USER_ONLY)
3748
    GEN_EXCP_PRIVOPC(ctx);
3749
#else
3750
    if (unlikely(!ctx->supervisor)) {
3751
        GEN_EXCP_PRIVOPC(ctx);
3752
        return;
3753
    }
3754
    gen_op_tlbia();
3755
#endif
3756
}
3757

    
3758
/* tlbie */
3759
GEN_HANDLER(tlbie, 0x1F, 0x12, 0x09, 0x03FF0001, PPC_MEM_TLBIE)
3760
{
3761
#if defined(CONFIG_USER_ONLY)
3762
    GEN_EXCP_PRIVOPC(ctx);
3763
#else
3764
    if (unlikely(!ctx->supervisor)) {
3765
        GEN_EXCP_PRIVOPC(ctx);
3766
        return;
3767
    }
3768
    gen_op_load_gpr_T0(rB(ctx->opcode));
3769
#if defined(TARGET_PPC64)
3770
    if (ctx->sf_mode)
3771
        gen_op_tlbie_64();
3772
    else
3773
#endif
3774
        gen_op_tlbie();
3775
#endif
3776
}
3777

    
3778
/* tlbsync */
3779
GEN_HANDLER(tlbsync, 0x1F, 0x16, 0x11, 0x03FFF801, PPC_MEM_TLBSYNC)
3780
{
3781
#if defined(CONFIG_USER_ONLY)
3782
    GEN_EXCP_PRIVOPC(ctx);
3783
#else
3784
    if (unlikely(!ctx->supervisor)) {
3785
        GEN_EXCP_PRIVOPC(ctx);
3786
        return;
3787
    }
3788
    /* This has no effect: it should ensure that all previous
3789
     * tlbie have completed
3790
     */
3791
    GEN_STOP(ctx);
3792
#endif
3793
}
3794

    
3795
#if defined(TARGET_PPC64)
3796
/* slbia */
3797
GEN_HANDLER(slbia, 0x1F, 0x12, 0x0F, 0x03FFFC01, PPC_SLBI)
3798
{
3799
#if defined(CONFIG_USER_ONLY)
3800
    GEN_EXCP_PRIVOPC(ctx);
3801
#else
3802
    if (unlikely(!ctx->supervisor)) {
3803
        GEN_EXCP_PRIVOPC(ctx);
3804
        return;
3805
    }
3806
    gen_op_slbia();
3807
#endif
3808
}
3809

    
3810
/* slbie */
3811
GEN_HANDLER(slbie, 0x1F, 0x12, 0x0D, 0x03FF0001, PPC_SLBI)
3812
{
3813
#if defined(CONFIG_USER_ONLY)
3814
    GEN_EXCP_PRIVOPC(ctx);
3815
#else
3816
    if (unlikely(!ctx->supervisor)) {
3817
        GEN_EXCP_PRIVOPC(ctx);
3818
        return;
3819
    }
3820
    gen_op_load_gpr_T0(rB(ctx->opcode));
3821
    gen_op_slbie();
3822
#endif
3823
}
3824
#endif
3825

    
3826
/***                              External control                         ***/
3827
/* Optional: */
3828
#define op_eciwx() (*gen_op_eciwx[ctx->mem_idx])()
3829
#define op_ecowx() (*gen_op_ecowx[ctx->mem_idx])()
3830
static GenOpFunc *gen_op_eciwx[NB_MEM_FUNCS] = {
3831
    GEN_MEM_FUNCS(eciwx),
3832
};
3833
static GenOpFunc *gen_op_ecowx[NB_MEM_FUNCS] = {
3834
    GEN_MEM_FUNCS(ecowx),
3835
};
3836

    
3837
/* eciwx */
3838
GEN_HANDLER(eciwx, 0x1F, 0x16, 0x0D, 0x00000001, PPC_EXTERN)
3839
{
3840
    /* Should check EAR[E] & alignment ! */
3841
    gen_addr_reg_index(ctx);
3842
    op_eciwx();
3843
    gen_op_store_T0_gpr(rD(ctx->opcode));
3844
}
3845

    
3846
/* ecowx */
3847
GEN_HANDLER(ecowx, 0x1F, 0x16, 0x09, 0x00000001, PPC_EXTERN)
3848
{
3849
    /* Should check EAR[E] & alignment ! */
3850
    gen_addr_reg_index(ctx);
3851
    gen_op_load_gpr_T1(rS(ctx->opcode));
3852
    op_ecowx();
3853
}
3854

    
3855
/* PowerPC 601 specific instructions */
3856
/* abs - abs. */
3857
GEN_HANDLER(abs, 0x1F, 0x08, 0x0B, 0x0000F800, PPC_POWER_BR)
3858
{
3859
    gen_op_load_gpr_T0(rA(ctx->opcode));
3860
    gen_op_POWER_abs();
3861
    gen_op_store_T0_gpr(rD(ctx->opcode));
3862
    if (unlikely(Rc(ctx->opcode) != 0))
3863
        gen_set_Rc0(ctx);
3864
}
3865

    
3866
/* abso - abso. */
3867
GEN_HANDLER(abso, 0x1F, 0x08, 0x1B, 0x0000F800, PPC_POWER_BR)
3868
{
3869
    gen_op_load_gpr_T0(rA(ctx->opcode));
3870
    gen_op_POWER_abso();
3871
    gen_op_store_T0_gpr(rD(ctx->opcode));
3872
    if (unlikely(Rc(ctx->opcode) != 0))
3873
        gen_set_Rc0(ctx);
3874
}
3875

    
3876
/* clcs */
3877
GEN_HANDLER(clcs, 0x1F, 0x10, 0x13, 0x0000F800, PPC_POWER_BR)
3878
{
3879
    gen_op_load_gpr_T0(rA(ctx->opcode));
3880
    gen_op_POWER_clcs();
3881
    /* Rc=1 sets CR0 to an undefined state */
3882
    gen_op_store_T0_gpr(rD(ctx->opcode));
3883
}
3884

    
3885
/* div - div. */
3886
GEN_HANDLER(div, 0x1F, 0x0B, 0x0A, 0x00000000, PPC_POWER_BR)
3887
{
3888
    gen_op_load_gpr_T0(rA(ctx->opcode));
3889
    gen_op_load_gpr_T1(rB(ctx->opcode));
3890
    gen_op_POWER_div();
3891
    gen_op_store_T0_gpr(rD(ctx->opcode));
3892
    if (unlikely(Rc(ctx->opcode) != 0))
3893
        gen_set_Rc0(ctx);
3894
}
3895

    
3896
/* divo - divo. */
3897
GEN_HANDLER(divo, 0x1F, 0x0B, 0x1A, 0x00000000, PPC_POWER_BR)
3898
{
3899
    gen_op_load_gpr_T0(rA(ctx->opcode));
3900
    gen_op_load_gpr_T1(rB(ctx->opcode));
3901
    gen_op_POWER_divo();
3902
    gen_op_store_T0_gpr(rD(ctx->opcode));
3903
    if (unlikely(Rc(ctx->opcode) != 0))
3904
        gen_set_Rc0(ctx);
3905
}
3906

    
3907
/* divs - divs. */
3908
GEN_HANDLER(divs, 0x1F, 0x0B, 0x0B, 0x00000000, PPC_POWER_BR)
3909
{
3910
    gen_op_load_gpr_T0(rA(ctx->opcode));
3911
    gen_op_load_gpr_T1(rB(ctx->opcode));
3912
    gen_op_POWER_divs();
3913
    gen_op_store_T0_gpr(rD(ctx->opcode));
3914
    if (unlikely(Rc(ctx->opcode) != 0))
3915
        gen_set_Rc0(ctx);
3916
}
3917

    
3918
/* divso - divso. */
3919
GEN_HANDLER(divso, 0x1F, 0x0B, 0x1B, 0x00000000, PPC_POWER_BR)
3920
{
3921
    gen_op_load_gpr_T0(rA(ctx->opcode));
3922
    gen_op_load_gpr_T1(rB(ctx->opcode));
3923
    gen_op_POWER_divso();
3924
    gen_op_store_T0_gpr(rD(ctx->opcode));
3925
    if (unlikely(Rc(ctx->opcode) != 0))
3926
        gen_set_Rc0(ctx);
3927
}
3928

    
3929
/* doz - doz. */
3930
GEN_HANDLER(doz, 0x1F, 0x08, 0x08, 0x00000000, PPC_POWER_BR)
3931
{
3932
    gen_op_load_gpr_T0(rA(ctx->opcode));
3933
    gen_op_load_gpr_T1(rB(ctx->opcode));
3934
    gen_op_POWER_doz();
3935
    gen_op_store_T0_gpr(rD(ctx->opcode));
3936
    if (unlikely(Rc(ctx->opcode) != 0))
3937
        gen_set_Rc0(ctx);
3938
}
3939

    
3940
/* dozo - dozo. */
3941
GEN_HANDLER(dozo, 0x1F, 0x08, 0x18, 0x00000000, PPC_POWER_BR)
3942
{
3943
    gen_op_load_gpr_T0(rA(ctx->opcode));
3944
    gen_op_load_gpr_T1(rB(ctx->opcode));
3945
    gen_op_POWER_dozo();
3946
    gen_op_store_T0_gpr(rD(ctx->opcode));
3947
    if (unlikely(Rc(ctx->opcode) != 0))
3948
        gen_set_Rc0(ctx);
3949
}
3950

    
3951
/* dozi */
3952
GEN_HANDLER(dozi, 0x09, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR)
3953
{
3954
    gen_op_load_gpr_T0(rA(ctx->opcode));
3955
    tcg_gen_movi_tl(cpu_T[1], SIMM(ctx->opcode));
3956
    gen_op_POWER_doz();
3957
    gen_op_store_T0_gpr(rD(ctx->opcode));
3958
}
3959

    
3960
/* As lscbx load from memory byte after byte, it's always endian safe.
3961
 * Original POWER is 32 bits only, define 64 bits ops as 32 bits ones
3962
 */
3963
#define op_POWER_lscbx(start, ra, rb)                                         \
3964
(*gen_op_POWER_lscbx[ctx->mem_idx])(start, ra, rb)
3965
#define gen_op_POWER_lscbx_64_raw       gen_op_POWER_lscbx_raw
3966
#define gen_op_POWER_lscbx_64_user      gen_op_POWER_lscbx_user
3967
#define gen_op_POWER_lscbx_64_kernel    gen_op_POWER_lscbx_kernel
3968
#define gen_op_POWER_lscbx_64_hypv      gen_op_POWER_lscbx_hypv
3969
#define gen_op_POWER_lscbx_le_raw       gen_op_POWER_lscbx_raw
3970
#define gen_op_POWER_lscbx_le_user      gen_op_POWER_lscbx_user
3971
#define gen_op_POWER_lscbx_le_kernel    gen_op_POWER_lscbx_kernel
3972
#define gen_op_POWER_lscbx_le_hypv      gen_op_POWER_lscbx_hypv
3973
#define gen_op_POWER_lscbx_le_64_raw    gen_op_POWER_lscbx_raw
3974
#define gen_op_POWER_lscbx_le_64_user   gen_op_POWER_lscbx_user
3975
#define gen_op_POWER_lscbx_le_64_kernel gen_op_POWER_lscbx_kernel
3976
#define gen_op_POWER_lscbx_le_64_hypv   gen_op_POWER_lscbx_hypv
3977
static GenOpFunc3 *gen_op_POWER_lscbx[NB_MEM_FUNCS] = {
3978
    GEN_MEM_FUNCS(POWER_lscbx),
3979
};
3980

    
3981
/* lscbx - lscbx. */
3982
GEN_HANDLER(lscbx, 0x1F, 0x15, 0x08, 0x00000000, PPC_POWER_BR)
3983
{
3984
    int ra = rA(ctx->opcode);
3985
    int rb = rB(ctx->opcode);
3986

    
3987
    gen_addr_reg_index(ctx);
3988
    if (ra == 0) {
3989
        ra = rb;
3990
    }
3991
    /* NIP cannot be restored if the memory exception comes from an helper */
3992
    gen_update_nip(ctx, ctx->nip - 4);
3993
    gen_op_load_xer_bc();
3994
    gen_op_load_xer_cmp();
3995
    op_POWER_lscbx(rD(ctx->opcode), ra, rb);
3996
    gen_op_store_xer_bc();
3997
    if (unlikely(Rc(ctx->opcode) != 0))
3998
        gen_set_Rc0(ctx);
3999
}
4000

    
4001
/* maskg - maskg. */
4002
GEN_HANDLER(maskg, 0x1F, 0x1D, 0x00, 0x00000000, PPC_POWER_BR)
4003
{
4004
    gen_op_load_gpr_T0(rS(ctx->opcode));
4005
    gen_op_load_gpr_T1(rB(ctx->opcode));
4006
    gen_op_POWER_maskg();
4007
    gen_op_store_T0_gpr(rA(ctx->opcode));
4008
    if (unlikely(Rc(ctx->opcode) != 0))
4009
        gen_set_Rc0(ctx);
4010
}
4011

    
4012
/* maskir - maskir. */
4013
GEN_HANDLER(maskir, 0x1F, 0x1D, 0x10, 0x00000000, PPC_POWER_BR)
4014
{
4015
    gen_op_load_gpr_T0(rA(ctx->opcode));
4016
    gen_op_load_gpr_T1(rS(ctx->opcode));
4017
    gen_op_load_gpr_T2(rB(ctx->opcode));
4018
    gen_op_POWER_maskir();
4019
    gen_op_store_T0_gpr(rA(ctx->opcode));
4020
    if (unlikely(Rc(ctx->opcode) != 0))
4021
        gen_set_Rc0(ctx);
4022
}
4023

    
4024
/* mul - mul. */
4025
GEN_HANDLER(mul, 0x1F, 0x0B, 0x03, 0x00000000, PPC_POWER_BR)
4026
{
4027
    gen_op_load_gpr_T0(rA(ctx->opcode));
4028
    gen_op_load_gpr_T1(rB(ctx->opcode));
4029
    gen_op_POWER_mul();
4030
    gen_op_store_T0_gpr(rD(ctx->opcode));
4031
    if (unlikely(Rc(ctx->opcode) != 0))
4032
        gen_set_Rc0(ctx);
4033
}
4034

    
4035
/* mulo - mulo. */
4036
GEN_HANDLER(mulo, 0x1F, 0x0B, 0x13, 0x00000000, PPC_POWER_BR)
4037
{
4038
    gen_op_load_gpr_T0(rA(ctx->opcode));
4039
    gen_op_load_gpr_T1(rB(ctx->opcode));
4040
    gen_op_POWER_mulo();
4041
    gen_op_store_T0_gpr(rD(ctx->opcode));
4042
    if (unlikely(Rc(ctx->opcode) != 0))
4043
        gen_set_Rc0(ctx);
4044
}
4045

    
4046
/* nabs - nabs. */
4047
GEN_HANDLER(nabs, 0x1F, 0x08, 0x0F, 0x00000000, PPC_POWER_BR)
4048
{
4049
    gen_op_load_gpr_T0(rA(ctx->opcode));
4050
    gen_op_POWER_nabs();
4051
    gen_op_store_T0_gpr(rD(ctx->opcode));
4052
    if (unlikely(Rc(ctx->opcode) != 0))
4053
        gen_set_Rc0(ctx);
4054
}
4055

    
4056
/* nabso - nabso. */
4057
GEN_HANDLER(nabso, 0x1F, 0x08, 0x1F, 0x00000000, PPC_POWER_BR)
4058
{
4059
    gen_op_load_gpr_T0(rA(ctx->opcode));
4060
    gen_op_POWER_nabso();
4061
    gen_op_store_T0_gpr(rD(ctx->opcode));
4062
    if (unlikely(Rc(ctx->opcode) != 0))
4063
        gen_set_Rc0(ctx);
4064
}
4065

    
4066
/* rlmi - rlmi. */
4067
GEN_HANDLER(rlmi, 0x16, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR)
4068
{
4069
    uint32_t mb, me;
4070

    
4071
    mb = MB(ctx->opcode);
4072
    me = ME(ctx->opcode);
4073
    gen_op_load_gpr_T0(rS(ctx->opcode));
4074
    gen_op_load_gpr_T1(rA(ctx->opcode));
4075
    gen_op_load_gpr_T2(rB(ctx->opcode));
4076
    gen_op_POWER_rlmi(MASK(mb, me), ~MASK(mb, me));
4077
    gen_op_store_T0_gpr(rA(ctx->opcode));
4078
    if (unlikely(Rc(ctx->opcode) != 0))
4079
        gen_set_Rc0(ctx);
4080
}
4081

    
4082
/* rrib - rrib. */
4083
GEN_HANDLER(rrib, 0x1F, 0x19, 0x10, 0x00000000, PPC_POWER_BR)
4084
{
4085
    gen_op_load_gpr_T0(rS(ctx->opcode));
4086
    gen_op_load_gpr_T1(rA(ctx->opcode));
4087
    gen_op_load_gpr_T2(rB(ctx->opcode));
4088
    gen_op_POWER_rrib();
4089
    gen_op_store_T0_gpr(rA(ctx->opcode));
4090
    if (unlikely(Rc(ctx->opcode) != 0))
4091
        gen_set_Rc0(ctx);
4092
}
4093

    
4094
/* sle - sle. */
4095
GEN_HANDLER(sle, 0x1F, 0x19, 0x04, 0x00000000, PPC_POWER_BR)
4096
{
4097
    gen_op_load_gpr_T0(rS(ctx->opcode));
4098
    gen_op_load_gpr_T1(rB(ctx->opcode));
4099
    gen_op_POWER_sle();
4100
    gen_op_store_T0_gpr(rA(ctx->opcode));
4101
    if (unlikely(Rc(ctx->opcode) != 0))
4102
        gen_set_Rc0(ctx);
4103
}
4104

    
4105
/* sleq - sleq. */
4106
GEN_HANDLER(sleq, 0x1F, 0x19, 0x06, 0x00000000, PPC_POWER_BR)
4107
{
4108
    gen_op_load_gpr_T0(rS(ctx->opcode));
4109
    gen_op_load_gpr_T1(rB(ctx->opcode));
4110
    gen_op_POWER_sleq();
4111
    gen_op_store_T0_gpr(rA(ctx->opcode));
4112
    if (unlikely(Rc(ctx->opcode) != 0))
4113
        gen_set_Rc0(ctx);
4114
}
4115

    
4116
/* sliq - sliq. */
4117
GEN_HANDLER(sliq, 0x1F, 0x18, 0x05, 0x00000000, PPC_POWER_BR)
4118
{
4119
    gen_op_load_gpr_T0(rS(ctx->opcode));
4120
    tcg_gen_movi_tl(cpu_T[1], SH(ctx->opcode));
4121
    gen_op_POWER_sle();
4122
    gen_op_store_T0_gpr(rA(ctx->opcode));
4123
    if (unlikely(Rc(ctx->opcode) != 0))
4124
        gen_set_Rc0(ctx);
4125
}
4126

    
4127
/* slliq - slliq. */
4128
GEN_HANDLER(slliq, 0x1F, 0x18, 0x07, 0x00000000, PPC_POWER_BR)
4129
{
4130
    gen_op_load_gpr_T0(rS(ctx->opcode));
4131
    tcg_gen_movi_tl(cpu_T[1], SH(ctx->opcode));
4132
    gen_op_POWER_sleq();
4133
    gen_op_store_T0_gpr(rA(ctx->opcode));
4134
    if (unlikely(Rc(ctx->opcode) != 0))
4135
        gen_set_Rc0(ctx);
4136
}
4137

    
4138
/* sllq - sllq. */
4139
GEN_HANDLER(sllq, 0x1F, 0x18, 0x06, 0x00000000, PPC_POWER_BR)
4140
{
4141
    gen_op_load_gpr_T0(rS(ctx->opcode));
4142
    gen_op_load_gpr_T1(rB(ctx->opcode));
4143
    gen_op_POWER_sllq();
4144
    gen_op_store_T0_gpr(rA(ctx->opcode));
4145
    if (unlikely(Rc(ctx->opcode) != 0))
4146
        gen_set_Rc0(ctx);
4147
}
4148

    
4149
/* slq - slq. */
4150
GEN_HANDLER(slq, 0x1F, 0x18, 0x04, 0x00000000, PPC_POWER_BR)
4151
{
4152
    gen_op_load_gpr_T0(rS(ctx->opcode));
4153
    gen_op_load_gpr_T1(rB(ctx->opcode));
4154
    gen_op_POWER_slq();
4155
    gen_op_store_T0_gpr(rA(ctx->opcode));
4156
    if (unlikely(Rc(ctx->opcode) != 0))
4157
        gen_set_Rc0(ctx);
4158
}
4159

    
4160
/* sraiq - sraiq. */
4161
GEN_HANDLER(sraiq, 0x1F, 0x18, 0x1D, 0x00000000, PPC_POWER_BR)
4162
{
4163
    gen_op_load_gpr_T0(rS(ctx->opcode));
4164
    tcg_gen_movi_tl(cpu_T[1], SH(ctx->opcode));
4165
    gen_op_POWER_sraq();
4166
    gen_op_store_T0_gpr(rA(ctx->opcode));
4167
    if (unlikely(Rc(ctx->opcode) != 0))
4168
        gen_set_Rc0(ctx);
4169
}
4170

    
4171
/* sraq - sraq. */
4172
GEN_HANDLER(sraq, 0x1F, 0x18, 0x1C, 0x00000000, PPC_POWER_BR)
4173
{
4174
    gen_op_load_gpr_T0(rS(ctx->opcode));
4175
    gen_op_load_gpr_T1(rB(ctx->opcode));
4176
    gen_op_POWER_sraq();
4177
    gen_op_store_T0_gpr(rA(ctx->opcode));
4178
    if (unlikely(Rc(ctx->opcode) != 0))
4179
        gen_set_Rc0(ctx);
4180
}
4181

    
4182
/* sre - sre. */
4183
GEN_HANDLER(sre, 0x1F, 0x19, 0x14, 0x00000000, PPC_POWER_BR)
4184
{
4185
    gen_op_load_gpr_T0(rS(ctx->opcode));
4186
    gen_op_load_gpr_T1(rB(ctx->opcode));
4187
    gen_op_POWER_sre();
4188
    gen_op_store_T0_gpr(rA(ctx->opcode));
4189
    if (unlikely(Rc(ctx->opcode) != 0))
4190
        gen_set_Rc0(ctx);
4191
}
4192

    
4193
/* srea - srea. */
4194
GEN_HANDLER(srea, 0x1F, 0x19, 0x1C, 0x00000000, PPC_POWER_BR)
4195
{
4196
    gen_op_load_gpr_T0(rS(ctx->opcode));
4197
    gen_op_load_gpr_T1(rB(ctx->opcode));
4198
    gen_op_POWER_srea();
4199
    gen_op_store_T0_gpr(rA(ctx->opcode));
4200
    if (unlikely(Rc(ctx->opcode) != 0))
4201
        gen_set_Rc0(ctx);
4202
}
4203

    
4204
/* sreq */
4205
GEN_HANDLER(sreq, 0x1F, 0x19, 0x16, 0x00000000, PPC_POWER_BR)
4206
{
4207
    gen_op_load_gpr_T0(rS(ctx->opcode));
4208
    gen_op_load_gpr_T1(rB(ctx->opcode));
4209
    gen_op_POWER_sreq();
4210
    gen_op_store_T0_gpr(rA(ctx->opcode));
4211
    if (unlikely(Rc(ctx->opcode) != 0))
4212
        gen_set_Rc0(ctx);
4213
}
4214

    
4215
/* sriq */
4216
GEN_HANDLER(sriq, 0x1F, 0x18, 0x15, 0x00000000, PPC_POWER_BR)
4217
{
4218
    gen_op_load_gpr_T0(rS(ctx->opcode));
4219
    tcg_gen_movi_tl(cpu_T[1], SH(ctx->opcode));
4220
    gen_op_POWER_srq();
4221
    gen_op_store_T0_gpr(rA(ctx->opcode));
4222
    if (unlikely(Rc(ctx->opcode) != 0))
4223
        gen_set_Rc0(ctx);
4224
}
4225

    
4226
/* srliq */
4227
GEN_HANDLER(srliq, 0x1F, 0x18, 0x17, 0x00000000, PPC_POWER_BR)
4228
{
4229
    gen_op_load_gpr_T0(rS(ctx->opcode));
4230
    gen_op_load_gpr_T1(rB(ctx->opcode));
4231
    tcg_gen_movi_tl(cpu_T[1], SH(ctx->opcode));
4232
    gen_op_POWER_srlq();
4233
    gen_op_store_T0_gpr(rA(ctx->opcode));
4234
    if (unlikely(Rc(ctx->opcode) != 0))
4235
        gen_set_Rc0(ctx);
4236
}
4237

    
4238
/* srlq */
4239
GEN_HANDLER(srlq, 0x1F, 0x18, 0x16, 0x00000000, PPC_POWER_BR)
4240
{
4241
    gen_op_load_gpr_T0(rS(ctx->opcode));
4242
    gen_op_load_gpr_T1(rB(ctx->opcode));
4243
    gen_op_POWER_srlq();
4244
    gen_op_store_T0_gpr(rA(ctx->opcode));
4245
    if (unlikely(Rc(ctx->opcode) != 0))
4246
        gen_set_Rc0(ctx);
4247
}
4248

    
4249
/* srq */
4250
GEN_HANDLER(srq, 0x1F, 0x18, 0x14, 0x00000000, PPC_POWER_BR)
4251
{
4252
    gen_op_load_gpr_T0(rS(ctx->opcode));
4253
    gen_op_load_gpr_T1(rB(ctx->opcode));
4254
    gen_op_POWER_srq();
4255
    gen_op_store_T0_gpr(rA(ctx->opcode));
4256
    if (unlikely(Rc(ctx->opcode) != 0))
4257
        gen_set_Rc0(ctx);
4258
}
4259

    
4260
/* PowerPC 602 specific instructions */
4261
/* dsa  */
4262
GEN_HANDLER(dsa, 0x1F, 0x14, 0x13, 0x03FFF801, PPC_602_SPEC)
4263
{
4264
    /* XXX: TODO */
4265
    GEN_EXCP_INVAL(ctx);
4266
}
4267

    
4268
/* esa */
4269
GEN_HANDLER(esa, 0x1F, 0x14, 0x12, 0x03FFF801, PPC_602_SPEC)
4270
{
4271
    /* XXX: TODO */
4272
    GEN_EXCP_INVAL(ctx);
4273
}
4274

    
4275
/* mfrom */
4276
GEN_HANDLER(mfrom, 0x1F, 0x09, 0x08, 0x03E0F801, PPC_602_SPEC)
4277
{
4278
#if defined(CONFIG_USER_ONLY)
4279
    GEN_EXCP_PRIVOPC(ctx);
4280
#else
4281
    if (unlikely(!ctx->supervisor)) {
4282
        GEN_EXCP_PRIVOPC(ctx);
4283
        return;
4284
    }
4285
    gen_op_load_gpr_T0(rA(ctx->opcode));
4286
    gen_op_602_mfrom();
4287
    gen_op_store_T0_gpr(rD(ctx->opcode));
4288
#endif
4289
}
4290

    
4291
/* 602 - 603 - G2 TLB management */
4292
/* tlbld */
4293
GEN_HANDLER2(tlbld_6xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_6xx_TLB)
4294
{
4295
#if defined(CONFIG_USER_ONLY)
4296
    GEN_EXCP_PRIVOPC(ctx);
4297
#else
4298
    if (unlikely(!ctx->supervisor)) {
4299
        GEN_EXCP_PRIVOPC(ctx);
4300
        return;
4301
    }
4302
    gen_op_load_gpr_T0(rB(ctx->opcode));
4303
    gen_op_6xx_tlbld();
4304
#endif
4305
}
4306

    
4307
/* tlbli */
4308
GEN_HANDLER2(tlbli_6xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_6xx_TLB)
4309
{
4310
#if defined(CONFIG_USER_ONLY)
4311
    GEN_EXCP_PRIVOPC(ctx);
4312
#else
4313
    if (unlikely(!ctx->supervisor)) {
4314
        GEN_EXCP_PRIVOPC(ctx);
4315
        return;
4316
    }
4317
    gen_op_load_gpr_T0(rB(ctx->opcode));
4318
    gen_op_6xx_tlbli();
4319
#endif
4320
}
4321

    
4322
/* 74xx TLB management */
4323
/* tlbld */
4324
GEN_HANDLER2(tlbld_74xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_74xx_TLB)
4325
{
4326
#if defined(CONFIG_USER_ONLY)
4327
    GEN_EXCP_PRIVOPC(ctx);
4328
#else
4329
    if (unlikely(!ctx->supervisor)) {
4330
        GEN_EXCP_PRIVOPC(ctx);
4331
        return;
4332
    }
4333
    gen_op_load_gpr_T0(rB(ctx->opcode));
4334
    gen_op_74xx_tlbld();
4335
#endif
4336
}
4337

    
4338
/* tlbli */
4339
GEN_HANDLER2(tlbli_74xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_74xx_TLB)
4340
{
4341
#if defined(CONFIG_USER_ONLY)
4342
    GEN_EXCP_PRIVOPC(ctx);
4343
#else
4344
    if (unlikely(!ctx->supervisor)) {
4345
        GEN_EXCP_PRIVOPC(ctx);
4346
        return;
4347
    }
4348
    gen_op_load_gpr_T0(rB(ctx->opcode));
4349
    gen_op_74xx_tlbli();
4350
#endif
4351
}
4352

    
4353
/* POWER instructions not in PowerPC 601 */
4354
/* clf */
4355
GEN_HANDLER(clf, 0x1F, 0x16, 0x03, 0x03E00000, PPC_POWER)
4356
{
4357
    /* Cache line flush: implemented as no-op */
4358
}
4359

    
4360
/* cli */
4361
GEN_HANDLER(cli, 0x1F, 0x16, 0x0F, 0x03E00000, PPC_POWER)
4362
{
4363
    /* Cache line invalidate: privileged and treated as no-op */
4364
#if defined(CONFIG_USER_ONLY)
4365
    GEN_EXCP_PRIVOPC(ctx);
4366
#else
4367
    if (unlikely(!ctx->supervisor)) {
4368
        GEN_EXCP_PRIVOPC(ctx);
4369
        return;
4370
    }
4371
#endif
4372
}
4373

    
4374
/* dclst */
4375
GEN_HANDLER(dclst, 0x1F, 0x16, 0x13, 0x03E00000, PPC_POWER)
4376
{
4377
    /* Data cache line store: treated as no-op */
4378
}
4379

    
4380
GEN_HANDLER(mfsri, 0x1F, 0x13, 0x13, 0x00000001, PPC_POWER)
4381
{
4382
#if defined(CONFIG_USER_ONLY)
4383
    GEN_EXCP_PRIVOPC(ctx);
4384
#else
4385
    if (unlikely(!ctx->supervisor)) {
4386
        GEN_EXCP_PRIVOPC(ctx);
4387
        return;
4388
    }
4389
    int ra = rA(ctx->opcode);
4390
    int rd = rD(ctx->opcode);
4391

    
4392
    gen_addr_reg_index(ctx);
4393
    gen_op_POWER_mfsri();
4394
    gen_op_store_T0_gpr(rd);
4395
    if (ra != 0 && ra != rd)
4396
        gen_op_store_T1_gpr(ra);
4397
#endif
4398
}
4399

    
4400
GEN_HANDLER(rac, 0x1F, 0x12, 0x19, 0x00000001, PPC_POWER)
4401
{
4402
#if defined(CONFIG_USER_ONLY)
4403
    GEN_EXCP_PRIVOPC(ctx);
4404
#else
4405
    if (unlikely(!ctx->supervisor)) {
4406
        GEN_EXCP_PRIVOPC(ctx);
4407
        return;
4408
    }
4409
    gen_addr_reg_index(ctx);
4410
    gen_op_POWER_rac();
4411
    gen_op_store_T0_gpr(rD(ctx->opcode));
4412
#endif
4413
}
4414

    
4415
GEN_HANDLER(rfsvc, 0x13, 0x12, 0x02, 0x03FFF0001, PPC_POWER)
4416
{
4417
#if defined(CONFIG_USER_ONLY)
4418
    GEN_EXCP_PRIVOPC(ctx);
4419
#else
4420
    if (unlikely(!ctx->supervisor)) {
4421
        GEN_EXCP_PRIVOPC(ctx);
4422
        return;
4423
    }
4424
    gen_op_POWER_rfsvc();
4425
    GEN_SYNC(ctx);
4426
#endif
4427
}
4428

    
4429
/* svc is not implemented for now */
4430

    
4431
/* POWER2 specific instructions */
4432
/* Quad manipulation (load/store two floats at a time) */
4433
/* Original POWER2 is 32 bits only, define 64 bits ops as 32 bits ones */
4434
#define op_POWER2_lfq() (*gen_op_POWER2_lfq[ctx->mem_idx])()
4435
#define op_POWER2_stfq() (*gen_op_POWER2_stfq[ctx->mem_idx])()
4436
#define gen_op_POWER2_lfq_64_raw        gen_op_POWER2_lfq_raw
4437
#define gen_op_POWER2_lfq_64_user       gen_op_POWER2_lfq_user
4438
#define gen_op_POWER2_lfq_64_kernel     gen_op_POWER2_lfq_kernel
4439
#define gen_op_POWER2_lfq_64_hypv       gen_op_POWER2_lfq_hypv
4440
#define gen_op_POWER2_lfq_le_64_raw     gen_op_POWER2_lfq_le_raw
4441
#define gen_op_POWER2_lfq_le_64_user    gen_op_POWER2_lfq_le_user
4442
#define gen_op_POWER2_lfq_le_64_kernel  gen_op_POWER2_lfq_le_kernel
4443
#define gen_op_POWER2_lfq_le_64_hypv    gen_op_POWER2_lfq_le_hypv
4444
#define gen_op_POWER2_stfq_64_raw       gen_op_POWER2_stfq_raw
4445
#define gen_op_POWER2_stfq_64_user      gen_op_POWER2_stfq_user
4446
#define gen_op_POWER2_stfq_64_kernel    gen_op_POWER2_stfq_kernel
4447
#define gen_op_POWER2_stfq_64_hypv      gen_op_POWER2_stfq_hypv
4448
#define gen_op_POWER2_stfq_le_64_raw    gen_op_POWER2_stfq_le_raw
4449
#define gen_op_POWER2_stfq_le_64_user   gen_op_POWER2_stfq_le_user
4450
#define gen_op_POWER2_stfq_le_64_kernel gen_op_POWER2_stfq_le_kernel
4451
#define gen_op_POWER2_stfq_le_64_hypv   gen_op_POWER2_stfq_le_hypv
4452
static GenOpFunc *gen_op_POWER2_lfq[NB_MEM_FUNCS] = {
4453
    GEN_MEM_FUNCS(POWER2_lfq),
4454
};
4455
static GenOpFunc *gen_op_POWER2_stfq[NB_MEM_FUNCS] = {
4456
    GEN_MEM_FUNCS(POWER2_stfq),
4457
};
4458

    
4459
/* lfq */
4460
GEN_HANDLER(lfq, 0x38, 0xFF, 0xFF, 0x00000003, PPC_POWER2)
4461
{
4462
    /* NIP cannot be restored if the memory exception comes from an helper */
4463
    gen_update_nip(ctx, ctx->nip - 4);
4464
    gen_addr_imm_index(ctx, 0);
4465
    op_POWER2_lfq();
4466
    gen_op_store_FT0_fpr(rD(ctx->opcode));
4467
    gen_op_store_FT1_fpr(rD(ctx->opcode) + 1);
4468
}
4469

    
4470
/* lfqu */
4471
GEN_HANDLER(lfqu, 0x39, 0xFF, 0xFF, 0x00000003, PPC_POWER2)
4472
{
4473
    int ra = rA(ctx->opcode);
4474

    
4475
    /* NIP cannot be restored if the memory exception comes from an helper */
4476
    gen_update_nip(ctx, ctx->nip - 4);
4477
    gen_addr_imm_index(ctx, 0);
4478
    op_POWER2_lfq();
4479
    gen_op_store_FT0_fpr(rD(ctx->opcode));
4480
    gen_op_store_FT1_fpr(rD(ctx->opcode) + 1);
4481
    if (ra != 0)
4482
        gen_op_store_T0_gpr(ra);
4483
}
4484

    
4485
/* lfqux */
4486
GEN_HANDLER(lfqux, 0x1F, 0x17, 0x19, 0x00000001, PPC_POWER2)
4487
{
4488
    int ra = rA(ctx->opcode);
4489

    
4490
    /* NIP cannot be restored if the memory exception comes from an helper */
4491
    gen_update_nip(ctx, ctx->nip - 4);
4492
    gen_addr_reg_index(ctx);
4493
    op_POWER2_lfq();
4494
    gen_op_store_FT0_fpr(rD(ctx->opcode));
4495
    gen_op_store_FT1_fpr(rD(ctx->opcode) + 1);
4496
    if (ra != 0)
4497
        gen_op_store_T0_gpr(ra);
4498
}
4499

    
4500
/* lfqx */
4501
GEN_HANDLER(lfqx, 0x1F, 0x17, 0x18, 0x00000001, PPC_POWER2)
4502
{
4503
    /* NIP cannot be restored if the memory exception comes from an helper */
4504
    gen_update_nip(ctx, ctx->nip - 4);
4505
    gen_addr_reg_index(ctx);
4506
    op_POWER2_lfq();
4507
    gen_op_store_FT0_fpr(rD(ctx->opcode));
4508
    gen_op_store_FT1_fpr(rD(ctx->opcode) + 1);
4509
}
4510

    
4511
/* stfq */
4512
GEN_HANDLER(stfq, 0x3C, 0xFF, 0xFF, 0x00000003, PPC_POWER2)
4513
{
4514
    /* NIP cannot be restored if the memory exception comes from an helper */
4515
    gen_update_nip(ctx, ctx->nip - 4);
4516
    gen_addr_imm_index(ctx, 0);
4517
    gen_op_load_fpr_FT0(rS(ctx->opcode));
4518
    gen_op_load_fpr_FT1(rS(ctx->opcode) + 1);
4519
    op_POWER2_stfq();
4520
}
4521

    
4522
/* stfqu */
4523
GEN_HANDLER(stfqu, 0x3D, 0xFF, 0xFF, 0x00000003, PPC_POWER2)
4524
{
4525
    int ra = rA(ctx->opcode);
4526

    
4527
    /* NIP cannot be restored if the memory exception comes from an helper */
4528
    gen_update_nip(ctx, ctx->nip - 4);
4529
    gen_addr_imm_index(ctx, 0);
4530
    gen_op_load_fpr_FT0(rS(ctx->opcode));
4531
    gen_op_load_fpr_FT1(rS(ctx->opcode) + 1);
4532
    op_POWER2_stfq();
4533
    if (ra != 0)
4534
        gen_op_store_T0_gpr(ra);
4535
}
4536

    
4537
/* stfqux */
4538
GEN_HANDLER(stfqux, 0x1F, 0x17, 0x1D, 0x00000001, PPC_POWER2)
4539
{
4540
    int ra = rA(ctx->opcode);
4541

    
4542
    /* NIP cannot be restored if the memory exception comes from an helper */
4543
    gen_update_nip(ctx, ctx->nip - 4);
4544
    gen_addr_reg_index(ctx);
4545
    gen_op_load_fpr_FT0(rS(ctx->opcode));
4546
    gen_op_load_fpr_FT1(rS(ctx->opcode) + 1);
4547
    op_POWER2_stfq();
4548
    if (ra != 0)
4549
        gen_op_store_T0_gpr(ra);
4550
}
4551

    
4552
/* stfqx */
4553
GEN_HANDLER(stfqx, 0x1F, 0x17, 0x1C, 0x00000001, PPC_POWER2)
4554
{
4555
    /* NIP cannot be restored if the memory exception comes from an helper */
4556
    gen_update_nip(ctx, ctx->nip - 4);
4557
    gen_addr_reg_index(ctx);
4558
    gen_op_load_fpr_FT0(rS(ctx->opcode));
4559
    gen_op_load_fpr_FT1(rS(ctx->opcode) + 1);
4560
    op_POWER2_stfq();
4561
}
4562

    
4563
/* BookE specific instructions */
4564
/* XXX: not implemented on 440 ? */
4565
GEN_HANDLER(mfapidi, 0x1F, 0x13, 0x08, 0x0000F801, PPC_MFAPIDI)
4566
{
4567
    /* XXX: TODO */
4568
    GEN_EXCP_INVAL(ctx);
4569
}
4570

    
4571
/* XXX: not implemented on 440 ? */
4572
GEN_HANDLER(tlbiva, 0x1F, 0x12, 0x18, 0x03FFF801, PPC_TLBIVA)
4573
{
4574
#if defined(CONFIG_USER_ONLY)
4575
    GEN_EXCP_PRIVOPC(ctx);
4576
#else
4577
    if (unlikely(!ctx->supervisor)) {
4578
        GEN_EXCP_PRIVOPC(ctx);
4579
        return;
4580
    }
4581
    gen_addr_reg_index(ctx);
4582
    /* Use the same micro-ops as for tlbie */
4583
#if defined(TARGET_PPC64)
4584
    if (ctx->sf_mode)
4585
        gen_op_tlbie_64();
4586
    else
4587
#endif
4588
        gen_op_tlbie();
4589
#endif
4590
}
4591

    
4592
/* All 405 MAC instructions are translated here */
4593
static always_inline void gen_405_mulladd_insn (DisasContext *ctx,
4594
                                                int opc2, int opc3,
4595
                                                int ra, int rb, int rt, int Rc)
4596
{
4597
    gen_op_load_gpr_T0(ra);
4598
    gen_op_load_gpr_T1(rb);
4599
    switch (opc3 & 0x0D) {
4600
    case 0x05:
4601
        /* macchw    - macchw.    - macchwo   - macchwo.   */
4602
        /* macchws   - macchws.   - macchwso  - macchwso.  */
4603
        /* nmacchw   - nmacchw.   - nmacchwo  - nmacchwo.  */
4604
        /* nmacchws  - nmacchws.  - nmacchwso - nmacchwso. */
4605
        /* mulchw - mulchw. */
4606
        gen_op_405_mulchw();
4607
        break;
4608
    case 0x04:
4609
        /* macchwu   - macchwu.   - macchwuo  - macchwuo.  */
4610
        /* macchwsu  - macchwsu.  - macchwsuo - macchwsuo. */
4611
        /* mulchwu - mulchwu. */
4612
        gen_op_405_mulchwu();
4613
        break;
4614
    case 0x01:
4615
        /* machhw    - machhw.    - machhwo   - machhwo.   */
4616
        /* machhws   - machhws.   - machhwso  - machhwso.  */
4617
        /* nmachhw   - nmachhw.   - nmachhwo  - nmachhwo.  */
4618
        /* nmachhws  - nmachhws.  - nmachhwso - nmachhwso. */
4619
        /* mulhhw - mulhhw. */
4620
        gen_op_405_mulhhw();
4621
        break;
4622
    case 0x00:
4623
        /* machhwu   - machhwu.   - machhwuo  - machhwuo.  */
4624
        /* machhwsu  - machhwsu.  - machhwsuo - machhwsuo. */
4625
        /* mulhhwu - mulhhwu. */
4626
        gen_op_405_mulhhwu();
4627
        break;
4628
    case 0x0D:
4629
        /* maclhw    - maclhw.    - maclhwo   - maclhwo.   */
4630
        /* maclhws   - maclhws.   - maclhwso  - maclhwso.  */
4631
        /* nmaclhw   - nmaclhw.   - nmaclhwo  - nmaclhwo.  */
4632
        /* nmaclhws  - nmaclhws.  - nmaclhwso - nmaclhwso. */
4633
        /* mullhw - mullhw. */
4634
        gen_op_405_mullhw();
4635
        break;
4636
    case 0x0C:
4637
        /* maclhwu   - maclhwu.   - maclhwuo  - maclhwuo.  */
4638
        /* maclhwsu  - maclhwsu.  - maclhwsuo - maclhwsuo. */
4639
        /* mullhwu - mullhwu. */
4640
        gen_op_405_mullhwu();
4641
        break;
4642
    }
4643
    if (opc2 & 0x02) {
4644
        /* nmultiply-and-accumulate (0x0E) */
4645
        gen_op_neg();
4646
    }
4647
    if (opc2 & 0x04) {
4648
        /* (n)multiply-and-accumulate (0x0C - 0x0E) */
4649
        gen_op_load_gpr_T2(rt);
4650
        tcg_gen_mov_tl(cpu_T[1], cpu_T[0]);
4651
        gen_op_405_add_T0_T2();
4652
    }
4653
    if (opc3 & 0x10) {
4654
        /* Check overflow */
4655
        if (opc3 & 0x01)
4656
            gen_op_check_addo();
4657
        else
4658
            gen_op_405_check_ovu();
4659
    }
4660
    if (opc3 & 0x02) {
4661
        /* Saturate */
4662
        if (opc3 & 0x01)
4663
            gen_op_405_check_sat();
4664
        else
4665
            gen_op_405_check_satu();
4666
    }
4667
    gen_op_store_T0_gpr(rt);
4668
    if (unlikely(Rc) != 0) {
4669
        /* Update Rc0 */
4670
        gen_set_Rc0(ctx);
4671
    }
4672
}
4673

    
4674
#define GEN_MAC_HANDLER(name, opc2, opc3)                                     \
4675
GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_405_MAC)                  \
4676
{                                                                             \
4677
    gen_405_mulladd_insn(ctx, opc2, opc3, rA(ctx->opcode), rB(ctx->opcode),   \
4678
                         rD(ctx->opcode), Rc(ctx->opcode));                   \
4679
}
4680

    
4681
/* macchw    - macchw.    */
4682
GEN_MAC_HANDLER(macchw, 0x0C, 0x05);
4683
/* macchwo   - macchwo.   */
4684
GEN_MAC_HANDLER(macchwo, 0x0C, 0x15);
4685
/* macchws   - macchws.   */
4686
GEN_MAC_HANDLER(macchws, 0x0C, 0x07);
4687
/* macchwso  - macchwso.  */
4688
GEN_MAC_HANDLER(macchwso, 0x0C, 0x17);
4689
/* macchwsu  - macchwsu.  */
4690
GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06);
4691
/* macchwsuo - macchwsuo. */
4692
GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16);
4693
/* macchwu   - macchwu.   */
4694
GEN_MAC_HANDLER(macchwu, 0x0C, 0x04);
4695
/* macchwuo  - macchwuo.  */
4696
GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14);
4697
/* machhw    - machhw.    */
4698
GEN_MAC_HANDLER(machhw, 0x0C, 0x01);
4699
/* machhwo   - machhwo.   */
4700
GEN_MAC_HANDLER(machhwo, 0x0C, 0x11);
4701
/* machhws   - machhws.   */
4702
GEN_MAC_HANDLER(machhws, 0x0C, 0x03);
4703
/* machhwso  - machhwso.  */
4704
GEN_MAC_HANDLER(machhwso, 0x0C, 0x13);
4705
/* machhwsu  - machhwsu.  */
4706
GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02);
4707
/* machhwsuo - machhwsuo. */
4708
GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12);
4709
/* machhwu   - machhwu.   */
4710
GEN_MAC_HANDLER(machhwu, 0x0C, 0x00);
4711
/* machhwuo  - machhwuo.  */
4712
GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10);
4713
/* maclhw    - maclhw.    */
4714
GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D);
4715
/* maclhwo   - maclhwo.   */
4716
GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D);
4717
/* maclhws   - maclhws.   */
4718
GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F);
4719
/* maclhwso  - maclhwso.  */
4720
GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F);
4721
/* maclhwu   - maclhwu.   */
4722
GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C);
4723
/* maclhwuo  - maclhwuo.  */
4724
GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C);
4725
/* maclhwsu  - maclhwsu.  */
4726
GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E);
4727
/* maclhwsuo - maclhwsuo. */
4728
GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E);
4729
/* nmacchw   - nmacchw.   */
4730
GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05);
4731
/* nmacchwo  - nmacchwo.  */
4732
GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15);
4733
/* nmacchws  - nmacchws.  */
4734
GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07);
4735
/* nmacchwso - nmacchwso. */
4736
GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17);
4737
/* nmachhw   - nmachhw.   */
4738
GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01);
4739
/* nmachhwo  - nmachhwo.  */
4740
GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11);
4741
/* nmachhws  - nmachhws.  */
4742
GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03);
4743
/* nmachhwso - nmachhwso. */
4744
GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13);
4745
/* nmaclhw   - nmaclhw.   */
4746
GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D);
4747
/* nmaclhwo  - nmaclhwo.  */
4748
GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D);
4749
/* nmaclhws  - nmaclhws.  */
4750
GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F);
4751
/* nmaclhwso - nmaclhwso. */
4752
GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F);
4753

    
4754
/* mulchw  - mulchw.  */
4755
GEN_MAC_HANDLER(mulchw, 0x08, 0x05);
4756
/* mulchwu - mulchwu. */
4757
GEN_MAC_HANDLER(mulchwu, 0x08, 0x04);
4758
/* mulhhw  - mulhhw.  */
4759
GEN_MAC_HANDLER(mulhhw, 0x08, 0x01);
4760
/* mulhhwu - mulhhwu. */
4761
GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00);
4762
/* mullhw  - mullhw.  */
4763
GEN_MAC_HANDLER(mullhw, 0x08, 0x0D);
4764
/* mullhwu - mullhwu. */
4765
GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C);
4766

    
4767
/* mfdcr */
4768
GEN_HANDLER(mfdcr, 0x1F, 0x03, 0x0A, 0x00000001, PPC_DCR)
4769
{
4770
#if defined(CONFIG_USER_ONLY)
4771
    GEN_EXCP_PRIVREG(ctx);
4772
#else
4773
    uint32_t dcrn = SPR(ctx->opcode);
4774

    
4775
    if (unlikely(!ctx->supervisor)) {
4776
        GEN_EXCP_PRIVREG(ctx);
4777
        return;
4778
    }
4779
    tcg_gen_movi_tl(cpu_T[0], dcrn);
4780
    gen_op_load_dcr();
4781
    gen_op_store_T0_gpr(rD(ctx->opcode));
4782
#endif
4783
}
4784

    
4785
/* mtdcr */
4786
GEN_HANDLER(mtdcr, 0x1F, 0x03, 0x0E, 0x00000001, PPC_DCR)
4787
{
4788
#if defined(CONFIG_USER_ONLY)
4789
    GEN_EXCP_PRIVREG(ctx);
4790
#else
4791
    uint32_t dcrn = SPR(ctx->opcode);
4792

    
4793
    if (unlikely(!ctx->supervisor)) {
4794
        GEN_EXCP_PRIVREG(ctx);
4795
        return;
4796
    }
4797
    tcg_gen_movi_tl(cpu_T[0], dcrn);
4798
    gen_op_load_gpr_T1(rS(ctx->opcode));
4799
    gen_op_store_dcr();
4800
#endif
4801
}
4802

    
4803
/* mfdcrx */
4804
/* XXX: not implemented on 440 ? */
4805
GEN_HANDLER(mfdcrx, 0x1F, 0x03, 0x08, 0x00000000, PPC_DCRX)
4806
{
4807
#if defined(CONFIG_USER_ONLY)
4808
    GEN_EXCP_PRIVREG(ctx);
4809
#else
4810
    if (unlikely(!ctx->supervisor)) {
4811
        GEN_EXCP_PRIVREG(ctx);
4812
        return;
4813
    }
4814
    gen_op_load_gpr_T0(rA(ctx->opcode));
4815
    gen_op_load_dcr();
4816
    gen_op_store_T0_gpr(rD(ctx->opcode));
4817
    /* Note: Rc update flag set leads to undefined state of Rc0 */
4818
#endif
4819
}
4820

    
4821
/* mtdcrx */
4822
/* XXX: not implemented on 440 ? */
4823
GEN_HANDLER(mtdcrx, 0x1F, 0x03, 0x0C, 0x00000000, PPC_DCRX)
4824
{
4825
#if defined(CONFIG_USER_ONLY)
4826
    GEN_EXCP_PRIVREG(ctx);
4827
#else
4828
    if (unlikely(!ctx->supervisor)) {
4829
        GEN_EXCP_PRIVREG(ctx);
4830
        return;
4831
    }
4832
    gen_op_load_gpr_T0(rA(ctx->opcode));
4833
    gen_op_load_gpr_T1(rS(ctx->opcode));
4834
    gen_op_store_dcr();
4835
    /* Note: Rc update flag set leads to undefined state of Rc0 */
4836
#endif
4837
}
4838

    
4839
/* mfdcrux (PPC 460) : user-mode access to DCR */
4840
GEN_HANDLER(mfdcrux, 0x1F, 0x03, 0x09, 0x00000000, PPC_DCRUX)
4841
{
4842
    gen_op_load_gpr_T0(rA(ctx->opcode));
4843
    gen_op_load_dcr();
4844
    gen_op_store_T0_gpr(rD(ctx->opcode));
4845
    /* Note: Rc update flag set leads to undefined state of Rc0 */
4846
}
4847

    
4848
/* mtdcrux (PPC 460) : user-mode access to DCR */
4849
GEN_HANDLER(mtdcrux, 0x1F, 0x03, 0x0D, 0x00000000, PPC_DCRUX)
4850
{
4851
    gen_op_load_gpr_T0(rA(ctx->opcode));
4852
    gen_op_load_gpr_T1(rS(ctx->opcode));
4853
    gen_op_store_dcr();
4854
    /* Note: Rc update flag set leads to undefined state of Rc0 */
4855
}
4856

    
4857
/* dccci */
4858
GEN_HANDLER(dccci, 0x1F, 0x06, 0x0E, 0x03E00001, PPC_4xx_COMMON)
4859
{
4860
#if defined(CONFIG_USER_ONLY)
4861
    GEN_EXCP_PRIVOPC(ctx);
4862
#else
4863
    if (unlikely(!ctx->supervisor)) {
4864
        GEN_EXCP_PRIVOPC(ctx);
4865
        return;
4866
    }
4867
    /* interpreted as no-op */
4868
#endif
4869
}
4870

    
4871
/* dcread */
4872
GEN_HANDLER(dcread, 0x1F, 0x06, 0x0F, 0x00000001, PPC_4xx_COMMON)
4873
{
4874
#if defined(CONFIG_USER_ONLY)
4875
    GEN_EXCP_PRIVOPC(ctx);
4876
#else
4877
    if (unlikely(!ctx->supervisor)) {
4878
        GEN_EXCP_PRIVOPC(ctx);
4879
        return;
4880
    }
4881
    gen_addr_reg_index(ctx);
4882
    op_ldst(lwz);
4883
    gen_op_store_T0_gpr(rD(ctx->opcode));
4884
#endif
4885
}
4886

    
4887
/* icbt */
4888
GEN_HANDLER2(icbt_40x, "icbt", 0x1F, 0x06, 0x08, 0x03E00001, PPC_40x_ICBT)
4889
{
4890
    /* interpreted as no-op */
4891
    /* XXX: specification say this is treated as a load by the MMU