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1 | 5a9fdfec | bellard | /*
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2 | 5a9fdfec | bellard | * defines common to all virtual CPUs
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3 | 5a9fdfec | bellard | *
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4 | 5a9fdfec | bellard | * Copyright (c) 2003 Fabrice Bellard
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5 | 5a9fdfec | bellard | *
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6 | 5a9fdfec | bellard | * This library is free software; you can redistribute it and/or
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7 | 5a9fdfec | bellard | * modify it under the terms of the GNU Lesser General Public
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8 | 5a9fdfec | bellard | * License as published by the Free Software Foundation; either
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9 | 5a9fdfec | bellard | * version 2 of the License, or (at your option) any later version.
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10 | 5a9fdfec | bellard | *
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11 | 5a9fdfec | bellard | * This library is distributed in the hope that it will be useful,
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12 | 5a9fdfec | bellard | * but WITHOUT ANY WARRANTY; without even the implied warranty of
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13 | 5a9fdfec | bellard | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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14 | 5a9fdfec | bellard | * Lesser General Public License for more details.
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15 | 5a9fdfec | bellard | *
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16 | 5a9fdfec | bellard | * You should have received a copy of the GNU Lesser General Public
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17 | 5a9fdfec | bellard | * License along with this library; if not, write to the Free Software
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18 | 5a9fdfec | bellard | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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19 | 5a9fdfec | bellard | */
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20 | 5a9fdfec | bellard | #ifndef CPU_ALL_H
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21 | 5a9fdfec | bellard | #define CPU_ALL_H
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22 | 5a9fdfec | bellard | |
23 | 0ac4bd56 | bellard | #if defined(__arm__) || defined(__sparc__)
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24 | 0ac4bd56 | bellard | #define WORDS_ALIGNED
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25 | 0ac4bd56 | bellard | #endif
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26 | 0ac4bd56 | bellard | |
27 | 0ac4bd56 | bellard | /* some important defines:
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28 | 0ac4bd56 | bellard | *
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29 | 0ac4bd56 | bellard | * WORDS_ALIGNED : if defined, the host cpu can only make word aligned
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30 | 0ac4bd56 | bellard | * memory accesses.
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31 | 0ac4bd56 | bellard | *
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32 | 0ac4bd56 | bellard | * WORDS_BIGENDIAN : if defined, the host cpu is big endian and
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33 | 0ac4bd56 | bellard | * otherwise little endian.
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34 | 0ac4bd56 | bellard | *
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35 | 0ac4bd56 | bellard | * (TARGET_WORDS_ALIGNED : same for target cpu (not supported yet))
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36 | 0ac4bd56 | bellard | *
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37 | 0ac4bd56 | bellard | * TARGET_WORDS_BIGENDIAN : same for target cpu
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38 | 0ac4bd56 | bellard | */
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39 | 0ac4bd56 | bellard | |
40 | f193c797 | bellard | #include "bswap.h" |
41 | f193c797 | bellard | |
42 | f193c797 | bellard | #if defined(WORDS_BIGENDIAN) != defined(TARGET_WORDS_BIGENDIAN)
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43 | f193c797 | bellard | #define BSWAP_NEEDED
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44 | f193c797 | bellard | #endif
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45 | f193c797 | bellard | |
46 | f193c797 | bellard | #ifdef BSWAP_NEEDED
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47 | f193c797 | bellard | |
48 | f193c797 | bellard | static inline uint16_t tswap16(uint16_t s) |
49 | f193c797 | bellard | { |
50 | f193c797 | bellard | return bswap16(s);
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51 | f193c797 | bellard | } |
52 | f193c797 | bellard | |
53 | f193c797 | bellard | static inline uint32_t tswap32(uint32_t s) |
54 | f193c797 | bellard | { |
55 | f193c797 | bellard | return bswap32(s);
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56 | f193c797 | bellard | } |
57 | f193c797 | bellard | |
58 | f193c797 | bellard | static inline uint64_t tswap64(uint64_t s) |
59 | f193c797 | bellard | { |
60 | f193c797 | bellard | return bswap64(s);
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61 | f193c797 | bellard | } |
62 | f193c797 | bellard | |
63 | f193c797 | bellard | static inline void tswap16s(uint16_t *s) |
64 | f193c797 | bellard | { |
65 | f193c797 | bellard | *s = bswap16(*s); |
66 | f193c797 | bellard | } |
67 | f193c797 | bellard | |
68 | f193c797 | bellard | static inline void tswap32s(uint32_t *s) |
69 | f193c797 | bellard | { |
70 | f193c797 | bellard | *s = bswap32(*s); |
71 | f193c797 | bellard | } |
72 | f193c797 | bellard | |
73 | f193c797 | bellard | static inline void tswap64s(uint64_t *s) |
74 | f193c797 | bellard | { |
75 | f193c797 | bellard | *s = bswap64(*s); |
76 | f193c797 | bellard | } |
77 | f193c797 | bellard | |
78 | f193c797 | bellard | #else
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79 | f193c797 | bellard | |
80 | f193c797 | bellard | static inline uint16_t tswap16(uint16_t s) |
81 | f193c797 | bellard | { |
82 | f193c797 | bellard | return s;
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83 | f193c797 | bellard | } |
84 | f193c797 | bellard | |
85 | f193c797 | bellard | static inline uint32_t tswap32(uint32_t s) |
86 | f193c797 | bellard | { |
87 | f193c797 | bellard | return s;
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88 | f193c797 | bellard | } |
89 | f193c797 | bellard | |
90 | f193c797 | bellard | static inline uint64_t tswap64(uint64_t s) |
91 | f193c797 | bellard | { |
92 | f193c797 | bellard | return s;
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93 | f193c797 | bellard | } |
94 | f193c797 | bellard | |
95 | f193c797 | bellard | static inline void tswap16s(uint16_t *s) |
96 | f193c797 | bellard | { |
97 | f193c797 | bellard | } |
98 | f193c797 | bellard | |
99 | f193c797 | bellard | static inline void tswap32s(uint32_t *s) |
100 | f193c797 | bellard | { |
101 | f193c797 | bellard | } |
102 | f193c797 | bellard | |
103 | f193c797 | bellard | static inline void tswap64s(uint64_t *s) |
104 | f193c797 | bellard | { |
105 | f193c797 | bellard | } |
106 | f193c797 | bellard | |
107 | f193c797 | bellard | #endif
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108 | f193c797 | bellard | |
109 | f193c797 | bellard | #if TARGET_LONG_SIZE == 4 |
110 | f193c797 | bellard | #define tswapl(s) tswap32(s)
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111 | f193c797 | bellard | #define tswapls(s) tswap32s((uint32_t *)(s))
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112 | 0a962c02 | bellard | #define bswaptls(s) bswap32s(s)
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113 | f193c797 | bellard | #else
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114 | f193c797 | bellard | #define tswapl(s) tswap64(s)
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115 | f193c797 | bellard | #define tswapls(s) tswap64s((uint64_t *)(s))
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116 | 0a962c02 | bellard | #define bswaptls(s) bswap64s(s)
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117 | f193c797 | bellard | #endif
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118 | f193c797 | bellard | |
119 | 832ed0fa | bellard | /* NOTE: arm FPA is horrible as double 32 bit words are stored in big
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120 | 832ed0fa | bellard | endian ! */
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121 | 0ac4bd56 | bellard | typedef union { |
122 | 53cd6637 | bellard | float64 d; |
123 | 9d60cac0 | bellard | #if defined(WORDS_BIGENDIAN) \
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124 | 9d60cac0 | bellard | || (defined(__arm__) && !defined(__VFP_FP__) && !defined(CONFIG_SOFTFLOAT)) |
125 | 0ac4bd56 | bellard | struct {
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126 | 0ac4bd56 | bellard | uint32_t upper; |
127 | 832ed0fa | bellard | uint32_t lower; |
128 | 0ac4bd56 | bellard | } l; |
129 | 0ac4bd56 | bellard | #else
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130 | 0ac4bd56 | bellard | struct {
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131 | 0ac4bd56 | bellard | uint32_t lower; |
132 | 832ed0fa | bellard | uint32_t upper; |
133 | 0ac4bd56 | bellard | } l; |
134 | 0ac4bd56 | bellard | #endif
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135 | 0ac4bd56 | bellard | uint64_t ll; |
136 | 0ac4bd56 | bellard | } CPU_DoubleU; |
137 | 0ac4bd56 | bellard | |
138 | 61382a50 | bellard | /* CPU memory access without any memory or io remapping */
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139 | 61382a50 | bellard | |
140 | 83d73968 | bellard | /*
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141 | 83d73968 | bellard | * the generic syntax for the memory accesses is:
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142 | 83d73968 | bellard | *
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143 | 83d73968 | bellard | * load: ld{type}{sign}{size}{endian}_{access_type}(ptr)
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144 | 83d73968 | bellard | *
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145 | 83d73968 | bellard | * store: st{type}{size}{endian}_{access_type}(ptr, val)
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146 | 83d73968 | bellard | *
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147 | 83d73968 | bellard | * type is:
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148 | 83d73968 | bellard | * (empty): integer access
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149 | 83d73968 | bellard | * f : float access
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150 | 83d73968 | bellard | *
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151 | 83d73968 | bellard | * sign is:
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152 | 83d73968 | bellard | * (empty): for floats or 32 bit size
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153 | 83d73968 | bellard | * u : unsigned
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154 | 83d73968 | bellard | * s : signed
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155 | 83d73968 | bellard | *
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156 | 83d73968 | bellard | * size is:
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157 | 83d73968 | bellard | * b: 8 bits
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158 | 83d73968 | bellard | * w: 16 bits
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159 | 83d73968 | bellard | * l: 32 bits
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160 | 83d73968 | bellard | * q: 64 bits
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161 | 83d73968 | bellard | *
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162 | 83d73968 | bellard | * endian is:
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163 | 83d73968 | bellard | * (empty): target cpu endianness or 8 bit access
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164 | 83d73968 | bellard | * r : reversed target cpu endianness (not implemented yet)
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165 | 83d73968 | bellard | * be : big endian (not implemented yet)
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166 | 83d73968 | bellard | * le : little endian (not implemented yet)
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167 | 83d73968 | bellard | *
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168 | 83d73968 | bellard | * access_type is:
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169 | 83d73968 | bellard | * raw : host memory access
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170 | 83d73968 | bellard | * user : user mode access using soft MMU
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171 | 83d73968 | bellard | * kernel : kernel mode access using soft MMU
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172 | 83d73968 | bellard | */
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173 | c27004ec | bellard | static inline int ldub_p(void *ptr) |
174 | 5a9fdfec | bellard | { |
175 | 5a9fdfec | bellard | return *(uint8_t *)ptr;
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176 | 5a9fdfec | bellard | } |
177 | 5a9fdfec | bellard | |
178 | c27004ec | bellard | static inline int ldsb_p(void *ptr) |
179 | 5a9fdfec | bellard | { |
180 | 5a9fdfec | bellard | return *(int8_t *)ptr;
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181 | 5a9fdfec | bellard | } |
182 | 5a9fdfec | bellard | |
183 | c27004ec | bellard | static inline void stb_p(void *ptr, int v) |
184 | 5a9fdfec | bellard | { |
185 | 5a9fdfec | bellard | *(uint8_t *)ptr = v; |
186 | 5a9fdfec | bellard | } |
187 | 5a9fdfec | bellard | |
188 | 5a9fdfec | bellard | /* NOTE: on arm, putting 2 in /proc/sys/debug/alignment so that the
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189 | 5a9fdfec | bellard | kernel handles unaligned load/stores may give better results, but
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190 | 5a9fdfec | bellard | it is a system wide setting : bad */
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191 | 2df3b95d | bellard | #if defined(WORDS_BIGENDIAN) || defined(WORDS_ALIGNED)
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192 | 5a9fdfec | bellard | |
193 | 5a9fdfec | bellard | /* conservative code for little endian unaligned accesses */
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194 | 2df3b95d | bellard | static inline int lduw_le_p(void *ptr) |
195 | 5a9fdfec | bellard | { |
196 | 5a9fdfec | bellard | #ifdef __powerpc__
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197 | 5a9fdfec | bellard | int val;
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198 | 5a9fdfec | bellard | __asm__ __volatile__ ("lhbrx %0,0,%1" : "=r" (val) : "r" (ptr)); |
199 | 5a9fdfec | bellard | return val;
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200 | 5a9fdfec | bellard | #else
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201 | 5a9fdfec | bellard | uint8_t *p = ptr; |
202 | 5a9fdfec | bellard | return p[0] | (p[1] << 8); |
203 | 5a9fdfec | bellard | #endif
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204 | 5a9fdfec | bellard | } |
205 | 5a9fdfec | bellard | |
206 | 2df3b95d | bellard | static inline int ldsw_le_p(void *ptr) |
207 | 5a9fdfec | bellard | { |
208 | 5a9fdfec | bellard | #ifdef __powerpc__
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209 | 5a9fdfec | bellard | int val;
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210 | 5a9fdfec | bellard | __asm__ __volatile__ ("lhbrx %0,0,%1" : "=r" (val) : "r" (ptr)); |
211 | 5a9fdfec | bellard | return (int16_t)val;
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212 | 5a9fdfec | bellard | #else
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213 | 5a9fdfec | bellard | uint8_t *p = ptr; |
214 | 5a9fdfec | bellard | return (int16_t)(p[0] | (p[1] << 8)); |
215 | 5a9fdfec | bellard | #endif
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216 | 5a9fdfec | bellard | } |
217 | 5a9fdfec | bellard | |
218 | 2df3b95d | bellard | static inline int ldl_le_p(void *ptr) |
219 | 5a9fdfec | bellard | { |
220 | 5a9fdfec | bellard | #ifdef __powerpc__
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221 | 5a9fdfec | bellard | int val;
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222 | 5a9fdfec | bellard | __asm__ __volatile__ ("lwbrx %0,0,%1" : "=r" (val) : "r" (ptr)); |
223 | 5a9fdfec | bellard | return val;
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224 | 5a9fdfec | bellard | #else
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225 | 5a9fdfec | bellard | uint8_t *p = ptr; |
226 | 5a9fdfec | bellard | return p[0] | (p[1] << 8) | (p[2] << 16) | (p[3] << 24); |
227 | 5a9fdfec | bellard | #endif
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228 | 5a9fdfec | bellard | } |
229 | 5a9fdfec | bellard | |
230 | 2df3b95d | bellard | static inline uint64_t ldq_le_p(void *ptr) |
231 | 5a9fdfec | bellard | { |
232 | 5a9fdfec | bellard | uint8_t *p = ptr; |
233 | 5a9fdfec | bellard | uint32_t v1, v2; |
234 | f0aca822 | bellard | v1 = ldl_le_p(p); |
235 | f0aca822 | bellard | v2 = ldl_le_p(p + 4);
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236 | 5a9fdfec | bellard | return v1 | ((uint64_t)v2 << 32); |
237 | 5a9fdfec | bellard | } |
238 | 5a9fdfec | bellard | |
239 | 2df3b95d | bellard | static inline void stw_le_p(void *ptr, int v) |
240 | 5a9fdfec | bellard | { |
241 | 5a9fdfec | bellard | #ifdef __powerpc__
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242 | 5a9fdfec | bellard | __asm__ __volatile__ ("sthbrx %1,0,%2" : "=m" (*(uint16_t *)ptr) : "r" (v), "r" (ptr)); |
243 | 5a9fdfec | bellard | #else
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244 | 5a9fdfec | bellard | uint8_t *p = ptr; |
245 | 5a9fdfec | bellard | p[0] = v;
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246 | 5a9fdfec | bellard | p[1] = v >> 8; |
247 | 5a9fdfec | bellard | #endif
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248 | 5a9fdfec | bellard | } |
249 | 5a9fdfec | bellard | |
250 | 2df3b95d | bellard | static inline void stl_le_p(void *ptr, int v) |
251 | 5a9fdfec | bellard | { |
252 | 5a9fdfec | bellard | #ifdef __powerpc__
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253 | 5a9fdfec | bellard | __asm__ __volatile__ ("stwbrx %1,0,%2" : "=m" (*(uint32_t *)ptr) : "r" (v), "r" (ptr)); |
254 | 5a9fdfec | bellard | #else
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255 | 5a9fdfec | bellard | uint8_t *p = ptr; |
256 | 5a9fdfec | bellard | p[0] = v;
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257 | 5a9fdfec | bellard | p[1] = v >> 8; |
258 | 5a9fdfec | bellard | p[2] = v >> 16; |
259 | 5a9fdfec | bellard | p[3] = v >> 24; |
260 | 5a9fdfec | bellard | #endif
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261 | 5a9fdfec | bellard | } |
262 | 5a9fdfec | bellard | |
263 | 2df3b95d | bellard | static inline void stq_le_p(void *ptr, uint64_t v) |
264 | 5a9fdfec | bellard | { |
265 | 5a9fdfec | bellard | uint8_t *p = ptr; |
266 | f0aca822 | bellard | stl_le_p(p, (uint32_t)v); |
267 | f0aca822 | bellard | stl_le_p(p + 4, v >> 32); |
268 | 5a9fdfec | bellard | } |
269 | 5a9fdfec | bellard | |
270 | 5a9fdfec | bellard | /* float access */
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271 | 5a9fdfec | bellard | |
272 | 2df3b95d | bellard | static inline float32 ldfl_le_p(void *ptr) |
273 | 5a9fdfec | bellard | { |
274 | 5a9fdfec | bellard | union {
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275 | 53cd6637 | bellard | float32 f; |
276 | 5a9fdfec | bellard | uint32_t i; |
277 | 5a9fdfec | bellard | } u; |
278 | 2df3b95d | bellard | u.i = ldl_le_p(ptr); |
279 | 5a9fdfec | bellard | return u.f;
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280 | 5a9fdfec | bellard | } |
281 | 5a9fdfec | bellard | |
282 | 2df3b95d | bellard | static inline void stfl_le_p(void *ptr, float32 v) |
283 | 5a9fdfec | bellard | { |
284 | 5a9fdfec | bellard | union {
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285 | 53cd6637 | bellard | float32 f; |
286 | 5a9fdfec | bellard | uint32_t i; |
287 | 5a9fdfec | bellard | } u; |
288 | 5a9fdfec | bellard | u.f = v; |
289 | 2df3b95d | bellard | stl_le_p(ptr, u.i); |
290 | 5a9fdfec | bellard | } |
291 | 5a9fdfec | bellard | |
292 | 2df3b95d | bellard | static inline float64 ldfq_le_p(void *ptr) |
293 | 5a9fdfec | bellard | { |
294 | 0ac4bd56 | bellard | CPU_DoubleU u; |
295 | 2df3b95d | bellard | u.l.lower = ldl_le_p(ptr); |
296 | 2df3b95d | bellard | u.l.upper = ldl_le_p(ptr + 4);
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297 | 5a9fdfec | bellard | return u.d;
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298 | 5a9fdfec | bellard | } |
299 | 5a9fdfec | bellard | |
300 | 2df3b95d | bellard | static inline void stfq_le_p(void *ptr, float64 v) |
301 | 5a9fdfec | bellard | { |
302 | 0ac4bd56 | bellard | CPU_DoubleU u; |
303 | 5a9fdfec | bellard | u.d = v; |
304 | 2df3b95d | bellard | stl_le_p(ptr, u.l.lower); |
305 | 2df3b95d | bellard | stl_le_p(ptr + 4, u.l.upper);
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306 | 5a9fdfec | bellard | } |
307 | 5a9fdfec | bellard | |
308 | 2df3b95d | bellard | #else
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309 | 2df3b95d | bellard | |
310 | 2df3b95d | bellard | static inline int lduw_le_p(void *ptr) |
311 | 2df3b95d | bellard | { |
312 | 2df3b95d | bellard | return *(uint16_t *)ptr;
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313 | 2df3b95d | bellard | } |
314 | 2df3b95d | bellard | |
315 | 2df3b95d | bellard | static inline int ldsw_le_p(void *ptr) |
316 | 2df3b95d | bellard | { |
317 | 2df3b95d | bellard | return *(int16_t *)ptr;
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318 | 2df3b95d | bellard | } |
319 | 93ac68bc | bellard | |
320 | 2df3b95d | bellard | static inline int ldl_le_p(void *ptr) |
321 | 2df3b95d | bellard | { |
322 | 2df3b95d | bellard | return *(uint32_t *)ptr;
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323 | 2df3b95d | bellard | } |
324 | 2df3b95d | bellard | |
325 | 2df3b95d | bellard | static inline uint64_t ldq_le_p(void *ptr) |
326 | 2df3b95d | bellard | { |
327 | 2df3b95d | bellard | return *(uint64_t *)ptr;
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328 | 2df3b95d | bellard | } |
329 | 2df3b95d | bellard | |
330 | 2df3b95d | bellard | static inline void stw_le_p(void *ptr, int v) |
331 | 2df3b95d | bellard | { |
332 | 2df3b95d | bellard | *(uint16_t *)ptr = v; |
333 | 2df3b95d | bellard | } |
334 | 2df3b95d | bellard | |
335 | 2df3b95d | bellard | static inline void stl_le_p(void *ptr, int v) |
336 | 2df3b95d | bellard | { |
337 | 2df3b95d | bellard | *(uint32_t *)ptr = v; |
338 | 2df3b95d | bellard | } |
339 | 2df3b95d | bellard | |
340 | 2df3b95d | bellard | static inline void stq_le_p(void *ptr, uint64_t v) |
341 | 2df3b95d | bellard | { |
342 | 2df3b95d | bellard | *(uint64_t *)ptr = v; |
343 | 2df3b95d | bellard | } |
344 | 2df3b95d | bellard | |
345 | 2df3b95d | bellard | /* float access */
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346 | 2df3b95d | bellard | |
347 | 2df3b95d | bellard | static inline float32 ldfl_le_p(void *ptr) |
348 | 2df3b95d | bellard | { |
349 | 2df3b95d | bellard | return *(float32 *)ptr;
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350 | 2df3b95d | bellard | } |
351 | 2df3b95d | bellard | |
352 | 2df3b95d | bellard | static inline float64 ldfq_le_p(void *ptr) |
353 | 2df3b95d | bellard | { |
354 | 2df3b95d | bellard | return *(float64 *)ptr;
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355 | 2df3b95d | bellard | } |
356 | 2df3b95d | bellard | |
357 | 2df3b95d | bellard | static inline void stfl_le_p(void *ptr, float32 v) |
358 | 2df3b95d | bellard | { |
359 | 2df3b95d | bellard | *(float32 *)ptr = v; |
360 | 2df3b95d | bellard | } |
361 | 2df3b95d | bellard | |
362 | 2df3b95d | bellard | static inline void stfq_le_p(void *ptr, float64 v) |
363 | 2df3b95d | bellard | { |
364 | 2df3b95d | bellard | *(float64 *)ptr = v; |
365 | 2df3b95d | bellard | } |
366 | 2df3b95d | bellard | #endif
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367 | 2df3b95d | bellard | |
368 | 2df3b95d | bellard | #if !defined(WORDS_BIGENDIAN) || defined(WORDS_ALIGNED)
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369 | 2df3b95d | bellard | |
370 | 2df3b95d | bellard | static inline int lduw_be_p(void *ptr) |
371 | 93ac68bc | bellard | { |
372 | 83d73968 | bellard | #if defined(__i386__)
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373 | 83d73968 | bellard | int val;
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374 | 83d73968 | bellard | asm volatile ("movzwl %1, %0\n" |
375 | 83d73968 | bellard | "xchgb %b0, %h0\n"
|
376 | 83d73968 | bellard | : "=q" (val)
|
377 | 83d73968 | bellard | : "m" (*(uint16_t *)ptr));
|
378 | 83d73968 | bellard | return val;
|
379 | 83d73968 | bellard | #else
|
380 | 93ac68bc | bellard | uint8_t *b = (uint8_t *) ptr; |
381 | 83d73968 | bellard | return ((b[0] << 8) | b[1]); |
382 | 83d73968 | bellard | #endif
|
383 | 93ac68bc | bellard | } |
384 | 93ac68bc | bellard | |
385 | 2df3b95d | bellard | static inline int ldsw_be_p(void *ptr) |
386 | 93ac68bc | bellard | { |
387 | 83d73968 | bellard | #if defined(__i386__)
|
388 | 83d73968 | bellard | int val;
|
389 | 83d73968 | bellard | asm volatile ("movzwl %1, %0\n" |
390 | 83d73968 | bellard | "xchgb %b0, %h0\n"
|
391 | 83d73968 | bellard | : "=q" (val)
|
392 | 83d73968 | bellard | : "m" (*(uint16_t *)ptr));
|
393 | 83d73968 | bellard | return (int16_t)val;
|
394 | 83d73968 | bellard | #else
|
395 | 83d73968 | bellard | uint8_t *b = (uint8_t *) ptr; |
396 | 83d73968 | bellard | return (int16_t)((b[0] << 8) | b[1]); |
397 | 83d73968 | bellard | #endif
|
398 | 93ac68bc | bellard | } |
399 | 93ac68bc | bellard | |
400 | 2df3b95d | bellard | static inline int ldl_be_p(void *ptr) |
401 | 93ac68bc | bellard | { |
402 | 4f2ac237 | bellard | #if defined(__i386__) || defined(__x86_64__)
|
403 | 83d73968 | bellard | int val;
|
404 | 83d73968 | bellard | asm volatile ("movl %1, %0\n" |
405 | 83d73968 | bellard | "bswap %0\n"
|
406 | 83d73968 | bellard | : "=r" (val)
|
407 | 83d73968 | bellard | : "m" (*(uint32_t *)ptr));
|
408 | 83d73968 | bellard | return val;
|
409 | 83d73968 | bellard | #else
|
410 | 93ac68bc | bellard | uint8_t *b = (uint8_t *) ptr; |
411 | 83d73968 | bellard | return (b[0] << 24) | (b[1] << 16) | (b[2] << 8) | b[3]; |
412 | 83d73968 | bellard | #endif
|
413 | 93ac68bc | bellard | } |
414 | 93ac68bc | bellard | |
415 | 2df3b95d | bellard | static inline uint64_t ldq_be_p(void *ptr) |
416 | 93ac68bc | bellard | { |
417 | 93ac68bc | bellard | uint32_t a,b; |
418 | 2df3b95d | bellard | a = ldl_be_p(ptr); |
419 | 2df3b95d | bellard | b = ldl_be_p(ptr+4);
|
420 | 93ac68bc | bellard | return (((uint64_t)a<<32)|b); |
421 | 93ac68bc | bellard | } |
422 | 93ac68bc | bellard | |
423 | 2df3b95d | bellard | static inline void stw_be_p(void *ptr, int v) |
424 | 93ac68bc | bellard | { |
425 | 83d73968 | bellard | #if defined(__i386__)
|
426 | 83d73968 | bellard | asm volatile ("xchgb %b0, %h0\n" |
427 | 83d73968 | bellard | "movw %w0, %1\n"
|
428 | 83d73968 | bellard | : "=q" (v)
|
429 | 83d73968 | bellard | : "m" (*(uint16_t *)ptr), "0" (v)); |
430 | 83d73968 | bellard | #else
|
431 | 93ac68bc | bellard | uint8_t *d = (uint8_t *) ptr; |
432 | 93ac68bc | bellard | d[0] = v >> 8; |
433 | 93ac68bc | bellard | d[1] = v;
|
434 | 83d73968 | bellard | #endif
|
435 | 93ac68bc | bellard | } |
436 | 93ac68bc | bellard | |
437 | 2df3b95d | bellard | static inline void stl_be_p(void *ptr, int v) |
438 | 93ac68bc | bellard | { |
439 | 4f2ac237 | bellard | #if defined(__i386__) || defined(__x86_64__)
|
440 | 83d73968 | bellard | asm volatile ("bswap %0\n" |
441 | 83d73968 | bellard | "movl %0, %1\n"
|
442 | 83d73968 | bellard | : "=r" (v)
|
443 | 83d73968 | bellard | : "m" (*(uint32_t *)ptr), "0" (v)); |
444 | 83d73968 | bellard | #else
|
445 | 93ac68bc | bellard | uint8_t *d = (uint8_t *) ptr; |
446 | 93ac68bc | bellard | d[0] = v >> 24; |
447 | 93ac68bc | bellard | d[1] = v >> 16; |
448 | 93ac68bc | bellard | d[2] = v >> 8; |
449 | 93ac68bc | bellard | d[3] = v;
|
450 | 83d73968 | bellard | #endif
|
451 | 93ac68bc | bellard | } |
452 | 93ac68bc | bellard | |
453 | 2df3b95d | bellard | static inline void stq_be_p(void *ptr, uint64_t v) |
454 | 93ac68bc | bellard | { |
455 | 2df3b95d | bellard | stl_be_p(ptr, v >> 32);
|
456 | 2df3b95d | bellard | stl_be_p(ptr + 4, v);
|
457 | 0ac4bd56 | bellard | } |
458 | 0ac4bd56 | bellard | |
459 | 0ac4bd56 | bellard | /* float access */
|
460 | 0ac4bd56 | bellard | |
461 | 2df3b95d | bellard | static inline float32 ldfl_be_p(void *ptr) |
462 | 0ac4bd56 | bellard | { |
463 | 0ac4bd56 | bellard | union {
|
464 | 53cd6637 | bellard | float32 f; |
465 | 0ac4bd56 | bellard | uint32_t i; |
466 | 0ac4bd56 | bellard | } u; |
467 | 2df3b95d | bellard | u.i = ldl_be_p(ptr); |
468 | 0ac4bd56 | bellard | return u.f;
|
469 | 0ac4bd56 | bellard | } |
470 | 0ac4bd56 | bellard | |
471 | 2df3b95d | bellard | static inline void stfl_be_p(void *ptr, float32 v) |
472 | 0ac4bd56 | bellard | { |
473 | 0ac4bd56 | bellard | union {
|
474 | 53cd6637 | bellard | float32 f; |
475 | 0ac4bd56 | bellard | uint32_t i; |
476 | 0ac4bd56 | bellard | } u; |
477 | 0ac4bd56 | bellard | u.f = v; |
478 | 2df3b95d | bellard | stl_be_p(ptr, u.i); |
479 | 0ac4bd56 | bellard | } |
480 | 0ac4bd56 | bellard | |
481 | 2df3b95d | bellard | static inline float64 ldfq_be_p(void *ptr) |
482 | 0ac4bd56 | bellard | { |
483 | 0ac4bd56 | bellard | CPU_DoubleU u; |
484 | 2df3b95d | bellard | u.l.upper = ldl_be_p(ptr); |
485 | 2df3b95d | bellard | u.l.lower = ldl_be_p(ptr + 4);
|
486 | 0ac4bd56 | bellard | return u.d;
|
487 | 0ac4bd56 | bellard | } |
488 | 0ac4bd56 | bellard | |
489 | 2df3b95d | bellard | static inline void stfq_be_p(void *ptr, float64 v) |
490 | 0ac4bd56 | bellard | { |
491 | 0ac4bd56 | bellard | CPU_DoubleU u; |
492 | 0ac4bd56 | bellard | u.d = v; |
493 | 2df3b95d | bellard | stl_be_p(ptr, u.l.upper); |
494 | 2df3b95d | bellard | stl_be_p(ptr + 4, u.l.lower);
|
495 | 93ac68bc | bellard | } |
496 | 93ac68bc | bellard | |
497 | 5a9fdfec | bellard | #else
|
498 | 5a9fdfec | bellard | |
499 | 2df3b95d | bellard | static inline int lduw_be_p(void *ptr) |
500 | 5a9fdfec | bellard | { |
501 | 5a9fdfec | bellard | return *(uint16_t *)ptr;
|
502 | 5a9fdfec | bellard | } |
503 | 5a9fdfec | bellard | |
504 | 2df3b95d | bellard | static inline int ldsw_be_p(void *ptr) |
505 | 5a9fdfec | bellard | { |
506 | 5a9fdfec | bellard | return *(int16_t *)ptr;
|
507 | 5a9fdfec | bellard | } |
508 | 5a9fdfec | bellard | |
509 | 2df3b95d | bellard | static inline int ldl_be_p(void *ptr) |
510 | 5a9fdfec | bellard | { |
511 | 5a9fdfec | bellard | return *(uint32_t *)ptr;
|
512 | 5a9fdfec | bellard | } |
513 | 5a9fdfec | bellard | |
514 | 2df3b95d | bellard | static inline uint64_t ldq_be_p(void *ptr) |
515 | 5a9fdfec | bellard | { |
516 | 5a9fdfec | bellard | return *(uint64_t *)ptr;
|
517 | 5a9fdfec | bellard | } |
518 | 5a9fdfec | bellard | |
519 | 2df3b95d | bellard | static inline void stw_be_p(void *ptr, int v) |
520 | 5a9fdfec | bellard | { |
521 | 5a9fdfec | bellard | *(uint16_t *)ptr = v; |
522 | 5a9fdfec | bellard | } |
523 | 5a9fdfec | bellard | |
524 | 2df3b95d | bellard | static inline void stl_be_p(void *ptr, int v) |
525 | 5a9fdfec | bellard | { |
526 | 5a9fdfec | bellard | *(uint32_t *)ptr = v; |
527 | 5a9fdfec | bellard | } |
528 | 5a9fdfec | bellard | |
529 | 2df3b95d | bellard | static inline void stq_be_p(void *ptr, uint64_t v) |
530 | 5a9fdfec | bellard | { |
531 | 5a9fdfec | bellard | *(uint64_t *)ptr = v; |
532 | 5a9fdfec | bellard | } |
533 | 5a9fdfec | bellard | |
534 | 5a9fdfec | bellard | /* float access */
|
535 | 5a9fdfec | bellard | |
536 | 2df3b95d | bellard | static inline float32 ldfl_be_p(void *ptr) |
537 | 5a9fdfec | bellard | { |
538 | 53cd6637 | bellard | return *(float32 *)ptr;
|
539 | 5a9fdfec | bellard | } |
540 | 5a9fdfec | bellard | |
541 | 2df3b95d | bellard | static inline float64 ldfq_be_p(void *ptr) |
542 | 5a9fdfec | bellard | { |
543 | 53cd6637 | bellard | return *(float64 *)ptr;
|
544 | 5a9fdfec | bellard | } |
545 | 5a9fdfec | bellard | |
546 | 2df3b95d | bellard | static inline void stfl_be_p(void *ptr, float32 v) |
547 | 5a9fdfec | bellard | { |
548 | 53cd6637 | bellard | *(float32 *)ptr = v; |
549 | 5a9fdfec | bellard | } |
550 | 5a9fdfec | bellard | |
551 | 2df3b95d | bellard | static inline void stfq_be_p(void *ptr, float64 v) |
552 | 5a9fdfec | bellard | { |
553 | 53cd6637 | bellard | *(float64 *)ptr = v; |
554 | 5a9fdfec | bellard | } |
555 | 2df3b95d | bellard | |
556 | 2df3b95d | bellard | #endif
|
557 | 2df3b95d | bellard | |
558 | 2df3b95d | bellard | /* target CPU memory access functions */
|
559 | 2df3b95d | bellard | #if defined(TARGET_WORDS_BIGENDIAN)
|
560 | 2df3b95d | bellard | #define lduw_p(p) lduw_be_p(p)
|
561 | 2df3b95d | bellard | #define ldsw_p(p) ldsw_be_p(p)
|
562 | 2df3b95d | bellard | #define ldl_p(p) ldl_be_p(p)
|
563 | 2df3b95d | bellard | #define ldq_p(p) ldq_be_p(p)
|
564 | 2df3b95d | bellard | #define ldfl_p(p) ldfl_be_p(p)
|
565 | 2df3b95d | bellard | #define ldfq_p(p) ldfq_be_p(p)
|
566 | 2df3b95d | bellard | #define stw_p(p, v) stw_be_p(p, v)
|
567 | 2df3b95d | bellard | #define stl_p(p, v) stl_be_p(p, v)
|
568 | 2df3b95d | bellard | #define stq_p(p, v) stq_be_p(p, v)
|
569 | 2df3b95d | bellard | #define stfl_p(p, v) stfl_be_p(p, v)
|
570 | 2df3b95d | bellard | #define stfq_p(p, v) stfq_be_p(p, v)
|
571 | 2df3b95d | bellard | #else
|
572 | 2df3b95d | bellard | #define lduw_p(p) lduw_le_p(p)
|
573 | 2df3b95d | bellard | #define ldsw_p(p) ldsw_le_p(p)
|
574 | 2df3b95d | bellard | #define ldl_p(p) ldl_le_p(p)
|
575 | 2df3b95d | bellard | #define ldq_p(p) ldq_le_p(p)
|
576 | 2df3b95d | bellard | #define ldfl_p(p) ldfl_le_p(p)
|
577 | 2df3b95d | bellard | #define ldfq_p(p) ldfq_le_p(p)
|
578 | 2df3b95d | bellard | #define stw_p(p, v) stw_le_p(p, v)
|
579 | 2df3b95d | bellard | #define stl_p(p, v) stl_le_p(p, v)
|
580 | 2df3b95d | bellard | #define stq_p(p, v) stq_le_p(p, v)
|
581 | 2df3b95d | bellard | #define stfl_p(p, v) stfl_le_p(p, v)
|
582 | 2df3b95d | bellard | #define stfq_p(p, v) stfq_le_p(p, v)
|
583 | 5a9fdfec | bellard | #endif
|
584 | 5a9fdfec | bellard | |
585 | 61382a50 | bellard | /* MMU memory access macros */
|
586 | 61382a50 | bellard | |
587 | 53a5960a | pbrook | #if defined(CONFIG_USER_ONLY)
|
588 | 53a5960a | pbrook | /* On some host systems the guest address space is reserved on the host.
|
589 | 53a5960a | pbrook | * This allows the guest address space to be offset to a convenient location.
|
590 | 53a5960a | pbrook | */
|
591 | 53a5960a | pbrook | //#define GUEST_BASE 0x20000000
|
592 | 53a5960a | pbrook | #define GUEST_BASE 0 |
593 | 53a5960a | pbrook | |
594 | 53a5960a | pbrook | /* All direct uses of g2h and h2g need to go away for usermode softmmu. */
|
595 | 53a5960a | pbrook | #define g2h(x) ((void *)((unsigned long)(x) + GUEST_BASE)) |
596 | 53a5960a | pbrook | #define h2g(x) ((target_ulong)(x - GUEST_BASE))
|
597 | 53a5960a | pbrook | |
598 | 53a5960a | pbrook | #define saddr(x) g2h(x)
|
599 | 53a5960a | pbrook | #define laddr(x) g2h(x)
|
600 | 53a5960a | pbrook | |
601 | 53a5960a | pbrook | #else /* !CONFIG_USER_ONLY */ |
602 | c27004ec | bellard | /* NOTE: we use double casts if pointers and target_ulong have
|
603 | c27004ec | bellard | different sizes */
|
604 | 53a5960a | pbrook | #define saddr(x) (uint8_t *)(long)(x) |
605 | 53a5960a | pbrook | #define laddr(x) (uint8_t *)(long)(x) |
606 | 53a5960a | pbrook | #endif
|
607 | 53a5960a | pbrook | |
608 | 53a5960a | pbrook | #define ldub_raw(p) ldub_p(laddr((p)))
|
609 | 53a5960a | pbrook | #define ldsb_raw(p) ldsb_p(laddr((p)))
|
610 | 53a5960a | pbrook | #define lduw_raw(p) lduw_p(laddr((p)))
|
611 | 53a5960a | pbrook | #define ldsw_raw(p) ldsw_p(laddr((p)))
|
612 | 53a5960a | pbrook | #define ldl_raw(p) ldl_p(laddr((p)))
|
613 | 53a5960a | pbrook | #define ldq_raw(p) ldq_p(laddr((p)))
|
614 | 53a5960a | pbrook | #define ldfl_raw(p) ldfl_p(laddr((p)))
|
615 | 53a5960a | pbrook | #define ldfq_raw(p) ldfq_p(laddr((p)))
|
616 | 53a5960a | pbrook | #define stb_raw(p, v) stb_p(saddr((p)), v)
|
617 | 53a5960a | pbrook | #define stw_raw(p, v) stw_p(saddr((p)), v)
|
618 | 53a5960a | pbrook | #define stl_raw(p, v) stl_p(saddr((p)), v)
|
619 | 53a5960a | pbrook | #define stq_raw(p, v) stq_p(saddr((p)), v)
|
620 | 53a5960a | pbrook | #define stfl_raw(p, v) stfl_p(saddr((p)), v)
|
621 | 53a5960a | pbrook | #define stfq_raw(p, v) stfq_p(saddr((p)), v)
|
622 | c27004ec | bellard | |
623 | c27004ec | bellard | |
624 | 61382a50 | bellard | #if defined(CONFIG_USER_ONLY)
|
625 | 61382a50 | bellard | |
626 | 61382a50 | bellard | /* if user mode, no other memory access functions */
|
627 | 61382a50 | bellard | #define ldub(p) ldub_raw(p)
|
628 | 61382a50 | bellard | #define ldsb(p) ldsb_raw(p)
|
629 | 61382a50 | bellard | #define lduw(p) lduw_raw(p)
|
630 | 61382a50 | bellard | #define ldsw(p) ldsw_raw(p)
|
631 | 61382a50 | bellard | #define ldl(p) ldl_raw(p)
|
632 | 61382a50 | bellard | #define ldq(p) ldq_raw(p)
|
633 | 61382a50 | bellard | #define ldfl(p) ldfl_raw(p)
|
634 | 61382a50 | bellard | #define ldfq(p) ldfq_raw(p)
|
635 | 61382a50 | bellard | #define stb(p, v) stb_raw(p, v)
|
636 | 61382a50 | bellard | #define stw(p, v) stw_raw(p, v)
|
637 | 61382a50 | bellard | #define stl(p, v) stl_raw(p, v)
|
638 | 61382a50 | bellard | #define stq(p, v) stq_raw(p, v)
|
639 | 61382a50 | bellard | #define stfl(p, v) stfl_raw(p, v)
|
640 | 61382a50 | bellard | #define stfq(p, v) stfq_raw(p, v)
|
641 | 61382a50 | bellard | |
642 | 61382a50 | bellard | #define ldub_code(p) ldub_raw(p)
|
643 | 61382a50 | bellard | #define ldsb_code(p) ldsb_raw(p)
|
644 | 61382a50 | bellard | #define lduw_code(p) lduw_raw(p)
|
645 | 61382a50 | bellard | #define ldsw_code(p) ldsw_raw(p)
|
646 | 61382a50 | bellard | #define ldl_code(p) ldl_raw(p)
|
647 | bc98a7ef | j_mayer | #define ldq_code(p) ldq_raw(p)
|
648 | 61382a50 | bellard | |
649 | 61382a50 | bellard | #define ldub_kernel(p) ldub_raw(p)
|
650 | 61382a50 | bellard | #define ldsb_kernel(p) ldsb_raw(p)
|
651 | 61382a50 | bellard | #define lduw_kernel(p) lduw_raw(p)
|
652 | 61382a50 | bellard | #define ldsw_kernel(p) ldsw_raw(p)
|
653 | 61382a50 | bellard | #define ldl_kernel(p) ldl_raw(p)
|
654 | bc98a7ef | j_mayer | #define ldq_kernel(p) ldq_raw(p)
|
655 | 0ac4bd56 | bellard | #define ldfl_kernel(p) ldfl_raw(p)
|
656 | 0ac4bd56 | bellard | #define ldfq_kernel(p) ldfq_raw(p)
|
657 | 61382a50 | bellard | #define stb_kernel(p, v) stb_raw(p, v)
|
658 | 61382a50 | bellard | #define stw_kernel(p, v) stw_raw(p, v)
|
659 | 61382a50 | bellard | #define stl_kernel(p, v) stl_raw(p, v)
|
660 | 61382a50 | bellard | #define stq_kernel(p, v) stq_raw(p, v)
|
661 | 0ac4bd56 | bellard | #define stfl_kernel(p, v) stfl_raw(p, v)
|
662 | 0ac4bd56 | bellard | #define stfq_kernel(p, vt) stfq_raw(p, v)
|
663 | 61382a50 | bellard | |
664 | 61382a50 | bellard | #endif /* defined(CONFIG_USER_ONLY) */ |
665 | 61382a50 | bellard | |
666 | 5a9fdfec | bellard | /* page related stuff */
|
667 | 5a9fdfec | bellard | |
668 | 5a9fdfec | bellard | #define TARGET_PAGE_SIZE (1 << TARGET_PAGE_BITS) |
669 | 5a9fdfec | bellard | #define TARGET_PAGE_MASK ~(TARGET_PAGE_SIZE - 1) |
670 | 5a9fdfec | bellard | #define TARGET_PAGE_ALIGN(addr) (((addr) + TARGET_PAGE_SIZE - 1) & TARGET_PAGE_MASK) |
671 | 5a9fdfec | bellard | |
672 | 53a5960a | pbrook | /* ??? These should be the larger of unsigned long and target_ulong. */
|
673 | 83fb7adf | bellard | extern unsigned long qemu_real_host_page_size; |
674 | 83fb7adf | bellard | extern unsigned long qemu_host_page_bits; |
675 | 83fb7adf | bellard | extern unsigned long qemu_host_page_size; |
676 | 83fb7adf | bellard | extern unsigned long qemu_host_page_mask; |
677 | 5a9fdfec | bellard | |
678 | 83fb7adf | bellard | #define HOST_PAGE_ALIGN(addr) (((addr) + qemu_host_page_size - 1) & qemu_host_page_mask) |
679 | 5a9fdfec | bellard | |
680 | 5a9fdfec | bellard | /* same as PROT_xxx */
|
681 | 5a9fdfec | bellard | #define PAGE_READ 0x0001 |
682 | 5a9fdfec | bellard | #define PAGE_WRITE 0x0002 |
683 | 5a9fdfec | bellard | #define PAGE_EXEC 0x0004 |
684 | 5a9fdfec | bellard | #define PAGE_BITS (PAGE_READ | PAGE_WRITE | PAGE_EXEC)
|
685 | 5a9fdfec | bellard | #define PAGE_VALID 0x0008 |
686 | 5a9fdfec | bellard | /* original state of the write flag (used when tracking self-modifying
|
687 | 5a9fdfec | bellard | code */
|
688 | 5a9fdfec | bellard | #define PAGE_WRITE_ORG 0x0010 |
689 | 5a9fdfec | bellard | |
690 | 5a9fdfec | bellard | void page_dump(FILE *f);
|
691 | 53a5960a | pbrook | int page_get_flags(target_ulong address);
|
692 | 53a5960a | pbrook | void page_set_flags(target_ulong start, target_ulong end, int flags); |
693 | 53a5960a | pbrook | void page_unprotect_range(target_ulong data, target_ulong data_size);
|
694 | 5a9fdfec | bellard | |
695 | 5a9fdfec | bellard | #define SINGLE_CPU_DEFINES
|
696 | 5a9fdfec | bellard | #ifdef SINGLE_CPU_DEFINES
|
697 | 5a9fdfec | bellard | |
698 | 5a9fdfec | bellard | #if defined(TARGET_I386)
|
699 | 5a9fdfec | bellard | |
700 | 5a9fdfec | bellard | #define CPUState CPUX86State
|
701 | 5a9fdfec | bellard | #define cpu_init cpu_x86_init
|
702 | 5a9fdfec | bellard | #define cpu_exec cpu_x86_exec
|
703 | 5a9fdfec | bellard | #define cpu_gen_code cpu_x86_gen_code
|
704 | 5a9fdfec | bellard | #define cpu_signal_handler cpu_x86_signal_handler
|
705 | 5a9fdfec | bellard | |
706 | 5a9fdfec | bellard | #elif defined(TARGET_ARM)
|
707 | 5a9fdfec | bellard | |
708 | 5a9fdfec | bellard | #define CPUState CPUARMState
|
709 | 5a9fdfec | bellard | #define cpu_init cpu_arm_init
|
710 | 5a9fdfec | bellard | #define cpu_exec cpu_arm_exec
|
711 | 5a9fdfec | bellard | #define cpu_gen_code cpu_arm_gen_code
|
712 | 5a9fdfec | bellard | #define cpu_signal_handler cpu_arm_signal_handler
|
713 | 5a9fdfec | bellard | |
714 | 93ac68bc | bellard | #elif defined(TARGET_SPARC)
|
715 | 93ac68bc | bellard | |
716 | 93ac68bc | bellard | #define CPUState CPUSPARCState
|
717 | 93ac68bc | bellard | #define cpu_init cpu_sparc_init
|
718 | 93ac68bc | bellard | #define cpu_exec cpu_sparc_exec
|
719 | 93ac68bc | bellard | #define cpu_gen_code cpu_sparc_gen_code
|
720 | 93ac68bc | bellard | #define cpu_signal_handler cpu_sparc_signal_handler
|
721 | 93ac68bc | bellard | |
722 | 67867308 | bellard | #elif defined(TARGET_PPC)
|
723 | 67867308 | bellard | |
724 | 67867308 | bellard | #define CPUState CPUPPCState
|
725 | 67867308 | bellard | #define cpu_init cpu_ppc_init
|
726 | 67867308 | bellard | #define cpu_exec cpu_ppc_exec
|
727 | 67867308 | bellard | #define cpu_gen_code cpu_ppc_gen_code
|
728 | 67867308 | bellard | #define cpu_signal_handler cpu_ppc_signal_handler
|
729 | 67867308 | bellard | |
730 | e6e5906b | pbrook | #elif defined(TARGET_M68K)
|
731 | e6e5906b | pbrook | #define CPUState CPUM68KState
|
732 | e6e5906b | pbrook | #define cpu_init cpu_m68k_init
|
733 | e6e5906b | pbrook | #define cpu_exec cpu_m68k_exec
|
734 | e6e5906b | pbrook | #define cpu_gen_code cpu_m68k_gen_code
|
735 | e6e5906b | pbrook | #define cpu_signal_handler cpu_m68k_signal_handler
|
736 | e6e5906b | pbrook | |
737 | 6af0bf9c | bellard | #elif defined(TARGET_MIPS)
|
738 | 6af0bf9c | bellard | #define CPUState CPUMIPSState
|
739 | 6af0bf9c | bellard | #define cpu_init cpu_mips_init
|
740 | 6af0bf9c | bellard | #define cpu_exec cpu_mips_exec
|
741 | 6af0bf9c | bellard | #define cpu_gen_code cpu_mips_gen_code
|
742 | 6af0bf9c | bellard | #define cpu_signal_handler cpu_mips_signal_handler
|
743 | 6af0bf9c | bellard | |
744 | fdf9b3e8 | bellard | #elif defined(TARGET_SH4)
|
745 | fdf9b3e8 | bellard | #define CPUState CPUSH4State
|
746 | fdf9b3e8 | bellard | #define cpu_init cpu_sh4_init
|
747 | fdf9b3e8 | bellard | #define cpu_exec cpu_sh4_exec
|
748 | fdf9b3e8 | bellard | #define cpu_gen_code cpu_sh4_gen_code
|
749 | fdf9b3e8 | bellard | #define cpu_signal_handler cpu_sh4_signal_handler
|
750 | fdf9b3e8 | bellard | |
751 | 5a9fdfec | bellard | #else
|
752 | 5a9fdfec | bellard | |
753 | 5a9fdfec | bellard | #error unsupported target CPU
|
754 | 5a9fdfec | bellard | |
755 | 5a9fdfec | bellard | #endif
|
756 | 5a9fdfec | bellard | |
757 | 972ddf78 | bellard | #endif /* SINGLE_CPU_DEFINES */ |
758 | 972ddf78 | bellard | |
759 | c5be9f08 | ths | CPUState *cpu_copy(CPUState *env); |
760 | c5be9f08 | ths | |
761 | 7fe48483 | bellard | void cpu_dump_state(CPUState *env, FILE *f,
|
762 | 7fe48483 | bellard | int (*cpu_fprintf)(FILE *f, const char *fmt, ...), |
763 | 7fe48483 | bellard | int flags);
|
764 | 76a66253 | j_mayer | void cpu_dump_statistics (CPUState *env, FILE *f,
|
765 | 76a66253 | j_mayer | int (*cpu_fprintf)(FILE *f, const char *fmt, ...), |
766 | 76a66253 | j_mayer | int flags);
|
767 | 7fe48483 | bellard | |
768 | 972ddf78 | bellard | void cpu_abort(CPUState *env, const char *fmt, ...); |
769 | f0aca822 | bellard | extern CPUState *first_cpu;
|
770 | e2f22898 | bellard | extern CPUState *cpu_single_env;
|
771 | 9acbed06 | bellard | extern int code_copy_enabled; |
772 | 5a9fdfec | bellard | |
773 | 9acbed06 | bellard | #define CPU_INTERRUPT_EXIT 0x01 /* wants exit from main loop */ |
774 | 9acbed06 | bellard | #define CPU_INTERRUPT_HARD 0x02 /* hardware interrupt pending */ |
775 | 9acbed06 | bellard | #define CPU_INTERRUPT_EXITTB 0x04 /* exit the current TB (use for x86 a20 case) */ |
776 | ef792f9d | bellard | #define CPU_INTERRUPT_TIMER 0x08 /* internal timer exception pending */ |
777 | 98699967 | bellard | #define CPU_INTERRUPT_FIQ 0x10 /* Fast interrupt pending. */ |
778 | ba3c64fb | bellard | #define CPU_INTERRUPT_HALT 0x20 /* CPU halt wanted */ |
779 | 3b21e03e | bellard | #define CPU_INTERRUPT_SMI 0x40 /* (x86 only) SMI interrupt pending */ |
780 | 6658ffb8 | pbrook | #define CPU_INTERRUPT_DEBUG 0x80 /* Debug event occured. */ |
781 | 98699967 | bellard | |
782 | 4690764b | bellard | void cpu_interrupt(CPUState *s, int mask); |
783 | b54ad049 | bellard | void cpu_reset_interrupt(CPUState *env, int mask); |
784 | 68a79315 | bellard | |
785 | 6658ffb8 | pbrook | int cpu_watchpoint_insert(CPUState *env, target_ulong addr);
|
786 | 6658ffb8 | pbrook | int cpu_watchpoint_remove(CPUState *env, target_ulong addr);
|
787 | 2e12669a | bellard | int cpu_breakpoint_insert(CPUState *env, target_ulong pc);
|
788 | 2e12669a | bellard | int cpu_breakpoint_remove(CPUState *env, target_ulong pc);
|
789 | c33a346e | bellard | void cpu_single_step(CPUState *env, int enabled); |
790 | d95dc32d | bellard | void cpu_reset(CPUState *s);
|
791 | 4c3a88a2 | bellard | |
792 | 13eb76e0 | bellard | /* Return the physical page corresponding to a virtual one. Use it
|
793 | 13eb76e0 | bellard | only for debugging because no protection checks are done. Return -1
|
794 | 13eb76e0 | bellard | if no page found. */
|
795 | 13eb76e0 | bellard | target_ulong cpu_get_phys_page_debug(CPUState *env, target_ulong addr); |
796 | 13eb76e0 | bellard | |
797 | 9fddaa0c | bellard | #define CPU_LOG_TB_OUT_ASM (1 << 0) |
798 | 9fddaa0c | bellard | #define CPU_LOG_TB_IN_ASM (1 << 1) |
799 | f193c797 | bellard | #define CPU_LOG_TB_OP (1 << 2) |
800 | f193c797 | bellard | #define CPU_LOG_TB_OP_OPT (1 << 3) |
801 | f193c797 | bellard | #define CPU_LOG_INT (1 << 4) |
802 | f193c797 | bellard | #define CPU_LOG_EXEC (1 << 5) |
803 | f193c797 | bellard | #define CPU_LOG_PCALL (1 << 6) |
804 | fd872598 | bellard | #define CPU_LOG_IOPORT (1 << 7) |
805 | 9fddaa0c | bellard | #define CPU_LOG_TB_CPU (1 << 8) |
806 | f193c797 | bellard | |
807 | f193c797 | bellard | /* define log items */
|
808 | f193c797 | bellard | typedef struct CPULogItem { |
809 | f193c797 | bellard | int mask;
|
810 | f193c797 | bellard | const char *name; |
811 | f193c797 | bellard | const char *help; |
812 | f193c797 | bellard | } CPULogItem; |
813 | f193c797 | bellard | |
814 | f193c797 | bellard | extern CPULogItem cpu_log_items[];
|
815 | f193c797 | bellard | |
816 | 34865134 | bellard | void cpu_set_log(int log_flags); |
817 | 34865134 | bellard | void cpu_set_log_filename(const char *filename); |
818 | f193c797 | bellard | int cpu_str_to_log_mask(const char *str); |
819 | 34865134 | bellard | |
820 | 09683d35 | bellard | /* IO ports API */
|
821 | 09683d35 | bellard | |
822 | 09683d35 | bellard | /* NOTE: as these functions may be even used when there is an isa
|
823 | 09683d35 | bellard | brige on non x86 targets, we always defined them */
|
824 | 09683d35 | bellard | #ifndef NO_CPU_IO_DEFS
|
825 | 09683d35 | bellard | void cpu_outb(CPUState *env, int addr, int val); |
826 | 09683d35 | bellard | void cpu_outw(CPUState *env, int addr, int val); |
827 | 09683d35 | bellard | void cpu_outl(CPUState *env, int addr, int val); |
828 | 09683d35 | bellard | int cpu_inb(CPUState *env, int addr); |
829 | 09683d35 | bellard | int cpu_inw(CPUState *env, int addr); |
830 | 09683d35 | bellard | int cpu_inl(CPUState *env, int addr); |
831 | 09683d35 | bellard | #endif
|
832 | 09683d35 | bellard | |
833 | 33417e70 | bellard | /* memory API */
|
834 | 33417e70 | bellard | |
835 | edf75d59 | bellard | extern int phys_ram_size; |
836 | edf75d59 | bellard | extern int phys_ram_fd; |
837 | edf75d59 | bellard | extern uint8_t *phys_ram_base;
|
838 | 1ccde1cb | bellard | extern uint8_t *phys_ram_dirty;
|
839 | edf75d59 | bellard | |
840 | edf75d59 | bellard | /* physical memory access */
|
841 | edf75d59 | bellard | #define TLB_INVALID_MASK (1 << 3) |
842 | edf75d59 | bellard | #define IO_MEM_SHIFT 4 |
843 | 98699967 | bellard | #define IO_MEM_NB_ENTRIES (1 << (TARGET_PAGE_BITS - IO_MEM_SHIFT)) |
844 | edf75d59 | bellard | |
845 | edf75d59 | bellard | #define IO_MEM_RAM (0 << IO_MEM_SHIFT) /* hardcoded offset */ |
846 | edf75d59 | bellard | #define IO_MEM_ROM (1 << IO_MEM_SHIFT) /* hardcoded offset */ |
847 | edf75d59 | bellard | #define IO_MEM_UNASSIGNED (2 << IO_MEM_SHIFT) |
848 | 1ccde1cb | bellard | #define IO_MEM_NOTDIRTY (4 << IO_MEM_SHIFT) /* used internally, never use directly */ |
849 | 2a4188a3 | bellard | /* acts like a ROM when read and like a device when written. As an
|
850 | 2a4188a3 | bellard | exception, the write memory callback gets the ram offset instead of
|
851 | 2a4188a3 | bellard | the physical address */
|
852 | 2a4188a3 | bellard | #define IO_MEM_ROMD (1) |
853 | edf75d59 | bellard | |
854 | 7727994d | bellard | typedef void CPUWriteMemoryFunc(void *opaque, target_phys_addr_t addr, uint32_t value); |
855 | 7727994d | bellard | typedef uint32_t CPUReadMemoryFunc(void *opaque, target_phys_addr_t addr); |
856 | 33417e70 | bellard | |
857 | 2e12669a | bellard | void cpu_register_physical_memory(target_phys_addr_t start_addr,
|
858 | 2e12669a | bellard | unsigned long size, |
859 | 2e12669a | bellard | unsigned long phys_offset); |
860 | 3b21e03e | bellard | uint32_t cpu_get_physical_page_desc(target_phys_addr_t addr); |
861 | e9a1ab19 | bellard | ram_addr_t qemu_ram_alloc(unsigned int size); |
862 | e9a1ab19 | bellard | void qemu_ram_free(ram_addr_t addr);
|
863 | 33417e70 | bellard | int cpu_register_io_memory(int io_index, |
864 | 33417e70 | bellard | CPUReadMemoryFunc **mem_read, |
865 | 7727994d | bellard | CPUWriteMemoryFunc **mem_write, |
866 | 7727994d | bellard | void *opaque);
|
867 | 8926b517 | bellard | CPUWriteMemoryFunc **cpu_get_io_memory_write(int io_index);
|
868 | 8926b517 | bellard | CPUReadMemoryFunc **cpu_get_io_memory_read(int io_index);
|
869 | 33417e70 | bellard | |
870 | 2e12669a | bellard | void cpu_physical_memory_rw(target_phys_addr_t addr, uint8_t *buf,
|
871 | 13eb76e0 | bellard | int len, int is_write); |
872 | 2e12669a | bellard | static inline void cpu_physical_memory_read(target_phys_addr_t addr, |
873 | 2e12669a | bellard | uint8_t *buf, int len)
|
874 | 8b1f24b0 | bellard | { |
875 | 8b1f24b0 | bellard | cpu_physical_memory_rw(addr, buf, len, 0);
|
876 | 8b1f24b0 | bellard | } |
877 | 2e12669a | bellard | static inline void cpu_physical_memory_write(target_phys_addr_t addr, |
878 | 2e12669a | bellard | const uint8_t *buf, int len) |
879 | 8b1f24b0 | bellard | { |
880 | 8b1f24b0 | bellard | cpu_physical_memory_rw(addr, (uint8_t *)buf, len, 1);
|
881 | 8b1f24b0 | bellard | } |
882 | aab33094 | bellard | uint32_t ldub_phys(target_phys_addr_t addr); |
883 | aab33094 | bellard | uint32_t lduw_phys(target_phys_addr_t addr); |
884 | 8df1cd07 | bellard | uint32_t ldl_phys(target_phys_addr_t addr); |
885 | aab33094 | bellard | uint64_t ldq_phys(target_phys_addr_t addr); |
886 | 8df1cd07 | bellard | void stl_phys_notdirty(target_phys_addr_t addr, uint32_t val);
|
887 | bc98a7ef | j_mayer | void stq_phys_notdirty(target_phys_addr_t addr, uint64_t val);
|
888 | aab33094 | bellard | void stb_phys(target_phys_addr_t addr, uint32_t val);
|
889 | aab33094 | bellard | void stw_phys(target_phys_addr_t addr, uint32_t val);
|
890 | 8df1cd07 | bellard | void stl_phys(target_phys_addr_t addr, uint32_t val);
|
891 | aab33094 | bellard | void stq_phys(target_phys_addr_t addr, uint64_t val);
|
892 | 8b1f24b0 | bellard | |
893 | d0ecd2aa | bellard | void cpu_physical_memory_write_rom(target_phys_addr_t addr,
|
894 | d0ecd2aa | bellard | const uint8_t *buf, int len); |
895 | 8b1f24b0 | bellard | int cpu_memory_rw_debug(CPUState *env, target_ulong addr,
|
896 | 8b1f24b0 | bellard | uint8_t *buf, int len, int is_write); |
897 | 13eb76e0 | bellard | |
898 | 04c504cc | bellard | #define VGA_DIRTY_FLAG 0x01 |
899 | 04c504cc | bellard | #define CODE_DIRTY_FLAG 0x02 |
900 | 0a962c02 | bellard | |
901 | 1ccde1cb | bellard | /* read dirty bit (return 0 or 1) */
|
902 | 04c504cc | bellard | static inline int cpu_physical_memory_is_dirty(ram_addr_t addr) |
903 | 1ccde1cb | bellard | { |
904 | 0a962c02 | bellard | return phys_ram_dirty[addr >> TARGET_PAGE_BITS] == 0xff; |
905 | 0a962c02 | bellard | } |
906 | 0a962c02 | bellard | |
907 | 04c504cc | bellard | static inline int cpu_physical_memory_get_dirty(ram_addr_t addr, |
908 | 0a962c02 | bellard | int dirty_flags)
|
909 | 0a962c02 | bellard | { |
910 | 0a962c02 | bellard | return phys_ram_dirty[addr >> TARGET_PAGE_BITS] & dirty_flags;
|
911 | 1ccde1cb | bellard | } |
912 | 1ccde1cb | bellard | |
913 | 04c504cc | bellard | static inline void cpu_physical_memory_set_dirty(ram_addr_t addr) |
914 | 1ccde1cb | bellard | { |
915 | 0a962c02 | bellard | phys_ram_dirty[addr >> TARGET_PAGE_BITS] = 0xff;
|
916 | 1ccde1cb | bellard | } |
917 | 1ccde1cb | bellard | |
918 | 04c504cc | bellard | void cpu_physical_memory_reset_dirty(ram_addr_t start, ram_addr_t end,
|
919 | 0a962c02 | bellard | int dirty_flags);
|
920 | 04c504cc | bellard | void cpu_tlb_update_dirty(CPUState *env);
|
921 | 1ccde1cb | bellard | |
922 | e3db7226 | bellard | void dump_exec_info(FILE *f,
|
923 | e3db7226 | bellard | int (*cpu_fprintf)(FILE *f, const char *fmt, ...)); |
924 | e3db7226 | bellard | |
925 | effedbc9 | bellard | /*******************************************/
|
926 | effedbc9 | bellard | /* host CPU ticks (if available) */
|
927 | effedbc9 | bellard | |
928 | effedbc9 | bellard | #if defined(__powerpc__)
|
929 | effedbc9 | bellard | |
930 | effedbc9 | bellard | static inline uint32_t get_tbl(void) |
931 | effedbc9 | bellard | { |
932 | effedbc9 | bellard | uint32_t tbl; |
933 | effedbc9 | bellard | asm volatile("mftb %0" : "=r" (tbl)); |
934 | effedbc9 | bellard | return tbl;
|
935 | effedbc9 | bellard | } |
936 | effedbc9 | bellard | |
937 | effedbc9 | bellard | static inline uint32_t get_tbu(void) |
938 | effedbc9 | bellard | { |
939 | effedbc9 | bellard | uint32_t tbl; |
940 | effedbc9 | bellard | asm volatile("mftbu %0" : "=r" (tbl)); |
941 | effedbc9 | bellard | return tbl;
|
942 | effedbc9 | bellard | } |
943 | effedbc9 | bellard | |
944 | effedbc9 | bellard | static inline int64_t cpu_get_real_ticks(void) |
945 | effedbc9 | bellard | { |
946 | effedbc9 | bellard | uint32_t l, h, h1; |
947 | effedbc9 | bellard | /* NOTE: we test if wrapping has occurred */
|
948 | effedbc9 | bellard | do {
|
949 | effedbc9 | bellard | h = get_tbu(); |
950 | effedbc9 | bellard | l = get_tbl(); |
951 | effedbc9 | bellard | h1 = get_tbu(); |
952 | effedbc9 | bellard | } while (h != h1);
|
953 | effedbc9 | bellard | return ((int64_t)h << 32) | l; |
954 | effedbc9 | bellard | } |
955 | effedbc9 | bellard | |
956 | effedbc9 | bellard | #elif defined(__i386__)
|
957 | effedbc9 | bellard | |
958 | effedbc9 | bellard | static inline int64_t cpu_get_real_ticks(void) |
959 | 5f1ce948 | bellard | { |
960 | 5f1ce948 | bellard | int64_t val; |
961 | 5f1ce948 | bellard | asm volatile ("rdtsc" : "=A" (val)); |
962 | 5f1ce948 | bellard | return val;
|
963 | 5f1ce948 | bellard | } |
964 | 5f1ce948 | bellard | |
965 | effedbc9 | bellard | #elif defined(__x86_64__)
|
966 | effedbc9 | bellard | |
967 | effedbc9 | bellard | static inline int64_t cpu_get_real_ticks(void) |
968 | effedbc9 | bellard | { |
969 | effedbc9 | bellard | uint32_t low,high; |
970 | effedbc9 | bellard | int64_t val; |
971 | effedbc9 | bellard | asm volatile("rdtsc" : "=a" (low), "=d" (high)); |
972 | effedbc9 | bellard | val = high; |
973 | effedbc9 | bellard | val <<= 32;
|
974 | effedbc9 | bellard | val |= low; |
975 | effedbc9 | bellard | return val;
|
976 | effedbc9 | bellard | } |
977 | effedbc9 | bellard | |
978 | effedbc9 | bellard | #elif defined(__ia64)
|
979 | effedbc9 | bellard | |
980 | effedbc9 | bellard | static inline int64_t cpu_get_real_ticks(void) |
981 | effedbc9 | bellard | { |
982 | effedbc9 | bellard | int64_t val; |
983 | effedbc9 | bellard | asm volatile ("mov %0 = ar.itc" : "=r"(val) :: "memory"); |
984 | effedbc9 | bellard | return val;
|
985 | effedbc9 | bellard | } |
986 | effedbc9 | bellard | |
987 | effedbc9 | bellard | #elif defined(__s390__)
|
988 | effedbc9 | bellard | |
989 | effedbc9 | bellard | static inline int64_t cpu_get_real_ticks(void) |
990 | effedbc9 | bellard | { |
991 | effedbc9 | bellard | int64_t val; |
992 | effedbc9 | bellard | asm volatile("stck 0(%1)" : "=m" (val) : "a" (&val) : "cc"); |
993 | effedbc9 | bellard | return val;
|
994 | effedbc9 | bellard | } |
995 | effedbc9 | bellard | |
996 | 74ccb34e | bellard | #elif defined(__sparc_v9__)
|
997 | effedbc9 | bellard | |
998 | effedbc9 | bellard | static inline int64_t cpu_get_real_ticks (void) |
999 | effedbc9 | bellard | { |
1000 | effedbc9 | bellard | #if defined(_LP64)
|
1001 | effedbc9 | bellard | uint64_t rval; |
1002 | effedbc9 | bellard | asm volatile("rd %%tick,%0" : "=r"(rval)); |
1003 | effedbc9 | bellard | return rval;
|
1004 | effedbc9 | bellard | #else
|
1005 | effedbc9 | bellard | union {
|
1006 | effedbc9 | bellard | uint64_t i64; |
1007 | effedbc9 | bellard | struct {
|
1008 | effedbc9 | bellard | uint32_t high; |
1009 | effedbc9 | bellard | uint32_t low; |
1010 | effedbc9 | bellard | } i32; |
1011 | effedbc9 | bellard | } rval; |
1012 | effedbc9 | bellard | asm volatile("rd %%tick,%1; srlx %1,32,%0" |
1013 | effedbc9 | bellard | : "=r"(rval.i32.high), "=r"(rval.i32.low)); |
1014 | effedbc9 | bellard | return rval.i64;
|
1015 | effedbc9 | bellard | #endif
|
1016 | effedbc9 | bellard | } |
1017 | 46152182 | pbrook | #else
|
1018 | 46152182 | pbrook | /* The host CPU doesn't have an easily accessible cycle counter.
|
1019 | 46152182 | pbrook | Just return a monotonically increasing vlue. This will be totally wrong,
|
1020 | 46152182 | pbrook | but hopefully better than nothing. */
|
1021 | 46152182 | pbrook | static inline int64_t cpu_get_real_ticks (void) |
1022 | 46152182 | pbrook | { |
1023 | 46152182 | pbrook | static int64_t ticks = 0; |
1024 | 46152182 | pbrook | return ticks++;
|
1025 | 46152182 | pbrook | } |
1026 | effedbc9 | bellard | #endif
|
1027 | effedbc9 | bellard | |
1028 | effedbc9 | bellard | /* profiling */
|
1029 | effedbc9 | bellard | #ifdef CONFIG_PROFILER
|
1030 | effedbc9 | bellard | static inline int64_t profile_getclock(void) |
1031 | effedbc9 | bellard | { |
1032 | effedbc9 | bellard | return cpu_get_real_ticks();
|
1033 | effedbc9 | bellard | } |
1034 | effedbc9 | bellard | |
1035 | 5f1ce948 | bellard | extern int64_t kqemu_time, kqemu_time_start;
|
1036 | 5f1ce948 | bellard | extern int64_t qemu_time, qemu_time_start;
|
1037 | 5f1ce948 | bellard | extern int64_t tlb_flush_time;
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1038 | 5f1ce948 | bellard | extern int64_t kqemu_exec_count;
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1039 | 5f1ce948 | bellard | extern int64_t dev_time;
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1040 | 5f1ce948 | bellard | extern int64_t kqemu_ret_int_count;
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1041 | 5f1ce948 | bellard | extern int64_t kqemu_ret_excp_count;
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1042 | 5f1ce948 | bellard | extern int64_t kqemu_ret_intr_count;
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1043 | 5f1ce948 | bellard | |
1044 | 5f1ce948 | bellard | #endif
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1045 | 5f1ce948 | bellard | |
1046 | 5a9fdfec | bellard | #endif /* CPU_ALL_H */ |