root / sh4-dis.c @ 86cc1ce0
History | View | Annotate | Download (83.1 kB)
1 | fdf9b3e8 | bellard | /* Disassemble SH instructions.
|
---|---|---|---|
2 | fdf9b3e8 | bellard | Copyright 1993, 1994, 1995, 1997, 1998, 2000, 2001, 2002, 2003, 2004
|
3 | fdf9b3e8 | bellard | Free Software Foundation, Inc.
|
4 | fdf9b3e8 | bellard | |
5 | fdf9b3e8 | bellard | This program is free software; you can redistribute it and/or modify
|
6 | fdf9b3e8 | bellard | it under the terms of the GNU General Public License as published by
|
7 | fdf9b3e8 | bellard | the Free Software Foundation; either version 2 of the License, or
|
8 | fdf9b3e8 | bellard | (at your option) any later version.
|
9 | fdf9b3e8 | bellard | |
10 | fdf9b3e8 | bellard | This program is distributed in the hope that it will be useful,
|
11 | fdf9b3e8 | bellard | but WITHOUT ANY WARRANTY; without even the implied warranty of
|
12 | fdf9b3e8 | bellard | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
13 | fdf9b3e8 | bellard | GNU General Public License for more details.
|
14 | fdf9b3e8 | bellard | |
15 | fdf9b3e8 | bellard | You should have received a copy of the GNU General Public License
|
16 | fdf9b3e8 | bellard | along with this program; if not, write to the Free Software
|
17 | fdf9b3e8 | bellard | Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
|
18 | fdf9b3e8 | bellard | |
19 | fdf9b3e8 | bellard | #include <stdio.h> |
20 | fdf9b3e8 | bellard | #include "dis-asm.h" |
21 | fdf9b3e8 | bellard | |
22 | fdf9b3e8 | bellard | #define DEFINE_TABLE
|
23 | fdf9b3e8 | bellard | |
24 | fdf9b3e8 | bellard | typedef enum |
25 | fdf9b3e8 | bellard | { |
26 | fdf9b3e8 | bellard | HEX_0, |
27 | fdf9b3e8 | bellard | HEX_1, |
28 | fdf9b3e8 | bellard | HEX_2, |
29 | fdf9b3e8 | bellard | HEX_3, |
30 | fdf9b3e8 | bellard | HEX_4, |
31 | fdf9b3e8 | bellard | HEX_5, |
32 | fdf9b3e8 | bellard | HEX_6, |
33 | fdf9b3e8 | bellard | HEX_7, |
34 | fdf9b3e8 | bellard | HEX_8, |
35 | fdf9b3e8 | bellard | HEX_9, |
36 | fdf9b3e8 | bellard | HEX_A, |
37 | fdf9b3e8 | bellard | HEX_B, |
38 | fdf9b3e8 | bellard | HEX_C, |
39 | fdf9b3e8 | bellard | HEX_D, |
40 | fdf9b3e8 | bellard | HEX_E, |
41 | fdf9b3e8 | bellard | HEX_F, |
42 | fdf9b3e8 | bellard | HEX_XX00, |
43 | fdf9b3e8 | bellard | HEX_00YY, |
44 | fdf9b3e8 | bellard | REG_N, |
45 | fdf9b3e8 | bellard | REG_N_D, /* nnn0 */
|
46 | fdf9b3e8 | bellard | REG_N_B01, /* nn01 */
|
47 | fdf9b3e8 | bellard | REG_M, |
48 | fdf9b3e8 | bellard | SDT_REG_N, |
49 | fdf9b3e8 | bellard | REG_NM, |
50 | fdf9b3e8 | bellard | REG_B, |
51 | fdf9b3e8 | bellard | BRANCH_12, |
52 | fdf9b3e8 | bellard | BRANCH_8, |
53 | fdf9b3e8 | bellard | IMM0_4, |
54 | fdf9b3e8 | bellard | IMM0_4BY2, |
55 | fdf9b3e8 | bellard | IMM0_4BY4, |
56 | fdf9b3e8 | bellard | IMM1_4, |
57 | fdf9b3e8 | bellard | IMM1_4BY2, |
58 | fdf9b3e8 | bellard | IMM1_4BY4, |
59 | fdf9b3e8 | bellard | PCRELIMM_8BY2, |
60 | fdf9b3e8 | bellard | PCRELIMM_8BY4, |
61 | fdf9b3e8 | bellard | IMM0_8, |
62 | fdf9b3e8 | bellard | IMM0_8BY2, |
63 | fdf9b3e8 | bellard | IMM0_8BY4, |
64 | fdf9b3e8 | bellard | IMM1_8, |
65 | fdf9b3e8 | bellard | IMM1_8BY2, |
66 | fdf9b3e8 | bellard | IMM1_8BY4, |
67 | fdf9b3e8 | bellard | PPI, |
68 | fdf9b3e8 | bellard | NOPX, |
69 | fdf9b3e8 | bellard | NOPY, |
70 | fdf9b3e8 | bellard | MOVX, |
71 | fdf9b3e8 | bellard | MOVY, |
72 | fdf9b3e8 | bellard | MOVX_NOPY, |
73 | fdf9b3e8 | bellard | MOVY_NOPX, |
74 | fdf9b3e8 | bellard | PSH, |
75 | fdf9b3e8 | bellard | PMUL, |
76 | fdf9b3e8 | bellard | PPI3, |
77 | fdf9b3e8 | bellard | PPI3NC, |
78 | fdf9b3e8 | bellard | PDC, |
79 | fdf9b3e8 | bellard | PPIC, |
80 | fdf9b3e8 | bellard | REPEAT, |
81 | fdf9b3e8 | bellard | IMM0_3c, /* xxxx 0iii */
|
82 | fdf9b3e8 | bellard | IMM0_3s, /* xxxx 1iii */
|
83 | fdf9b3e8 | bellard | IMM0_3Uc, /* 0iii xxxx */
|
84 | fdf9b3e8 | bellard | IMM0_3Us, /* 1iii xxxx */
|
85 | fdf9b3e8 | bellard | IMM0_20_4, |
86 | fdf9b3e8 | bellard | IMM0_20, /* follows IMM0_20_4 */
|
87 | fdf9b3e8 | bellard | IMM0_20BY8, /* follows IMM0_20_4 */
|
88 | fdf9b3e8 | bellard | DISP0_12, |
89 | fdf9b3e8 | bellard | DISP0_12BY2, |
90 | fdf9b3e8 | bellard | DISP0_12BY4, |
91 | fdf9b3e8 | bellard | DISP0_12BY8, |
92 | fdf9b3e8 | bellard | DISP1_12, |
93 | fdf9b3e8 | bellard | DISP1_12BY2, |
94 | fdf9b3e8 | bellard | DISP1_12BY4, |
95 | fdf9b3e8 | bellard | DISP1_12BY8 |
96 | fdf9b3e8 | bellard | } |
97 | fdf9b3e8 | bellard | sh_nibble_type; |
98 | fdf9b3e8 | bellard | |
99 | fdf9b3e8 | bellard | typedef enum |
100 | fdf9b3e8 | bellard | { |
101 | fdf9b3e8 | bellard | A_END, |
102 | fdf9b3e8 | bellard | A_BDISP12, |
103 | fdf9b3e8 | bellard | A_BDISP8, |
104 | fdf9b3e8 | bellard | A_DEC_M, |
105 | fdf9b3e8 | bellard | A_DEC_N, |
106 | fdf9b3e8 | bellard | A_DISP_GBR, |
107 | fdf9b3e8 | bellard | A_PC, |
108 | fdf9b3e8 | bellard | A_DISP_PC, |
109 | fdf9b3e8 | bellard | A_DISP_PC_ABS, |
110 | fdf9b3e8 | bellard | A_DISP_REG_M, |
111 | fdf9b3e8 | bellard | A_DISP_REG_N, |
112 | fdf9b3e8 | bellard | A_GBR, |
113 | fdf9b3e8 | bellard | A_IMM, |
114 | fdf9b3e8 | bellard | A_INC_M, |
115 | fdf9b3e8 | bellard | A_INC_N, |
116 | fdf9b3e8 | bellard | A_IND_M, |
117 | fdf9b3e8 | bellard | A_IND_N, |
118 | fdf9b3e8 | bellard | A_IND_R0_REG_M, |
119 | fdf9b3e8 | bellard | A_IND_R0_REG_N, |
120 | fdf9b3e8 | bellard | A_MACH, |
121 | fdf9b3e8 | bellard | A_MACL, |
122 | fdf9b3e8 | bellard | A_PR, |
123 | fdf9b3e8 | bellard | A_R0, |
124 | fdf9b3e8 | bellard | A_R0_GBR, |
125 | fdf9b3e8 | bellard | A_REG_M, |
126 | fdf9b3e8 | bellard | A_REG_N, |
127 | fdf9b3e8 | bellard | A_REG_B, |
128 | fdf9b3e8 | bellard | A_SR, |
129 | fdf9b3e8 | bellard | A_VBR, |
130 | fdf9b3e8 | bellard | A_TBR, |
131 | fdf9b3e8 | bellard | A_DISP_TBR, |
132 | fdf9b3e8 | bellard | A_DISP2_TBR, |
133 | fdf9b3e8 | bellard | A_DEC_R15, |
134 | fdf9b3e8 | bellard | A_INC_R15, |
135 | fdf9b3e8 | bellard | A_MOD, |
136 | fdf9b3e8 | bellard | A_RE, |
137 | fdf9b3e8 | bellard | A_RS, |
138 | fdf9b3e8 | bellard | A_DSR, |
139 | fdf9b3e8 | bellard | DSP_REG_M, |
140 | fdf9b3e8 | bellard | DSP_REG_N, |
141 | fdf9b3e8 | bellard | DSP_REG_X, |
142 | fdf9b3e8 | bellard | DSP_REG_Y, |
143 | fdf9b3e8 | bellard | DSP_REG_E, |
144 | fdf9b3e8 | bellard | DSP_REG_F, |
145 | fdf9b3e8 | bellard | DSP_REG_G, |
146 | fdf9b3e8 | bellard | DSP_REG_A_M, |
147 | fdf9b3e8 | bellard | DSP_REG_AX, |
148 | fdf9b3e8 | bellard | DSP_REG_XY, |
149 | fdf9b3e8 | bellard | DSP_REG_AY, |
150 | fdf9b3e8 | bellard | DSP_REG_YX, |
151 | fdf9b3e8 | bellard | AX_INC_N, |
152 | fdf9b3e8 | bellard | AY_INC_N, |
153 | fdf9b3e8 | bellard | AXY_INC_N, |
154 | fdf9b3e8 | bellard | AYX_INC_N, |
155 | fdf9b3e8 | bellard | AX_IND_N, |
156 | fdf9b3e8 | bellard | AY_IND_N, |
157 | fdf9b3e8 | bellard | AXY_IND_N, |
158 | fdf9b3e8 | bellard | AYX_IND_N, |
159 | fdf9b3e8 | bellard | AX_PMOD_N, |
160 | fdf9b3e8 | bellard | AXY_PMOD_N, |
161 | fdf9b3e8 | bellard | AY_PMOD_N, |
162 | fdf9b3e8 | bellard | AYX_PMOD_N, |
163 | fdf9b3e8 | bellard | AS_DEC_N, |
164 | fdf9b3e8 | bellard | AS_INC_N, |
165 | fdf9b3e8 | bellard | AS_IND_N, |
166 | fdf9b3e8 | bellard | AS_PMOD_N, |
167 | fdf9b3e8 | bellard | A_A0, |
168 | fdf9b3e8 | bellard | A_X0, |
169 | fdf9b3e8 | bellard | A_X1, |
170 | fdf9b3e8 | bellard | A_Y0, |
171 | fdf9b3e8 | bellard | A_Y1, |
172 | fdf9b3e8 | bellard | A_SSR, |
173 | fdf9b3e8 | bellard | A_SPC, |
174 | fdf9b3e8 | bellard | A_SGR, |
175 | fdf9b3e8 | bellard | A_DBR, |
176 | fdf9b3e8 | bellard | F_REG_N, |
177 | fdf9b3e8 | bellard | F_REG_M, |
178 | fdf9b3e8 | bellard | D_REG_N, |
179 | fdf9b3e8 | bellard | D_REG_M, |
180 | fdf9b3e8 | bellard | X_REG_N, /* Only used for argument parsing. */
|
181 | fdf9b3e8 | bellard | X_REG_M, /* Only used for argument parsing. */
|
182 | fdf9b3e8 | bellard | DX_REG_N, |
183 | fdf9b3e8 | bellard | DX_REG_M, |
184 | fdf9b3e8 | bellard | V_REG_N, |
185 | fdf9b3e8 | bellard | V_REG_M, |
186 | fdf9b3e8 | bellard | XMTRX_M4, |
187 | fdf9b3e8 | bellard | F_FR0, |
188 | fdf9b3e8 | bellard | FPUL_N, |
189 | fdf9b3e8 | bellard | FPUL_M, |
190 | fdf9b3e8 | bellard | FPSCR_N, |
191 | fdf9b3e8 | bellard | FPSCR_M |
192 | fdf9b3e8 | bellard | } |
193 | fdf9b3e8 | bellard | sh_arg_type; |
194 | fdf9b3e8 | bellard | |
195 | fdf9b3e8 | bellard | typedef enum |
196 | fdf9b3e8 | bellard | { |
197 | fdf9b3e8 | bellard | A_A1_NUM = 5,
|
198 | fdf9b3e8 | bellard | A_A0_NUM = 7,
|
199 | fdf9b3e8 | bellard | A_X0_NUM, A_X1_NUM, A_Y0_NUM, A_Y1_NUM, |
200 | fdf9b3e8 | bellard | A_M0_NUM, A_A1G_NUM, A_M1_NUM, A_A0G_NUM |
201 | fdf9b3e8 | bellard | } |
202 | fdf9b3e8 | bellard | sh_dsp_reg_nums; |
203 | fdf9b3e8 | bellard | |
204 | fdf9b3e8 | bellard | #define arch_sh1_base 0x0001 |
205 | fdf9b3e8 | bellard | #define arch_sh2_base 0x0002 |
206 | fdf9b3e8 | bellard | #define arch_sh3_base 0x0004 |
207 | fdf9b3e8 | bellard | #define arch_sh4_base 0x0008 |
208 | fdf9b3e8 | bellard | #define arch_sh4a_base 0x0010 |
209 | fdf9b3e8 | bellard | #define arch_sh2a_base 0x0020 |
210 | fdf9b3e8 | bellard | |
211 | fdf9b3e8 | bellard | /* This is an annotation on instruction types, but we abuse the arch
|
212 | fdf9b3e8 | bellard | field in instructions to denote it. */
|
213 | fdf9b3e8 | bellard | #define arch_op32 0x00100000 /* This is a 32-bit opcode. */ |
214 | fdf9b3e8 | bellard | |
215 | fdf9b3e8 | bellard | #define arch_sh_no_mmu 0x04000000 |
216 | fdf9b3e8 | bellard | #define arch_sh_has_mmu 0x08000000 |
217 | fdf9b3e8 | bellard | #define arch_sh_no_co 0x10000000 /* neither FPU nor DSP co-processor */ |
218 | fdf9b3e8 | bellard | #define arch_sh_sp_fpu 0x20000000 /* single precision FPU */ |
219 | fdf9b3e8 | bellard | #define arch_sh_dp_fpu 0x40000000 /* double precision FPU */ |
220 | fdf9b3e8 | bellard | #define arch_sh_has_dsp 0x80000000 |
221 | fdf9b3e8 | bellard | |
222 | fdf9b3e8 | bellard | |
223 | fdf9b3e8 | bellard | #define arch_sh_base_mask 0x0000003f |
224 | fdf9b3e8 | bellard | #define arch_opann_mask 0x00100000 |
225 | fdf9b3e8 | bellard | #define arch_sh_mmu_mask 0x0c000000 |
226 | fdf9b3e8 | bellard | #define arch_sh_co_mask 0xf0000000 |
227 | fdf9b3e8 | bellard | |
228 | fdf9b3e8 | bellard | |
229 | fdf9b3e8 | bellard | #define arch_sh1 (arch_sh1_base|arch_sh_no_mmu|arch_sh_no_co)
|
230 | fdf9b3e8 | bellard | #define arch_sh2 (arch_sh2_base|arch_sh_no_mmu|arch_sh_no_co)
|
231 | fdf9b3e8 | bellard | #define arch_sh2a (arch_sh2a_base|arch_sh_no_mmu|arch_sh_dp_fpu)
|
232 | fdf9b3e8 | bellard | #define arch_sh2a_nofpu (arch_sh2a_base|arch_sh_no_mmu|arch_sh_no_co)
|
233 | fdf9b3e8 | bellard | #define arch_sh2e (arch_sh2_base|arch_sh2a_base|arch_sh_no_mmu|arch_sh_sp_fpu)
|
234 | fdf9b3e8 | bellard | #define arch_sh_dsp (arch_sh2_base|arch_sh_no_mmu|arch_sh_has_dsp)
|
235 | fdf9b3e8 | bellard | #define arch_sh3_nommu (arch_sh3_base|arch_sh_no_mmu|arch_sh_no_co)
|
236 | fdf9b3e8 | bellard | #define arch_sh3 (arch_sh3_base|arch_sh_has_mmu|arch_sh_no_co)
|
237 | fdf9b3e8 | bellard | #define arch_sh3e (arch_sh3_base|arch_sh_has_mmu|arch_sh_sp_fpu)
|
238 | fdf9b3e8 | bellard | #define arch_sh3_dsp (arch_sh3_base|arch_sh_has_mmu|arch_sh_has_dsp)
|
239 | fdf9b3e8 | bellard | #define arch_sh4 (arch_sh4_base|arch_sh_has_mmu|arch_sh_dp_fpu)
|
240 | fdf9b3e8 | bellard | #define arch_sh4a (arch_sh4a_base|arch_sh_has_mmu|arch_sh_dp_fpu)
|
241 | fdf9b3e8 | bellard | #define arch_sh4al_dsp (arch_sh4a_base|arch_sh_has_mmu|arch_sh_has_dsp)
|
242 | fdf9b3e8 | bellard | #define arch_sh4_nofpu (arch_sh4_base|arch_sh_has_mmu|arch_sh_no_co)
|
243 | fdf9b3e8 | bellard | #define arch_sh4a_nofpu (arch_sh4a_base|arch_sh_has_mmu|arch_sh_no_co)
|
244 | fdf9b3e8 | bellard | #define arch_sh4_nommu_nofpu (arch_sh4_base|arch_sh_no_mmu|arch_sh_no_co)
|
245 | fdf9b3e8 | bellard | |
246 | fdf9b3e8 | bellard | #define SH_MERGE_ARCH_SET(SET1, SET2) ((SET1) & (SET2))
|
247 | fdf9b3e8 | bellard | #define SH_VALID_BASE_ARCH_SET(SET) (((SET) & arch_sh_base_mask) != 0) |
248 | fdf9b3e8 | bellard | #define SH_VALID_MMU_ARCH_SET(SET) (((SET) & arch_sh_mmu_mask) != 0) |
249 | fdf9b3e8 | bellard | #define SH_VALID_CO_ARCH_SET(SET) (((SET) & arch_sh_co_mask) != 0) |
250 | fdf9b3e8 | bellard | #define SH_VALID_ARCH_SET(SET) \
|
251 | fdf9b3e8 | bellard | (SH_VALID_BASE_ARCH_SET (SET) \ |
252 | fdf9b3e8 | bellard | && SH_VALID_MMU_ARCH_SET (SET) \ |
253 | fdf9b3e8 | bellard | && SH_VALID_CO_ARCH_SET (SET)) |
254 | fdf9b3e8 | bellard | #define SH_MERGE_ARCH_SET_VALID(SET1, SET2) \
|
255 | fdf9b3e8 | bellard | SH_VALID_ARCH_SET (SH_MERGE_ARCH_SET (SET1, SET2)) |
256 | fdf9b3e8 | bellard | |
257 | fdf9b3e8 | bellard | #define SH_ARCH_SET_HAS_FPU(SET) \
|
258 | fdf9b3e8 | bellard | (((SET) & (arch_sh_sp_fpu | arch_sh_dp_fpu)) != 0)
|
259 | fdf9b3e8 | bellard | #define SH_ARCH_SET_HAS_DSP(SET) \
|
260 | fdf9b3e8 | bellard | (((SET) & arch_sh_has_dsp) != 0)
|
261 | fdf9b3e8 | bellard | |
262 | fdf9b3e8 | bellard | /* This is returned from the functions below when an error occurs
|
263 | fdf9b3e8 | bellard | (in addition to a call to BFD_FAIL). The value should allow
|
264 | fdf9b3e8 | bellard | the tools to continue to function in most cases - there may
|
265 | fdf9b3e8 | bellard | be some confusion between DSP and FPU etc. */
|
266 | fdf9b3e8 | bellard | #define SH_ARCH_UNKNOWN_ARCH 0xffffffff |
267 | fdf9b3e8 | bellard | |
268 | fdf9b3e8 | bellard | /* These are defined in bfd/cpu-sh.c . */
|
269 | fdf9b3e8 | bellard | unsigned int sh_get_arch_from_bfd_mach (unsigned long mach); |
270 | fdf9b3e8 | bellard | unsigned int sh_get_arch_up_from_bfd_mach (unsigned long mach); |
271 | fdf9b3e8 | bellard | unsigned long sh_get_bfd_mach_from_arch_set (unsigned int arch_set); |
272 | fdf9b3e8 | bellard | /* bfd_boolean sh_merge_bfd_arch (bfd *ibfd, bfd *obfd); */
|
273 | fdf9b3e8 | bellard | |
274 | fdf9b3e8 | bellard | /* Below are the 'architecture sets'.
|
275 | fdf9b3e8 | bellard | They describe the following inheritance graph:
|
276 | fdf9b3e8 | bellard | |
277 | fdf9b3e8 | bellard | SH1
|
278 | fdf9b3e8 | bellard | |
|
279 | fdf9b3e8 | bellard | SH2
|
280 | fdf9b3e8 | bellard | .------------'|`--------------------.
|
281 | fdf9b3e8 | bellard | / | \
|
282 | fdf9b3e8 | bellard | SH-DSP SH3-nommu SH2E
|
283 | fdf9b3e8 | bellard | | |`--------. |
|
284 | fdf9b3e8 | bellard | | | \ |
|
285 | fdf9b3e8 | bellard | | SH3 SH4-nommu-nofpu |
|
286 | fdf9b3e8 | bellard | | | | |
|
287 | fdf9b3e8 | bellard | | .------------'|`----------+---------. |
|
288 | fdf9b3e8 | bellard | |/ / \|
|
289 | fdf9b3e8 | bellard | | | .-------' |
|
290 | fdf9b3e8 | bellard | | |/ |
|
291 | fdf9b3e8 | bellard | SH3-dsp SH4-nofpu SH3E
|
292 | fdf9b3e8 | bellard | | |`--------------------. |
|
293 | fdf9b3e8 | bellard | | | \|
|
294 | fdf9b3e8 | bellard | | SH4A-nofpu SH4
|
295 | fdf9b3e8 | bellard | | .------------' `--------------------. |
|
296 | fdf9b3e8 | bellard | |/ \|
|
297 | fdf9b3e8 | bellard | SH4AL-dsp SH4A
|
298 | fdf9b3e8 | bellard | |
299 | fdf9b3e8 | bellard | */
|
300 | fdf9b3e8 | bellard | |
301 | fdf9b3e8 | bellard | /* Central branches */
|
302 | fdf9b3e8 | bellard | #define arch_sh1_up (arch_sh1 | arch_sh2_up)
|
303 | fdf9b3e8 | bellard | #define arch_sh2_up (arch_sh2 | arch_sh2e_up | arch_sh2a_nofpu_up | arch_sh3_nommu_up | arch_sh_dsp_up)
|
304 | fdf9b3e8 | bellard | #define arch_sh3_nommu_up (arch_sh3_nommu | arch_sh3_up | arch_sh4_nommu_nofpu_up)
|
305 | fdf9b3e8 | bellard | #define arch_sh3_up (arch_sh3 | arch_sh3e_up | arch_sh3_dsp_up | arch_sh4_nofp_up)
|
306 | fdf9b3e8 | bellard | #define arch_sh4_nommu_nofpu_up (arch_sh4_nommu_nofpu | arch_sh4_nofp_up)
|
307 | fdf9b3e8 | bellard | #define arch_sh4_nofp_up (arch_sh4_nofpu | arch_sh4_up | arch_sh4a_nofp_up)
|
308 | fdf9b3e8 | bellard | #define arch_sh4a_nofp_up (arch_sh4a_nofpu | arch_sh4a_up | arch_sh4al_dsp_up)
|
309 | fdf9b3e8 | bellard | |
310 | fdf9b3e8 | bellard | /* Right branch */
|
311 | fdf9b3e8 | bellard | #define arch_sh2e_up (arch_sh2e | arch_sh2a_up | arch_sh3e_up)
|
312 | fdf9b3e8 | bellard | #define arch_sh3e_up (arch_sh3e | arch_sh4_up)
|
313 | fdf9b3e8 | bellard | #define arch_sh4_up (arch_sh4 | arch_sh4a_up)
|
314 | fdf9b3e8 | bellard | #define arch_sh4a_up (arch_sh4a)
|
315 | fdf9b3e8 | bellard | |
316 | fdf9b3e8 | bellard | /* Left branch */
|
317 | fdf9b3e8 | bellard | #define arch_sh_dsp_up (arch_sh_dsp | arch_sh3_dsp_up)
|
318 | fdf9b3e8 | bellard | #define arch_sh3_dsp_up (arch_sh3_dsp | arch_sh4al_dsp_up)
|
319 | fdf9b3e8 | bellard | #define arch_sh4al_dsp_up (arch_sh4al_dsp)
|
320 | fdf9b3e8 | bellard | |
321 | fdf9b3e8 | bellard | /* SH 2a branched off SH2e, adding a lot but not all of SH4 and SH4a. */
|
322 | fdf9b3e8 | bellard | #define arch_sh2a_up (arch_sh2a)
|
323 | fdf9b3e8 | bellard | #define arch_sh2a_nofpu_up (arch_sh2a_nofpu | arch_sh2a_up)
|
324 | fdf9b3e8 | bellard | |
325 | fdf9b3e8 | bellard | |
326 | fdf9b3e8 | bellard | typedef struct |
327 | fdf9b3e8 | bellard | { |
328 | fdf9b3e8 | bellard | char *name;
|
329 | fdf9b3e8 | bellard | sh_arg_type arg[4];
|
330 | fdf9b3e8 | bellard | sh_nibble_type nibbles[9];
|
331 | fdf9b3e8 | bellard | unsigned int arch; |
332 | fdf9b3e8 | bellard | } sh_opcode_info; |
333 | fdf9b3e8 | bellard | |
334 | fdf9b3e8 | bellard | #ifdef DEFINE_TABLE
|
335 | fdf9b3e8 | bellard | |
336 | fdf9b3e8 | bellard | const sh_opcode_info sh_table[] =
|
337 | fdf9b3e8 | bellard | { |
338 | fdf9b3e8 | bellard | /* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh1_up}, |
339 | fdf9b3e8 | bellard | |
340 | fdf9b3e8 | bellard | /* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh1_up}, |
341 | fdf9b3e8 | bellard | |
342 | fdf9b3e8 | bellard | /* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh1_up}, |
343 | fdf9b3e8 | bellard | |
344 | fdf9b3e8 | bellard | /* 0011nnnnmmmm1111 addv <REG_M>,<REG_N>*/{"addv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_F}, arch_sh1_up}, |
345 | fdf9b3e8 | bellard | |
346 | fdf9b3e8 | bellard | /* 11001001i8*1.... and #<imm>,R0 */{"and",{A_IMM,A_R0},{HEX_C,HEX_9,IMM0_8}, arch_sh1_up}, |
347 | fdf9b3e8 | bellard | |
348 | fdf9b3e8 | bellard | /* 0010nnnnmmmm1001 and <REG_M>,<REG_N> */{"and",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_9}, arch_sh1_up}, |
349 | fdf9b3e8 | bellard | |
350 | fdf9b3e8 | bellard | /* 11001101i8*1.... and.b #<imm>,@(R0,GBR)*/{"and.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_D,IMM0_8}, arch_sh1_up}, |
351 | fdf9b3e8 | bellard | |
352 | fdf9b3e8 | bellard | /* 1010i12......... bra <bdisp12> */{"bra",{A_BDISP12},{HEX_A,BRANCH_12}, arch_sh1_up}, |
353 | fdf9b3e8 | bellard | |
354 | fdf9b3e8 | bellard | /* 1011i12......... bsr <bdisp12> */{"bsr",{A_BDISP12},{HEX_B,BRANCH_12}, arch_sh1_up}, |
355 | fdf9b3e8 | bellard | |
356 | fdf9b3e8 | bellard | /* 10001001i8p1.... bt <bdisp8> */{"bt",{A_BDISP8},{HEX_8,HEX_9,BRANCH_8}, arch_sh1_up}, |
357 | fdf9b3e8 | bellard | |
358 | fdf9b3e8 | bellard | /* 10001011i8p1.... bf <bdisp8> */{"bf",{A_BDISP8},{HEX_8,HEX_B,BRANCH_8}, arch_sh1_up}, |
359 | fdf9b3e8 | bellard | |
360 | fdf9b3e8 | bellard | /* 10001101i8p1.... bt.s <bdisp8> */{"bt.s",{A_BDISP8},{HEX_8,HEX_D,BRANCH_8}, arch_sh2_up}, |
361 | fdf9b3e8 | bellard | |
362 | fdf9b3e8 | bellard | /* 10001101i8p1.... bt/s <bdisp8> */{"bt/s",{A_BDISP8},{HEX_8,HEX_D,BRANCH_8}, arch_sh2_up}, |
363 | fdf9b3e8 | bellard | |
364 | fdf9b3e8 | bellard | /* 10001111i8p1.... bf.s <bdisp8> */{"bf.s",{A_BDISP8},{HEX_8,HEX_F,BRANCH_8}, arch_sh2_up}, |
365 | fdf9b3e8 | bellard | |
366 | fdf9b3e8 | bellard | /* 10001111i8p1.... bf/s <bdisp8> */{"bf/s",{A_BDISP8},{HEX_8,HEX_F,BRANCH_8}, arch_sh2_up}, |
367 | fdf9b3e8 | bellard | |
368 | fdf9b3e8 | bellard | /* 0000000010001000 clrdmxy */{"clrdmxy",{0},{HEX_0,HEX_0,HEX_8,HEX_8}, arch_sh4al_dsp_up}, |
369 | fdf9b3e8 | bellard | |
370 | fdf9b3e8 | bellard | /* 0000000000101000 clrmac */{"clrmac",{0},{HEX_0,HEX_0,HEX_2,HEX_8}, arch_sh1_up}, |
371 | fdf9b3e8 | bellard | |
372 | fdf9b3e8 | bellard | /* 0000000001001000 clrs */{"clrs",{0},{HEX_0,HEX_0,HEX_4,HEX_8}, arch_sh1_up}, |
373 | fdf9b3e8 | bellard | |
374 | fdf9b3e8 | bellard | /* 0000000000001000 clrt */{"clrt",{0},{HEX_0,HEX_0,HEX_0,HEX_8}, arch_sh1_up}, |
375 | fdf9b3e8 | bellard | |
376 | fdf9b3e8 | bellard | /* 10001000i8*1.... cmp/eq #<imm>,R0 */{"cmp/eq",{A_IMM,A_R0},{HEX_8,HEX_8,IMM0_8}, arch_sh1_up}, |
377 | fdf9b3e8 | bellard | |
378 | fdf9b3e8 | bellard | /* 0011nnnnmmmm0000 cmp/eq <REG_M>,<REG_N>*/{"cmp/eq",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_0}, arch_sh1_up}, |
379 | fdf9b3e8 | bellard | |
380 | fdf9b3e8 | bellard | /* 0011nnnnmmmm0011 cmp/ge <REG_M>,<REG_N>*/{"cmp/ge",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_3}, arch_sh1_up}, |
381 | fdf9b3e8 | bellard | |
382 | fdf9b3e8 | bellard | /* 0011nnnnmmmm0111 cmp/gt <REG_M>,<REG_N>*/{"cmp/gt",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_7}, arch_sh1_up}, |
383 | fdf9b3e8 | bellard | |
384 | fdf9b3e8 | bellard | /* 0011nnnnmmmm0110 cmp/hi <REG_M>,<REG_N>*/{"cmp/hi",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_6}, arch_sh1_up}, |
385 | fdf9b3e8 | bellard | |
386 | fdf9b3e8 | bellard | /* 0011nnnnmmmm0010 cmp/hs <REG_M>,<REG_N>*/{"cmp/hs",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_2}, arch_sh1_up}, |
387 | fdf9b3e8 | bellard | |
388 | fdf9b3e8 | bellard | /* 0100nnnn00010101 cmp/pl <REG_N> */{"cmp/pl",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_5}, arch_sh1_up}, |
389 | fdf9b3e8 | bellard | |
390 | fdf9b3e8 | bellard | /* 0100nnnn00010001 cmp/pz <REG_N> */{"cmp/pz",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_1}, arch_sh1_up}, |
391 | fdf9b3e8 | bellard | |
392 | fdf9b3e8 | bellard | /* 0010nnnnmmmm1100 cmp/str <REG_M>,<REG_N>*/{"cmp/str",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_C}, arch_sh1_up}, |
393 | fdf9b3e8 | bellard | |
394 | fdf9b3e8 | bellard | /* 0010nnnnmmmm0111 div0s <REG_M>,<REG_N>*/{"div0s",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_7}, arch_sh1_up}, |
395 | fdf9b3e8 | bellard | |
396 | fdf9b3e8 | bellard | /* 0000000000011001 div0u */{"div0u",{0},{HEX_0,HEX_0,HEX_1,HEX_9}, arch_sh1_up}, |
397 | fdf9b3e8 | bellard | |
398 | fdf9b3e8 | bellard | /* 0011nnnnmmmm0100 div1 <REG_M>,<REG_N>*/{"div1",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_4}, arch_sh1_up}, |
399 | fdf9b3e8 | bellard | |
400 | fdf9b3e8 | bellard | /* 0110nnnnmmmm1110 exts.b <REG_M>,<REG_N>*/{"exts.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_E}, arch_sh1_up}, |
401 | fdf9b3e8 | bellard | |
402 | fdf9b3e8 | bellard | /* 0110nnnnmmmm1111 exts.w <REG_M>,<REG_N>*/{"exts.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_F}, arch_sh1_up}, |
403 | fdf9b3e8 | bellard | |
404 | fdf9b3e8 | bellard | /* 0110nnnnmmmm1100 extu.b <REG_M>,<REG_N>*/{"extu.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_C}, arch_sh1_up}, |
405 | fdf9b3e8 | bellard | |
406 | fdf9b3e8 | bellard | /* 0110nnnnmmmm1101 extu.w <REG_M>,<REG_N>*/{"extu.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_D}, arch_sh1_up}, |
407 | fdf9b3e8 | bellard | |
408 | fdf9b3e8 | bellard | /* 0000nnnn11100011 icbi @<REG_N> */{"icbi",{A_IND_N},{HEX_0,REG_N,HEX_E,HEX_3}, arch_sh4a_nofp_up}, |
409 | fdf9b3e8 | bellard | |
410 | fdf9b3e8 | bellard | /* 0100nnnn00101011 jmp @<REG_N> */{"jmp",{A_IND_N},{HEX_4,REG_N,HEX_2,HEX_B}, arch_sh1_up}, |
411 | fdf9b3e8 | bellard | |
412 | fdf9b3e8 | bellard | /* 0100nnnn00001011 jsr @<REG_N> */{"jsr",{A_IND_N},{HEX_4,REG_N,HEX_0,HEX_B}, arch_sh1_up}, |
413 | fdf9b3e8 | bellard | |
414 | fdf9b3e8 | bellard | /* 0100nnnn00001110 ldc <REG_N>,SR */{"ldc",{A_REG_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_E}, arch_sh1_up}, |
415 | fdf9b3e8 | bellard | |
416 | fdf9b3e8 | bellard | /* 0100nnnn00011110 ldc <REG_N>,GBR */{"ldc",{A_REG_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_E}, arch_sh1_up}, |
417 | fdf9b3e8 | bellard | |
418 | fdf9b3e8 | bellard | /* 0100nnnn00111010 ldc <REG_N>,SGR */{"ldc",{A_REG_N,A_SGR},{HEX_4,REG_N,HEX_3,HEX_A}, arch_sh4_nommu_nofpu_up}, |
419 | fdf9b3e8 | bellard | |
420 | fdf9b3e8 | bellard | /* 0100mmmm01001010 ldc <REG_M>,TBR */{"ldc",{A_REG_M,A_TBR},{HEX_4,REG_M,HEX_4,HEX_A}, arch_sh2a_nofpu_up}, |
421 | fdf9b3e8 | bellard | |
422 | fdf9b3e8 | bellard | /* 0100nnnn00101110 ldc <REG_N>,VBR */{"ldc",{A_REG_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_E}, arch_sh1_up}, |
423 | fdf9b3e8 | bellard | |
424 | fdf9b3e8 | bellard | /* 0100nnnn01011110 ldc <REG_N>,MOD */{"ldc",{A_REG_N,A_MOD},{HEX_4,REG_N,HEX_5,HEX_E}, arch_sh_dsp_up}, |
425 | fdf9b3e8 | bellard | |
426 | fdf9b3e8 | bellard | /* 0100nnnn01111110 ldc <REG_N>,RE */{"ldc",{A_REG_N,A_RE},{HEX_4,REG_N,HEX_7,HEX_E}, arch_sh_dsp_up}, |
427 | fdf9b3e8 | bellard | |
428 | fdf9b3e8 | bellard | /* 0100nnnn01101110 ldc <REG_N>,RS */{"ldc",{A_REG_N,A_RS},{HEX_4,REG_N,HEX_6,HEX_E}, arch_sh_dsp_up}, |
429 | fdf9b3e8 | bellard | |
430 | fdf9b3e8 | bellard | /* 0100nnnn00111110 ldc <REG_N>,SSR */{"ldc",{A_REG_N,A_SSR},{HEX_4,REG_N,HEX_3,HEX_E}, arch_sh3_nommu_up}, |
431 | fdf9b3e8 | bellard | |
432 | fdf9b3e8 | bellard | /* 0100nnnn01001110 ldc <REG_N>,SPC */{"ldc",{A_REG_N,A_SPC},{HEX_4,REG_N,HEX_4,HEX_E}, arch_sh3_nommu_up}, |
433 | fdf9b3e8 | bellard | |
434 | fdf9b3e8 | bellard | /* 0100nnnn11111010 ldc <REG_N>,DBR */{"ldc",{A_REG_N,A_DBR},{HEX_4,REG_N,HEX_F,HEX_A}, arch_sh4_nommu_nofpu_up}, |
435 | fdf9b3e8 | bellard | |
436 | fdf9b3e8 | bellard | /* 0100nnnn1xxx1110 ldc <REG_N>,Rn_BANK */{"ldc",{A_REG_N,A_REG_B},{HEX_4,REG_N,REG_B,HEX_E}, arch_sh3_nommu_up}, |
437 | fdf9b3e8 | bellard | |
438 | fdf9b3e8 | bellard | /* 0100nnnn00000111 ldc.l @<REG_N>+,SR */{"ldc.l",{A_INC_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_7}, arch_sh1_up}, |
439 | fdf9b3e8 | bellard | |
440 | fdf9b3e8 | bellard | /* 0100nnnn00010111 ldc.l @<REG_N>+,GBR */{"ldc.l",{A_INC_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_7}, arch_sh1_up}, |
441 | fdf9b3e8 | bellard | |
442 | fdf9b3e8 | bellard | /* 0100nnnn00100111 ldc.l @<REG_N>+,VBR */{"ldc.l",{A_INC_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_7}, arch_sh1_up}, |
443 | fdf9b3e8 | bellard | |
444 | fdf9b3e8 | bellard | /* 0100nnnn00110110 ldc.l @<REG_N>+,SGR */{"ldc.l",{A_INC_N,A_SGR},{HEX_4,REG_N,HEX_3,HEX_6}, arch_sh4_nommu_nofpu_up}, |
445 | fdf9b3e8 | bellard | |
446 | fdf9b3e8 | bellard | /* 0100nnnn01010111 ldc.l @<REG_N>+,MOD */{"ldc.l",{A_INC_N,A_MOD},{HEX_4,REG_N,HEX_5,HEX_7}, arch_sh_dsp_up}, |
447 | fdf9b3e8 | bellard | |
448 | fdf9b3e8 | bellard | /* 0100nnnn01110111 ldc.l @<REG_N>+,RE */{"ldc.l",{A_INC_N,A_RE},{HEX_4,REG_N,HEX_7,HEX_7}, arch_sh_dsp_up}, |
449 | fdf9b3e8 | bellard | |
450 | fdf9b3e8 | bellard | /* 0100nnnn01100111 ldc.l @<REG_N>+,RS */{"ldc.l",{A_INC_N,A_RS},{HEX_4,REG_N,HEX_6,HEX_7}, arch_sh_dsp_up}, |
451 | fdf9b3e8 | bellard | |
452 | fdf9b3e8 | bellard | /* 0100nnnn00110111 ldc.l @<REG_N>+,SSR */{"ldc.l",{A_INC_N,A_SSR},{HEX_4,REG_N,HEX_3,HEX_7}, arch_sh3_nommu_up}, |
453 | fdf9b3e8 | bellard | |
454 | fdf9b3e8 | bellard | /* 0100nnnn01000111 ldc.l @<REG_N>+,SPC */{"ldc.l",{A_INC_N,A_SPC},{HEX_4,REG_N,HEX_4,HEX_7}, arch_sh3_nommu_up}, |
455 | fdf9b3e8 | bellard | |
456 | fdf9b3e8 | bellard | /* 0100nnnn11110110 ldc.l @<REG_N>+,DBR */{"ldc.l",{A_INC_N,A_DBR},{HEX_4,REG_N,HEX_F,HEX_6}, arch_sh4_nommu_nofpu_up}, |
457 | fdf9b3e8 | bellard | |
458 | fdf9b3e8 | bellard | /* 0100nnnn1xxx0111 ldc.l <REG_N>,Rn_BANK */{"ldc.l",{A_INC_N,A_REG_B},{HEX_4,REG_N,REG_B,HEX_7}, arch_sh3_nommu_up}, |
459 | fdf9b3e8 | bellard | |
460 | fdf9b3e8 | bellard | /* 0100mmmm00110100 ldrc <REG_M> */{"ldrc",{A_REG_M},{HEX_4,REG_M,HEX_3,HEX_4}, arch_sh4al_dsp_up}, |
461 | fdf9b3e8 | bellard | /* 10001010i8*1.... ldrc #<imm> */{"ldrc",{A_IMM},{HEX_8,HEX_A,IMM0_8}, arch_sh4al_dsp_up}, |
462 | fdf9b3e8 | bellard | |
463 | fdf9b3e8 | bellard | /* 10001110i8p2.... ldre @(<disp>,PC) */{"ldre",{A_DISP_PC},{HEX_8,HEX_E,PCRELIMM_8BY2}, arch_sh_dsp_up}, |
464 | fdf9b3e8 | bellard | |
465 | fdf9b3e8 | bellard | /* 10001100i8p2.... ldrs @(<disp>,PC) */{"ldrs",{A_DISP_PC},{HEX_8,HEX_C,PCRELIMM_8BY2}, arch_sh_dsp_up}, |
466 | fdf9b3e8 | bellard | |
467 | fdf9b3e8 | bellard | /* 0100nnnn00001010 lds <REG_N>,MACH */{"lds",{A_REG_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_A}, arch_sh1_up}, |
468 | fdf9b3e8 | bellard | |
469 | fdf9b3e8 | bellard | /* 0100nnnn00011010 lds <REG_N>,MACL */{"lds",{A_REG_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_A}, arch_sh1_up}, |
470 | fdf9b3e8 | bellard | |
471 | fdf9b3e8 | bellard | /* 0100nnnn00101010 lds <REG_N>,PR */{"lds",{A_REG_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_A}, arch_sh1_up}, |
472 | fdf9b3e8 | bellard | |
473 | fdf9b3e8 | bellard | /* 0100nnnn01101010 lds <REG_N>,DSR */{"lds",{A_REG_N,A_DSR},{HEX_4,REG_N,HEX_6,HEX_A}, arch_sh_dsp_up}, |
474 | fdf9b3e8 | bellard | |
475 | fdf9b3e8 | bellard | /* 0100nnnn01111010 lds <REG_N>,A0 */{"lds",{A_REG_N,A_A0},{HEX_4,REG_N,HEX_7,HEX_A}, arch_sh_dsp_up}, |
476 | fdf9b3e8 | bellard | |
477 | fdf9b3e8 | bellard | /* 0100nnnn10001010 lds <REG_N>,X0 */{"lds",{A_REG_N,A_X0},{HEX_4,REG_N,HEX_8,HEX_A}, arch_sh_dsp_up}, |
478 | fdf9b3e8 | bellard | |
479 | fdf9b3e8 | bellard | /* 0100nnnn10011010 lds <REG_N>,X1 */{"lds",{A_REG_N,A_X1},{HEX_4,REG_N,HEX_9,HEX_A}, arch_sh_dsp_up}, |
480 | fdf9b3e8 | bellard | |
481 | fdf9b3e8 | bellard | /* 0100nnnn10101010 lds <REG_N>,Y0 */{"lds",{A_REG_N,A_Y0},{HEX_4,REG_N,HEX_A,HEX_A}, arch_sh_dsp_up}, |
482 | fdf9b3e8 | bellard | |
483 | fdf9b3e8 | bellard | /* 0100nnnn10111010 lds <REG_N>,Y1 */{"lds",{A_REG_N,A_Y1},{HEX_4,REG_N,HEX_B,HEX_A}, arch_sh_dsp_up}, |
484 | fdf9b3e8 | bellard | |
485 | fdf9b3e8 | bellard | /* 0100nnnn01011010 lds <REG_N>,FPUL */{"lds",{A_REG_M,FPUL_N},{HEX_4,REG_M,HEX_5,HEX_A}, arch_sh2e_up}, |
486 | fdf9b3e8 | bellard | |
487 | fdf9b3e8 | bellard | /* 0100nnnn01101010 lds <REG_M>,FPSCR */{"lds",{A_REG_M,FPSCR_N},{HEX_4,REG_M,HEX_6,HEX_A}, arch_sh2e_up}, |
488 | fdf9b3e8 | bellard | |
489 | fdf9b3e8 | bellard | /* 0100nnnn00000110 lds.l @<REG_N>+,MACH*/{"lds.l",{A_INC_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_6}, arch_sh1_up}, |
490 | fdf9b3e8 | bellard | |
491 | fdf9b3e8 | bellard | /* 0100nnnn00010110 lds.l @<REG_N>+,MACL*/{"lds.l",{A_INC_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_6}, arch_sh1_up}, |
492 | fdf9b3e8 | bellard | |
493 | fdf9b3e8 | bellard | /* 0100nnnn00100110 lds.l @<REG_N>+,PR */{"lds.l",{A_INC_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_6}, arch_sh1_up}, |
494 | fdf9b3e8 | bellard | |
495 | fdf9b3e8 | bellard | /* 0100nnnn01100110 lds.l @<REG_N>+,DSR */{"lds.l",{A_INC_N,A_DSR},{HEX_4,REG_N,HEX_6,HEX_6}, arch_sh_dsp_up}, |
496 | fdf9b3e8 | bellard | |
497 | fdf9b3e8 | bellard | /* 0100nnnn01110110 lds.l @<REG_N>+,A0 */{"lds.l",{A_INC_N,A_A0},{HEX_4,REG_N,HEX_7,HEX_6}, arch_sh_dsp_up}, |
498 | fdf9b3e8 | bellard | |
499 | fdf9b3e8 | bellard | /* 0100nnnn10000110 lds.l @<REG_N>+,X0 */{"lds.l",{A_INC_N,A_X0},{HEX_4,REG_N,HEX_8,HEX_6}, arch_sh_dsp_up}, |
500 | fdf9b3e8 | bellard | |
501 | fdf9b3e8 | bellard | /* 0100nnnn10010110 lds.l @<REG_N>+,X1 */{"lds.l",{A_INC_N,A_X1},{HEX_4,REG_N,HEX_9,HEX_6}, arch_sh_dsp_up}, |
502 | fdf9b3e8 | bellard | |
503 | fdf9b3e8 | bellard | /* 0100nnnn10100110 lds.l @<REG_N>+,Y0 */{"lds.l",{A_INC_N,A_Y0},{HEX_4,REG_N,HEX_A,HEX_6}, arch_sh_dsp_up}, |
504 | fdf9b3e8 | bellard | |
505 | fdf9b3e8 | bellard | /* 0100nnnn10110110 lds.l @<REG_N>+,Y1 */{"lds.l",{A_INC_N,A_Y1},{HEX_4,REG_N,HEX_B,HEX_6}, arch_sh_dsp_up}, |
506 | fdf9b3e8 | bellard | |
507 | fdf9b3e8 | bellard | /* 0100nnnn01010110 lds.l @<REG_M>+,FPUL*/{"lds.l",{A_INC_M,FPUL_N},{HEX_4,REG_M,HEX_5,HEX_6}, arch_sh2e_up}, |
508 | fdf9b3e8 | bellard | |
509 | fdf9b3e8 | bellard | /* 0100nnnn01100110 lds.l @<REG_M>+,FPSCR*/{"lds.l",{A_INC_M,FPSCR_N},{HEX_4,REG_M,HEX_6,HEX_6}, arch_sh2e_up}, |
510 | fdf9b3e8 | bellard | |
511 | fdf9b3e8 | bellard | /* 0000000000111000 ldtlb */{"ldtlb",{0},{HEX_0,HEX_0,HEX_3,HEX_8}, arch_sh3_up}, |
512 | fdf9b3e8 | bellard | |
513 | fdf9b3e8 | bellard | /* 0100nnnnmmmm1111 mac.w @<REG_M>+,@<REG_N>+*/{"mac.w",{A_INC_M,A_INC_N},{HEX_4,REG_N,REG_M,HEX_F}, arch_sh1_up}, |
514 | fdf9b3e8 | bellard | |
515 | fdf9b3e8 | bellard | /* 1110nnnni8*1.... mov #<imm>,<REG_N> */{"mov",{A_IMM,A_REG_N},{HEX_E,REG_N,IMM0_8}, arch_sh1_up}, |
516 | fdf9b3e8 | bellard | |
517 | fdf9b3e8 | bellard | /* 0110nnnnmmmm0011 mov <REG_M>,<REG_N> */{"mov",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_3}, arch_sh1_up}, |
518 | fdf9b3e8 | bellard | |
519 | fdf9b3e8 | bellard | /* 0000nnnnmmmm0100 mov.b <REG_M>,@(R0,<REG_N>)*/{"mov.b",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_4}, arch_sh1_up}, |
520 | fdf9b3e8 | bellard | |
521 | fdf9b3e8 | bellard | /* 0010nnnnmmmm0100 mov.b <REG_M>,@-<REG_N>*/{"mov.b",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_4}, arch_sh1_up}, |
522 | fdf9b3e8 | bellard | |
523 | fdf9b3e8 | bellard | /* 0010nnnnmmmm0000 mov.b <REG_M>,@<REG_N>*/{"mov.b",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_0}, arch_sh1_up}, |
524 | fdf9b3e8 | bellard | |
525 | fdf9b3e8 | bellard | /* 10000100mmmmi4*1 mov.b @(<disp>,<REG_M>),R0*/{"mov.b",{A_DISP_REG_M,A_R0},{HEX_8,HEX_4,REG_M,IMM0_4}, arch_sh1_up}, |
526 | fdf9b3e8 | bellard | |
527 | fdf9b3e8 | bellard | /* 11000100i8*1.... mov.b @(<disp>,GBR),R0*/{"mov.b",{A_DISP_GBR,A_R0},{HEX_C,HEX_4,IMM0_8}, arch_sh1_up}, |
528 | fdf9b3e8 | bellard | |
529 | fdf9b3e8 | bellard | /* 0000nnnnmmmm1100 mov.b @(R0,<REG_M>),<REG_N>*/{"mov.b",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_C}, arch_sh1_up}, |
530 | fdf9b3e8 | bellard | |
531 | fdf9b3e8 | bellard | /* 0110nnnnmmmm0100 mov.b @<REG_M>+,<REG_N>*/{"mov.b",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_4}, arch_sh1_up}, |
532 | fdf9b3e8 | bellard | |
533 | fdf9b3e8 | bellard | /* 0110nnnnmmmm0000 mov.b @<REG_M>,<REG_N>*/{"mov.b",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_0}, arch_sh1_up}, |
534 | fdf9b3e8 | bellard | |
535 | fdf9b3e8 | bellard | /* 10000000mmmmi4*1 mov.b R0,@(<disp>,<REG_M>)*/{"mov.b",{A_R0,A_DISP_REG_M},{HEX_8,HEX_0,REG_M,IMM1_4}, arch_sh1_up}, |
536 | fdf9b3e8 | bellard | |
537 | fdf9b3e8 | bellard | /* 11000000i8*1.... mov.b R0,@(<disp>,GBR)*/{"mov.b",{A_R0,A_DISP_GBR},{HEX_C,HEX_0,IMM1_8}, arch_sh1_up}, |
538 | fdf9b3e8 | bellard | |
539 | fdf9b3e8 | bellard | /* 0100nnnn10001011 mov.b R0,@<REG_N>+ */{"mov.b",{A_R0,A_INC_N},{HEX_4,REG_N,HEX_8,HEX_B}, arch_sh2a_nofpu_up}, |
540 | fdf9b3e8 | bellard | /* 0100nnnn11001011 mov.b @-<REG_M>,R0 */{"mov.b",{A_DEC_M,A_R0},{HEX_4,REG_M,HEX_C,HEX_B}, arch_sh2a_nofpu_up}, |
541 | fdf9b3e8 | bellard | /* 0011nnnnmmmm0001 0000dddddddddddd mov.b <REG_M>,@(<DISP12>,<REG_N>) */
|
542 | fdf9b3e8 | bellard | {"mov.b",{A_REG_M,A_DISP_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_0,DISP1_12}, arch_sh2a_nofpu_up | arch_op32},
|
543 | fdf9b3e8 | bellard | /* 0011nnnnmmmm0001 0100dddddddddddd mov.b @(<DISP12>,<REG_M>),<REG_N> */
|
544 | fdf9b3e8 | bellard | {"mov.b",{A_DISP_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_4,DISP0_12}, arch_sh2a_nofpu_up | arch_op32},
|
545 | fdf9b3e8 | bellard | /* 0001nnnnmmmmi4*4 mov.l <REG_M>,@(<disp>,<REG_N>)*/{"mov.l",{ A_REG_M,A_DISP_REG_N},{HEX_1,REG_N,REG_M,IMM1_4BY4}, arch_sh1_up}, |
546 | fdf9b3e8 | bellard | |
547 | fdf9b3e8 | bellard | /* 0000nnnnmmmm0110 mov.l <REG_M>,@(R0,<REG_N>)*/{"mov.l",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_6}, arch_sh1_up}, |
548 | fdf9b3e8 | bellard | |
549 | fdf9b3e8 | bellard | /* 0010nnnnmmmm0110 mov.l <REG_M>,@-<REG_N>*/{"mov.l",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_6}, arch_sh1_up}, |
550 | fdf9b3e8 | bellard | |
551 | fdf9b3e8 | bellard | /* 0010nnnnmmmm0010 mov.l <REG_M>,@<REG_N>*/{"mov.l",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_2}, arch_sh1_up}, |
552 | fdf9b3e8 | bellard | |
553 | fdf9b3e8 | bellard | /* 0101nnnnmmmmi4*4 mov.l @(<disp>,<REG_M>),<REG_N>*/{"mov.l",{A_DISP_REG_M,A_REG_N},{HEX_5,REG_N,REG_M,IMM0_4BY4}, arch_sh1_up}, |
554 | fdf9b3e8 | bellard | |
555 | fdf9b3e8 | bellard | /* 11000110i8*4.... mov.l @(<disp>,GBR),R0*/{"mov.l",{A_DISP_GBR,A_R0},{HEX_C,HEX_6,IMM0_8BY4}, arch_sh1_up}, |
556 | fdf9b3e8 | bellard | |
557 | fdf9b3e8 | bellard | /* 1101nnnni8p4.... mov.l @(<disp>,PC),<REG_N>*/{"mov.l",{A_DISP_PC,A_REG_N},{HEX_D,REG_N,PCRELIMM_8BY4}, arch_sh1_up}, |
558 | fdf9b3e8 | bellard | |
559 | fdf9b3e8 | bellard | /* 0000nnnnmmmm1110 mov.l @(R0,<REG_M>),<REG_N>*/{"mov.l",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_E}, arch_sh1_up}, |
560 | fdf9b3e8 | bellard | |
561 | fdf9b3e8 | bellard | /* 0110nnnnmmmm0110 mov.l @<REG_M>+,<REG_N>*/{"mov.l",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_6}, arch_sh1_up}, |
562 | fdf9b3e8 | bellard | |
563 | fdf9b3e8 | bellard | /* 0110nnnnmmmm0010 mov.l @<REG_M>,<REG_N>*/{"mov.l",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_2}, arch_sh1_up}, |
564 | fdf9b3e8 | bellard | |
565 | fdf9b3e8 | bellard | /* 11000010i8*4.... mov.l R0,@(<disp>,GBR)*/{"mov.l",{A_R0,A_DISP_GBR},{HEX_C,HEX_2,IMM1_8BY4}, arch_sh1_up}, |
566 | fdf9b3e8 | bellard | |
567 | fdf9b3e8 | bellard | /* 0100nnnn10101011 mov.l R0,@<REG_N>+ */{"mov.l",{A_R0,A_INC_N},{HEX_4,REG_N,HEX_A,HEX_B}, arch_sh2a_nofpu_up}, |
568 | fdf9b3e8 | bellard | /* 0100nnnn11001011 mov.l @-<REG_M>,R0 */{"mov.l",{A_DEC_M,A_R0},{HEX_4,REG_M,HEX_E,HEX_B}, arch_sh2a_nofpu_up}, |
569 | fdf9b3e8 | bellard | /* 0011nnnnmmmm0001 0010dddddddddddd mov.l <REG_M>,@(<DISP12>,<REG_N>) */
|
570 | fdf9b3e8 | bellard | {"mov.l",{A_REG_M,A_DISP_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_2,DISP1_12BY4}, arch_sh2a_nofpu_up | arch_op32},
|
571 | fdf9b3e8 | bellard | /* 0011nnnnmmmm0001 0110dddddddddddd mov.l @(<DISP12>,<REG_M>),<REG_N> */
|
572 | fdf9b3e8 | bellard | {"mov.l",{A_DISP_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_6,DISP0_12BY4}, arch_sh2a_nofpu_up | arch_op32},
|
573 | fdf9b3e8 | bellard | /* 0000nnnnmmmm0101 mov.w <REG_M>,@(R0,<REG_N>)*/{"mov.w",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_5}, arch_sh1_up}, |
574 | fdf9b3e8 | bellard | |
575 | fdf9b3e8 | bellard | /* 0010nnnnmmmm0101 mov.w <REG_M>,@-<REG_N>*/{"mov.w",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_5}, arch_sh1_up}, |
576 | fdf9b3e8 | bellard | |
577 | fdf9b3e8 | bellard | /* 0010nnnnmmmm0001 mov.w <REG_M>,@<REG_N>*/{"mov.w",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_1}, arch_sh1_up}, |
578 | fdf9b3e8 | bellard | |
579 | fdf9b3e8 | bellard | /* 10000101mmmmi4*2 mov.w @(<disp>,<REG_M>),R0*/{"mov.w",{A_DISP_REG_M,A_R0},{HEX_8,HEX_5,REG_M,IMM0_4BY2}, arch_sh1_up}, |
580 | fdf9b3e8 | bellard | |
581 | fdf9b3e8 | bellard | /* 11000101i8*2.... mov.w @(<disp>,GBR),R0*/{"mov.w",{A_DISP_GBR,A_R0},{HEX_C,HEX_5,IMM0_8BY2}, arch_sh1_up}, |
582 | fdf9b3e8 | bellard | |
583 | fdf9b3e8 | bellard | /* 1001nnnni8p2.... mov.w @(<disp>,PC),<REG_N>*/{"mov.w",{A_DISP_PC,A_REG_N},{HEX_9,REG_N,PCRELIMM_8BY2}, arch_sh1_up}, |
584 | fdf9b3e8 | bellard | |
585 | fdf9b3e8 | bellard | /* 0000nnnnmmmm1101 mov.w @(R0,<REG_M>),<REG_N>*/{"mov.w",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_D}, arch_sh1_up}, |
586 | fdf9b3e8 | bellard | |
587 | fdf9b3e8 | bellard | /* 0110nnnnmmmm0101 mov.w @<REG_M>+,<REG_N>*/{"mov.w",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_5}, arch_sh1_up}, |
588 | fdf9b3e8 | bellard | |
589 | fdf9b3e8 | bellard | /* 0110nnnnmmmm0001 mov.w @<REG_M>,<REG_N>*/{"mov.w",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_1}, arch_sh1_up}, |
590 | fdf9b3e8 | bellard | |
591 | fdf9b3e8 | bellard | /* 10000001mmmmi4*2 mov.w R0,@(<disp>,<REG_M>)*/{"mov.w",{A_R0,A_DISP_REG_M},{HEX_8,HEX_1,REG_M,IMM1_4BY2}, arch_sh1_up}, |
592 | fdf9b3e8 | bellard | |
593 | fdf9b3e8 | bellard | /* 11000001i8*2.... mov.w R0,@(<disp>,GBR)*/{"mov.w",{A_R0,A_DISP_GBR},{HEX_C,HEX_1,IMM1_8BY2}, arch_sh1_up}, |
594 | fdf9b3e8 | bellard | |
595 | fdf9b3e8 | bellard | /* 0100nnnn10011011 mov.w R0,@<REG_N>+ */{"mov.w",{A_R0,A_INC_N},{HEX_4,REG_N,HEX_9,HEX_B}, arch_sh2a_nofpu_up}, |
596 | fdf9b3e8 | bellard | /* 0100nnnn11011011 mov.w @-<REG_M>,R0 */{"mov.w",{A_DEC_M,A_R0},{HEX_4,REG_M,HEX_D,HEX_B}, arch_sh2a_nofpu_up}, |
597 | fdf9b3e8 | bellard | /* 0011nnnnmmmm0001 0001dddddddddddd mov.w <REG_M>,@(<DISP12>,<REG_N>) */
|
598 | fdf9b3e8 | bellard | {"mov.w",{A_REG_M,A_DISP_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_1,DISP1_12BY2}, arch_sh2a_nofpu_up | arch_op32},
|
599 | fdf9b3e8 | bellard | /* 0011nnnnmmmm0001 0101dddddddddddd mov.w @(<DISP12>,<REG_M>),<REG_N> */
|
600 | fdf9b3e8 | bellard | {"mov.w",{A_DISP_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_5,DISP0_12BY2}, arch_sh2a_nofpu_up | arch_op32},
|
601 | fdf9b3e8 | bellard | /* 11000111i8p4.... mova @(<disp>,PC),R0*/{"mova",{A_DISP_PC,A_R0},{HEX_C,HEX_7,PCRELIMM_8BY4}, arch_sh1_up}, |
602 | fdf9b3e8 | bellard | /* 0000nnnn11000011 movca.l R0,@<REG_N> */{"movca.l",{A_R0,A_IND_N},{HEX_0,REG_N,HEX_C,HEX_3}, arch_sh4_nommu_nofpu_up}, |
603 | fdf9b3e8 | bellard | |
604 | fdf9b3e8 | bellard | /* 0000nnnn01110011 movco.l r0,@<REG_N> */{"movco.l",{A_R0,A_IND_N},{HEX_0,REG_N,HEX_7,HEX_3}, arch_sh4a_nofp_up}, |
605 | fdf9b3e8 | bellard | /* 0000mmmm01100011 movli.l @<REG_M>,r0 */{"movli.l",{A_IND_M,A_R0},{HEX_0,REG_M,HEX_6,HEX_3}, arch_sh4a_nofp_up}, |
606 | fdf9b3e8 | bellard | |
607 | fdf9b3e8 | bellard | /* 0000nnnn00101001 movt <REG_N> */{"movt",{A_REG_N},{HEX_0,REG_N,HEX_2,HEX_9}, arch_sh1_up}, |
608 | fdf9b3e8 | bellard | |
609 | fdf9b3e8 | bellard | /* 0100mmmm10101001 movua.l @<REG_M>,r0 */{"movua.l",{A_IND_M,A_R0},{HEX_4,REG_M,HEX_A,HEX_9}, arch_sh4a_nofp_up}, |
610 | fdf9b3e8 | bellard | /* 0100mmmm11101001 movua.l @<REG_M>+,r0 */{"movua.l",{A_INC_M,A_R0},{HEX_4,REG_M,HEX_E,HEX_9}, arch_sh4a_nofp_up}, |
611 | fdf9b3e8 | bellard | |
612 | fdf9b3e8 | bellard | /* 0010nnnnmmmm1111 muls.w <REG_M>,<REG_N>*/{"muls.w",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_F}, arch_sh1_up}, |
613 | fdf9b3e8 | bellard | /* 0010nnnnmmmm1111 muls <REG_M>,<REG_N>*/{"muls",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_F}, arch_sh1_up}, |
614 | fdf9b3e8 | bellard | |
615 | fdf9b3e8 | bellard | /* 0000nnnnmmmm0111 mul.l <REG_M>,<REG_N>*/{"mul.l",{ A_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_7}, arch_sh2_up}, |
616 | fdf9b3e8 | bellard | |
617 | fdf9b3e8 | bellard | /* 0010nnnnmmmm1110 mulu.w <REG_M>,<REG_N>*/{"mulu.w",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_E}, arch_sh1_up}, |
618 | fdf9b3e8 | bellard | /* 0010nnnnmmmm1110 mulu <REG_M>,<REG_N>*/{"mulu",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_E}, arch_sh1_up}, |
619 | fdf9b3e8 | bellard | |
620 | fdf9b3e8 | bellard | /* 0110nnnnmmmm1011 neg <REG_M>,<REG_N> */{"neg",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_B}, arch_sh1_up}, |
621 | fdf9b3e8 | bellard | |
622 | fdf9b3e8 | bellard | /* 0110nnnnmmmm1010 negc <REG_M>,<REG_N>*/{"negc",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_A}, arch_sh1_up}, |
623 | fdf9b3e8 | bellard | |
624 | fdf9b3e8 | bellard | /* 0000000000001001 nop */{"nop",{0},{HEX_0,HEX_0,HEX_0,HEX_9}, arch_sh1_up}, |
625 | fdf9b3e8 | bellard | |
626 | fdf9b3e8 | bellard | /* 0110nnnnmmmm0111 not <REG_M>,<REG_N> */{"not",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_7}, arch_sh1_up}, |
627 | fdf9b3e8 | bellard | /* 0000nnnn10010011 ocbi @<REG_N> */{"ocbi",{A_IND_N},{HEX_0,REG_N,HEX_9,HEX_3}, arch_sh4_nommu_nofpu_up}, |
628 | fdf9b3e8 | bellard | |
629 | fdf9b3e8 | bellard | /* 0000nnnn10100011 ocbp @<REG_N> */{"ocbp",{A_IND_N},{HEX_0,REG_N,HEX_A,HEX_3}, arch_sh4_nommu_nofpu_up}, |
630 | fdf9b3e8 | bellard | |
631 | fdf9b3e8 | bellard | /* 0000nnnn10110011 ocbwb @<REG_N> */{"ocbwb",{A_IND_N},{HEX_0,REG_N,HEX_B,HEX_3}, arch_sh4_nommu_nofpu_up}, |
632 | fdf9b3e8 | bellard | |
633 | fdf9b3e8 | bellard | |
634 | fdf9b3e8 | bellard | /* 11001011i8*1.... or #<imm>,R0 */{"or",{A_IMM,A_R0},{HEX_C,HEX_B,IMM0_8}, arch_sh1_up}, |
635 | fdf9b3e8 | bellard | |
636 | fdf9b3e8 | bellard | /* 0010nnnnmmmm1011 or <REG_M>,<REG_N> */{"or",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_B}, arch_sh1_up}, |
637 | fdf9b3e8 | bellard | |
638 | fdf9b3e8 | bellard | /* 11001111i8*1.... or.b #<imm>,@(R0,GBR)*/{"or.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_F,IMM0_8}, arch_sh1_up}, |
639 | fdf9b3e8 | bellard | |
640 | fdf9b3e8 | bellard | /* 0000nnnn10000011 pref @<REG_N> */{"pref",{A_IND_N},{HEX_0,REG_N,HEX_8,HEX_3}, arch_sh4_nommu_nofpu_up | arch_sh2a_nofpu_up}, |
641 | fdf9b3e8 | bellard | |
642 | fdf9b3e8 | bellard | /* 0000nnnn11010011 prefi @<REG_N> */{"prefi",{A_IND_N},{HEX_0,REG_N,HEX_D,HEX_3}, arch_sh4a_nofp_up}, |
643 | fdf9b3e8 | bellard | |
644 | fdf9b3e8 | bellard | /* 0100nnnn00100100 rotcl <REG_N> */{"rotcl",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_4}, arch_sh1_up}, |
645 | fdf9b3e8 | bellard | |
646 | fdf9b3e8 | bellard | /* 0100nnnn00100101 rotcr <REG_N> */{"rotcr",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_5}, arch_sh1_up}, |
647 | fdf9b3e8 | bellard | |
648 | fdf9b3e8 | bellard | /* 0100nnnn00000100 rotl <REG_N> */{"rotl",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_4}, arch_sh1_up}, |
649 | fdf9b3e8 | bellard | |
650 | fdf9b3e8 | bellard | /* 0100nnnn00000101 rotr <REG_N> */{"rotr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_5}, arch_sh1_up}, |
651 | fdf9b3e8 | bellard | |
652 | fdf9b3e8 | bellard | /* 0000000000101011 rte */{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh1_up}, |
653 | fdf9b3e8 | bellard | |
654 | fdf9b3e8 | bellard | /* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh1_up}, |
655 | fdf9b3e8 | bellard | |
656 | fdf9b3e8 | bellard | /* 0000000010011000 setdmx */{"setdmx",{0},{HEX_0,HEX_0,HEX_9,HEX_8}, arch_sh4al_dsp_up}, |
657 | fdf9b3e8 | bellard | /* 0000000011001000 setdmy */{"setdmy",{0},{HEX_0,HEX_0,HEX_C,HEX_8}, arch_sh4al_dsp_up}, |
658 | fdf9b3e8 | bellard | |
659 | fdf9b3e8 | bellard | /* 0000000001011000 sets */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh1_up}, |
660 | fdf9b3e8 | bellard | /* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh1_up}, |
661 | fdf9b3e8 | bellard | |
662 | fdf9b3e8 | bellard | /* 0100nnnn00010100 setrc <REG_N> */{"setrc",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_4}, arch_sh_dsp_up}, |
663 | fdf9b3e8 | bellard | |
664 | fdf9b3e8 | bellard | /* 10000010i8*1.... setrc #<imm> */{"setrc",{A_IMM},{HEX_8,HEX_2,IMM0_8}, arch_sh_dsp_up}, |
665 | fdf9b3e8 | bellard | |
666 | fdf9b3e8 | bellard | /* repeat start end <REG_N> */{"repeat",{A_DISP_PC,A_DISP_PC,A_REG_N},{REPEAT,REG_N,HEX_1,HEX_4}, arch_sh_dsp_up}, |
667 | fdf9b3e8 | bellard | |
668 | fdf9b3e8 | bellard | /* repeat start end #<imm> */{"repeat",{A_DISP_PC,A_DISP_PC,A_IMM},{REPEAT,HEX_2,IMM0_8,HEX_8}, arch_sh_dsp_up}, |
669 | fdf9b3e8 | bellard | |
670 | fdf9b3e8 | bellard | /* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh3_nommu_up | arch_sh2a_nofpu_up}, |
671 | fdf9b3e8 | bellard | |
672 | fdf9b3e8 | bellard | /* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh3_nommu_up | arch_sh2a_nofpu_up}, |
673 | fdf9b3e8 | bellard | |
674 | fdf9b3e8 | bellard | /* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh1_up}, |
675 | fdf9b3e8 | bellard | |
676 | fdf9b3e8 | bellard | /* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh1_up}, |
677 | fdf9b3e8 | bellard | |
678 | fdf9b3e8 | bellard | /* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh1_up}, |
679 | fdf9b3e8 | bellard | |
680 | fdf9b3e8 | bellard | /* 0100nnnn00101000 shll16 <REG_N> */{"shll16",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_8}, arch_sh1_up}, |
681 | fdf9b3e8 | bellard | |
682 | fdf9b3e8 | bellard | /* 0100nnnn00001000 shll2 <REG_N> */{"shll2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_8}, arch_sh1_up}, |
683 | fdf9b3e8 | bellard | |
684 | fdf9b3e8 | bellard | /* 0100nnnn00011000 shll8 <REG_N> */{"shll8",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_8}, arch_sh1_up}, |
685 | fdf9b3e8 | bellard | |
686 | fdf9b3e8 | bellard | /* 0100nnnn00000001 shlr <REG_N> */{"shlr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_1}, arch_sh1_up}, |
687 | fdf9b3e8 | bellard | |
688 | fdf9b3e8 | bellard | /* 0100nnnn00101001 shlr16 <REG_N> */{"shlr16",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_9}, arch_sh1_up}, |
689 | fdf9b3e8 | bellard | |
690 | fdf9b3e8 | bellard | /* 0100nnnn00001001 shlr2 <REG_N> */{"shlr2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_9}, arch_sh1_up}, |
691 | fdf9b3e8 | bellard | |
692 | fdf9b3e8 | bellard | /* 0100nnnn00011001 shlr8 <REG_N> */{"shlr8",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_9}, arch_sh1_up}, |
693 | fdf9b3e8 | bellard | |
694 | fdf9b3e8 | bellard | /* 0000000000011011 sleep */{"sleep",{0},{HEX_0,HEX_0,HEX_1,HEX_B}, arch_sh1_up}, |
695 | fdf9b3e8 | bellard | |
696 | fdf9b3e8 | bellard | /* 0000nnnn00000010 stc SR,<REG_N> */{"stc",{A_SR,A_REG_N},{HEX_0,REG_N,HEX_0,HEX_2}, arch_sh1_up}, |
697 | fdf9b3e8 | bellard | |
698 | fdf9b3e8 | bellard | /* 0000nnnn00010010 stc GBR,<REG_N> */{"stc",{A_GBR,A_REG_N},{HEX_0,REG_N,HEX_1,HEX_2}, arch_sh1_up}, |
699 | fdf9b3e8 | bellard | |
700 | fdf9b3e8 | bellard | /* 0000nnnn00100010 stc VBR,<REG_N> */{"stc",{A_VBR,A_REG_N},{HEX_0,REG_N,HEX_2,HEX_2}, arch_sh1_up}, |
701 | fdf9b3e8 | bellard | |
702 | fdf9b3e8 | bellard | /* 0000nnnn01010010 stc MOD,<REG_N> */{"stc",{A_MOD,A_REG_N},{HEX_0,REG_N,HEX_5,HEX_2}, arch_sh_dsp_up}, |
703 | fdf9b3e8 | bellard | |
704 | fdf9b3e8 | bellard | /* 0000nnnn01110010 stc RE,<REG_N> */{"stc",{A_RE,A_REG_N},{HEX_0,REG_N,HEX_7,HEX_2}, arch_sh_dsp_up}, |
705 | fdf9b3e8 | bellard | |
706 | fdf9b3e8 | bellard | /* 0000nnnn01100010 stc RS,<REG_N> */{"stc",{A_RS,A_REG_N},{HEX_0,REG_N,HEX_6,HEX_2}, arch_sh_dsp_up}, |
707 | fdf9b3e8 | bellard | |
708 | fdf9b3e8 | bellard | /* 0000nnnn00110010 stc SSR,<REG_N> */{"stc",{A_SSR,A_REG_N},{HEX_0,REG_N,HEX_3,HEX_2}, arch_sh3_nommu_up}, |
709 | fdf9b3e8 | bellard | |
710 | fdf9b3e8 | bellard | /* 0000nnnn01000010 stc SPC,<REG_N> */{"stc",{A_SPC,A_REG_N},{HEX_0,REG_N,HEX_4,HEX_2}, arch_sh3_nommu_up}, |
711 | fdf9b3e8 | bellard | |
712 | fdf9b3e8 | bellard | /* 0000nnnn00111010 stc SGR,<REG_N> */{"stc",{A_SGR,A_REG_N},{HEX_0,REG_N,HEX_3,HEX_A}, arch_sh4_nommu_nofpu_up}, |
713 | fdf9b3e8 | bellard | |
714 | fdf9b3e8 | bellard | /* 0000nnnn11111010 stc DBR,<REG_N> */{"stc",{A_DBR,A_REG_N},{HEX_0,REG_N,HEX_F,HEX_A}, arch_sh4_nommu_nofpu_up}, |
715 | fdf9b3e8 | bellard | |
716 | fdf9b3e8 | bellard | /* 0000nnnn1xxx0010 stc Rn_BANK,<REG_N> */{"stc",{A_REG_B,A_REG_N},{HEX_0,REG_N,REG_B,HEX_2}, arch_sh3_nommu_up}, |
717 | fdf9b3e8 | bellard | |
718 | fdf9b3e8 | bellard | /* 0000nnnn01001010 stc TBR,<REG_N> */ {"stc",{A_TBR,A_REG_N},{HEX_0,REG_N,HEX_4,HEX_A}, arch_sh2a_nofpu_up}, |
719 | fdf9b3e8 | bellard | |
720 | fdf9b3e8 | bellard | /* 0100nnnn00000011 stc.l SR,@-<REG_N> */{"stc.l",{A_SR,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_3}, arch_sh1_up}, |
721 | fdf9b3e8 | bellard | |
722 | fdf9b3e8 | bellard | /* 0100nnnn00100011 stc.l VBR,@-<REG_N> */{"stc.l",{A_VBR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_3}, arch_sh1_up}, |
723 | fdf9b3e8 | bellard | |
724 | fdf9b3e8 | bellard | /* 0100nnnn01010011 stc.l MOD,@-<REG_N> */{"stc.l",{A_MOD,A_DEC_N},{HEX_4,REG_N,HEX_5,HEX_3}, arch_sh_dsp_up}, |
725 | fdf9b3e8 | bellard | |
726 | fdf9b3e8 | bellard | /* 0100nnnn01110011 stc.l RE,@-<REG_N> */{"stc.l",{A_RE,A_DEC_N},{HEX_4,REG_N,HEX_7,HEX_3}, arch_sh_dsp_up}, |
727 | fdf9b3e8 | bellard | |
728 | fdf9b3e8 | bellard | /* 0100nnnn01100011 stc.l RS,@-<REG_N> */{"stc.l",{A_RS,A_DEC_N},{HEX_4,REG_N,HEX_6,HEX_3}, arch_sh_dsp_up}, |
729 | fdf9b3e8 | bellard | |
730 | fdf9b3e8 | bellard | /* 0100nnnn00110011 stc.l SSR,@-<REG_N> */{"stc.l",{A_SSR,A_DEC_N},{HEX_4,REG_N,HEX_3,HEX_3}, arch_sh3_nommu_up}, |
731 | fdf9b3e8 | bellard | |
732 | fdf9b3e8 | bellard | /* 0100nnnn01000011 stc.l SPC,@-<REG_N> */{"stc.l",{A_SPC,A_DEC_N},{HEX_4,REG_N,HEX_4,HEX_3}, arch_sh3_nommu_up}, |
733 | fdf9b3e8 | bellard | |
734 | fdf9b3e8 | bellard | /* 0100nnnn00010011 stc.l GBR,@-<REG_N> */{"stc.l",{A_GBR,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_3}, arch_sh1_up}, |
735 | fdf9b3e8 | bellard | |
736 | fdf9b3e8 | bellard | /* 0100nnnn00110010 stc.l SGR,@-<REG_N> */{"stc.l",{A_SGR,A_DEC_N},{HEX_4,REG_N,HEX_3,HEX_2}, arch_sh4_nommu_nofpu_up}, |
737 | fdf9b3e8 | bellard | |
738 | fdf9b3e8 | bellard | /* 0100nnnn11110010 stc.l DBR,@-<REG_N> */{"stc.l",{A_DBR,A_DEC_N},{HEX_4,REG_N,HEX_F,HEX_2}, arch_sh4_nommu_nofpu_up}, |
739 | fdf9b3e8 | bellard | |
740 | fdf9b3e8 | bellard | /* 0100nnnn1xxx0011 stc.l Rn_BANK,@-<REG_N> */{"stc.l",{A_REG_B,A_DEC_N},{HEX_4,REG_N,REG_B,HEX_3}, arch_sh3_nommu_up}, |
741 | fdf9b3e8 | bellard | |
742 | fdf9b3e8 | bellard | /* 0000nnnn00001010 sts MACH,<REG_N> */{"sts",{A_MACH,A_REG_N},{HEX_0,REG_N,HEX_0,HEX_A}, arch_sh1_up}, |
743 | fdf9b3e8 | bellard | |
744 | fdf9b3e8 | bellard | /* 0000nnnn00011010 sts MACL,<REG_N> */{"sts",{A_MACL,A_REG_N},{HEX_0,REG_N,HEX_1,HEX_A}, arch_sh1_up}, |
745 | fdf9b3e8 | bellard | |
746 | fdf9b3e8 | bellard | /* 0000nnnn00101010 sts PR,<REG_N> */{"sts",{A_PR,A_REG_N},{HEX_0,REG_N,HEX_2,HEX_A}, arch_sh1_up}, |
747 | fdf9b3e8 | bellard | |
748 | fdf9b3e8 | bellard | /* 0000nnnn01101010 sts DSR,<REG_N> */{"sts",{A_DSR,A_REG_N},{HEX_0,REG_N,HEX_6,HEX_A}, arch_sh_dsp_up}, |
749 | fdf9b3e8 | bellard | |
750 | fdf9b3e8 | bellard | /* 0000nnnn01111010 sts A0,<REG_N> */{"sts",{A_A0,A_REG_N},{HEX_0,REG_N,HEX_7,HEX_A}, arch_sh_dsp_up}, |
751 | fdf9b3e8 | bellard | |
752 | fdf9b3e8 | bellard | /* 0000nnnn10001010 sts X0,<REG_N> */{"sts",{A_X0,A_REG_N},{HEX_0,REG_N,HEX_8,HEX_A}, arch_sh_dsp_up}, |
753 | fdf9b3e8 | bellard | |
754 | fdf9b3e8 | bellard | /* 0000nnnn10011010 sts X1,<REG_N> */{"sts",{A_X1,A_REG_N},{HEX_0,REG_N,HEX_9,HEX_A}, arch_sh_dsp_up}, |
755 | fdf9b3e8 | bellard | |
756 | fdf9b3e8 | bellard | /* 0000nnnn10101010 sts Y0,<REG_N> */{"sts",{A_Y0,A_REG_N},{HEX_0,REG_N,HEX_A,HEX_A}, arch_sh_dsp_up}, |
757 | fdf9b3e8 | bellard | |
758 | fdf9b3e8 | bellard | /* 0000nnnn10111010 sts Y1,<REG_N> */{"sts",{A_Y1,A_REG_N},{HEX_0,REG_N,HEX_B,HEX_A}, arch_sh_dsp_up}, |
759 | fdf9b3e8 | bellard | |
760 | fdf9b3e8 | bellard | /* 0000nnnn01011010 sts FPUL,<REG_N> */{"sts",{FPUL_M,A_REG_N},{HEX_0,REG_N,HEX_5,HEX_A}, arch_sh2e_up}, |
761 | fdf9b3e8 | bellard | |
762 | fdf9b3e8 | bellard | /* 0000nnnn01101010 sts FPSCR,<REG_N> */{"sts",{FPSCR_M,A_REG_N},{HEX_0,REG_N,HEX_6,HEX_A}, arch_sh2e_up}, |
763 | fdf9b3e8 | bellard | |
764 | fdf9b3e8 | bellard | /* 0100nnnn00000010 sts.l MACH,@-<REG_N>*/{"sts.l",{A_MACH,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_2}, arch_sh1_up}, |
765 | fdf9b3e8 | bellard | |
766 | fdf9b3e8 | bellard | /* 0100nnnn00010010 sts.l MACL,@-<REG_N>*/{"sts.l",{A_MACL,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_2}, arch_sh1_up}, |
767 | fdf9b3e8 | bellard | |
768 | fdf9b3e8 | bellard | /* 0100nnnn00100010 sts.l PR,@-<REG_N> */{"sts.l",{A_PR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_2}, arch_sh1_up}, |
769 | fdf9b3e8 | bellard | |
770 | fdf9b3e8 | bellard | /* 0100nnnn01100110 sts.l DSR,@-<REG_N> */{"sts.l",{A_DSR,A_DEC_N},{HEX_4,REG_N,HEX_6,HEX_2}, arch_sh_dsp_up}, |
771 | fdf9b3e8 | bellard | |
772 | fdf9b3e8 | bellard | /* 0100nnnn01110110 sts.l A0,@-<REG_N> */{"sts.l",{A_A0,A_DEC_N},{HEX_4,REG_N,HEX_7,HEX_2}, arch_sh_dsp_up}, |
773 | fdf9b3e8 | bellard | |
774 | fdf9b3e8 | bellard | /* 0100nnnn10000110 sts.l X0,@-<REG_N> */{"sts.l",{A_X0,A_DEC_N},{HEX_4,REG_N,HEX_8,HEX_2}, arch_sh_dsp_up}, |
775 | fdf9b3e8 | bellard | |
776 | fdf9b3e8 | bellard | /* 0100nnnn10010110 sts.l X1,@-<REG_N> */{"sts.l",{A_X1,A_DEC_N},{HEX_4,REG_N,HEX_9,HEX_2}, arch_sh_dsp_up}, |
777 | fdf9b3e8 | bellard | |
778 | fdf9b3e8 | bellard | /* 0100nnnn10100110 sts.l Y0,@-<REG_N> */{"sts.l",{A_Y0,A_DEC_N},{HEX_4,REG_N,HEX_A,HEX_2}, arch_sh_dsp_up}, |
779 | fdf9b3e8 | bellard | |
780 | fdf9b3e8 | bellard | /* 0100nnnn10110110 sts.l Y1,@-<REG_N> */{"sts.l",{A_Y1,A_DEC_N},{HEX_4,REG_N,HEX_B,HEX_2}, arch_sh_dsp_up}, |
781 | fdf9b3e8 | bellard | |
782 | fdf9b3e8 | bellard | /* 0100nnnn01010010 sts.l FPUL,@-<REG_N>*/{"sts.l",{FPUL_M,A_DEC_N},{HEX_4,REG_N,HEX_5,HEX_2}, arch_sh2e_up}, |
783 | fdf9b3e8 | bellard | |
784 | fdf9b3e8 | bellard | /* 0100nnnn01100010 sts.l FPSCR,@-<REG_N>*/{"sts.l",{FPSCR_M,A_DEC_N},{HEX_4,REG_N,HEX_6,HEX_2}, arch_sh2e_up}, |
785 | fdf9b3e8 | bellard | |
786 | fdf9b3e8 | bellard | /* 0011nnnnmmmm1000 sub <REG_M>,<REG_N> */{"sub",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_8}, arch_sh1_up}, |
787 | fdf9b3e8 | bellard | |
788 | fdf9b3e8 | bellard | /* 0011nnnnmmmm1010 subc <REG_M>,<REG_N>*/{"subc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_A}, arch_sh1_up}, |
789 | fdf9b3e8 | bellard | |
790 | fdf9b3e8 | bellard | /* 0011nnnnmmmm1011 subv <REG_M>,<REG_N>*/{"subv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_B}, arch_sh1_up}, |
791 | fdf9b3e8 | bellard | |
792 | fdf9b3e8 | bellard | /* 0110nnnnmmmm1000 swap.b <REG_M>,<REG_N>*/{"swap.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_8}, arch_sh1_up}, |
793 | fdf9b3e8 | bellard | |
794 | fdf9b3e8 | bellard | /* 0110nnnnmmmm1001 swap.w <REG_M>,<REG_N>*/{"swap.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_9}, arch_sh1_up}, |
795 | fdf9b3e8 | bellard | |
796 | fdf9b3e8 | bellard | /* 0000000010101011 synco */{"synco",{0},{HEX_0,HEX_0,HEX_A,HEX_B}, arch_sh4a_nofp_up}, |
797 | fdf9b3e8 | bellard | |
798 | fdf9b3e8 | bellard | /* 0100nnnn00011011 tas.b @<REG_N> */{"tas.b",{A_IND_N},{HEX_4,REG_N,HEX_1,HEX_B}, arch_sh1_up}, |
799 | fdf9b3e8 | bellard | |
800 | fdf9b3e8 | bellard | /* 11000011i8*1.... trapa #<imm> */{"trapa",{A_IMM},{HEX_C,HEX_3,IMM0_8}, arch_sh1_up}, |
801 | fdf9b3e8 | bellard | |
802 | fdf9b3e8 | bellard | /* 11001000i8*1.... tst #<imm>,R0 */{"tst",{A_IMM,A_R0},{HEX_C,HEX_8,IMM0_8}, arch_sh1_up}, |
803 | fdf9b3e8 | bellard | |
804 | fdf9b3e8 | bellard | /* 0010nnnnmmmm1000 tst <REG_M>,<REG_N> */{"tst",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_8}, arch_sh1_up}, |
805 | fdf9b3e8 | bellard | |
806 | fdf9b3e8 | bellard | /* 11001100i8*1.... tst.b #<imm>,@(R0,GBR)*/{"tst.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_C,IMM0_8}, arch_sh1_up}, |
807 | fdf9b3e8 | bellard | |
808 | fdf9b3e8 | bellard | /* 11001010i8*1.... xor #<imm>,R0 */{"xor",{A_IMM,A_R0},{HEX_C,HEX_A,IMM0_8}, arch_sh1_up}, |
809 | fdf9b3e8 | bellard | |
810 | fdf9b3e8 | bellard | /* 0010nnnnmmmm1010 xor <REG_M>,<REG_N> */{"xor",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_A}, arch_sh1_up}, |
811 | fdf9b3e8 | bellard | |
812 | fdf9b3e8 | bellard | /* 11001110i8*1.... xor.b #<imm>,@(R0,GBR)*/{"xor.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_E,IMM0_8}, arch_sh1_up}, |
813 | fdf9b3e8 | bellard | |
814 | fdf9b3e8 | bellard | /* 0010nnnnmmmm1101 xtrct <REG_M>,<REG_N>*/{"xtrct",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_D}, arch_sh1_up}, |
815 | fdf9b3e8 | bellard | |
816 | fdf9b3e8 | bellard | /* 0000nnnnmmmm0111 mul.l <REG_M>,<REG_N>*/{"mul.l",{ A_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_7}, arch_sh1_up}, |
817 | fdf9b3e8 | bellard | |
818 | fdf9b3e8 | bellard | /* 0100nnnn00010000 dt <REG_N> */{"dt",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_0}, arch_sh2_up}, |
819 | fdf9b3e8 | bellard | |
820 | fdf9b3e8 | bellard | /* 0011nnnnmmmm1101 dmuls.l <REG_M>,<REG_N>*/{"dmuls.l",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_D}, arch_sh2_up}, |
821 | fdf9b3e8 | bellard | |
822 | fdf9b3e8 | bellard | /* 0011nnnnmmmm0101 dmulu.l <REG_M>,<REG_N>*/{"dmulu.l",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_5}, arch_sh2_up}, |
823 | fdf9b3e8 | bellard | |
824 | fdf9b3e8 | bellard | /* 0000nnnnmmmm1111 mac.l @<REG_M>+,@<REG_N>+*/{"mac.l",{A_INC_M,A_INC_N},{HEX_0,REG_N,REG_M,HEX_F}, arch_sh2_up}, |
825 | fdf9b3e8 | bellard | |
826 | fdf9b3e8 | bellard | /* 0000nnnn00100011 braf <REG_N> */{"braf",{A_REG_N},{HEX_0,REG_N,HEX_2,HEX_3}, arch_sh2_up}, |
827 | fdf9b3e8 | bellard | |
828 | fdf9b3e8 | bellard | /* 0000nnnn00000011 bsrf <REG_N> */{"bsrf",{A_REG_N},{HEX_0,REG_N,HEX_0,HEX_3}, arch_sh2_up}, |
829 | fdf9b3e8 | bellard | |
830 | fdf9b3e8 | bellard | /* 111101nnmmmm0000 movs.w @-<REG_N>,<DSP_REG_M> */ {"movs.w",{A_DEC_N,DSP_REG_M},{HEX_F,SDT_REG_N,REG_M,HEX_0}, arch_sh_dsp_up}, |
831 | fdf9b3e8 | bellard | |
832 | fdf9b3e8 | bellard | /* 111101nnmmmm0001 movs.w @<REG_N>,<DSP_REG_M> */ {"movs.w",{A_IND_N,DSP_REG_M},{HEX_F,SDT_REG_N,REG_M,HEX_4}, arch_sh_dsp_up}, |
833 | fdf9b3e8 | bellard | |
834 | fdf9b3e8 | bellard | /* 111101nnmmmm0010 movs.w @<REG_N>+,<DSP_REG_M> */ {"movs.w",{A_INC_N,DSP_REG_M},{HEX_F,SDT_REG_N,REG_M,HEX_8}, arch_sh_dsp_up}, |
835 | fdf9b3e8 | bellard | |
836 | fdf9b3e8 | bellard | /* 111101nnmmmm0011 movs.w @<REG_N>+r8,<DSP_REG_M> */ {"movs.w",{AS_PMOD_N,DSP_REG_M},{HEX_F,SDT_REG_N,REG_M,HEX_C}, arch_sh_dsp_up}, |
837 | fdf9b3e8 | bellard | |
838 | fdf9b3e8 | bellard | /* 111101nnmmmm0100 movs.w <DSP_REG_M>,@-<REG_N> */ {"movs.w",{DSP_REG_M,A_DEC_N},{HEX_F,SDT_REG_N,REG_M,HEX_1}, arch_sh_dsp_up}, |
839 | fdf9b3e8 | bellard | |
840 | fdf9b3e8 | bellard | /* 111101nnmmmm0101 movs.w <DSP_REG_M>,@<REG_N> */ {"movs.w",{DSP_REG_M,A_IND_N},{HEX_F,SDT_REG_N,REG_M,HEX_5}, arch_sh_dsp_up}, |
841 | fdf9b3e8 | bellard | |
842 | fdf9b3e8 | bellard | /* 111101nnmmmm0110 movs.w <DSP_REG_M>,@<REG_N>+ */ {"movs.w",{DSP_REG_M,A_INC_N},{HEX_F,SDT_REG_N,REG_M,HEX_9}, arch_sh_dsp_up}, |
843 | fdf9b3e8 | bellard | |
844 | fdf9b3e8 | bellard | /* 111101nnmmmm0111 movs.w <DSP_REG_M>,@<REG_N>+r8 */ {"movs.w",{DSP_REG_M,AS_PMOD_N},{HEX_F,SDT_REG_N,REG_M,HEX_D}, arch_sh_dsp_up}, |
845 | fdf9b3e8 | bellard | |
846 | fdf9b3e8 | bellard | /* 111101nnmmmm1000 movs.l @-<REG_N>,<DSP_REG_M> */ {"movs.l",{A_DEC_N,DSP_REG_M},{HEX_F,SDT_REG_N,REG_M,HEX_2}, arch_sh_dsp_up}, |
847 | fdf9b3e8 | bellard | |
848 | fdf9b3e8 | bellard | /* 111101nnmmmm1001 movs.l @<REG_N>,<DSP_REG_M> */ {"movs.l",{A_IND_N,DSP_REG_M},{HEX_F,SDT_REG_N,REG_M,HEX_6}, arch_sh_dsp_up}, |
849 | fdf9b3e8 | bellard | |
850 | fdf9b3e8 | bellard | /* 111101nnmmmm1010 movs.l @<REG_N>+,<DSP_REG_M> */ {"movs.l",{A_INC_N,DSP_REG_M},{HEX_F,SDT_REG_N,REG_M,HEX_A}, arch_sh_dsp_up}, |
851 | fdf9b3e8 | bellard | |
852 | fdf9b3e8 | bellard | /* 111101nnmmmm1011 movs.l @<REG_N>+r8,<DSP_REG_M> */ {"movs.l",{AS_PMOD_N,DSP_REG_M},{HEX_F,SDT_REG_N,REG_M,HEX_E}, arch_sh_dsp_up}, |
853 | fdf9b3e8 | bellard | |
854 | fdf9b3e8 | bellard | /* 111101nnmmmm1100 movs.l <DSP_REG_M>,@-<REG_N> */ {"movs.l",{DSP_REG_M,A_DEC_N},{HEX_F,SDT_REG_N,REG_M,HEX_3}, arch_sh_dsp_up}, |
855 | fdf9b3e8 | bellard | |
856 | fdf9b3e8 | bellard | /* 111101nnmmmm1101 movs.l <DSP_REG_M>,@<REG_N> */ {"movs.l",{DSP_REG_M,A_IND_N},{HEX_F,SDT_REG_N,REG_M,HEX_7}, arch_sh_dsp_up}, |
857 | fdf9b3e8 | bellard | |
858 | fdf9b3e8 | bellard | /* 111101nnmmmm1110 movs.l <DSP_REG_M>,@<REG_N>+ */ {"movs.l",{DSP_REG_M,A_INC_N},{HEX_F,SDT_REG_N,REG_M,HEX_B}, arch_sh_dsp_up}, |
859 | fdf9b3e8 | bellard | |
860 | fdf9b3e8 | bellard | /* 111101nnmmmm1111 movs.l <DSP_REG_M>,@<REG_N>+r8 */ {"movs.l",{DSP_REG_M,AS_PMOD_N},{HEX_F,SDT_REG_N,REG_M,HEX_F}, arch_sh_dsp_up}, |
861 | fdf9b3e8 | bellard | |
862 | fdf9b3e8 | bellard | /* 0*0*0*00** nopx */ {"nopx",{0},{PPI,NOPX}, arch_sh_dsp_up}, |
863 | fdf9b3e8 | bellard | /* *0*0*0**00 nopy */ {"nopy",{0},{PPI,NOPY}, arch_sh_dsp_up}, |
864 | fdf9b3e8 | bellard | /* n*m*0*01** movx.w @<REG_N>,<DSP_REG_X> */ {"movx.w",{AX_IND_N,DSP_REG_X},{PPI,MOVX,HEX_1}, arch_sh_dsp_up}, |
865 | fdf9b3e8 | bellard | /* n*m*0*10** movx.w @<REG_N>+,<DSP_REG_X> */ {"movx.w",{AX_INC_N,DSP_REG_X},{PPI,MOVX,HEX_2}, arch_sh_dsp_up}, |
866 | fdf9b3e8 | bellard | /* n*m*0*11** movx.w @<REG_N>+r8,<DSP_REG_X> */ {"movx.w",{AX_PMOD_N,DSP_REG_X},{PPI,MOVX,HEX_3}, arch_sh_dsp_up}, |
867 | fdf9b3e8 | bellard | /* n*m*1*01** movx.w <DSP_REG_M>,@<REG_N> */ {"movx.w",{DSP_REG_A_M,AX_IND_N},{PPI,MOVX,HEX_9}, arch_sh_dsp_up}, |
868 | fdf9b3e8 | bellard | /* n*m*1*10** movx.w <DSP_REG_M>,@<REG_N>+ */ {"movx.w",{DSP_REG_A_M,AX_INC_N},{PPI,MOVX,HEX_A}, arch_sh_dsp_up}, |
869 | fdf9b3e8 | bellard | /* n*m*1*11** movx.w <DSP_REG_M>,@<REG_N>+r8 */ {"movx.w",{DSP_REG_A_M,AX_PMOD_N},{PPI,MOVX,HEX_B}, arch_sh_dsp_up}, |
870 | fdf9b3e8 | bellard | |
871 | fdf9b3e8 | bellard | /* nnmm000100 movx.w @<REG_Axy>,<DSP_REG_XY> */ {"movx.w",{AXY_IND_N,DSP_REG_XY},{PPI,MOVX_NOPY,HEX_0,HEX_4}, arch_sh4al_dsp_up}, |
872 | fdf9b3e8 | bellard | /* nnmm001000 movx.w @<REG_Axy>+,<DSP_REG_XY> */{"movx.w",{AXY_INC_N,DSP_REG_XY},{PPI,MOVX_NOPY,HEX_0,HEX_8}, arch_sh4al_dsp_up}, |
873 | fdf9b3e8 | bellard | /* nnmm001100 movx.w @<REG_Axy>+r8,<DSP_REG_XY> */{"movx.w",{AXY_PMOD_N,DSP_REG_XY},{PPI,MOVX_NOPY,HEX_0,HEX_C}, arch_sh4al_dsp_up}, |
874 | fdf9b3e8 | bellard | /* nnmm100100 movx.w <DSP_REG_AX>,@<REG_Axy> */ {"movx.w",{DSP_REG_AX,AXY_IND_N},{PPI,MOVX_NOPY,HEX_2,HEX_4}, arch_sh4al_dsp_up}, |
875 | fdf9b3e8 | bellard | /* nnmm101000 movx.w <DSP_REG_AX>,@<REG_Axy>+ */{"movx.w",{DSP_REG_AX,AXY_INC_N},{PPI,MOVX_NOPY,HEX_2,HEX_8}, arch_sh4al_dsp_up}, |
876 | fdf9b3e8 | bellard | /* nnmm101100 movx.w <DSP_REG_AX>,@<REG_Axy>+r8 */{"movx.w",{DSP_REG_AX,AXY_PMOD_N},{PPI,MOVX_NOPY,HEX_2,HEX_C}, arch_sh4al_dsp_up}, |
877 | fdf9b3e8 | bellard | |
878 | fdf9b3e8 | bellard | /* nnmm010100 movx.l @<REG_Axy>,<DSP_REG_XY> */ {"movx.l",{AXY_IND_N,DSP_REG_XY},{PPI,MOVX_NOPY,HEX_1,HEX_4}, arch_sh4al_dsp_up}, |
879 | fdf9b3e8 | bellard | /* nnmm011000 movx.l @<REG_Axy>+,<DSP_REG_XY> */{"movx.l",{AXY_INC_N,DSP_REG_XY},{PPI,MOVX_NOPY,HEX_1,HEX_8}, arch_sh4al_dsp_up}, |
880 | fdf9b3e8 | bellard | /* nnmm011100 movx.l @<REG_Axy>+r8,<DSP_REG_XY> */{"movx.l",{AXY_PMOD_N,DSP_REG_XY},{PPI,MOVX_NOPY,HEX_1,HEX_C}, arch_sh4al_dsp_up}, |
881 | fdf9b3e8 | bellard | /* nnmm110100 movx.l <DSP_REG_AX>,@<REG_Axy> */ {"movx.l",{DSP_REG_AX,AXY_IND_N},{PPI,MOVX_NOPY,HEX_3,HEX_4}, arch_sh4al_dsp_up}, |
882 | fdf9b3e8 | bellard | /* nnmm111000 movx.l <DSP_REG_AX>,@<REG_Axy>+ */{"movx.l",{DSP_REG_AX,AXY_INC_N},{PPI,MOVX_NOPY,HEX_3,HEX_8}, arch_sh4al_dsp_up}, |
883 | fdf9b3e8 | bellard | /* nnmm111100 movx.l <DSP_REG_AX>,@<REG_Axy>+r8 */{"movx.l",{DSP_REG_AX,AXY_PMOD_N},{PPI,MOVX_NOPY,HEX_3,HEX_C}, arch_sh4al_dsp_up}, |
884 | fdf9b3e8 | bellard | |
885 | fdf9b3e8 | bellard | /* *n*m*0**01 movy.w @<REG_N>,<DSP_REG_Y> */ {"movy.w",{AY_IND_N,DSP_REG_Y},{PPI,MOVY,HEX_1}, arch_sh_dsp_up}, |
886 | fdf9b3e8 | bellard | /* *n*m*0**10 movy.w @<REG_N>+,<DSP_REG_Y> */ {"movy.w",{AY_INC_N,DSP_REG_Y},{PPI,MOVY,HEX_2}, arch_sh_dsp_up}, |
887 | fdf9b3e8 | bellard | /* *n*m*0**11 movy.w @<REG_N>+r9,<DSP_REG_Y> */ {"movy.w",{AY_PMOD_N,DSP_REG_Y},{PPI,MOVY,HEX_3}, arch_sh_dsp_up}, |
888 | fdf9b3e8 | bellard | /* *n*m*1**01 movy.w <DSP_REG_M>,@<REG_N> */ {"movy.w",{DSP_REG_A_M,AY_IND_N},{PPI,MOVY,HEX_9}, arch_sh_dsp_up}, |
889 | fdf9b3e8 | bellard | /* *n*m*1**10 movy.w <DSP_REG_M>,@<REG_N>+ */ {"movy.w",{DSP_REG_A_M,AY_INC_N},{PPI,MOVY,HEX_A}, arch_sh_dsp_up}, |
890 | fdf9b3e8 | bellard | /* *n*m*1**11 movy.w <DSP_REG_M>,@<REG_N>+r9 */ {"movy.w",{DSP_REG_A_M,AY_PMOD_N},{PPI,MOVY,HEX_B}, arch_sh_dsp_up}, |
891 | fdf9b3e8 | bellard | |
892 | fdf9b3e8 | bellard | /* nnmm000001 movy.w @<REG_Ayx>,<DSP_REG_YX> */ {"movy.w",{AYX_IND_N,DSP_REG_YX},{PPI,MOVY_NOPX,HEX_0,HEX_1}, arch_sh4al_dsp_up}, |
893 | fdf9b3e8 | bellard | /* nnmm000010 movy.w @<REG_Ayx>+,<DSP_REG_YX> */{"movy.w",{AYX_INC_N,DSP_REG_YX},{PPI,MOVY_NOPX,HEX_0,HEX_2}, arch_sh4al_dsp_up}, |
894 | fdf9b3e8 | bellard | /* nnmm000011 movy.w @<REG_Ayx>+r8,<DSP_REG_YX> */{"movy.w",{AYX_PMOD_N,DSP_REG_YX},{PPI,MOVY_NOPX,HEX_0,HEX_3}, arch_sh4al_dsp_up}, |
895 | fdf9b3e8 | bellard | /* nnmm010001 movy.w <DSP_REG_AY>,@<REG_Ayx> */ {"movy.w",{DSP_REG_AY,AYX_IND_N},{PPI,MOVY_NOPX,HEX_1,HEX_1}, arch_sh4al_dsp_up}, |
896 | fdf9b3e8 | bellard | /* nnmm010010 movy.w <DSP_REG_AY>,@<REG_Ayx>+ */{"movy.w",{DSP_REG_AY,AYX_INC_N},{PPI,MOVY_NOPX,HEX_1,HEX_2}, arch_sh4al_dsp_up}, |
897 | fdf9b3e8 | bellard | /* nnmm010011 movy.w <DSP_REG_AY>,@<REG_Ayx>+r8 */{"movy.w",{DSP_REG_AY,AYX_PMOD_N},{PPI,MOVY_NOPX,HEX_1,HEX_3}, arch_sh4al_dsp_up}, |
898 | fdf9b3e8 | bellard | |
899 | fdf9b3e8 | bellard | /* nnmm100001 movy.l @<REG_Ayx>,<DSP_REG_YX> */ {"movy.l",{AYX_IND_N,DSP_REG_YX},{PPI,MOVY_NOPX,HEX_2,HEX_1}, arch_sh4al_dsp_up}, |
900 | fdf9b3e8 | bellard | /* nnmm100010 movy.l @<REG_Ayx>+,<DSP_REG_YX> */{"movy.l",{AYX_INC_N,DSP_REG_YX},{PPI,MOVY_NOPX,HEX_2,HEX_2}, arch_sh4al_dsp_up}, |
901 | fdf9b3e8 | bellard | /* nnmm100011 movy.l @<REG_Ayx>+r8,<DSP_REG_YX> */{"movy.l",{AYX_PMOD_N,DSP_REG_YX},{PPI,MOVY_NOPX,HEX_2,HEX_3}, arch_sh4al_dsp_up}, |
902 | fdf9b3e8 | bellard | /* nnmm110001 movy.l <DSP_REG_AY>,@<REG_Ayx> */ {"movy.l",{DSP_REG_AY,AYX_IND_N},{PPI,MOVY_NOPX,HEX_3,HEX_1}, arch_sh4al_dsp_up}, |
903 | fdf9b3e8 | bellard | /* nnmm110010 movy.l <DSP_REG_AY>,@<REG_Ayx>+ */{"movy.l",{DSP_REG_AY,AYX_INC_N},{PPI,MOVY_NOPX,HEX_3,HEX_2}, arch_sh4al_dsp_up}, |
904 | fdf9b3e8 | bellard | /* nnmm110011 movy.l <DSP_REG_AY>,@<REG_Ayx>+r8 */{"movy.l",{DSP_REG_AY,AYX_PMOD_N},{PPI,MOVY_NOPX,HEX_3,HEX_3}, arch_sh4al_dsp_up}, |
905 | fdf9b3e8 | bellard | |
906 | fdf9b3e8 | bellard | /* 01aaeeffxxyyggnn pmuls Se,Sf,Dg */ {"pmuls",{DSP_REG_E,DSP_REG_F,DSP_REG_G},{PPI,PMUL}, arch_sh_dsp_up}, |
907 | fdf9b3e8 | bellard | /* 10100000xxyynnnn psubc <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> */
|
908 | fdf9b3e8 | bellard | {"psubc",{DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPI3,HEX_A,HEX_0}, arch_sh_dsp_up},
|
909 | fdf9b3e8 | bellard | /* 10110000xxyynnnn paddc <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> */
|
910 | fdf9b3e8 | bellard | {"paddc",{DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPI3,HEX_B,HEX_0}, arch_sh_dsp_up},
|
911 | fdf9b3e8 | bellard | /* 10000100xxyynnnn pcmp <DSP_REG_X>,<DSP_REG_Y> */
|
912 | fdf9b3e8 | bellard | {"pcmp", {DSP_REG_X,DSP_REG_Y},{PPI,PPI3,HEX_8,HEX_4}, arch_sh_dsp_up},
|
913 | fdf9b3e8 | bellard | /* 10100100xxyynnnn pwsb <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> */
|
914 | fdf9b3e8 | bellard | {"pwsb", {DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPI3,HEX_A,HEX_4}, arch_sh_dsp_up},
|
915 | fdf9b3e8 | bellard | /* 10110100xxyynnnn pwad <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> */
|
916 | fdf9b3e8 | bellard | {"pwad", {DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPI3,HEX_B,HEX_4}, arch_sh_dsp_up},
|
917 | fdf9b3e8 | bellard | /* 10001000xxyynnnn pabs <DSP_REG_X>,<DSP_REG_N> */
|
918 | fdf9b3e8 | bellard | {"pabs", {DSP_REG_X,DSP_REG_N},{PPI,PPI3NC,HEX_8,HEX_8}, arch_sh_dsp_up},
|
919 | fdf9b3e8 | bellard | /* 1000100!xx01nnnn pabs <DSP_REG_X>,<DSP_REG_N> */
|
920 | fdf9b3e8 | bellard | {"pabs", {DSP_REG_X,DSP_REG_N},{PPI,PPIC,HEX_8,HEX_9,HEX_1}, arch_sh4al_dsp_up},
|
921 | fdf9b3e8 | bellard | /* 10101000xxyynnnn pabs <DSP_REG_Y>,<DSP_REG_N> */
|
922 | fdf9b3e8 | bellard | {"pabs", {DSP_REG_Y,DSP_REG_N},{PPI,PPI3NC,HEX_A,HEX_8}, arch_sh_dsp_up},
|
923 | fdf9b3e8 | bellard | /* 1010100!01yynnnn pabs <DSP_REG_Y>,<DSP_REG_N> */
|
924 | fdf9b3e8 | bellard | {"pabs", {DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_A,HEX_9,HEX_4}, arch_sh4al_dsp_up},
|
925 | fdf9b3e8 | bellard | /* 10011000xxyynnnn prnd <DSP_REG_X>,<DSP_REG_N> */
|
926 | fdf9b3e8 | bellard | {"prnd", {DSP_REG_X,DSP_REG_N},{PPI,PPI3NC,HEX_9,HEX_8}, arch_sh_dsp_up},
|
927 | fdf9b3e8 | bellard | /* 1001100!xx01nnnn prnd <DSP_REG_X>,<DSP_REG_N> */
|
928 | fdf9b3e8 | bellard | {"prnd", {DSP_REG_X,DSP_REG_N},{PPI,PPIC,HEX_9,HEX_9,HEX_1}, arch_sh4al_dsp_up},
|
929 | fdf9b3e8 | bellard | /* 10111000xxyynnnn prnd <DSP_REG_Y>,<DSP_REG_N> */
|
930 | fdf9b3e8 | bellard | {"prnd", {DSP_REG_Y,DSP_REG_N},{PPI,PPI3NC,HEX_B,HEX_8}, arch_sh_dsp_up},
|
931 | fdf9b3e8 | bellard | /* 1011100!01yynnnn prnd <DSP_REG_Y>,<DSP_REG_N> */
|
932 | fdf9b3e8 | bellard | {"prnd", {DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_B,HEX_9,HEX_4}, arch_sh4al_dsp_up},
|
933 | fdf9b3e8 | bellard | |
934 | fdf9b3e8 | bellard | {"dct",{0},{PPI,PDC,HEX_1}, arch_sh_dsp_up}, |
935 | fdf9b3e8 | bellard | {"dcf",{0},{PPI,PDC,HEX_2}, arch_sh_dsp_up}, |
936 | fdf9b3e8 | bellard | |
937 | fdf9b3e8 | bellard | /* 10000001xxyynnnn pshl <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> */
|
938 | fdf9b3e8 | bellard | {"pshl", {DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_8,HEX_1}, arch_sh_dsp_up},
|
939 | fdf9b3e8 | bellard | /* 00000iiiiiiinnnn pshl #<imm>,<DSP_REG_N> */ {"pshl",{A_IMM,DSP_REG_N},{PPI,PSH,HEX_0}, arch_sh_dsp_up}, |
940 | fdf9b3e8 | bellard | /* 10010001xxyynnnn psha <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> */
|
941 | fdf9b3e8 | bellard | {"psha", {DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_9,HEX_1}, arch_sh_dsp_up},
|
942 | fdf9b3e8 | bellard | /* 00010iiiiiiinnnn psha #<imm>,<DSP_REG_N> */ {"psha",{A_IMM,DSP_REG_N},{PPI,PSH,HEX_1}, arch_sh_dsp_up}, |
943 | fdf9b3e8 | bellard | /* 10100001xxyynnnn psub <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> */
|
944 | fdf9b3e8 | bellard | {"psub", {DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_A,HEX_1}, arch_sh_dsp_up},
|
945 | fdf9b3e8 | bellard | /* 10000101xxyynnnn psub <DSP_REG_Y>,<DSP_REG_X>,<DSP_REG_N> */
|
946 | fdf9b3e8 | bellard | {"psub", {DSP_REG_Y,DSP_REG_X,DSP_REG_N},{PPI,PPIC,HEX_8,HEX_5}, arch_sh4al_dsp_up},
|
947 | fdf9b3e8 | bellard | /* 10110001xxyynnnn padd <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> */
|
948 | fdf9b3e8 | bellard | {"padd", {DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_B,HEX_1}, arch_sh_dsp_up},
|
949 | fdf9b3e8 | bellard | /* 10010101xxyynnnn pand <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> */
|
950 | fdf9b3e8 | bellard | {"pand", {DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_9,HEX_5}, arch_sh_dsp_up},
|
951 | fdf9b3e8 | bellard | /* 10100101xxyynnnn pxor <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> */
|
952 | fdf9b3e8 | bellard | {"pxor", {DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_A,HEX_5}, arch_sh_dsp_up},
|
953 | fdf9b3e8 | bellard | /* 10110101xxyynnnn por <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> */
|
954 | fdf9b3e8 | bellard | {"por", {DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_B,HEX_5}, arch_sh_dsp_up},
|
955 | fdf9b3e8 | bellard | /* 10001001xxyynnnn pdec <DSP_REG_X>,<DSP_REG_N> */
|
956 | fdf9b3e8 | bellard | {"pdec", {DSP_REG_X,DSP_REG_N},{PPI,PPIC,HEX_8,HEX_9}, arch_sh_dsp_up},
|
957 | fdf9b3e8 | bellard | /* 10101001xxyynnnn pdec <DSP_REG_Y>,<DSP_REG_N> */
|
958 | fdf9b3e8 | bellard | {"pdec", {DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_A,HEX_9}, arch_sh_dsp_up},
|
959 | fdf9b3e8 | bellard | /* 10011001xx00nnnn pinc <DSP_REG_X>,<DSP_REG_N> */
|
960 | fdf9b3e8 | bellard | {"pinc", {DSP_REG_X,DSP_REG_N},{PPI,PPIC,HEX_9,HEX_9,HEX_XX00}, arch_sh_dsp_up},
|
961 | fdf9b3e8 | bellard | /* 1011100100yynnnn pinc <DSP_REG_Y>,<DSP_REG_N> */
|
962 | fdf9b3e8 | bellard | {"pinc", {DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_B,HEX_9,HEX_00YY}, arch_sh_dsp_up},
|
963 | fdf9b3e8 | bellard | /* 10001101xxyynnnn pclr <DSP_REG_N> */
|
964 | fdf9b3e8 | bellard | {"pclr", {DSP_REG_N},{PPI,PPIC,HEX_8,HEX_D}, arch_sh_dsp_up},
|
965 | fdf9b3e8 | bellard | /* 10011101xx00nnnn pdmsb <DSP_REG_X>,<DSP_REG_N> */
|
966 | fdf9b3e8 | bellard | {"pdmsb", {DSP_REG_X,DSP_REG_N},{PPI,PPIC,HEX_9,HEX_D,HEX_XX00}, arch_sh_dsp_up},
|
967 | fdf9b3e8 | bellard | /* 1011110100yynnnn pdmsb <DSP_REG_Y>,<DSP_REG_N> */
|
968 | fdf9b3e8 | bellard | {"pdmsb", {DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_B,HEX_D,HEX_00YY}, arch_sh_dsp_up},
|
969 | fdf9b3e8 | bellard | /* 11001001xxyynnnn pneg <DSP_REG_X>,<DSP_REG_N> */
|
970 | fdf9b3e8 | bellard | {"pneg", {DSP_REG_X,DSP_REG_N},{PPI,PPIC,HEX_C,HEX_9}, arch_sh_dsp_up},
|
971 | fdf9b3e8 | bellard | /* 11101001xxyynnnn pneg <DSP_REG_Y>,<DSP_REG_N> */
|
972 | fdf9b3e8 | bellard | {"pneg", {DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_E,HEX_9}, arch_sh_dsp_up},
|
973 | fdf9b3e8 | bellard | /* 11011001xxyynnnn pcopy <DSP_REG_X>,<DSP_REG_N> */
|
974 | fdf9b3e8 | bellard | {"pcopy", {DSP_REG_X,DSP_REG_N},{PPI,PPIC,HEX_D,HEX_9}, arch_sh_dsp_up},
|
975 | fdf9b3e8 | bellard | /* 11111001xxyynnnn pcopy <DSP_REG_Y>,<DSP_REG_N> */
|
976 | fdf9b3e8 | bellard | {"pcopy", {DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_F,HEX_9}, arch_sh_dsp_up},
|
977 | fdf9b3e8 | bellard | /* 11001101xxyynnnn psts MACH,<DSP_REG_N> */
|
978 | fdf9b3e8 | bellard | {"psts", {A_MACH,DSP_REG_N},{PPI,PPIC,HEX_C,HEX_D}, arch_sh_dsp_up},
|
979 | fdf9b3e8 | bellard | /* 11011101xxyynnnn psts MACL,<DSP_REG_N> */
|
980 | fdf9b3e8 | bellard | {"psts", {A_MACL,DSP_REG_N},{PPI,PPIC,HEX_D,HEX_D}, arch_sh_dsp_up},
|
981 | fdf9b3e8 | bellard | /* 11101101xxyynnnn plds <DSP_REG_N>,MACH */
|
982 | fdf9b3e8 | bellard | {"plds", {DSP_REG_N,A_MACH},{PPI,PPIC,HEX_E,HEX_D}, arch_sh_dsp_up},
|
983 | fdf9b3e8 | bellard | /* 11111101xxyynnnn plds <DSP_REG_N>,MACL */
|
984 | fdf9b3e8 | bellard | {"plds", {DSP_REG_N,A_MACL},{PPI,PPIC,HEX_F,HEX_D}, arch_sh_dsp_up},
|
985 | fdf9b3e8 | bellard | /* 10011101xx01zzzz pswap <DSP_REG_X>,<DSP_REG_N> */
|
986 | fdf9b3e8 | bellard | {"pswap", {DSP_REG_X,DSP_REG_N},{PPI,PPIC,HEX_9,HEX_D,HEX_1}, arch_sh4al_dsp_up},
|
987 | fdf9b3e8 | bellard | /* 1011110101yyzzzz pswap <DSP_REG_Y>,<DSP_REG_N> */
|
988 | fdf9b3e8 | bellard | {"pswap", {DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_B,HEX_D,HEX_4}, arch_sh4al_dsp_up},
|
989 | fdf9b3e8 | bellard | |
990 | fdf9b3e8 | bellard | /* 1111nnnn01011101 fabs <F_REG_N> */{"fabs",{F_REG_N},{HEX_F,REG_N,HEX_5,HEX_D}, arch_sh2e_up}, |
991 | fdf9b3e8 | bellard | /* 1111nnn001011101 fabs <D_REG_N> */{"fabs",{D_REG_N},{HEX_F,REG_N,HEX_5,HEX_D}, arch_sh4_up | arch_sh2a_up}, |
992 | fdf9b3e8 | bellard | |
993 | fdf9b3e8 | bellard | /* 1111nnnnmmmm0000 fadd <F_REG_M>,<F_REG_N>*/{"fadd",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_0}, arch_sh2e_up}, |
994 | fdf9b3e8 | bellard | /* 1111nnn0mmm00000 fadd <D_REG_M>,<D_REG_N>*/{"fadd",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_0}, arch_sh4_up | arch_sh2a_up}, |
995 | fdf9b3e8 | bellard | |
996 | fdf9b3e8 | bellard | /* 1111nnnnmmmm0100 fcmp/eq <F_REG_M>,<F_REG_N>*/{"fcmp/eq",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_4}, arch_sh2e_up}, |
997 | fdf9b3e8 | bellard | /* 1111nnn0mmm00100 fcmp/eq <D_REG_M>,<D_REG_N>*/{"fcmp/eq",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_4}, arch_sh4_up | arch_sh2a_up}, |
998 | fdf9b3e8 | bellard | |
999 | fdf9b3e8 | bellard | /* 1111nnnnmmmm0101 fcmp/gt <F_REG_M>,<F_REG_N>*/{"fcmp/gt",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_5}, arch_sh2e_up}, |
1000 | fdf9b3e8 | bellard | /* 1111nnn0mmm00101 fcmp/gt <D_REG_M>,<D_REG_N>*/{"fcmp/gt",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_5}, arch_sh4_up | arch_sh2a_up}, |
1001 | fdf9b3e8 | bellard | |
1002 | fdf9b3e8 | bellard | /* 1111nnn010111101 fcnvds <D_REG_N>,FPUL*/{"fcnvds",{D_REG_N,FPUL_M},{HEX_F,REG_N_D,HEX_B,HEX_D}, arch_sh4_up | arch_sh2a_up}, |
1003 | fdf9b3e8 | bellard | |
1004 | fdf9b3e8 | bellard | /* 1111nnn010101101 fcnvsd FPUL,<D_REG_N>*/{"fcnvsd",{FPUL_M,D_REG_N},{HEX_F,REG_N_D,HEX_A,HEX_D}, arch_sh4_up | arch_sh2a_up}, |
1005 | fdf9b3e8 | bellard | |
1006 | fdf9b3e8 | bellard | /* 1111nnnnmmmm0011 fdiv <F_REG_M>,<F_REG_N>*/{"fdiv",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_3}, arch_sh2e_up}, |
1007 | fdf9b3e8 | bellard | /* 1111nnn0mmm00011 fdiv <D_REG_M>,<D_REG_N>*/{"fdiv",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_3}, arch_sh4_up | arch_sh2a_up}, |
1008 | fdf9b3e8 | bellard | |
1009 | fdf9b3e8 | bellard | /* 1111nnmm11101101 fipr <V_REG_M>,<V_REG_N>*/{"fipr",{V_REG_M,V_REG_N},{HEX_F,REG_NM,HEX_E,HEX_D}, arch_sh4_up}, |
1010 | fdf9b3e8 | bellard | |
1011 | fdf9b3e8 | bellard | /* 1111nnnn10001101 fldi0 <F_REG_N> */{"fldi0",{F_REG_N},{HEX_F,REG_N,HEX_8,HEX_D}, arch_sh2e_up}, |
1012 | fdf9b3e8 | bellard | |
1013 | fdf9b3e8 | bellard | /* 1111nnnn10011101 fldi1 <F_REG_N> */{"fldi1",{F_REG_N},{HEX_F,REG_N,HEX_9,HEX_D}, arch_sh2e_up}, |
1014 | fdf9b3e8 | bellard | |
1015 | fdf9b3e8 | bellard | /* 1111nnnn00011101 flds <F_REG_N>,FPUL*/{"flds",{F_REG_N,FPUL_M},{HEX_F,REG_N,HEX_1,HEX_D}, arch_sh2e_up}, |
1016 | fdf9b3e8 | bellard | |
1017 | fdf9b3e8 | bellard | /* 1111nnnn00101101 float FPUL,<F_REG_N>*/{"float",{FPUL_M,F_REG_N},{HEX_F,REG_N,HEX_2,HEX_D}, arch_sh2e_up}, |
1018 | fdf9b3e8 | bellard | /* 1111nnn000101101 float FPUL,<D_REG_N>*/{"float",{FPUL_M,D_REG_N},{HEX_F,REG_N,HEX_2,HEX_D}, arch_sh4_up | arch_sh2a_up}, |
1019 | fdf9b3e8 | bellard | |
1020 | fdf9b3e8 | bellard | /* 1111nnnnmmmm1110 fmac FR0,<F_REG_M>,<F_REG_N>*/{"fmac",{F_FR0,F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_E}, arch_sh2e_up}, |
1021 | fdf9b3e8 | bellard | |
1022 | fdf9b3e8 | bellard | /* 1111nnnnmmmm1100 fmov <F_REG_M>,<F_REG_N>*/{"fmov",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_C}, arch_sh2e_up}, |
1023 | fdf9b3e8 | bellard | /* 1111nnn1mmmm1100 fmov <DX_REG_M>,<DX_REG_N>*/{"fmov",{DX_REG_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_C}, arch_sh4_up | arch_sh2a_up}, |
1024 | fdf9b3e8 | bellard | |
1025 | fdf9b3e8 | bellard | /* 1111nnnnmmmm1000 fmov @<REG_M>,<F_REG_N>*/{"fmov",{A_IND_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_8}, arch_sh2e_up}, |
1026 | fdf9b3e8 | bellard | /* 1111nnn1mmmm1000 fmov @<REG_M>,<DX_REG_N>*/{"fmov",{A_IND_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_8}, arch_sh4_up | arch_sh2a_up}, |
1027 | fdf9b3e8 | bellard | |
1028 | fdf9b3e8 | bellard | /* 1111nnnnmmmm1010 fmov <F_REG_M>,@<REG_N>*/{"fmov",{F_REG_M,A_IND_N},{HEX_F,REG_N,REG_M,HEX_A}, arch_sh2e_up}, |
1029 | fdf9b3e8 | bellard | /* 1111nnnnmmm11010 fmov <DX_REG_M>,@<REG_N>*/{"fmov",{DX_REG_M,A_IND_N},{HEX_F,REG_N,REG_M,HEX_A}, arch_sh4_up | arch_sh2a_up}, |
1030 | fdf9b3e8 | bellard | |
1031 | fdf9b3e8 | bellard | /* 1111nnnnmmmm1001 fmov @<REG_M>+,<F_REG_N>*/{"fmov",{A_INC_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_9}, arch_sh2e_up}, |
1032 | fdf9b3e8 | bellard | /* 1111nnn1mmmm1001 fmov @<REG_M>+,<DX_REG_N>*/{"fmov",{A_INC_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_9}, arch_sh4_up | arch_sh2a_up}, |
1033 | fdf9b3e8 | bellard | |
1034 | fdf9b3e8 | bellard | /* 1111nnnnmmmm1011 fmov <F_REG_M>,@-<REG_N>*/{"fmov",{F_REG_M,A_DEC_N},{HEX_F,REG_N,REG_M,HEX_B}, arch_sh2e_up}, |
1035 | fdf9b3e8 | bellard | /* 1111nnnnmmm11011 fmov <DX_REG_M>,@-<REG_N>*/{"fmov",{DX_REG_M,A_DEC_N},{HEX_F,REG_N,REG_M,HEX_B}, arch_sh4_up | arch_sh2a_up}, |
1036 | fdf9b3e8 | bellard | |
1037 | fdf9b3e8 | bellard | /* 1111nnnnmmmm0110 fmov @(R0,<REG_M>),<F_REG_N>*/{"fmov",{A_IND_R0_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_6}, arch_sh2e_up}, |
1038 | fdf9b3e8 | bellard | /* 1111nnn1mmmm0110 fmov @(R0,<REG_M>),<DX_REG_N>*/{"fmov",{A_IND_R0_REG_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_6}, arch_sh4_up | arch_sh2a_up}, |
1039 | fdf9b3e8 | bellard | |
1040 | fdf9b3e8 | bellard | /* 1111nnnnmmmm0111 fmov <F_REG_M>,@(R0,<REG_N>)*/{"fmov",{F_REG_M,A_IND_R0_REG_N},{HEX_F,REG_N,REG_M,HEX_7}, arch_sh2e_up}, |
1041 | fdf9b3e8 | bellard | /* 1111nnnnmmm10111 fmov <DX_REG_M>,@(R0,<REG_N>)*/{"fmov",{DX_REG_M,A_IND_R0_REG_N},{HEX_F,REG_N,REG_M,HEX_7}, arch_sh4_up | arch_sh2a_up}, |
1042 | fdf9b3e8 | bellard | |
1043 | fdf9b3e8 | bellard | /* 1111nnn1mmmm1000 fmov.d @<REG_M>,<DX_REG_N>*/{"fmov.d",{A_IND_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_8}, arch_sh4_up | arch_sh2a_up}, |
1044 | fdf9b3e8 | bellard | |
1045 | fdf9b3e8 | bellard | /* 1111nnnnmmm11010 fmov.d <DX_REG_M>,@<REG_N>*/{"fmov.d",{DX_REG_M,A_IND_N},{HEX_F,REG_N,REG_M,HEX_A}, arch_sh4_up | arch_sh2a_up}, |
1046 | fdf9b3e8 | bellard | |
1047 | fdf9b3e8 | bellard | /* 1111nnn1mmmm1001 fmov.d @<REG_M>+,<DX_REG_N>*/{"fmov.d",{A_INC_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_9}, arch_sh4_up | arch_sh2a_up}, |
1048 | fdf9b3e8 | bellard | |
1049 | fdf9b3e8 | bellard | /* 1111nnnnmmm11011 fmov.d <DX_REG_M>,@-<REG_N>*/{"fmov.d",{DX_REG_M,A_DEC_N},{HEX_F,REG_N,REG_M,HEX_B}, arch_sh4_up | arch_sh2a_up}, |
1050 | fdf9b3e8 | bellard | |
1051 | fdf9b3e8 | bellard | /* 1111nnn1mmmm0110 fmov.d @(R0,<REG_M>),<DX_REG_N>*/{"fmov.d",{A_IND_R0_REG_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_6}, arch_sh4_up | arch_sh2a_up}, |
1052 | fdf9b3e8 | bellard | |
1053 | fdf9b3e8 | bellard | /* 1111nnnnmmm10111 fmov.d <DX_REG_M>,@(R0,<REG_N>)*/{"fmov.d",{DX_REG_M,A_IND_R0_REG_N},{HEX_F,REG_N,REG_M,HEX_7}, arch_sh4_up | arch_sh2a_up}, |
1054 | fdf9b3e8 | bellard | /* 0011nnnnmmmm0001 0011dddddddddddd fmov.d <F_REG_M>,@(<DISP12>,<REG_N>) */
|
1055 | fdf9b3e8 | bellard | {"fmov.d",{DX_REG_M,A_DISP_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_3,DISP1_12BY8}, arch_sh2a_up | arch_op32},
|
1056 | fdf9b3e8 | bellard | /* 0011nnnnmmmm0001 0111dddddddddddd fmov.d @(<DISP12>,<REG_M>),F_REG_N */
|
1057 | fdf9b3e8 | bellard | {"fmov.d",{A_DISP_REG_M,DX_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_7,DISP0_12BY8}, arch_sh2a_up | arch_op32},
|
1058 | fdf9b3e8 | bellard | |
1059 | fdf9b3e8 | bellard | /* 1111nnnnmmmm1000 fmov.s @<REG_M>,<F_REG_N>*/{"fmov.s",{A_IND_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_8}, arch_sh2e_up}, |
1060 | fdf9b3e8 | bellard | |
1061 | fdf9b3e8 | bellard | /* 1111nnnnmmmm1010 fmov.s <F_REG_M>,@<REG_N>*/{"fmov.s",{F_REG_M,A_IND_N},{HEX_F,REG_N,REG_M,HEX_A}, arch_sh2e_up}, |
1062 | fdf9b3e8 | bellard | |
1063 | fdf9b3e8 | bellard | /* 1111nnnnmmmm1001 fmov.s @<REG_M>+,<F_REG_N>*/{"fmov.s",{A_INC_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_9}, arch_sh2e_up}, |
1064 | fdf9b3e8 | bellard | |
1065 | fdf9b3e8 | bellard | /* 1111nnnnmmmm1011 fmov.s <F_REG_M>,@-<REG_N>*/{"fmov.s",{F_REG_M,A_DEC_N},{HEX_F,REG_N,REG_M,HEX_B}, arch_sh2e_up}, |
1066 | fdf9b3e8 | bellard | |
1067 | fdf9b3e8 | bellard | /* 1111nnnnmmmm0110 fmov.s @(R0,<REG_M>),<F_REG_N>*/{"fmov.s",{A_IND_R0_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_6}, arch_sh2e_up}, |
1068 | fdf9b3e8 | bellard | |
1069 | fdf9b3e8 | bellard | /* 1111nnnnmmmm0111 fmov.s <F_REG_M>,@(R0,<REG_N>)*/{"fmov.s",{F_REG_M,A_IND_R0_REG_N},{HEX_F,REG_N,REG_M,HEX_7}, arch_sh2e_up}, |
1070 | fdf9b3e8 | bellard | /* 0011nnnnmmmm0001 0011dddddddddddd fmov.s <F_REG_M>,@(<DISP12>,<REG_N>) */
|
1071 | fdf9b3e8 | bellard | {"fmov.s",{F_REG_M,A_DISP_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_3,DISP1_12BY4}, arch_sh2a_up | arch_op32},
|
1072 | fdf9b3e8 | bellard | /* 0011nnnnmmmm0001 0111dddddddddddd fmov.s @(<DISP12>,<REG_M>),F_REG_N */
|
1073 | fdf9b3e8 | bellard | {"fmov.s",{A_DISP_REG_M,F_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_7,DISP0_12BY4}, arch_sh2a_up | arch_op32},
|
1074 | fdf9b3e8 | bellard | |
1075 | fdf9b3e8 | bellard | /* 1111nnnnmmmm0010 fmul <F_REG_M>,<F_REG_N>*/{"fmul",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_2}, arch_sh2e_up}, |
1076 | fdf9b3e8 | bellard | /* 1111nnn0mmm00010 fmul <D_REG_M>,<D_REG_N>*/{"fmul",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_2}, arch_sh4_up | arch_sh2a_up}, |
1077 | fdf9b3e8 | bellard | |
1078 | fdf9b3e8 | bellard | /* 1111nnnn01001101 fneg <F_REG_N> */{"fneg",{F_REG_N},{HEX_F,REG_N,HEX_4,HEX_D}, arch_sh2e_up}, |
1079 | fdf9b3e8 | bellard | /* 1111nnn001001101 fneg <D_REG_N> */{"fneg",{D_REG_N},{HEX_F,REG_N,HEX_4,HEX_D}, arch_sh4_up | arch_sh2a_up}, |
1080 | fdf9b3e8 | bellard | |
1081 | fdf9b3e8 | bellard | /* 1111011111111101 fpchg */{"fpchg",{0},{HEX_F,HEX_7,HEX_F,HEX_D}, arch_sh4a_up}, |
1082 | fdf9b3e8 | bellard | |
1083 | fdf9b3e8 | bellard | /* 1111101111111101 frchg */{"frchg",{0},{HEX_F,HEX_B,HEX_F,HEX_D}, arch_sh4_up}, |
1084 | fdf9b3e8 | bellard | |
1085 | fdf9b3e8 | bellard | /* 1111nnn011111101 fsca FPUL,<D_REG_N> */{"fsca",{FPUL_M,D_REG_N},{HEX_F,REG_N_D,HEX_F,HEX_D}, arch_sh4_up}, |
1086 | fdf9b3e8 | bellard | |
1087 | fdf9b3e8 | bellard | /* 1111001111111101 fschg */{"fschg",{0},{HEX_F,HEX_3,HEX_F,HEX_D}, arch_sh4_up | arch_sh2a_up}, |
1088 | fdf9b3e8 | bellard | |
1089 | fdf9b3e8 | bellard | /* 1111nnnn01101101 fsqrt <F_REG_N> */{"fsqrt",{F_REG_N},{HEX_F,REG_N,HEX_6,HEX_D}, arch_sh3e_up | arch_sh2a_up}, |
1090 | fdf9b3e8 | bellard | /* 1111nnn001101101 fsqrt <D_REG_N> */{"fsqrt",{D_REG_N},{HEX_F,REG_N,HEX_6,HEX_D}, arch_sh4_up | arch_sh2a_up}, |
1091 | fdf9b3e8 | bellard | |
1092 | fdf9b3e8 | bellard | /* 1111nnnn01111101 fsrra <F_REG_N> */{"fsrra",{F_REG_N},{HEX_F,REG_N,HEX_7,HEX_D}, arch_sh4_up}, |
1093 | fdf9b3e8 | bellard | |
1094 | fdf9b3e8 | bellard | /* 1111nnnn00001101 fsts FPUL,<F_REG_N>*/{"fsts",{FPUL_M,F_REG_N},{HEX_F,REG_N,HEX_0,HEX_D}, arch_sh2e_up}, |
1095 | fdf9b3e8 | bellard | |
1096 | fdf9b3e8 | bellard | /* 1111nnnnmmmm0001 fsub <F_REG_M>,<F_REG_N>*/{"fsub",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_1}, arch_sh2e_up}, |
1097 | fdf9b3e8 | bellard | /* 1111nnn0mmm00001 fsub <D_REG_M>,<D_REG_N>*/{"fsub",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_1}, arch_sh4_up | arch_sh2a_up}, |
1098 | fdf9b3e8 | bellard | |
1099 | fdf9b3e8 | bellard | /* 1111nnnn00111101 ftrc <F_REG_N>,FPUL*/{"ftrc",{F_REG_N,FPUL_M},{HEX_F,REG_N,HEX_3,HEX_D}, arch_sh2e_up}, |
1100 | fdf9b3e8 | bellard | /* 1111nnnn00111101 ftrc <D_REG_N>,FPUL*/{"ftrc",{D_REG_N,FPUL_M},{HEX_F,REG_N,HEX_3,HEX_D}, arch_sh4_up | arch_sh2a_up}, |
1101 | fdf9b3e8 | bellard | |
1102 | fdf9b3e8 | bellard | /* 1111nn0111111101 ftrv XMTRX_M4,<V_REG_n>*/{"ftrv",{XMTRX_M4,V_REG_N},{HEX_F,REG_N_B01,HEX_F,HEX_D}, arch_sh4_up}, |
1103 | fdf9b3e8 | bellard | |
1104 | fdf9b3e8 | bellard | /* 10000110nnnn0iii bclr #<imm>, <REG_N> */ {"bclr",{A_IMM, A_REG_N},{HEX_8,HEX_6,REG_N,IMM0_3c}, arch_sh2a_nofpu_up}, |
1105 | fdf9b3e8 | bellard | /* 0011nnnn0iii1001 0000dddddddddddd bclr.b #<imm>,@(<DISP12>,<REG_N>) */
|
1106 | fdf9b3e8 | bellard | {"bclr.b",{A_IMM,A_DISP_REG_N},{HEX_3,REG_N,IMM0_3Uc,HEX_9,HEX_0,DISP1_12}, arch_sh2a_nofpu_up | arch_op32},
|
1107 | fdf9b3e8 | bellard | /* 10000111nnnn1iii bld #<imm>, <REG_N> */ {"bld",{A_IMM, A_REG_N},{HEX_8,HEX_7,REG_N,IMM0_3s}, arch_sh2a_nofpu_up}, |
1108 | fdf9b3e8 | bellard | /* 0011nnnn0iii1001 0011dddddddddddd bld.b #<imm>,@(<DISP12>,<REG_N>) */
|
1109 | fdf9b3e8 | bellard | {"bld.b",{A_IMM,A_DISP_REG_N},{HEX_3,REG_N,IMM0_3Uc,HEX_9,HEX_3,DISP1_12}, arch_sh2a_nofpu_up | arch_op32},
|
1110 | fdf9b3e8 | bellard | /* 10000110nnnn1iii bset #<imm>, <REG_N> */ {"bset",{A_IMM, A_REG_N},{HEX_8,HEX_6,REG_N,IMM0_3s}, arch_sh2a_nofpu_up}, |
1111 | fdf9b3e8 | bellard | /* 0011nnnn0iii1001 0001dddddddddddd bset.b #<imm>,@(<DISP12>,<REG_N>) */
|
1112 | fdf9b3e8 | bellard | {"bset.b",{A_IMM,A_DISP_REG_N},{HEX_3,REG_N,IMM0_3Uc,HEX_9,HEX_1,DISP1_12}, arch_sh2a_nofpu_up | arch_op32},
|
1113 | fdf9b3e8 | bellard | /* 10000111nnnn0iii bst #<imm>, <REG_N> */ {"bst",{A_IMM, A_REG_N},{HEX_8,HEX_7,REG_N,IMM0_3c}, arch_sh2a_nofpu_up}, |
1114 | fdf9b3e8 | bellard | /* 0011nnnn0iii1001 0010dddddddddddd bst.b #<imm>,@(<DISP12>,<REG_N>) */
|
1115 | fdf9b3e8 | bellard | {"bst.b",{A_IMM,A_DISP_REG_N},{HEX_3,REG_N,IMM0_3Uc,HEX_9,HEX_2,DISP1_12}, arch_sh2a_nofpu_up | arch_op32},
|
1116 | fdf9b3e8 | bellard | /* 0100nnnn10010001 clips.b <REG_N> */ {"clips.b",{A_REG_N},{HEX_4,REG_N,HEX_9,HEX_1}, arch_sh2a_nofpu_up}, |
1117 | fdf9b3e8 | bellard | /* 0100nnnn10010101 clips.w <REG_N> */ {"clips.w",{A_REG_N},{HEX_4,REG_N,HEX_9,HEX_5}, arch_sh2a_nofpu_up}, |
1118 | fdf9b3e8 | bellard | /* 0100nnnn10000001 clipu.b <REG_N> */ {"clipu.b",{A_REG_N},{HEX_4,REG_N,HEX_8,HEX_1}, arch_sh2a_nofpu_up}, |
1119 | fdf9b3e8 | bellard | /* 0100nnnn10000101 clipu.w <REG_N> */ {"clipu.w",{A_REG_N},{HEX_4,REG_N,HEX_8,HEX_5}, arch_sh2a_nofpu_up}, |
1120 | fdf9b3e8 | bellard | /* 0100nnnn10010100 divs R0,<REG_N> */ {"divs",{A_R0,A_REG_N},{HEX_4,REG_N,HEX_9,HEX_4}, arch_sh2a_nofpu_up}, |
1121 | fdf9b3e8 | bellard | /* 0100nnnn10000100 divu R0,<REG_N> */ {"divu",{A_R0,A_REG_N},{HEX_4,REG_N,HEX_8,HEX_4}, arch_sh2a_nofpu_up}, |
1122 | fdf9b3e8 | bellard | /* 0100mmmm01001011 jsr/n @<REG_M> */ {"jsr/n",{A_IND_M},{HEX_4,REG_M,HEX_4,HEX_B}, arch_sh2a_nofpu_up}, |
1123 | fdf9b3e8 | bellard | /* 10000011dddddddd jsr/n @@(<disp>,TBR) */ {"jsr/n",{A_DISP2_TBR},{HEX_8,HEX_3,IMM0_8BY4}, arch_sh2a_nofpu_up}, |
1124 | fdf9b3e8 | bellard | /* 0100mmmm11100101 ldbank @<REG_M>,R0 */ {"ldbank",{A_IND_M,A_R0},{HEX_4,REG_M,HEX_E,HEX_5}, arch_sh2a_nofpu_up}, |
1125 | fdf9b3e8 | bellard | /* 0100mmmm11110001 movml.l <REG_M>,@-R15 */ {"movml.l",{A_REG_M,A_DEC_R15},{HEX_4,REG_M,HEX_F,HEX_1}, arch_sh2a_nofpu_up}, |
1126 | fdf9b3e8 | bellard | /* 0100mmmm11110101 movml.l @R15+,<REG_M> */ {"movml.l",{A_INC_R15,A_REG_M},{HEX_4,REG_M,HEX_F,HEX_5}, arch_sh2a_nofpu_up}, |
1127 | fdf9b3e8 | bellard | /* 0100mmmm11110000 movml.l <REG_M>,@-R15 */ {"movmu.l",{A_REG_M,A_DEC_R15},{HEX_4,REG_M,HEX_F,HEX_0}, arch_sh2a_nofpu_up}, |
1128 | fdf9b3e8 | bellard | /* 0100mmmm11110100 movml.l @R15+,<REG_M> */ {"movmu.l",{A_INC_R15,A_REG_M},{HEX_4,REG_M,HEX_F,HEX_4}, arch_sh2a_nofpu_up}, |
1129 | fdf9b3e8 | bellard | /* 0000nnnn00111001 movrt <REG_N> */ {"movrt",{A_REG_N},{HEX_0,REG_N,HEX_3,HEX_9}, arch_sh2a_nofpu_up}, |
1130 | fdf9b3e8 | bellard | /* 0100nnnn10000000 mulr R0,<REG_N> */ {"mulr",{A_R0,A_REG_N},{HEX_4,REG_N,HEX_8,HEX_0}, arch_sh2a_nofpu_up}, |
1131 | fdf9b3e8 | bellard | /* 0000000001101000 nott */ {"nott",{A_END},{HEX_0,HEX_0,HEX_6,HEX_8}, arch_sh2a_nofpu_up}, |
1132 | fdf9b3e8 | bellard | /* 0000000001011011 resbank */ {"resbank",{A_END},{HEX_0,HEX_0,HEX_5,HEX_B}, arch_sh2a_nofpu_up}, |
1133 | fdf9b3e8 | bellard | /* 0000000001101011 rts/n */ {"rts/n",{A_END},{HEX_0,HEX_0,HEX_6,HEX_B}, arch_sh2a_nofpu_up}, |
1134 | fdf9b3e8 | bellard | /* 0000mmmm01111011 rtv/n <REG_M>*/ {"rtv/n",{A_REG_M},{HEX_0,REG_M,HEX_7,HEX_B}, arch_sh2a_nofpu_up}, |
1135 | fdf9b3e8 | bellard | /* 0100nnnn11100001 stbank R0,@<REG_N>*/ {"stbank",{A_R0,A_IND_N},{HEX_4,REG_N,HEX_E,HEX_1}, arch_sh2a_nofpu_up}, |
1136 | fdf9b3e8 | bellard | |
1137 | fdf9b3e8 | bellard | /* 0011nnnn0iii1001 0100dddddddddddd band.b #<imm>,@(<DISP12>,<REG_N>) */
|
1138 | fdf9b3e8 | bellard | {"band.b",{A_IMM,A_DISP_REG_N},{HEX_3,REG_N,IMM0_3Uc,HEX_9,HEX_4,DISP1_12}, arch_sh2a_nofpu_up | arch_op32},
|
1139 | fdf9b3e8 | bellard | /* 0011nnnn0iii1001 1100dddddddddddd bandnot.b #<imm>,@(<DISP12>,<REG_N>) */
|
1140 | fdf9b3e8 | bellard | {"bandnot.b",{A_IMM,A_DISP_REG_N},{HEX_3,REG_N,IMM0_3Uc,HEX_9,HEX_C,DISP1_12}, arch_sh2a_nofpu_up | arch_op32},
|
1141 | fdf9b3e8 | bellard | /* 0011nnnn0iii1001 1011dddddddddddd bldnot.b #<imm>,@(<DISP12>,<REG_N>) */
|
1142 | fdf9b3e8 | bellard | {"bldnot.b",{A_IMM,A_DISP_REG_N},{HEX_3,REG_N,IMM0_3Uc,HEX_9,HEX_B,DISP1_12}, arch_sh2a_nofpu_up | arch_op32},
|
1143 | fdf9b3e8 | bellard | /* 0011nnnn0iii1001 0101dddddddddddd bor.b #<imm>,@(<DISP12>,<REG_N>) */
|
1144 | fdf9b3e8 | bellard | {"bor.b",{A_IMM,A_DISP_REG_N},{HEX_3,REG_N,IMM0_3Uc,HEX_9,HEX_5,DISP1_12}, arch_sh2a_nofpu_up | arch_op32},
|
1145 | fdf9b3e8 | bellard | /* 0011nnnn0iii1001 1101dddddddddddd bornot.b #<imm>,@(<DISP12>,<REG_N>) */
|
1146 | fdf9b3e8 | bellard | {"bornot.b",{A_IMM,A_DISP_REG_N},{HEX_3,REG_N,IMM0_3Uc,HEX_9,HEX_D,DISP1_12}, arch_sh2a_nofpu_up | arch_op32},
|
1147 | fdf9b3e8 | bellard | /* 0011nnnn0iii1001 0110dddddddddddd bxor.b #<imm>,@(<DISP12>,<REG_N>) */
|
1148 | fdf9b3e8 | bellard | {"bxor.b",{A_IMM,A_DISP_REG_N},{HEX_3,REG_N,IMM0_3Uc,HEX_9,HEX_6,DISP1_12}, arch_sh2a_nofpu_up | arch_op32},
|
1149 | fdf9b3e8 | bellard | /* 0000nnnniiii0000 iiiiiiiiiiiiiiii movi20 #<imm>,<REG_N> */
|
1150 | fdf9b3e8 | bellard | {"movi20",{A_IMM,A_REG_N},{HEX_0,REG_N,IMM0_20_4,HEX_0,IMM0_20}, arch_sh2a_nofpu_up | arch_op32},
|
1151 | fdf9b3e8 | bellard | /* 0000nnnniiii0001 iiiiiiiiiiiiiiii movi20s #<imm>,<REG_N> */
|
1152 | fdf9b3e8 | bellard | {"movi20s",{A_IMM,A_REG_N},{HEX_0,REG_N,IMM0_20_4,HEX_1,IMM0_20BY8}, arch_sh2a_nofpu_up | arch_op32},
|
1153 | fdf9b3e8 | bellard | /* 0011nnnnmmmm0001 1000dddddddddddd movu.b @(<DISP12>,<REG_M>),<REG_N> */
|
1154 | fdf9b3e8 | bellard | {"movu.b",{A_DISP_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_8,DISP0_12}, arch_sh2a_nofpu_up | arch_op32},
|
1155 | fdf9b3e8 | bellard | /* 0011nnnnmmmm0001 1001dddddddddddd movu.w @(<DISP12>,<REG_M>),<REG_N> */
|
1156 | fdf9b3e8 | bellard | {"movu.w",{A_DISP_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_9,DISP0_12BY2}, arch_sh2a_nofpu_up | arch_op32},
|
1157 | fdf9b3e8 | bellard | |
1158 | fdf9b3e8 | bellard | { 0, {0}, {0}, 0 } |
1159 | fdf9b3e8 | bellard | }; |
1160 | fdf9b3e8 | bellard | |
1161 | fdf9b3e8 | bellard | #endif
|
1162 | fdf9b3e8 | bellard | |
1163 | fdf9b3e8 | bellard | #ifdef ARCH_all
|
1164 | fdf9b3e8 | bellard | #define INCLUDE_SHMEDIA
|
1165 | fdf9b3e8 | bellard | #endif
|
1166 | fdf9b3e8 | bellard | |
1167 | fdf9b3e8 | bellard | static void print_movxy |
1168 | fdf9b3e8 | bellard | PARAMS ((const sh_opcode_info *, int, int, fprintf_ftype, void *)); |
1169 | fdf9b3e8 | bellard | static void print_insn_ddt PARAMS ((int, struct disassemble_info *)); |
1170 | fdf9b3e8 | bellard | static void print_dsp_reg PARAMS ((int, fprintf_ftype, void *)); |
1171 | fdf9b3e8 | bellard | static void print_insn_ppi PARAMS ((int, struct disassemble_info *)); |
1172 | fdf9b3e8 | bellard | |
1173 | fdf9b3e8 | bellard | static void |
1174 | fdf9b3e8 | bellard | print_movxy (op, rn, rm, fprintf_fn, stream) |
1175 | fdf9b3e8 | bellard | const sh_opcode_info *op;
|
1176 | fdf9b3e8 | bellard | int rn, rm;
|
1177 | fdf9b3e8 | bellard | fprintf_ftype fprintf_fn; |
1178 | fdf9b3e8 | bellard | void *stream;
|
1179 | fdf9b3e8 | bellard | { |
1180 | fdf9b3e8 | bellard | int n;
|
1181 | fdf9b3e8 | bellard | |
1182 | fdf9b3e8 | bellard | fprintf_fn (stream, "%s\t", op->name);
|
1183 | fdf9b3e8 | bellard | for (n = 0; n < 2; n++) |
1184 | fdf9b3e8 | bellard | { |
1185 | fdf9b3e8 | bellard | switch (op->arg[n])
|
1186 | fdf9b3e8 | bellard | { |
1187 | fdf9b3e8 | bellard | case A_IND_N:
|
1188 | fdf9b3e8 | bellard | case AX_IND_N:
|
1189 | fdf9b3e8 | bellard | case AXY_IND_N:
|
1190 | fdf9b3e8 | bellard | case AY_IND_N:
|
1191 | fdf9b3e8 | bellard | case AYX_IND_N:
|
1192 | fdf9b3e8 | bellard | fprintf_fn (stream, "@r%d", rn);
|
1193 | fdf9b3e8 | bellard | break;
|
1194 | fdf9b3e8 | bellard | case A_INC_N:
|
1195 | fdf9b3e8 | bellard | case AX_INC_N:
|
1196 | fdf9b3e8 | bellard | case AXY_INC_N:
|
1197 | fdf9b3e8 | bellard | case AY_INC_N:
|
1198 | fdf9b3e8 | bellard | case AYX_INC_N:
|
1199 | fdf9b3e8 | bellard | fprintf_fn (stream, "@r%d+", rn);
|
1200 | fdf9b3e8 | bellard | break;
|
1201 | fdf9b3e8 | bellard | case AX_PMOD_N:
|
1202 | fdf9b3e8 | bellard | case AXY_PMOD_N:
|
1203 | fdf9b3e8 | bellard | fprintf_fn (stream, "@r%d+r8", rn);
|
1204 | fdf9b3e8 | bellard | break;
|
1205 | fdf9b3e8 | bellard | case AY_PMOD_N:
|
1206 | fdf9b3e8 | bellard | case AYX_PMOD_N:
|
1207 | fdf9b3e8 | bellard | fprintf_fn (stream, "@r%d+r9", rn);
|
1208 | fdf9b3e8 | bellard | break;
|
1209 | fdf9b3e8 | bellard | case DSP_REG_A_M:
|
1210 | fdf9b3e8 | bellard | fprintf_fn (stream, "a%c", '0' + rm); |
1211 | fdf9b3e8 | bellard | break;
|
1212 | fdf9b3e8 | bellard | case DSP_REG_X:
|
1213 | fdf9b3e8 | bellard | fprintf_fn (stream, "x%c", '0' + rm); |
1214 | fdf9b3e8 | bellard | break;
|
1215 | fdf9b3e8 | bellard | case DSP_REG_Y:
|
1216 | fdf9b3e8 | bellard | fprintf_fn (stream, "y%c", '0' + rm); |
1217 | fdf9b3e8 | bellard | break;
|
1218 | fdf9b3e8 | bellard | case DSP_REG_AX:
|
1219 | fdf9b3e8 | bellard | fprintf_fn (stream, "%c%c",
|
1220 | fdf9b3e8 | bellard | (rm & 1) ? 'x' : 'a', |
1221 | fdf9b3e8 | bellard | (rm & 2) ? '1' : '0'); |
1222 | fdf9b3e8 | bellard | break;
|
1223 | fdf9b3e8 | bellard | case DSP_REG_XY:
|
1224 | fdf9b3e8 | bellard | fprintf_fn (stream, "%c%c",
|
1225 | fdf9b3e8 | bellard | (rm & 1) ? 'y' : 'x', |
1226 | fdf9b3e8 | bellard | (rm & 2) ? '1' : '0'); |
1227 | fdf9b3e8 | bellard | break;
|
1228 | fdf9b3e8 | bellard | case DSP_REG_AY:
|
1229 | fdf9b3e8 | bellard | fprintf_fn (stream, "%c%c",
|
1230 | fdf9b3e8 | bellard | (rm & 2) ? 'y' : 'a', |
1231 | fdf9b3e8 | bellard | (rm & 1) ? '1' : '0'); |
1232 | fdf9b3e8 | bellard | break;
|
1233 | fdf9b3e8 | bellard | case DSP_REG_YX:
|
1234 | fdf9b3e8 | bellard | fprintf_fn (stream, "%c%c",
|
1235 | fdf9b3e8 | bellard | (rm & 2) ? 'x' : 'y', |
1236 | fdf9b3e8 | bellard | (rm & 1) ? '1' : '0'); |
1237 | fdf9b3e8 | bellard | break;
|
1238 | fdf9b3e8 | bellard | default:
|
1239 | fdf9b3e8 | bellard | abort (); |
1240 | fdf9b3e8 | bellard | } |
1241 | fdf9b3e8 | bellard | if (n == 0) |
1242 | fdf9b3e8 | bellard | fprintf_fn (stream, ",");
|
1243 | fdf9b3e8 | bellard | } |
1244 | fdf9b3e8 | bellard | } |
1245 | fdf9b3e8 | bellard | |
1246 | fdf9b3e8 | bellard | /* Print a double data transfer insn. INSN is just the lower three
|
1247 | fdf9b3e8 | bellard | nibbles of the insn, i.e. field a and the bit that indicates if
|
1248 | fdf9b3e8 | bellard | a parallel processing insn follows.
|
1249 | fdf9b3e8 | bellard | Return nonzero if a field b of a parallel processing insns follows. */
|
1250 | fdf9b3e8 | bellard | |
1251 | fdf9b3e8 | bellard | static void |
1252 | fdf9b3e8 | bellard | print_insn_ddt (insn, info) |
1253 | fdf9b3e8 | bellard | int insn;
|
1254 | fdf9b3e8 | bellard | struct disassemble_info *info;
|
1255 | fdf9b3e8 | bellard | { |
1256 | fdf9b3e8 | bellard | fprintf_ftype fprintf_fn = info->fprintf_func; |
1257 | fdf9b3e8 | bellard | void *stream = info->stream;
|
1258 | fdf9b3e8 | bellard | |
1259 | fdf9b3e8 | bellard | /* If this is just a nop, make sure to emit something. */
|
1260 | fdf9b3e8 | bellard | if (insn == 0x000) |
1261 | fdf9b3e8 | bellard | fprintf_fn (stream, "nopx\tnopy");
|
1262 | fdf9b3e8 | bellard | |
1263 | fdf9b3e8 | bellard | /* If a parallel processing insn was printed before,
|
1264 | fdf9b3e8 | bellard | and we got a non-nop, emit a tab. */
|
1265 | fdf9b3e8 | bellard | if ((insn & 0x800) && (insn & 0x3ff)) |
1266 | fdf9b3e8 | bellard | fprintf_fn (stream, "\t");
|
1267 | fdf9b3e8 | bellard | |
1268 | fdf9b3e8 | bellard | /* Check if either the x or y part is invalid. */
|
1269 | fdf9b3e8 | bellard | if (((insn & 0xc) == 0 && (insn & 0x2a0)) |
1270 | fdf9b3e8 | bellard | || ((insn & 3) == 0 && (insn & 0x150))) |
1271 | fdf9b3e8 | bellard | if (info->mach != bfd_mach_sh_dsp
|
1272 | fdf9b3e8 | bellard | && info->mach != bfd_mach_sh3_dsp) |
1273 | fdf9b3e8 | bellard | { |
1274 | fdf9b3e8 | bellard | static const sh_opcode_info *first_movx, *first_movy; |
1275 | fdf9b3e8 | bellard | const sh_opcode_info *op;
|
1276 | fdf9b3e8 | bellard | int is_movy;
|
1277 | fdf9b3e8 | bellard | |
1278 | fdf9b3e8 | bellard | if (! first_movx)
|
1279 | fdf9b3e8 | bellard | { |
1280 | fdf9b3e8 | bellard | for (first_movx = sh_table; first_movx->nibbles[1] != MOVX_NOPY;) |
1281 | fdf9b3e8 | bellard | first_movx++; |
1282 | fdf9b3e8 | bellard | for (first_movy = first_movx; first_movy->nibbles[1] != MOVY_NOPX;) |
1283 | fdf9b3e8 | bellard | first_movy++; |
1284 | fdf9b3e8 | bellard | } |
1285 | fdf9b3e8 | bellard | |
1286 | fdf9b3e8 | bellard | is_movy = ((insn & 3) != 0); |
1287 | fdf9b3e8 | bellard | |
1288 | fdf9b3e8 | bellard | if (is_movy)
|
1289 | fdf9b3e8 | bellard | op = first_movy; |
1290 | fdf9b3e8 | bellard | else
|
1291 | fdf9b3e8 | bellard | op = first_movx; |
1292 | fdf9b3e8 | bellard | |
1293 | fdf9b3e8 | bellard | while (op->nibbles[2] != (unsigned) ((insn >> 4) & 3) |
1294 | fdf9b3e8 | bellard | || op->nibbles[3] != (unsigned) (insn & 0xf)) |
1295 | fdf9b3e8 | bellard | op++; |
1296 | fdf9b3e8 | bellard | |
1297 | fdf9b3e8 | bellard | print_movxy (op, |
1298 | fdf9b3e8 | bellard | (4 * ((insn & (is_movy ? 0x200 : 0x100)) == 0) |
1299 | fdf9b3e8 | bellard | + 2 * is_movy
|
1300 | fdf9b3e8 | bellard | + 1 * ((insn & (is_movy ? 0x100 : 0x200)) != 0)), |
1301 | fdf9b3e8 | bellard | (insn >> 6) & 3, |
1302 | fdf9b3e8 | bellard | fprintf_fn, stream); |
1303 | fdf9b3e8 | bellard | } |
1304 | fdf9b3e8 | bellard | else
|
1305 | fdf9b3e8 | bellard | fprintf_fn (stream, ".word 0x%x", insn);
|
1306 | fdf9b3e8 | bellard | else
|
1307 | fdf9b3e8 | bellard | { |
1308 | fdf9b3e8 | bellard | static const sh_opcode_info *first_movx, *first_movy; |
1309 | fdf9b3e8 | bellard | const sh_opcode_info *opx, *opy;
|
1310 | fdf9b3e8 | bellard | unsigned int insn_x, insn_y; |
1311 | fdf9b3e8 | bellard | |
1312 | fdf9b3e8 | bellard | if (! first_movx)
|
1313 | fdf9b3e8 | bellard | { |
1314 | fdf9b3e8 | bellard | for (first_movx = sh_table; first_movx->nibbles[1] != MOVX;) |
1315 | fdf9b3e8 | bellard | first_movx++; |
1316 | fdf9b3e8 | bellard | for (first_movy = first_movx; first_movy->nibbles[1] != MOVY;) |
1317 | fdf9b3e8 | bellard | first_movy++; |
1318 | fdf9b3e8 | bellard | } |
1319 | fdf9b3e8 | bellard | insn_x = (insn >> 2) & 0xb; |
1320 | fdf9b3e8 | bellard | if (insn_x)
|
1321 | fdf9b3e8 | bellard | { |
1322 | fdf9b3e8 | bellard | for (opx = first_movx; opx->nibbles[2] != insn_x;) |
1323 | fdf9b3e8 | bellard | opx++; |
1324 | fdf9b3e8 | bellard | print_movxy (opx, ((insn >> 9) & 1) + 4, (insn >> 7) & 1, |
1325 | fdf9b3e8 | bellard | fprintf_fn, stream); |
1326 | fdf9b3e8 | bellard | } |
1327 | fdf9b3e8 | bellard | insn_y = (insn & 3) | ((insn >> 1) & 8); |
1328 | fdf9b3e8 | bellard | if (insn_y)
|
1329 | fdf9b3e8 | bellard | { |
1330 | fdf9b3e8 | bellard | if (insn_x)
|
1331 | fdf9b3e8 | bellard | fprintf_fn (stream, "\t");
|
1332 | fdf9b3e8 | bellard | for (opy = first_movy; opy->nibbles[2] != insn_y;) |
1333 | fdf9b3e8 | bellard | opy++; |
1334 | fdf9b3e8 | bellard | print_movxy (opy, ((insn >> 8) & 1) + 6, (insn >> 6) & 1, |
1335 | fdf9b3e8 | bellard | fprintf_fn, stream); |
1336 | fdf9b3e8 | bellard | } |
1337 | fdf9b3e8 | bellard | } |
1338 | fdf9b3e8 | bellard | } |
1339 | fdf9b3e8 | bellard | |
1340 | fdf9b3e8 | bellard | static void |
1341 | fdf9b3e8 | bellard | print_dsp_reg (rm, fprintf_fn, stream) |
1342 | fdf9b3e8 | bellard | int rm;
|
1343 | fdf9b3e8 | bellard | fprintf_ftype fprintf_fn; |
1344 | fdf9b3e8 | bellard | void *stream;
|
1345 | fdf9b3e8 | bellard | { |
1346 | fdf9b3e8 | bellard | switch (rm)
|
1347 | fdf9b3e8 | bellard | { |
1348 | fdf9b3e8 | bellard | case A_A1_NUM:
|
1349 | fdf9b3e8 | bellard | fprintf_fn (stream, "a1");
|
1350 | fdf9b3e8 | bellard | break;
|
1351 | fdf9b3e8 | bellard | case A_A0_NUM:
|
1352 | fdf9b3e8 | bellard | fprintf_fn (stream, "a0");
|
1353 | fdf9b3e8 | bellard | break;
|
1354 | fdf9b3e8 | bellard | case A_X0_NUM:
|
1355 | fdf9b3e8 | bellard | fprintf_fn (stream, "x0");
|
1356 | fdf9b3e8 | bellard | break;
|
1357 | fdf9b3e8 | bellard | case A_X1_NUM:
|
1358 | fdf9b3e8 | bellard | fprintf_fn (stream, "x1");
|
1359 | fdf9b3e8 | bellard | break;
|
1360 | fdf9b3e8 | bellard | case A_Y0_NUM:
|
1361 | fdf9b3e8 | bellard | fprintf_fn (stream, "y0");
|
1362 | fdf9b3e8 | bellard | break;
|
1363 | fdf9b3e8 | bellard | case A_Y1_NUM:
|
1364 | fdf9b3e8 | bellard | fprintf_fn (stream, "y1");
|
1365 | fdf9b3e8 | bellard | break;
|
1366 | fdf9b3e8 | bellard | case A_M0_NUM:
|
1367 | fdf9b3e8 | bellard | fprintf_fn (stream, "m0");
|
1368 | fdf9b3e8 | bellard | break;
|
1369 | fdf9b3e8 | bellard | case A_A1G_NUM:
|
1370 | fdf9b3e8 | bellard | fprintf_fn (stream, "a1g");
|
1371 | fdf9b3e8 | bellard | break;
|
1372 | fdf9b3e8 | bellard | case A_M1_NUM:
|
1373 | fdf9b3e8 | bellard | fprintf_fn (stream, "m1");
|
1374 | fdf9b3e8 | bellard | break;
|
1375 | fdf9b3e8 | bellard | case A_A0G_NUM:
|
1376 | fdf9b3e8 | bellard | fprintf_fn (stream, "a0g");
|
1377 | fdf9b3e8 | bellard | break;
|
1378 | fdf9b3e8 | bellard | default:
|
1379 | fdf9b3e8 | bellard | fprintf_fn (stream, "0x%x", rm);
|
1380 | fdf9b3e8 | bellard | break;
|
1381 | fdf9b3e8 | bellard | } |
1382 | fdf9b3e8 | bellard | } |
1383 | fdf9b3e8 | bellard | |
1384 | fdf9b3e8 | bellard | static void |
1385 | fdf9b3e8 | bellard | print_insn_ppi (field_b, info) |
1386 | fdf9b3e8 | bellard | int field_b;
|
1387 | fdf9b3e8 | bellard | struct disassemble_info *info;
|
1388 | fdf9b3e8 | bellard | { |
1389 | fdf9b3e8 | bellard | static char *sx_tab[] = { "x0", "x1", "a0", "a1" }; |
1390 | fdf9b3e8 | bellard | static char *sy_tab[] = { "y0", "y1", "m0", "m1" }; |
1391 | fdf9b3e8 | bellard | fprintf_ftype fprintf_fn = info->fprintf_func; |
1392 | fdf9b3e8 | bellard | void *stream = info->stream;
|
1393 | fdf9b3e8 | bellard | unsigned int nib1, nib2, nib3; |
1394 | fdf9b3e8 | bellard | unsigned int altnib1, nib4; |
1395 | fdf9b3e8 | bellard | char *dc = NULL; |
1396 | fdf9b3e8 | bellard | const sh_opcode_info *op;
|
1397 | fdf9b3e8 | bellard | |
1398 | fdf9b3e8 | bellard | if ((field_b & 0xe800) == 0) |
1399 | fdf9b3e8 | bellard | { |
1400 | fdf9b3e8 | bellard | fprintf_fn (stream, "psh%c\t#%d,",
|
1401 | fdf9b3e8 | bellard | field_b & 0x1000 ? 'a' : 'l', |
1402 | fdf9b3e8 | bellard | (field_b >> 4) & 127); |
1403 | fdf9b3e8 | bellard | print_dsp_reg (field_b & 0xf, fprintf_fn, stream);
|
1404 | fdf9b3e8 | bellard | return;
|
1405 | fdf9b3e8 | bellard | } |
1406 | fdf9b3e8 | bellard | if ((field_b & 0xc000) == 0x4000 && (field_b & 0x3000) != 0x1000) |
1407 | fdf9b3e8 | bellard | { |
1408 | fdf9b3e8 | bellard | static char *du_tab[] = { "x0", "y0", "a0", "a1" }; |
1409 | fdf9b3e8 | bellard | static char *se_tab[] = { "x0", "x1", "y0", "a1" }; |
1410 | fdf9b3e8 | bellard | static char *sf_tab[] = { "y0", "y1", "x0", "a1" }; |
1411 | fdf9b3e8 | bellard | static char *sg_tab[] = { "m0", "m1", "a0", "a1" }; |
1412 | fdf9b3e8 | bellard | |
1413 | fdf9b3e8 | bellard | if (field_b & 0x2000) |
1414 | fdf9b3e8 | bellard | { |
1415 | fdf9b3e8 | bellard | fprintf_fn (stream, "p%s %s,%s,%s\t",
|
1416 | fdf9b3e8 | bellard | (field_b & 0x1000) ? "add" : "sub", |
1417 | fdf9b3e8 | bellard | sx_tab[(field_b >> 6) & 3], |
1418 | fdf9b3e8 | bellard | sy_tab[(field_b >> 4) & 3], |
1419 | fdf9b3e8 | bellard | du_tab[(field_b >> 0) & 3]); |
1420 | fdf9b3e8 | bellard | } |
1421 | fdf9b3e8 | bellard | else if ((field_b & 0xf0) == 0x10 |
1422 | fdf9b3e8 | bellard | && info->mach != bfd_mach_sh_dsp |
1423 | fdf9b3e8 | bellard | && info->mach != bfd_mach_sh3_dsp) |
1424 | fdf9b3e8 | bellard | { |
1425 | fdf9b3e8 | bellard | fprintf_fn (stream, "pclr %s \t", du_tab[(field_b >> 0) & 3]); |
1426 | fdf9b3e8 | bellard | } |
1427 | fdf9b3e8 | bellard | else if ((field_b & 0xf3) != 0) |
1428 | fdf9b3e8 | bellard | { |
1429 | fdf9b3e8 | bellard | fprintf_fn (stream, ".word 0x%x\t", field_b);
|
1430 | fdf9b3e8 | bellard | } |
1431 | fdf9b3e8 | bellard | fprintf_fn (stream, "pmuls%c%s,%s,%s",
|
1432 | fdf9b3e8 | bellard | field_b & 0x2000 ? ' ' : '\t', |
1433 | fdf9b3e8 | bellard | se_tab[(field_b >> 10) & 3], |
1434 | fdf9b3e8 | bellard | sf_tab[(field_b >> 8) & 3], |
1435 | fdf9b3e8 | bellard | sg_tab[(field_b >> 2) & 3]); |
1436 | fdf9b3e8 | bellard | return;
|
1437 | fdf9b3e8 | bellard | } |
1438 | fdf9b3e8 | bellard | |
1439 | fdf9b3e8 | bellard | nib1 = PPIC; |
1440 | fdf9b3e8 | bellard | nib2 = field_b >> 12 & 0xf; |
1441 | fdf9b3e8 | bellard | nib3 = field_b >> 8 & 0xf; |
1442 | fdf9b3e8 | bellard | nib4 = field_b >> 4 & 0xf; |
1443 | fdf9b3e8 | bellard | switch (nib3 & 0x3) |
1444 | fdf9b3e8 | bellard | { |
1445 | fdf9b3e8 | bellard | case 0: |
1446 | fdf9b3e8 | bellard | dc = "";
|
1447 | fdf9b3e8 | bellard | nib1 = PPI3; |
1448 | fdf9b3e8 | bellard | break;
|
1449 | fdf9b3e8 | bellard | case 1: |
1450 | fdf9b3e8 | bellard | dc = "";
|
1451 | fdf9b3e8 | bellard | break;
|
1452 | fdf9b3e8 | bellard | case 2: |
1453 | fdf9b3e8 | bellard | dc = "dct ";
|
1454 | fdf9b3e8 | bellard | nib3 -= 1;
|
1455 | fdf9b3e8 | bellard | break;
|
1456 | fdf9b3e8 | bellard | case 3: |
1457 | fdf9b3e8 | bellard | dc = "dcf ";
|
1458 | fdf9b3e8 | bellard | nib3 -= 2;
|
1459 | fdf9b3e8 | bellard | break;
|
1460 | fdf9b3e8 | bellard | } |
1461 | fdf9b3e8 | bellard | if (nib1 == PPI3)
|
1462 | fdf9b3e8 | bellard | altnib1 = PPI3NC; |
1463 | fdf9b3e8 | bellard | else
|
1464 | fdf9b3e8 | bellard | altnib1 = nib1; |
1465 | fdf9b3e8 | bellard | for (op = sh_table; op->name; op++)
|
1466 | fdf9b3e8 | bellard | { |
1467 | fdf9b3e8 | bellard | if ((op->nibbles[1] == nib1 || op->nibbles[1] == altnib1) |
1468 | fdf9b3e8 | bellard | && op->nibbles[2] == nib2
|
1469 | fdf9b3e8 | bellard | && op->nibbles[3] == nib3)
|
1470 | fdf9b3e8 | bellard | { |
1471 | fdf9b3e8 | bellard | int n;
|
1472 | fdf9b3e8 | bellard | |
1473 | fdf9b3e8 | bellard | switch (op->nibbles[4]) |
1474 | fdf9b3e8 | bellard | { |
1475 | fdf9b3e8 | bellard | case HEX_0:
|
1476 | fdf9b3e8 | bellard | break;
|
1477 | fdf9b3e8 | bellard | case HEX_XX00:
|
1478 | fdf9b3e8 | bellard | if ((nib4 & 3) != 0) |
1479 | fdf9b3e8 | bellard | continue;
|
1480 | fdf9b3e8 | bellard | break;
|
1481 | fdf9b3e8 | bellard | case HEX_1:
|
1482 | fdf9b3e8 | bellard | if ((nib4 & 3) != 1) |
1483 | fdf9b3e8 | bellard | continue;
|
1484 | fdf9b3e8 | bellard | break;
|
1485 | fdf9b3e8 | bellard | case HEX_00YY:
|
1486 | fdf9b3e8 | bellard | if ((nib4 & 0xc) != 0) |
1487 | fdf9b3e8 | bellard | continue;
|
1488 | fdf9b3e8 | bellard | break;
|
1489 | fdf9b3e8 | bellard | case HEX_4:
|
1490 | fdf9b3e8 | bellard | if ((nib4 & 0xc) != 4) |
1491 | fdf9b3e8 | bellard | continue;
|
1492 | fdf9b3e8 | bellard | break;
|
1493 | fdf9b3e8 | bellard | default:
|
1494 | fdf9b3e8 | bellard | abort (); |
1495 | fdf9b3e8 | bellard | } |
1496 | fdf9b3e8 | bellard | fprintf_fn (stream, "%s%s\t", dc, op->name);
|
1497 | fdf9b3e8 | bellard | for (n = 0; n < 3 && op->arg[n] != A_END; n++) |
1498 | fdf9b3e8 | bellard | { |
1499 | fdf9b3e8 | bellard | if (n && op->arg[1] != A_END) |
1500 | fdf9b3e8 | bellard | fprintf_fn (stream, ",");
|
1501 | fdf9b3e8 | bellard | switch (op->arg[n])
|
1502 | fdf9b3e8 | bellard | { |
1503 | fdf9b3e8 | bellard | case DSP_REG_N:
|
1504 | fdf9b3e8 | bellard | print_dsp_reg (field_b & 0xf, fprintf_fn, stream);
|
1505 | fdf9b3e8 | bellard | break;
|
1506 | fdf9b3e8 | bellard | case DSP_REG_X:
|
1507 | fdf9b3e8 | bellard | fprintf_fn (stream, sx_tab[(field_b >> 6) & 3]); |
1508 | fdf9b3e8 | bellard | break;
|
1509 | fdf9b3e8 | bellard | case DSP_REG_Y:
|
1510 | fdf9b3e8 | bellard | fprintf_fn (stream, sy_tab[(field_b >> 4) & 3]); |
1511 | fdf9b3e8 | bellard | break;
|
1512 | fdf9b3e8 | bellard | case A_MACH:
|
1513 | fdf9b3e8 | bellard | fprintf_fn (stream, "mach");
|
1514 | fdf9b3e8 | bellard | break;
|
1515 | fdf9b3e8 | bellard | case A_MACL:
|
1516 | fdf9b3e8 | bellard | fprintf_fn (stream, "macl");
|
1517 | fdf9b3e8 | bellard | break;
|
1518 | fdf9b3e8 | bellard | default:
|
1519 | fdf9b3e8 | bellard | abort (); |
1520 | fdf9b3e8 | bellard | } |
1521 | fdf9b3e8 | bellard | } |
1522 | fdf9b3e8 | bellard | return;
|
1523 | fdf9b3e8 | bellard | } |
1524 | fdf9b3e8 | bellard | } |
1525 | fdf9b3e8 | bellard | /* Not found. */
|
1526 | fdf9b3e8 | bellard | fprintf_fn (stream, ".word 0x%x", field_b);
|
1527 | fdf9b3e8 | bellard | } |
1528 | fdf9b3e8 | bellard | |
1529 | fdf9b3e8 | bellard | /* FIXME mvs: movx insns print as ".word 0x%03x", insn & 0xfff
|
1530 | fdf9b3e8 | bellard | (ie. the upper nibble is missing). */
|
1531 | fdf9b3e8 | bellard | int
|
1532 | fdf9b3e8 | bellard | print_insn_sh (memaddr, info) |
1533 | fdf9b3e8 | bellard | bfd_vma memaddr; |
1534 | fdf9b3e8 | bellard | struct disassemble_info *info;
|
1535 | fdf9b3e8 | bellard | { |
1536 | fdf9b3e8 | bellard | fprintf_ftype fprintf_fn = info->fprintf_func; |
1537 | fdf9b3e8 | bellard | void *stream = info->stream;
|
1538 | fdf9b3e8 | bellard | unsigned char insn[4]; |
1539 | fdf9b3e8 | bellard | unsigned char nibs[8]; |
1540 | fdf9b3e8 | bellard | int status;
|
1541 | fdf9b3e8 | bellard | bfd_vma relmask = ~(bfd_vma) 0;
|
1542 | fdf9b3e8 | bellard | const sh_opcode_info *op;
|
1543 | fdf9b3e8 | bellard | unsigned int target_arch; |
1544 | fdf9b3e8 | bellard | int allow_op32;
|
1545 | fdf9b3e8 | bellard | |
1546 | fdf9b3e8 | bellard | switch (info->mach)
|
1547 | fdf9b3e8 | bellard | { |
1548 | fdf9b3e8 | bellard | case bfd_mach_sh:
|
1549 | fdf9b3e8 | bellard | target_arch = arch_sh1; |
1550 | fdf9b3e8 | bellard | break;
|
1551 | fdf9b3e8 | bellard | case bfd_mach_sh4:
|
1552 | fdf9b3e8 | bellard | target_arch = arch_sh4; |
1553 | fdf9b3e8 | bellard | break;
|
1554 | fdf9b3e8 | bellard | case bfd_mach_sh5:
|
1555 | fdf9b3e8 | bellard | #ifdef INCLUDE_SHMEDIA
|
1556 | fdf9b3e8 | bellard | status = print_insn_sh64 (memaddr, info); |
1557 | fdf9b3e8 | bellard | if (status != -2) |
1558 | fdf9b3e8 | bellard | return status;
|
1559 | fdf9b3e8 | bellard | #endif
|
1560 | fdf9b3e8 | bellard | /* When we get here for sh64, it's because we want to disassemble
|
1561 | fdf9b3e8 | bellard | SHcompact, i.e. arch_sh4. */
|
1562 | fdf9b3e8 | bellard | target_arch = arch_sh4; |
1563 | fdf9b3e8 | bellard | break;
|
1564 | fdf9b3e8 | bellard | default:
|
1565 | fdf9b3e8 | bellard | fprintf (stderr, "sh architecture not supported\n");
|
1566 | fdf9b3e8 | bellard | return -1; |
1567 | fdf9b3e8 | bellard | } |
1568 | fdf9b3e8 | bellard | |
1569 | fdf9b3e8 | bellard | status = info->read_memory_func (memaddr, insn, 2, info);
|
1570 | fdf9b3e8 | bellard | |
1571 | fdf9b3e8 | bellard | if (status != 0) |
1572 | fdf9b3e8 | bellard | { |
1573 | fdf9b3e8 | bellard | info->memory_error_func (status, memaddr, info); |
1574 | fdf9b3e8 | bellard | return -1; |
1575 | fdf9b3e8 | bellard | } |
1576 | fdf9b3e8 | bellard | |
1577 | fdf9b3e8 | bellard | if (info->endian == BFD_ENDIAN_LITTLE)
|
1578 | fdf9b3e8 | bellard | { |
1579 | fdf9b3e8 | bellard | nibs[0] = (insn[1] >> 4) & 0xf; |
1580 | fdf9b3e8 | bellard | nibs[1] = insn[1] & 0xf; |
1581 | fdf9b3e8 | bellard | |
1582 | fdf9b3e8 | bellard | nibs[2] = (insn[0] >> 4) & 0xf; |
1583 | fdf9b3e8 | bellard | nibs[3] = insn[0] & 0xf; |
1584 | fdf9b3e8 | bellard | } |
1585 | fdf9b3e8 | bellard | else
|
1586 | fdf9b3e8 | bellard | { |
1587 | fdf9b3e8 | bellard | nibs[0] = (insn[0] >> 4) & 0xf; |
1588 | fdf9b3e8 | bellard | nibs[1] = insn[0] & 0xf; |
1589 | fdf9b3e8 | bellard | |
1590 | fdf9b3e8 | bellard | nibs[2] = (insn[1] >> 4) & 0xf; |
1591 | fdf9b3e8 | bellard | nibs[3] = insn[1] & 0xf; |
1592 | fdf9b3e8 | bellard | } |
1593 | fdf9b3e8 | bellard | status = info->read_memory_func (memaddr + 2, insn + 2, 2, info); |
1594 | fdf9b3e8 | bellard | if (status != 0) |
1595 | fdf9b3e8 | bellard | allow_op32 = 0;
|
1596 | fdf9b3e8 | bellard | else
|
1597 | fdf9b3e8 | bellard | { |
1598 | fdf9b3e8 | bellard | allow_op32 = 1;
|
1599 | fdf9b3e8 | bellard | |
1600 | fdf9b3e8 | bellard | if (info->endian == BFD_ENDIAN_LITTLE)
|
1601 | fdf9b3e8 | bellard | { |
1602 | fdf9b3e8 | bellard | nibs[4] = (insn[3] >> 4) & 0xf; |
1603 | fdf9b3e8 | bellard | nibs[5] = insn[3] & 0xf; |
1604 | fdf9b3e8 | bellard | |
1605 | fdf9b3e8 | bellard | nibs[6] = (insn[2] >> 4) & 0xf; |
1606 | fdf9b3e8 | bellard | nibs[7] = insn[2] & 0xf; |
1607 | fdf9b3e8 | bellard | } |
1608 | fdf9b3e8 | bellard | else
|
1609 | fdf9b3e8 | bellard | { |
1610 | fdf9b3e8 | bellard | nibs[4] = (insn[2] >> 4) & 0xf; |
1611 | fdf9b3e8 | bellard | nibs[5] = insn[2] & 0xf; |
1612 | fdf9b3e8 | bellard | |
1613 | fdf9b3e8 | bellard | nibs[6] = (insn[3] >> 4) & 0xf; |
1614 | fdf9b3e8 | bellard | nibs[7] = insn[3] & 0xf; |
1615 | fdf9b3e8 | bellard | } |
1616 | fdf9b3e8 | bellard | } |
1617 | fdf9b3e8 | bellard | |
1618 | fdf9b3e8 | bellard | if (nibs[0] == 0xf && (nibs[1] & 4) == 0 |
1619 | fdf9b3e8 | bellard | && SH_MERGE_ARCH_SET_VALID (target_arch, arch_sh_dsp_up)) |
1620 | fdf9b3e8 | bellard | { |
1621 | fdf9b3e8 | bellard | if (nibs[1] & 8) |
1622 | fdf9b3e8 | bellard | { |
1623 | fdf9b3e8 | bellard | int field_b;
|
1624 | fdf9b3e8 | bellard | |
1625 | fdf9b3e8 | bellard | status = info->read_memory_func (memaddr + 2, insn, 2, info); |
1626 | fdf9b3e8 | bellard | |
1627 | fdf9b3e8 | bellard | if (status != 0) |
1628 | fdf9b3e8 | bellard | { |
1629 | fdf9b3e8 | bellard | info->memory_error_func (status, memaddr + 2, info);
|
1630 | fdf9b3e8 | bellard | return -1; |
1631 | fdf9b3e8 | bellard | } |
1632 | fdf9b3e8 | bellard | |
1633 | fdf9b3e8 | bellard | if (info->endian == BFD_ENDIAN_LITTLE)
|
1634 | fdf9b3e8 | bellard | field_b = insn[1] << 8 | insn[0]; |
1635 | fdf9b3e8 | bellard | else
|
1636 | fdf9b3e8 | bellard | field_b = insn[0] << 8 | insn[1]; |
1637 | fdf9b3e8 | bellard | |
1638 | fdf9b3e8 | bellard | print_insn_ppi (field_b, info); |
1639 | fdf9b3e8 | bellard | print_insn_ddt ((nibs[1] << 8) | (nibs[2] << 4) | nibs[3], info); |
1640 | fdf9b3e8 | bellard | return 4; |
1641 | fdf9b3e8 | bellard | } |
1642 | fdf9b3e8 | bellard | print_insn_ddt ((nibs[1] << 8) | (nibs[2] << 4) | nibs[3], info); |
1643 | fdf9b3e8 | bellard | return 2; |
1644 | fdf9b3e8 | bellard | } |
1645 | fdf9b3e8 | bellard | for (op = sh_table; op->name; op++)
|
1646 | fdf9b3e8 | bellard | { |
1647 | fdf9b3e8 | bellard | int n;
|
1648 | fdf9b3e8 | bellard | int imm = 0; |
1649 | fdf9b3e8 | bellard | int rn = 0; |
1650 | fdf9b3e8 | bellard | int rm = 0; |
1651 | fdf9b3e8 | bellard | int rb = 0; |
1652 | fdf9b3e8 | bellard | int disp_pc;
|
1653 | fdf9b3e8 | bellard | bfd_vma disp_pc_addr = 0;
|
1654 | fdf9b3e8 | bellard | int disp = 0; |
1655 | fdf9b3e8 | bellard | int has_disp = 0; |
1656 | fdf9b3e8 | bellard | int max_n = SH_MERGE_ARCH_SET (op->arch, arch_op32) ? 8 : 4; |
1657 | fdf9b3e8 | bellard | |
1658 | fdf9b3e8 | bellard | if (!allow_op32
|
1659 | fdf9b3e8 | bellard | && SH_MERGE_ARCH_SET (op->arch, arch_op32)) |
1660 | fdf9b3e8 | bellard | goto fail;
|
1661 | fdf9b3e8 | bellard | |
1662 | fdf9b3e8 | bellard | if (!SH_MERGE_ARCH_SET_VALID (op->arch, target_arch))
|
1663 | fdf9b3e8 | bellard | goto fail;
|
1664 | fdf9b3e8 | bellard | for (n = 0; n < max_n; n++) |
1665 | fdf9b3e8 | bellard | { |
1666 | fdf9b3e8 | bellard | int i = op->nibbles[n];
|
1667 | fdf9b3e8 | bellard | |
1668 | fdf9b3e8 | bellard | if (i < 16) |
1669 | fdf9b3e8 | bellard | { |
1670 | fdf9b3e8 | bellard | if (nibs[n] == i)
|
1671 | fdf9b3e8 | bellard | continue;
|
1672 | fdf9b3e8 | bellard | goto fail;
|
1673 | fdf9b3e8 | bellard | } |
1674 | fdf9b3e8 | bellard | switch (i)
|
1675 | fdf9b3e8 | bellard | { |
1676 | fdf9b3e8 | bellard | case BRANCH_8:
|
1677 | fdf9b3e8 | bellard | imm = (nibs[2] << 4) | (nibs[3]); |
1678 | fdf9b3e8 | bellard | if (imm & 0x80) |
1679 | fdf9b3e8 | bellard | imm |= ~0xff;
|
1680 | fdf9b3e8 | bellard | imm = ((char) imm) * 2 + 4; |
1681 | fdf9b3e8 | bellard | goto ok;
|
1682 | fdf9b3e8 | bellard | case BRANCH_12:
|
1683 | fdf9b3e8 | bellard | imm = ((nibs[1]) << 8) | (nibs[2] << 4) | (nibs[3]); |
1684 | fdf9b3e8 | bellard | if (imm & 0x800) |
1685 | fdf9b3e8 | bellard | imm |= ~0xfff;
|
1686 | fdf9b3e8 | bellard | imm = imm * 2 + 4; |
1687 | fdf9b3e8 | bellard | goto ok;
|
1688 | fdf9b3e8 | bellard | case IMM0_3c:
|
1689 | fdf9b3e8 | bellard | if (nibs[3] & 0x8) |
1690 | fdf9b3e8 | bellard | goto fail;
|
1691 | fdf9b3e8 | bellard | imm = nibs[3] & 0x7; |
1692 | fdf9b3e8 | bellard | break;
|
1693 | fdf9b3e8 | bellard | case IMM0_3s:
|
1694 | fdf9b3e8 | bellard | if (!(nibs[3] & 0x8)) |
1695 | fdf9b3e8 | bellard | goto fail;
|
1696 | fdf9b3e8 | bellard | imm = nibs[3] & 0x7; |
1697 | fdf9b3e8 | bellard | break;
|
1698 | fdf9b3e8 | bellard | case IMM0_3Uc:
|
1699 | fdf9b3e8 | bellard | if (nibs[2] & 0x8) |
1700 | fdf9b3e8 | bellard | goto fail;
|
1701 | fdf9b3e8 | bellard | imm = nibs[2] & 0x7; |
1702 | fdf9b3e8 | bellard | break;
|
1703 | fdf9b3e8 | bellard | case IMM0_3Us:
|
1704 | fdf9b3e8 | bellard | if (!(nibs[2] & 0x8)) |
1705 | fdf9b3e8 | bellard | goto fail;
|
1706 | fdf9b3e8 | bellard | imm = nibs[2] & 0x7; |
1707 | fdf9b3e8 | bellard | break;
|
1708 | fdf9b3e8 | bellard | case DISP0_12:
|
1709 | fdf9b3e8 | bellard | case DISP1_12:
|
1710 | fdf9b3e8 | bellard | disp = (nibs[5] << 8) | (nibs[6] << 4) | nibs[7]; |
1711 | fdf9b3e8 | bellard | has_disp = 1;
|
1712 | fdf9b3e8 | bellard | goto ok;
|
1713 | fdf9b3e8 | bellard | case DISP0_12BY2:
|
1714 | fdf9b3e8 | bellard | case DISP1_12BY2:
|
1715 | fdf9b3e8 | bellard | disp = ((nibs[5] << 8) | (nibs[6] << 4) | nibs[7]) << 1; |
1716 | fdf9b3e8 | bellard | relmask = ~(bfd_vma) 1;
|
1717 | fdf9b3e8 | bellard | has_disp = 1;
|
1718 | fdf9b3e8 | bellard | goto ok;
|
1719 | fdf9b3e8 | bellard | case DISP0_12BY4:
|
1720 | fdf9b3e8 | bellard | case DISP1_12BY4:
|
1721 | fdf9b3e8 | bellard | disp = ((nibs[5] << 8) | (nibs[6] << 4) | nibs[7]) << 2; |
1722 | fdf9b3e8 | bellard | relmask = ~(bfd_vma) 3;
|
1723 | fdf9b3e8 | bellard | has_disp = 1;
|
1724 | fdf9b3e8 | bellard | goto ok;
|
1725 | fdf9b3e8 | bellard | case DISP0_12BY8:
|
1726 | fdf9b3e8 | bellard | case DISP1_12BY8:
|
1727 | fdf9b3e8 | bellard | disp = ((nibs[5] << 8) | (nibs[6] << 4) | nibs[7]) << 3; |
1728 | fdf9b3e8 | bellard | relmask = ~(bfd_vma) 7;
|
1729 | fdf9b3e8 | bellard | has_disp = 1;
|
1730 | fdf9b3e8 | bellard | goto ok;
|
1731 | fdf9b3e8 | bellard | case IMM0_20_4:
|
1732 | fdf9b3e8 | bellard | break;
|
1733 | fdf9b3e8 | bellard | case IMM0_20:
|
1734 | fdf9b3e8 | bellard | imm = ((nibs[2] << 16) | (nibs[4] << 12) | (nibs[5] << 8) |
1735 | fdf9b3e8 | bellard | | (nibs[6] << 4) | nibs[7]); |
1736 | fdf9b3e8 | bellard | if (imm & 0x80000) |
1737 | fdf9b3e8 | bellard | imm -= 0x100000;
|
1738 | fdf9b3e8 | bellard | goto ok;
|
1739 | fdf9b3e8 | bellard | case IMM0_20BY8:
|
1740 | fdf9b3e8 | bellard | imm = ((nibs[2] << 16) | (nibs[4] << 12) | (nibs[5] << 8) |
1741 | fdf9b3e8 | bellard | | (nibs[6] << 4) | nibs[7]); |
1742 | fdf9b3e8 | bellard | imm <<= 8;
|
1743 | fdf9b3e8 | bellard | if (imm & 0x8000000) |
1744 | fdf9b3e8 | bellard | imm -= 0x10000000;
|
1745 | fdf9b3e8 | bellard | goto ok;
|
1746 | fdf9b3e8 | bellard | case IMM0_4:
|
1747 | fdf9b3e8 | bellard | case IMM1_4:
|
1748 | fdf9b3e8 | bellard | imm = nibs[3];
|
1749 | fdf9b3e8 | bellard | goto ok;
|
1750 | fdf9b3e8 | bellard | case IMM0_4BY2:
|
1751 | fdf9b3e8 | bellard | case IMM1_4BY2:
|
1752 | fdf9b3e8 | bellard | imm = nibs[3] << 1; |
1753 | fdf9b3e8 | bellard | goto ok;
|
1754 | fdf9b3e8 | bellard | case IMM0_4BY4:
|
1755 | fdf9b3e8 | bellard | case IMM1_4BY4:
|
1756 | fdf9b3e8 | bellard | imm = nibs[3] << 2; |
1757 | fdf9b3e8 | bellard | goto ok;
|
1758 | fdf9b3e8 | bellard | case IMM0_8:
|
1759 | fdf9b3e8 | bellard | case IMM1_8:
|
1760 | fdf9b3e8 | bellard | imm = (nibs[2] << 4) | nibs[3]; |
1761 | fdf9b3e8 | bellard | disp = imm; |
1762 | fdf9b3e8 | bellard | has_disp = 1;
|
1763 | fdf9b3e8 | bellard | if (imm & 0x80) |
1764 | fdf9b3e8 | bellard | imm -= 0x100;
|
1765 | fdf9b3e8 | bellard | goto ok;
|
1766 | fdf9b3e8 | bellard | case PCRELIMM_8BY2:
|
1767 | fdf9b3e8 | bellard | imm = ((nibs[2] << 4) | nibs[3]) << 1; |
1768 | fdf9b3e8 | bellard | relmask = ~(bfd_vma) 1;
|
1769 | fdf9b3e8 | bellard | goto ok;
|
1770 | fdf9b3e8 | bellard | case PCRELIMM_8BY4:
|
1771 | fdf9b3e8 | bellard | imm = ((nibs[2] << 4) | nibs[3]) << 2; |
1772 | fdf9b3e8 | bellard | relmask = ~(bfd_vma) 3;
|
1773 | fdf9b3e8 | bellard | goto ok;
|
1774 | fdf9b3e8 | bellard | case IMM0_8BY2:
|
1775 | fdf9b3e8 | bellard | case IMM1_8BY2:
|
1776 | fdf9b3e8 | bellard | imm = ((nibs[2] << 4) | nibs[3]) << 1; |
1777 | fdf9b3e8 | bellard | goto ok;
|
1778 | fdf9b3e8 | bellard | case IMM0_8BY4:
|
1779 | fdf9b3e8 | bellard | case IMM1_8BY4:
|
1780 | fdf9b3e8 | bellard | imm = ((nibs[2] << 4) | nibs[3]) << 2; |
1781 | fdf9b3e8 | bellard | goto ok;
|
1782 | fdf9b3e8 | bellard | case REG_N_D:
|
1783 | fdf9b3e8 | bellard | if ((nibs[n] & 1) != 0) |
1784 | fdf9b3e8 | bellard | goto fail;
|
1785 | fdf9b3e8 | bellard | /* fall through */
|
1786 | fdf9b3e8 | bellard | case REG_N:
|
1787 | fdf9b3e8 | bellard | rn = nibs[n]; |
1788 | fdf9b3e8 | bellard | break;
|
1789 | fdf9b3e8 | bellard | case REG_M:
|
1790 | fdf9b3e8 | bellard | rm = nibs[n]; |
1791 | fdf9b3e8 | bellard | break;
|
1792 | fdf9b3e8 | bellard | case REG_N_B01:
|
1793 | fdf9b3e8 | bellard | if ((nibs[n] & 0x3) != 1 /* binary 01 */) |
1794 | fdf9b3e8 | bellard | goto fail;
|
1795 | fdf9b3e8 | bellard | rn = (nibs[n] & 0xc) >> 2; |
1796 | fdf9b3e8 | bellard | break;
|
1797 | fdf9b3e8 | bellard | case REG_NM:
|
1798 | fdf9b3e8 | bellard | rn = (nibs[n] & 0xc) >> 2; |
1799 | fdf9b3e8 | bellard | rm = (nibs[n] & 0x3);
|
1800 | fdf9b3e8 | bellard | break;
|
1801 | fdf9b3e8 | bellard | case REG_B:
|
1802 | fdf9b3e8 | bellard | rb = nibs[n] & 0x07;
|
1803 | fdf9b3e8 | bellard | break;
|
1804 | fdf9b3e8 | bellard | case SDT_REG_N:
|
1805 | fdf9b3e8 | bellard | /* sh-dsp: single data transfer. */
|
1806 | fdf9b3e8 | bellard | rn = nibs[n]; |
1807 | fdf9b3e8 | bellard | if ((rn & 0xc) != 4) |
1808 | fdf9b3e8 | bellard | goto fail;
|
1809 | fdf9b3e8 | bellard | rn = rn & 0x3;
|
1810 | fdf9b3e8 | bellard | rn |= (!(rn & 2)) << 2; |
1811 | fdf9b3e8 | bellard | break;
|
1812 | fdf9b3e8 | bellard | case PPI:
|
1813 | fdf9b3e8 | bellard | case REPEAT:
|
1814 | fdf9b3e8 | bellard | goto fail;
|
1815 | fdf9b3e8 | bellard | default:
|
1816 | fdf9b3e8 | bellard | abort (); |
1817 | fdf9b3e8 | bellard | } |
1818 | fdf9b3e8 | bellard | } |
1819 | fdf9b3e8 | bellard | |
1820 | fdf9b3e8 | bellard | ok:
|
1821 | fdf9b3e8 | bellard | /* sh2a has D_REG but not X_REG. We don't know the pattern
|
1822 | fdf9b3e8 | bellard | doesn't match unless we check the output args to see if they
|
1823 | fdf9b3e8 | bellard | make sense. */
|
1824 | fdf9b3e8 | bellard | if (target_arch == arch_sh2a
|
1825 | fdf9b3e8 | bellard | && ((op->arg[0] == DX_REG_M && (rm & 1) != 0) |
1826 | fdf9b3e8 | bellard | || (op->arg[1] == DX_REG_N && (rn & 1) != 0))) |
1827 | fdf9b3e8 | bellard | goto fail;
|
1828 | fdf9b3e8 | bellard | |
1829 | fdf9b3e8 | bellard | fprintf_fn (stream, "%s\t", op->name);
|
1830 | fdf9b3e8 | bellard | disp_pc = 0;
|
1831 | fdf9b3e8 | bellard | for (n = 0; n < 3 && op->arg[n] != A_END; n++) |
1832 | fdf9b3e8 | bellard | { |
1833 | fdf9b3e8 | bellard | if (n && op->arg[1] != A_END) |
1834 | fdf9b3e8 | bellard | fprintf_fn (stream, ",");
|
1835 | fdf9b3e8 | bellard | switch (op->arg[n])
|
1836 | fdf9b3e8 | bellard | { |
1837 | fdf9b3e8 | bellard | case A_IMM:
|
1838 | fdf9b3e8 | bellard | fprintf_fn (stream, "#%d", imm);
|
1839 | fdf9b3e8 | bellard | break;
|
1840 | fdf9b3e8 | bellard | case A_R0:
|
1841 | fdf9b3e8 | bellard | fprintf_fn (stream, "r0");
|
1842 | fdf9b3e8 | bellard | break;
|
1843 | fdf9b3e8 | bellard | case A_REG_N:
|
1844 | fdf9b3e8 | bellard | fprintf_fn (stream, "r%d", rn);
|
1845 | fdf9b3e8 | bellard | break;
|
1846 | fdf9b3e8 | bellard | case A_INC_N:
|
1847 | fdf9b3e8 | bellard | case AS_INC_N:
|
1848 | fdf9b3e8 | bellard | fprintf_fn (stream, "@r%d+", rn);
|
1849 | fdf9b3e8 | bellard | break;
|
1850 | fdf9b3e8 | bellard | case A_DEC_N:
|
1851 | fdf9b3e8 | bellard | case AS_DEC_N:
|
1852 | fdf9b3e8 | bellard | fprintf_fn (stream, "@-r%d", rn);
|
1853 | fdf9b3e8 | bellard | break;
|
1854 | fdf9b3e8 | bellard | case A_IND_N:
|
1855 | fdf9b3e8 | bellard | case AS_IND_N:
|
1856 | fdf9b3e8 | bellard | fprintf_fn (stream, "@r%d", rn);
|
1857 | fdf9b3e8 | bellard | break;
|
1858 | fdf9b3e8 | bellard | case A_DISP_REG_N:
|
1859 | fdf9b3e8 | bellard | fprintf_fn (stream, "@(%d,r%d)", has_disp?disp:imm, rn);
|
1860 | fdf9b3e8 | bellard | break;
|
1861 | fdf9b3e8 | bellard | case AS_PMOD_N:
|
1862 | fdf9b3e8 | bellard | fprintf_fn (stream, "@r%d+r8", rn);
|
1863 | fdf9b3e8 | bellard | break;
|
1864 | fdf9b3e8 | bellard | case A_REG_M:
|
1865 | fdf9b3e8 | bellard | fprintf_fn (stream, "r%d", rm);
|
1866 | fdf9b3e8 | bellard | break;
|
1867 | fdf9b3e8 | bellard | case A_INC_M:
|
1868 | fdf9b3e8 | bellard | fprintf_fn (stream, "@r%d+", rm);
|
1869 | fdf9b3e8 | bellard | break;
|
1870 | fdf9b3e8 | bellard | case A_DEC_M:
|
1871 | fdf9b3e8 | bellard | fprintf_fn (stream, "@-r%d", rm);
|
1872 | fdf9b3e8 | bellard | break;
|
1873 | fdf9b3e8 | bellard | case A_IND_M:
|
1874 | fdf9b3e8 | bellard | fprintf_fn (stream, "@r%d", rm);
|
1875 | fdf9b3e8 | bellard | break;
|
1876 | fdf9b3e8 | bellard | case A_DISP_REG_M:
|
1877 | fdf9b3e8 | bellard | fprintf_fn (stream, "@(%d,r%d)", has_disp?disp:imm, rm);
|
1878 | fdf9b3e8 | bellard | break;
|
1879 | fdf9b3e8 | bellard | case A_REG_B:
|
1880 | fdf9b3e8 | bellard | fprintf_fn (stream, "r%d_bank", rb);
|
1881 | fdf9b3e8 | bellard | break;
|
1882 | fdf9b3e8 | bellard | case A_DISP_PC:
|
1883 | fdf9b3e8 | bellard | disp_pc = 1;
|
1884 | fdf9b3e8 | bellard | disp_pc_addr = imm + 4 + (memaddr & relmask);
|
1885 | fdf9b3e8 | bellard | (*info->print_address_func) (disp_pc_addr, info); |
1886 | fdf9b3e8 | bellard | break;
|
1887 | fdf9b3e8 | bellard | case A_IND_R0_REG_N:
|
1888 | fdf9b3e8 | bellard | fprintf_fn (stream, "@(r0,r%d)", rn);
|
1889 | fdf9b3e8 | bellard | break;
|
1890 | fdf9b3e8 | bellard | case A_IND_R0_REG_M:
|
1891 | fdf9b3e8 | bellard | fprintf_fn (stream, "@(r0,r%d)", rm);
|
1892 | fdf9b3e8 | bellard | break;
|
1893 | fdf9b3e8 | bellard | case A_DISP_GBR:
|
1894 | fdf9b3e8 | bellard | fprintf_fn (stream, "@(%d,gbr)", has_disp?disp:imm);
|
1895 | fdf9b3e8 | bellard | break;
|
1896 | fdf9b3e8 | bellard | case A_TBR:
|
1897 | fdf9b3e8 | bellard | fprintf_fn (stream, "tbr");
|
1898 | fdf9b3e8 | bellard | break;
|
1899 | fdf9b3e8 | bellard | case A_DISP2_TBR:
|
1900 | fdf9b3e8 | bellard | fprintf_fn (stream, "@@(%d,tbr)", has_disp?disp:imm);
|
1901 | fdf9b3e8 | bellard | break;
|
1902 | fdf9b3e8 | bellard | case A_INC_R15:
|
1903 | fdf9b3e8 | bellard | fprintf_fn (stream, "@r15+");
|
1904 | fdf9b3e8 | bellard | break;
|
1905 | fdf9b3e8 | bellard | case A_DEC_R15:
|
1906 | fdf9b3e8 | bellard | fprintf_fn (stream, "@-r15");
|
1907 | fdf9b3e8 | bellard | break;
|
1908 | fdf9b3e8 | bellard | case A_R0_GBR:
|
1909 | fdf9b3e8 | bellard | fprintf_fn (stream, "@(r0,gbr)");
|
1910 | fdf9b3e8 | bellard | break;
|
1911 | fdf9b3e8 | bellard | case A_BDISP12:
|
1912 | fdf9b3e8 | bellard | case A_BDISP8:
|
1913 | fdf9b3e8 | bellard | { |
1914 | fdf9b3e8 | bellard | bfd_vma addr; |
1915 | fdf9b3e8 | bellard | addr = imm + memaddr; |
1916 | fdf9b3e8 | bellard | (*info->print_address_func) (addr, info); |
1917 | fdf9b3e8 | bellard | } |
1918 | fdf9b3e8 | bellard | break;
|
1919 | fdf9b3e8 | bellard | case A_SR:
|
1920 | fdf9b3e8 | bellard | fprintf_fn (stream, "sr");
|
1921 | fdf9b3e8 | bellard | break;
|
1922 | fdf9b3e8 | bellard | case A_GBR:
|
1923 | fdf9b3e8 | bellard | fprintf_fn (stream, "gbr");
|
1924 | fdf9b3e8 | bellard | break;
|
1925 | fdf9b3e8 | bellard | case A_VBR:
|
1926 | fdf9b3e8 | bellard | fprintf_fn (stream, "vbr");
|
1927 | fdf9b3e8 | bellard | break;
|
1928 | fdf9b3e8 | bellard | case A_DSR:
|
1929 | fdf9b3e8 | bellard | fprintf_fn (stream, "dsr");
|
1930 | fdf9b3e8 | bellard | break;
|
1931 | fdf9b3e8 | bellard | case A_MOD:
|
1932 | fdf9b3e8 | bellard | fprintf_fn (stream, "mod");
|
1933 | fdf9b3e8 | bellard | break;
|
1934 | fdf9b3e8 | bellard | case A_RE:
|
1935 | fdf9b3e8 | bellard | fprintf_fn (stream, "re");
|
1936 | fdf9b3e8 | bellard | break;
|
1937 | fdf9b3e8 | bellard | case A_RS:
|
1938 | fdf9b3e8 | bellard | fprintf_fn (stream, "rs");
|
1939 | fdf9b3e8 | bellard | break;
|
1940 | fdf9b3e8 | bellard | case A_A0:
|
1941 | fdf9b3e8 | bellard | fprintf_fn (stream, "a0");
|
1942 | fdf9b3e8 | bellard | break;
|
1943 | fdf9b3e8 | bellard | case A_X0:
|
1944 | fdf9b3e8 | bellard | fprintf_fn (stream, "x0");
|
1945 | fdf9b3e8 | bellard | break;
|
1946 | fdf9b3e8 | bellard | case A_X1:
|
1947 | fdf9b3e8 | bellard | fprintf_fn (stream, "x1");
|
1948 | fdf9b3e8 | bellard | break;
|
1949 | fdf9b3e8 | bellard | case A_Y0:
|
1950 | fdf9b3e8 | bellard | fprintf_fn (stream, "y0");
|
1951 | fdf9b3e8 | bellard | break;
|
1952 | fdf9b3e8 | bellard | case A_Y1:
|
1953 | fdf9b3e8 | bellard | fprintf_fn (stream, "y1");
|
1954 | fdf9b3e8 | bellard | break;
|
1955 | fdf9b3e8 | bellard | case DSP_REG_M:
|
1956 | fdf9b3e8 | bellard | print_dsp_reg (rm, fprintf_fn, stream); |
1957 | fdf9b3e8 | bellard | break;
|
1958 | fdf9b3e8 | bellard | case A_SSR:
|
1959 | fdf9b3e8 | bellard | fprintf_fn (stream, "ssr");
|
1960 | fdf9b3e8 | bellard | break;
|
1961 | fdf9b3e8 | bellard | case A_SPC:
|
1962 | fdf9b3e8 | bellard | fprintf_fn (stream, "spc");
|
1963 | fdf9b3e8 | bellard | break;
|
1964 | fdf9b3e8 | bellard | case A_MACH:
|
1965 | fdf9b3e8 | bellard | fprintf_fn (stream, "mach");
|
1966 | fdf9b3e8 | bellard | break;
|
1967 | fdf9b3e8 | bellard | case A_MACL:
|
1968 | fdf9b3e8 | bellard | fprintf_fn (stream, "macl");
|
1969 | fdf9b3e8 | bellard | break;
|
1970 | fdf9b3e8 | bellard | case A_PR:
|
1971 | fdf9b3e8 | bellard | fprintf_fn (stream, "pr");
|
1972 | fdf9b3e8 | bellard | break;
|
1973 | fdf9b3e8 | bellard | case A_SGR:
|
1974 | fdf9b3e8 | bellard | fprintf_fn (stream, "sgr");
|
1975 | fdf9b3e8 | bellard | break;
|
1976 | fdf9b3e8 | bellard | case A_DBR:
|
1977 | fdf9b3e8 | bellard | fprintf_fn (stream, "dbr");
|
1978 | fdf9b3e8 | bellard | break;
|
1979 | fdf9b3e8 | bellard | case F_REG_N:
|
1980 | fdf9b3e8 | bellard | fprintf_fn (stream, "fr%d", rn);
|
1981 | fdf9b3e8 | bellard | break;
|
1982 | fdf9b3e8 | bellard | case F_REG_M:
|
1983 | fdf9b3e8 | bellard | fprintf_fn (stream, "fr%d", rm);
|
1984 | fdf9b3e8 | bellard | break;
|
1985 | fdf9b3e8 | bellard | case DX_REG_N:
|
1986 | fdf9b3e8 | bellard | if (rn & 1) |
1987 | fdf9b3e8 | bellard | { |
1988 | fdf9b3e8 | bellard | fprintf_fn (stream, "xd%d", rn & ~1); |
1989 | fdf9b3e8 | bellard | break;
|
1990 | fdf9b3e8 | bellard | } |
1991 | fdf9b3e8 | bellard | case D_REG_N:
|
1992 | fdf9b3e8 | bellard | fprintf_fn (stream, "dr%d", rn);
|
1993 | fdf9b3e8 | bellard | break;
|
1994 | fdf9b3e8 | bellard | case DX_REG_M:
|
1995 | fdf9b3e8 | bellard | if (rm & 1) |
1996 | fdf9b3e8 | bellard | { |
1997 | fdf9b3e8 | bellard | fprintf_fn (stream, "xd%d", rm & ~1); |
1998 | fdf9b3e8 | bellard | break;
|
1999 | fdf9b3e8 | bellard | } |
2000 | fdf9b3e8 | bellard | case D_REG_M:
|
2001 | fdf9b3e8 | bellard | fprintf_fn (stream, "dr%d", rm);
|
2002 | fdf9b3e8 | bellard | break;
|
2003 | fdf9b3e8 | bellard | case FPSCR_M:
|
2004 | fdf9b3e8 | bellard | case FPSCR_N:
|
2005 | fdf9b3e8 | bellard | fprintf_fn (stream, "fpscr");
|
2006 | fdf9b3e8 | bellard | break;
|
2007 | fdf9b3e8 | bellard | case FPUL_M:
|
2008 | fdf9b3e8 | bellard | case FPUL_N:
|
2009 | fdf9b3e8 | bellard | fprintf_fn (stream, "fpul");
|
2010 | fdf9b3e8 | bellard | break;
|
2011 | fdf9b3e8 | bellard | case F_FR0:
|
2012 | fdf9b3e8 | bellard | fprintf_fn (stream, "fr0");
|
2013 | fdf9b3e8 | bellard | break;
|
2014 | fdf9b3e8 | bellard | case V_REG_N:
|
2015 | fdf9b3e8 | bellard | fprintf_fn (stream, "fv%d", rn * 4); |
2016 | fdf9b3e8 | bellard | break;
|
2017 | fdf9b3e8 | bellard | case V_REG_M:
|
2018 | fdf9b3e8 | bellard | fprintf_fn (stream, "fv%d", rm * 4); |
2019 | fdf9b3e8 | bellard | break;
|
2020 | fdf9b3e8 | bellard | case XMTRX_M4:
|
2021 | fdf9b3e8 | bellard | fprintf_fn (stream, "xmtrx");
|
2022 | fdf9b3e8 | bellard | break;
|
2023 | fdf9b3e8 | bellard | default:
|
2024 | fdf9b3e8 | bellard | abort (); |
2025 | fdf9b3e8 | bellard | } |
2026 | fdf9b3e8 | bellard | } |
2027 | fdf9b3e8 | bellard | |
2028 | fdf9b3e8 | bellard | #if 0
|
2029 | fdf9b3e8 | bellard | /* This code prints instructions in delay slots on the same line
|
2030 | fdf9b3e8 | bellard | as the instruction which needs the delay slots. This can be
|
2031 | fdf9b3e8 | bellard | confusing, since other disassembler don't work this way, and
|
2032 | fdf9b3e8 | bellard | it means that the instructions are not all in a line. So I
|
2033 | fdf9b3e8 | bellard | disabled it. Ian. */
|
2034 | fdf9b3e8 | bellard | if (!(info->flags & 1)
|
2035 | fdf9b3e8 | bellard | && (op->name[0] == 'j'
|
2036 | fdf9b3e8 | bellard | || (op->name[0] == 'b'
|
2037 | fdf9b3e8 | bellard | && (op->name[1] == 'r'
|
2038 | fdf9b3e8 | bellard | || op->name[1] == 's'))
|
2039 | fdf9b3e8 | bellard | || (op->name[0] == 'r' && op->name[1] == 't')
|
2040 | fdf9b3e8 | bellard | || (op->name[0] == 'b' && op->name[2] == '.')))
|
2041 | fdf9b3e8 | bellard | {
|
2042 | fdf9b3e8 | bellard | info->flags |= 1;
|
2043 | fdf9b3e8 | bellard | fprintf_fn (stream, "\t(slot ");
|
2044 | fdf9b3e8 | bellard | print_insn_sh (memaddr + 2, info);
|
2045 | fdf9b3e8 | bellard | info->flags &= ~1;
|
2046 | fdf9b3e8 | bellard | fprintf_fn (stream, ")");
|
2047 | fdf9b3e8 | bellard | return 4;
|
2048 | fdf9b3e8 | bellard | }
|
2049 | fdf9b3e8 | bellard | #endif
|
2050 | fdf9b3e8 | bellard | |
2051 | fdf9b3e8 | bellard | if (disp_pc && strcmp (op->name, "mova") != 0) |
2052 | fdf9b3e8 | bellard | { |
2053 | fdf9b3e8 | bellard | int size;
|
2054 | fdf9b3e8 | bellard | bfd_byte bytes[4];
|
2055 | fdf9b3e8 | bellard | |
2056 | fdf9b3e8 | bellard | if (relmask == ~(bfd_vma) 1) |
2057 | fdf9b3e8 | bellard | size = 2;
|
2058 | fdf9b3e8 | bellard | else
|
2059 | fdf9b3e8 | bellard | size = 4;
|
2060 | fdf9b3e8 | bellard | status = info->read_memory_func (disp_pc_addr, bytes, size, info); |
2061 | fdf9b3e8 | bellard | if (status == 0) |
2062 | fdf9b3e8 | bellard | { |
2063 | fdf9b3e8 | bellard | unsigned int val; |
2064 | fdf9b3e8 | bellard | |
2065 | fdf9b3e8 | bellard | if (size == 2) |
2066 | fdf9b3e8 | bellard | { |
2067 | fdf9b3e8 | bellard | if (info->endian == BFD_ENDIAN_LITTLE)
|
2068 | fdf9b3e8 | bellard | val = bfd_getl16 (bytes); |
2069 | fdf9b3e8 | bellard | else
|
2070 | fdf9b3e8 | bellard | val = bfd_getb16 (bytes); |
2071 | fdf9b3e8 | bellard | } |
2072 | fdf9b3e8 | bellard | else
|
2073 | fdf9b3e8 | bellard | { |
2074 | fdf9b3e8 | bellard | if (info->endian == BFD_ENDIAN_LITTLE)
|
2075 | fdf9b3e8 | bellard | val = bfd_getl32 (bytes); |
2076 | fdf9b3e8 | bellard | else
|
2077 | fdf9b3e8 | bellard | val = bfd_getb32 (bytes); |
2078 | fdf9b3e8 | bellard | } |
2079 | fdf9b3e8 | bellard | if ((*info->symbol_at_address_func) (val, info))
|
2080 | fdf9b3e8 | bellard | { |
2081 | fdf9b3e8 | bellard | fprintf_fn (stream, "\t! 0x");
|
2082 | fdf9b3e8 | bellard | (*info->print_address_func) (val, info); |
2083 | fdf9b3e8 | bellard | } |
2084 | fdf9b3e8 | bellard | else
|
2085 | fdf9b3e8 | bellard | fprintf_fn (stream, "\t! 0x%x", val);
|
2086 | fdf9b3e8 | bellard | } |
2087 | fdf9b3e8 | bellard | } |
2088 | fdf9b3e8 | bellard | |
2089 | fdf9b3e8 | bellard | return SH_MERGE_ARCH_SET (op->arch, arch_op32) ? 4 : 2; |
2090 | fdf9b3e8 | bellard | fail:
|
2091 | fdf9b3e8 | bellard | ; |
2092 | fdf9b3e8 | bellard | |
2093 | fdf9b3e8 | bellard | } |
2094 | fdf9b3e8 | bellard | fprintf_fn (stream, ".word 0x%x%x%x%x", nibs[0], nibs[1], nibs[2], nibs[3]); |
2095 | fdf9b3e8 | bellard | return 2; |
2096 | fdf9b3e8 | bellard | } |