root / target-mips / fop_template.c @ 86cc1ce0
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1 | 6ea83fed | bellard | /*
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2 | 6ea83fed | bellard | * MIPS emulation micro-operations templates for floating point reg
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3 | 6ea83fed | bellard | * load & store for qemu.
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4 | 6ea83fed | bellard | *
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5 | 6ea83fed | bellard | * Copyright (c) 2006 Marius Groeger
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6 | 6ea83fed | bellard | *
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7 | 6ea83fed | bellard | * This library is free software; you can redistribute it and/or
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8 | 6ea83fed | bellard | * modify it under the terms of the GNU Lesser General Public
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9 | 6ea83fed | bellard | * License as published by the Free Software Foundation; either
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10 | 6ea83fed | bellard | * version 2 of the License, or (at your option) any later version.
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11 | 6ea83fed | bellard | *
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12 | 6ea83fed | bellard | * This library is distributed in the hope that it will be useful,
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13 | 6ea83fed | bellard | * but WITHOUT ANY WARRANTY; without even the implied warranty of
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14 | 6ea83fed | bellard | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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15 | 6ea83fed | bellard | * Lesser General Public License for more details.
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16 | 6ea83fed | bellard | *
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17 | 6ea83fed | bellard | * You should have received a copy of the GNU Lesser General Public
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18 | 6ea83fed | bellard | * License along with this library; if not, write to the Free Software
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19 | 6ea83fed | bellard | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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20 | 6ea83fed | bellard | */
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21 | 6ea83fed | bellard | |
22 | 6ea83fed | bellard | #if defined(SFREG)
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23 | 6ea83fed | bellard | |
24 | 6ea83fed | bellard | #define OP_WLOAD_FREG(treg, tregname, SFREG) \
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25 | 6ea83fed | bellard | void glue(glue(op_load_fpr_,tregname), SFREG) (void) \ |
26 | 6ea83fed | bellard | { \ |
27 | 6ea83fed | bellard | treg = FPR_W(env, SFREG); \ |
28 | 6ea83fed | bellard | RETURN(); \ |
29 | 6ea83fed | bellard | } |
30 | 6ea83fed | bellard | |
31 | 6ea83fed | bellard | #define OP_WSTORE_FREG(treg, tregname, SFREG) \
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32 | 6ea83fed | bellard | void glue(glue(op_store_fpr_,tregname), SFREG) (void)\ |
33 | 6ea83fed | bellard | { \ |
34 | 6ea83fed | bellard | FPR_W(env, SFREG) = treg; \ |
35 | 6ea83fed | bellard | RETURN(); \ |
36 | 6ea83fed | bellard | } |
37 | 6ea83fed | bellard | |
38 | 6ea83fed | bellard | /* WT0 = SFREG.w: op_load_fpr_WT0_fprSFREG */
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39 | 6ea83fed | bellard | OP_WLOAD_FREG(WT0, WT0_fpr, SFREG) |
40 | 6ea83fed | bellard | /* SFREG.w = WT0: op_store_fpr_WT0_fprSFREG */
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41 | 6ea83fed | bellard | OP_WSTORE_FREG(WT0, WT0_fpr, SFREG) |
42 | 6ea83fed | bellard | |
43 | 6ea83fed | bellard | OP_WLOAD_FREG(WT1, WT1_fpr, SFREG) |
44 | 6ea83fed | bellard | OP_WSTORE_FREG(WT1, WT1_fpr, SFREG) |
45 | 6ea83fed | bellard | |
46 | 6ea83fed | bellard | OP_WLOAD_FREG(WT2, WT2_fpr, SFREG) |
47 | 6ea83fed | bellard | OP_WSTORE_FREG(WT2, WT2_fpr, SFREG) |
48 | 6ea83fed | bellard | |
49 | 6ea83fed | bellard | #endif
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50 | 6ea83fed | bellard | |
51 | 6ea83fed | bellard | #if defined(DFREG)
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52 | 6ea83fed | bellard | |
53 | 6ea83fed | bellard | #define OP_DLOAD_FREG(treg, tregname, DFREG) \
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54 | 6ea83fed | bellard | void glue(glue(op_load_fpr_,tregname), DFREG) (void) \ |
55 | 6ea83fed | bellard | { \ |
56 | 6ea83fed | bellard | treg = FPR_D(env, DFREG); \ |
57 | 6ea83fed | bellard | RETURN(); \ |
58 | 6ea83fed | bellard | } |
59 | 6ea83fed | bellard | |
60 | 6ea83fed | bellard | #define OP_DSTORE_FREG(treg, tregname, DFREG) \
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61 | 6ea83fed | bellard | void glue(glue(op_store_fpr_,tregname), DFREG) (void)\ |
62 | 6ea83fed | bellard | { \ |
63 | 6ea83fed | bellard | FPR_D(env, DFREG) = treg; \ |
64 | 6ea83fed | bellard | RETURN(); \ |
65 | 6ea83fed | bellard | } |
66 | 6ea83fed | bellard | |
67 | 6ea83fed | bellard | OP_DLOAD_FREG(DT0, DT0_fpr, DFREG) |
68 | 6ea83fed | bellard | OP_DSTORE_FREG(DT0, DT0_fpr, DFREG) |
69 | 6ea83fed | bellard | |
70 | 6ea83fed | bellard | OP_DLOAD_FREG(DT1, DT1_fpr, DFREG) |
71 | 6ea83fed | bellard | OP_DSTORE_FREG(DT1, DT1_fpr, DFREG) |
72 | 6ea83fed | bellard | |
73 | 6ea83fed | bellard | OP_DLOAD_FREG(DT2, DT2_fpr, DFREG) |
74 | 6ea83fed | bellard | OP_DSTORE_FREG(DT2, DT2_fpr, DFREG) |
75 | 6ea83fed | bellard | |
76 | 6ea83fed | bellard | #endif
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77 | 6ea83fed | bellard | |
78 | 6ea83fed | bellard | #if defined (FTN)
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79 | 6ea83fed | bellard | |
80 | 6ea83fed | bellard | #define SET_RESET(treg, tregname) \
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81 | 6ea83fed | bellard | void glue(op_set, tregname)(void) \ |
82 | 6ea83fed | bellard | { \ |
83 | 6ea83fed | bellard | treg = PARAM1; \ |
84 | 6ea83fed | bellard | RETURN(); \ |
85 | 6ea83fed | bellard | } \ |
86 | 6ea83fed | bellard | void glue(op_reset, tregname)(void) \ |
87 | 6ea83fed | bellard | { \ |
88 | 6ea83fed | bellard | treg = 0; \
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89 | 6ea83fed | bellard | RETURN(); \ |
90 | 6ea83fed | bellard | } \ |
91 | 6ea83fed | bellard | |
92 | 6ea83fed | bellard | SET_RESET(WT0, _WT0) |
93 | 6ea83fed | bellard | SET_RESET(WT1, _WT1) |
94 | 6ea83fed | bellard | SET_RESET(WT2, _WT2) |
95 | 6ea83fed | bellard | SET_RESET(DT0, _DT0) |
96 | 6ea83fed | bellard | SET_RESET(DT1, _DT1) |
97 | 6ea83fed | bellard | SET_RESET(DT2, _DT2) |
98 | 6ea83fed | bellard | |
99 | c570fd16 | ths | #undef SET_RESET
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100 | 6ea83fed | bellard | #endif |