root / target-ppc / cpu.h @ 86cc1ce0
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1 | 79aceca5 | bellard | /*
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2 | 3fc6c082 | bellard | * PowerPC emulation cpu definitions for qemu.
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3 | 79aceca5 | bellard | *
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4 | 76a66253 | j_mayer | * Copyright (c) 2003-2007 Jocelyn Mayer
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5 | 79aceca5 | bellard | *
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6 | 79aceca5 | bellard | * This library is free software; you can redistribute it and/or
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7 | 79aceca5 | bellard | * modify it under the terms of the GNU Lesser General Public
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8 | 79aceca5 | bellard | * License as published by the Free Software Foundation; either
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9 | 79aceca5 | bellard | * version 2 of the License, or (at your option) any later version.
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10 | 79aceca5 | bellard | *
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11 | 79aceca5 | bellard | * This library is distributed in the hope that it will be useful,
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12 | 79aceca5 | bellard | * but WITHOUT ANY WARRANTY; without even the implied warranty of
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13 | 79aceca5 | bellard | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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14 | 79aceca5 | bellard | * Lesser General Public License for more details.
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15 | 79aceca5 | bellard | *
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16 | 79aceca5 | bellard | * You should have received a copy of the GNU Lesser General Public
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17 | 79aceca5 | bellard | * License along with this library; if not, write to the Free Software
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18 | 79aceca5 | bellard | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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19 | 79aceca5 | bellard | */
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20 | 79aceca5 | bellard | #if !defined (__CPU_PPC_H__)
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21 | 79aceca5 | bellard | #define __CPU_PPC_H__
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22 | 79aceca5 | bellard | |
23 | 3fc6c082 | bellard | #include "config.h" |
24 | de270b3c | j_mayer | #include <inttypes.h> |
25 | 3fc6c082 | bellard | |
26 | 51789c41 | j_mayer | #if defined(TARGET_PPC64) || (HOST_LONG_BITS >= 64) |
27 | 51789c41 | j_mayer | /* When using 64 bits temporary registers,
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28 | 51789c41 | j_mayer | * we can use 64 bits GPR with no extra cost
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29 | 51789c41 | j_mayer | */
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30 | 51789c41 | j_mayer | #define TARGET_PPCSPE
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31 | 51789c41 | j_mayer | #endif
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32 | 51789c41 | j_mayer | |
33 | 76a66253 | j_mayer | #if defined (TARGET_PPC64)
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34 | 76a66253 | j_mayer | typedef uint64_t ppc_gpr_t;
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35 | 76a66253 | j_mayer | #define TARGET_LONG_BITS 64 |
36 | 0487d6a8 | j_mayer | #define TARGET_GPR_BITS 64 |
37 | 76a66253 | j_mayer | #define REGX "%016" PRIx64 |
38 | 1b9eb036 | j_mayer | #define ADDRX "%016" PRIx64 |
39 | 0487d6a8 | j_mayer | #elif defined(TARGET_PPCSPE)
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40 | 76a66253 | j_mayer | /* GPR are 64 bits: used by vector extension */
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41 | 76a66253 | j_mayer | typedef uint64_t ppc_gpr_t;
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42 | 3cf1e035 | bellard | #define TARGET_LONG_BITS 32 |
43 | 0487d6a8 | j_mayer | #define TARGET_GPR_BITS 64 |
44 | 1b9eb036 | j_mayer | #define REGX "%016" PRIx64 |
45 | 1b9eb036 | j_mayer | #define ADDRX "%08" PRIx32 |
46 | 76a66253 | j_mayer | #else
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47 | 76a66253 | j_mayer | typedef uint32_t ppc_gpr_t;
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48 | 76a66253 | j_mayer | #define TARGET_LONG_BITS 32 |
49 | 0487d6a8 | j_mayer | #define TARGET_GPR_BITS 32 |
50 | 76a66253 | j_mayer | #define REGX "%08" PRIx32 |
51 | 1b9eb036 | j_mayer | #define ADDRX "%08" PRIx32 |
52 | 76a66253 | j_mayer | #endif
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53 | 3cf1e035 | bellard | |
54 | 79aceca5 | bellard | #include "cpu-defs.h" |
55 | 79aceca5 | bellard | |
56 | 79aceca5 | bellard | #include <setjmp.h> |
57 | 79aceca5 | bellard | |
58 | 4ecc3190 | bellard | #include "softfloat.h" |
59 | 4ecc3190 | bellard | |
60 | 1fddef4b | bellard | #define TARGET_HAS_ICE 1 |
61 | 1fddef4b | bellard | |
62 | 76a66253 | j_mayer | #if defined (TARGET_PPC64)
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63 | 76a66253 | j_mayer | #define ELF_MACHINE EM_PPC64
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64 | 76a66253 | j_mayer | #else
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65 | 76a66253 | j_mayer | #define ELF_MACHINE EM_PPC
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66 | 76a66253 | j_mayer | #endif
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67 | 9042c0e2 | ths | |
68 | fdabc366 | bellard | /* XXX: this should be tunable: PowerPC 601 & 64 bits PowerPC
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69 | fdabc366 | bellard | * have different cache line sizes
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70 | fdabc366 | bellard | */
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71 | fdabc366 | bellard | #define ICACHE_LINE_SIZE 32 |
72 | fdabc366 | bellard | #define DCACHE_LINE_SIZE 32 |
73 | fdabc366 | bellard | |
74 | fdabc366 | bellard | /* XXX: put this in a common place */
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75 | fdabc366 | bellard | #define likely(x) __builtin_expect(!!(x), 1) |
76 | 76a66253 | j_mayer | #define unlikely(x) __builtin_expect(!!(x), 0) |
77 | fdabc366 | bellard | |
78 | 3fc6c082 | bellard | /*****************************************************************************/
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79 | 3fc6c082 | bellard | /* PVR definitions for most known PowerPC */
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80 | 3fc6c082 | bellard | enum {
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81 | 3fc6c082 | bellard | /* PowerPC 401 cores */
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82 | 3fc6c082 | bellard | CPU_PPC_401A1 = 0x00210000,
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83 | 3fc6c082 | bellard | CPU_PPC_401B2 = 0x00220000,
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84 | 3fc6c082 | bellard | CPU_PPC_401C2 = 0x00230000,
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85 | 3fc6c082 | bellard | CPU_PPC_401D2 = 0x00240000,
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86 | 3fc6c082 | bellard | CPU_PPC_401E2 = 0x00250000,
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87 | 3fc6c082 | bellard | CPU_PPC_401F2 = 0x00260000,
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88 | 3fc6c082 | bellard | CPU_PPC_401G2 = 0x00270000,
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89 | 76a66253 | j_mayer | #define CPU_PPC_401 CPU_PPC_401G2
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90 | 76a66253 | j_mayer | CPU_PPC_IOP480 = 0x40100000, /* 401B2 ? */ |
91 | 76a66253 | j_mayer | CPU_PPC_COBRA = 0x10100000, /* IBM Processor for Network Resources */ |
92 | 3fc6c082 | bellard | /* PowerPC 403 cores */
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93 | 76a66253 | j_mayer | CPU_PPC_403GA = 0x00200011,
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94 | 3fc6c082 | bellard | CPU_PPC_403GB = 0x00200100,
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95 | 3fc6c082 | bellard | CPU_PPC_403GC = 0x00200200,
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96 | 3fc6c082 | bellard | CPU_PPC_403GCX = 0x00201400,
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97 | 76a66253 | j_mayer | #define CPU_PPC_403 CPU_PPC_403GCX
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98 | 3fc6c082 | bellard | /* PowerPC 405 cores */
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99 | 76a66253 | j_mayer | CPU_PPC_405CR = 0x40110145,
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100 | 76a66253 | j_mayer | #define CPU_PPC_405GP CPU_PPC_405CR
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101 | 76a66253 | j_mayer | CPU_PPC_405EP = 0x51210950,
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102 | 76a66253 | j_mayer | CPU_PPC_405GPR = 0x50910951,
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103 | 3fc6c082 | bellard | CPU_PPC_405D2 = 0x20010000,
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104 | 3fc6c082 | bellard | CPU_PPC_405D4 = 0x41810000,
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105 | 76a66253 | j_mayer | #define CPU_PPC_405 CPU_PPC_405D4
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106 | 76a66253 | j_mayer | CPU_PPC_NPE405H = 0x414100C0,
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107 | 76a66253 | j_mayer | CPU_PPC_NPE405H2 = 0x41410140,
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108 | 76a66253 | j_mayer | CPU_PPC_NPE405L = 0x416100C0,
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109 | 76a66253 | j_mayer | /* XXX: missing 405LP, LC77700 */
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110 | 76a66253 | j_mayer | /* IBM STBxxx (PowerPC 401/403/405 core based microcontrollers) */
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111 | 76a66253 | j_mayer | #if 0
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112 | 76a66253 | j_mayer | CPU_PPC_STB01000 = xxx,
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113 | 76a66253 | j_mayer | #endif
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114 | 3fc6c082 | bellard | #if 0
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115 | 76a66253 | j_mayer | CPU_PPC_STB01010 = xxx,
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116 | 76a66253 | j_mayer | #endif
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117 | 76a66253 | j_mayer | #if 0
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118 | 76a66253 | j_mayer | CPU_PPC_STB0210 = xxx,
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119 | 3fc6c082 | bellard | #endif
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120 | 3fc6c082 | bellard | CPU_PPC_STB03 = 0x40310000,
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121 | 3fc6c082 | bellard | #if 0
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122 | 76a66253 | j_mayer | CPU_PPC_STB043 = xxx,
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123 | 3fc6c082 | bellard | #endif
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124 | 76a66253 | j_mayer | #if 0
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125 | 76a66253 | j_mayer | CPU_PPC_STB045 = xxx,
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126 | 76a66253 | j_mayer | #endif
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127 | 76a66253 | j_mayer | CPU_PPC_STB25 = 0x51510950,
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128 | 3fc6c082 | bellard | #if 0
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129 | 3fc6c082 | bellard | CPU_PPC_STB130 = xxx,
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130 | 3fc6c082 | bellard | #endif
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131 | 76a66253 | j_mayer | /* Xilinx cores */
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132 | 76a66253 | j_mayer | CPU_PPC_X2VP4 = 0x20010820,
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133 | 76a66253 | j_mayer | #define CPU_PPC_X2VP7 CPU_PPC_X2VP4
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134 | 76a66253 | j_mayer | CPU_PPC_X2VP20 = 0x20010860,
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135 | 76a66253 | j_mayer | #define CPU_PPC_X2VP50 CPU_PPC_X2VP20
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136 | 3fc6c082 | bellard | /* PowerPC 440 cores */
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137 | 76a66253 | j_mayer | CPU_PPC_440EP = 0x422218D3,
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138 | 76a66253 | j_mayer | #define CPU_PPC_440GR CPU_PPC_440EP
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139 | 76a66253 | j_mayer | CPU_PPC_440GP = 0x40120481,
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140 | 76a66253 | j_mayer | CPU_PPC_440GX = 0x51B21850,
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141 | 76a66253 | j_mayer | CPU_PPC_440GXc = 0x51B21892,
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142 | 76a66253 | j_mayer | CPU_PPC_440GXf = 0x51B21894,
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143 | 76a66253 | j_mayer | CPU_PPC_440SP = 0x53221850,
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144 | 76a66253 | j_mayer | CPU_PPC_440SP2 = 0x53221891,
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145 | 76a66253 | j_mayer | CPU_PPC_440SPE = 0x53421890,
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146 | 76a66253 | j_mayer | /* XXX: missing 440GRX */
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147 | 76a66253 | j_mayer | /* PowerPC 460 cores - TODO */
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148 | 76a66253 | j_mayer | /* PowerPC MPC 5xx cores */
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149 | 76a66253 | j_mayer | CPU_PPC_5xx = 0x00020020,
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150 | 76a66253 | j_mayer | /* PowerPC MPC 8xx cores (aka PowerQUICC) */
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151 | 3fc6c082 | bellard | CPU_PPC_8xx = 0x00500000,
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152 | 76a66253 | j_mayer | /* PowerPC MPC 8xxx cores (aka PowerQUICC-II) */
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153 | 76a66253 | j_mayer | CPU_PPC_82xx_HIP3 = 0x00810101,
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154 | 76a66253 | j_mayer | CPU_PPC_82xx_HIP4 = 0x80811014,
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155 | 76a66253 | j_mayer | CPU_PPC_827x = 0x80822013,
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156 | 76a66253 | j_mayer | /* eCores */
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157 | 76a66253 | j_mayer | CPU_PPC_e200 = 0x81120000,
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158 | 76a66253 | j_mayer | CPU_PPC_e500v110 = 0x80200010,
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159 | 76a66253 | j_mayer | CPU_PPC_e500v120 = 0x80200020,
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160 | 76a66253 | j_mayer | CPU_PPC_e500v210 = 0x80210010,
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161 | 76a66253 | j_mayer | CPU_PPC_e500v220 = 0x80210020,
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162 | 76a66253 | j_mayer | #define CPU_PPC_e500 CPU_PPC_e500v220
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163 | 76a66253 | j_mayer | CPU_PPC_e600 = 0x80040010,
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164 | 3fc6c082 | bellard | /* PowerPC 6xx cores */
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165 | 76a66253 | j_mayer | CPU_PPC_601 = 0x00010001,
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166 | 76a66253 | j_mayer | CPU_PPC_602 = 0x00050100,
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167 | 76a66253 | j_mayer | CPU_PPC_603 = 0x00030100,
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168 | 76a66253 | j_mayer | CPU_PPC_603E = 0x00060101,
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169 | 76a66253 | j_mayer | CPU_PPC_603P = 0x00070000,
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170 | 76a66253 | j_mayer | CPU_PPC_603E7v = 0x00070100,
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171 | 76a66253 | j_mayer | CPU_PPC_603E7v2 = 0x00070201,
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172 | 76a66253 | j_mayer | CPU_PPC_603E7 = 0x00070200,
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173 | 76a66253 | j_mayer | CPU_PPC_603R = 0x00071201,
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174 | 76a66253 | j_mayer | CPU_PPC_G2 = 0x00810011,
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175 | 76a66253 | j_mayer | CPU_PPC_G2H4 = 0x80811010,
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176 | 76a66253 | j_mayer | CPU_PPC_G2gp = 0x80821010,
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177 | 76a66253 | j_mayer | CPU_PPC_G2ls = 0x90810010,
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178 | 76a66253 | j_mayer | CPU_PPC_G2LE = 0x80820010,
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179 | 76a66253 | j_mayer | CPU_PPC_G2LEgp = 0x80822010,
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180 | 76a66253 | j_mayer | CPU_PPC_G2LEls = 0xA0822010,
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181 | 3fc6c082 | bellard | CPU_PPC_604 = 0x00040000,
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182 | 76a66253 | j_mayer | CPU_PPC_604E = 0x00090100, /* Also 2110 & 2120 */ |
183 | 76a66253 | j_mayer | CPU_PPC_604R = 0x000a0101,
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184 | 3fc6c082 | bellard | /* PowerPC 74x/75x cores (aka G3) */
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185 | 3fc6c082 | bellard | CPU_PPC_74x = 0x00080000,
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186 | 76a66253 | j_mayer | CPU_PPC_740E = 0x00080100,
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187 | 76a66253 | j_mayer | CPU_PPC_750E = 0x00080200,
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188 | 76a66253 | j_mayer | CPU_PPC_755_10 = 0x00083100,
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189 | 76a66253 | j_mayer | CPU_PPC_755_11 = 0x00083101,
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190 | 76a66253 | j_mayer | CPU_PPC_755_20 = 0x00083200,
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191 | 76a66253 | j_mayer | CPU_PPC_755D = 0x00083202,
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192 | 76a66253 | j_mayer | CPU_PPC_755E = 0x00083203,
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193 | 76a66253 | j_mayer | #define CPU_PPC_755 CPU_PPC_755E
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194 | 3fc6c082 | bellard | CPU_PPC_74xP = 0x10080000,
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195 | 76a66253 | j_mayer | CPU_PPC_750CXE21 = 0x00082201,
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196 | 76a66253 | j_mayer | CPU_PPC_750CXE22 = 0x00082212,
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197 | 76a66253 | j_mayer | CPU_PPC_750CXE23 = 0x00082203,
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198 | 3fc6c082 | bellard | CPU_PPC_750CXE24 = 0x00082214,
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199 | 3fc6c082 | bellard | CPU_PPC_750CXE24b = 0x00083214,
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200 | 3fc6c082 | bellard | CPU_PPC_750CXE31 = 0x00083211,
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201 | 3fc6c082 | bellard | CPU_PPC_750CXE31b = 0x00083311,
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202 | 3fc6c082 | bellard | #define CPU_PPC_750CXE CPU_PPC_750CXE31b
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203 | 76a66253 | j_mayer | CPU_PPC_750CXR = 0x00083410,
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204 | 76a66253 | j_mayer | CPU_PPC_750FX10 = 0x70000100,
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205 | 76a66253 | j_mayer | CPU_PPC_750FX20 = 0x70000200,
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206 | 76a66253 | j_mayer | CPU_PPC_750FX21 = 0x70000201,
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207 | 76a66253 | j_mayer | CPU_PPC_750FX22 = 0x70000202,
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208 | 76a66253 | j_mayer | CPU_PPC_750FX23 = 0x70000203,
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209 | 76a66253 | j_mayer | #define CPU_PPC_750FX CPU_PPC_750FX23
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210 | 76a66253 | j_mayer | CPU_PPC_750FL = 0x700A0203,
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211 | 76a66253 | j_mayer | CPU_PPC_750GX10 = 0x70020100,
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212 | 76a66253 | j_mayer | CPU_PPC_750GX11 = 0x70020101,
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213 | 76a66253 | j_mayer | CPU_PPC_750GX12 = 0x70020102,
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214 | 76a66253 | j_mayer | #define CPU_PPC_750GX CPU_PPC_750GX12
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215 | 76a66253 | j_mayer | CPU_PPC_750GL = 0x70020102,
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216 | 76a66253 | j_mayer | CPU_PPC_750L30 = 0x00088300,
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217 | 76a66253 | j_mayer | CPU_PPC_750L32 = 0x00088302,
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218 | 76a66253 | j_mayer | CPU_PPC_750CL = 0x00087200,
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219 | 3fc6c082 | bellard | /* PowerPC 74xx cores (aka G4) */
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220 | 76a66253 | j_mayer | CPU_PPC_7400 = 0x000C0100,
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221 | 76a66253 | j_mayer | CPU_PPC_7410C = 0x800C1102,
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222 | 76a66253 | j_mayer | CPU_PPC_7410D = 0x800C1103,
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223 | 76a66253 | j_mayer | CPU_PPC_7410E = 0x800C1104,
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224 | 76a66253 | j_mayer | CPU_PPC_7441 = 0x80000210,
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225 | 76a66253 | j_mayer | CPU_PPC_7445 = 0x80010100,
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226 | 76a66253 | j_mayer | CPU_PPC_7447 = 0x80020100,
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227 | 76a66253 | j_mayer | CPU_PPC_7447A = 0x80030101,
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228 | 76a66253 | j_mayer | CPU_PPC_7448 = 0x80040100,
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229 | 76a66253 | j_mayer | CPU_PPC_7450 = 0x80000200,
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230 | 76a66253 | j_mayer | CPU_PPC_7450b = 0x80000201,
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231 | 3fc6c082 | bellard | CPU_PPC_7451 = 0x80000203,
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232 | 76a66253 | j_mayer | CPU_PPC_7451G = 0x80000210,
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233 | 76a66253 | j_mayer | CPU_PPC_7455 = 0x80010201,
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234 | 76a66253 | j_mayer | CPU_PPC_7455F = 0x80010303,
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235 | 76a66253 | j_mayer | CPU_PPC_7455G = 0x80010304,
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236 | 76a66253 | j_mayer | CPU_PPC_7457 = 0x80020101,
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237 | 76a66253 | j_mayer | CPU_PPC_7457C = 0x80020102,
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238 | 3fc6c082 | bellard | CPU_PPC_7457A = 0x80030000,
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239 | 3fc6c082 | bellard | /* 64 bits PowerPC */
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240 | 3fc6c082 | bellard | CPU_PPC_620 = 0x00140000,
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241 | 3fc6c082 | bellard | CPU_PPC_630 = 0x00400000,
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242 | 3fc6c082 | bellard | CPU_PPC_631 = 0x00410000,
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243 | 3fc6c082 | bellard | CPU_PPC_POWER4 = 0x00350000,
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244 | 3fc6c082 | bellard | CPU_PPC_POWER4P = 0x00380000,
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245 | 3fc6c082 | bellard | CPU_PPC_POWER5 = 0x003A0000,
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246 | 3fc6c082 | bellard | CPU_PPC_POWER5P = 0x003B0000,
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247 | 3fc6c082 | bellard | CPU_PPC_970 = 0x00390000,
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248 | 76a66253 | j_mayer | CPU_PPC_970FX10 = 0x00391100,
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249 | 76a66253 | j_mayer | CPU_PPC_970FX20 = 0x003C0200,
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250 | 76a66253 | j_mayer | CPU_PPC_970FX21 = 0x003C0201,
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251 | 76a66253 | j_mayer | CPU_PPC_970FX30 = 0x003C0300,
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252 | 76a66253 | j_mayer | CPU_PPC_970FX31 = 0x003C0301,
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253 | 76a66253 | j_mayer | #define CPU_PPC_970FX CPU_PPC_970FX31
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254 | 76a66253 | j_mayer | CPU_PPC_970MP10 = 0x00440100,
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255 | 76a66253 | j_mayer | CPU_PPC_970MP11 = 0x00440101,
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256 | 76a66253 | j_mayer | #define CPU_PPC_970MP CPU_PPC_970MP11
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257 | 76a66253 | j_mayer | CPU_PPC_CELL10 = 0x00700100,
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258 | 76a66253 | j_mayer | CPU_PPC_CELL20 = 0x00700400,
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259 | 76a66253 | j_mayer | CPU_PPC_CELL30 = 0x00700500,
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260 | 76a66253 | j_mayer | CPU_PPC_CELL31 = 0x00700501,
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261 | 76a66253 | j_mayer | #define CPU_PPC_CELL32 CPU_PPC_CELL31
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262 | 76a66253 | j_mayer | #define CPU_PPC_CELL CPU_PPC_CELL32
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263 | 3fc6c082 | bellard | CPU_PPC_RS64 = 0x00330000,
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264 | 3fc6c082 | bellard | CPU_PPC_RS64II = 0x00340000,
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265 | 3fc6c082 | bellard | CPU_PPC_RS64III = 0x00360000,
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266 | 3fc6c082 | bellard | CPU_PPC_RS64IV = 0x00370000,
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267 | 3fc6c082 | bellard | /* Original POWER */
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268 | 3fc6c082 | bellard | /* XXX: should be POWER (RIOS), RSC3308, RSC4608,
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269 | 3fc6c082 | bellard | * POWER2 (RIOS2) & RSC2 (P2SC) here
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270 | 3fc6c082 | bellard | */
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271 | 3fc6c082 | bellard | #if 0
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272 | 3fc6c082 | bellard | CPU_POWER = xxx,
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273 | 3fc6c082 | bellard | #endif
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274 | 3fc6c082 | bellard | #if 0
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275 | 3fc6c082 | bellard | CPU_POWER2 = xxx,
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276 | 3fc6c082 | bellard | #endif
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277 | 3fc6c082 | bellard | }; |
278 | 3fc6c082 | bellard | |
279 | 76a66253 | j_mayer | /* System version register (used on MPC 8xxx) */
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280 | 3fc6c082 | bellard | enum {
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281 | 3fc6c082 | bellard | PPC_SVR_8540 = 0x80300000,
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282 | 76a66253 | j_mayer | PPC_SVR_8541E = 0x807A0010,
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283 | 76a66253 | j_mayer | PPC_SVR_8543v10 = 0x80320010,
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284 | 76a66253 | j_mayer | PPC_SVR_8543v11 = 0x80320011,
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285 | 76a66253 | j_mayer | PPC_SVR_8543v20 = 0x80320020,
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286 | 76a66253 | j_mayer | PPC_SVR_8543Ev10 = 0x803A0010,
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287 | 76a66253 | j_mayer | PPC_SVR_8543Ev11 = 0x803A0011,
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288 | 76a66253 | j_mayer | PPC_SVR_8543Ev20 = 0x803A0020,
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289 | 76a66253 | j_mayer | PPC_SVR_8545 = 0x80310220,
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290 | 76a66253 | j_mayer | PPC_SVR_8545E = 0x80390220,
|
291 | 76a66253 | j_mayer | PPC_SVR_8547E = 0x80390120,
|
292 | 76a66253 | j_mayer | PPC_SCR_8548v10 = 0x80310010,
|
293 | 76a66253 | j_mayer | PPC_SCR_8548v11 = 0x80310011,
|
294 | 76a66253 | j_mayer | PPC_SCR_8548v20 = 0x80310020,
|
295 | 76a66253 | j_mayer | PPC_SVR_8548Ev10 = 0x80390010,
|
296 | 76a66253 | j_mayer | PPC_SVR_8548Ev11 = 0x80390011,
|
297 | 76a66253 | j_mayer | PPC_SVR_8548Ev20 = 0x80390020,
|
298 | 76a66253 | j_mayer | PPC_SVR_8555E = 0x80790010,
|
299 | 76a66253 | j_mayer | PPC_SVR_8560v10 = 0x80700010,
|
300 | 76a66253 | j_mayer | PPC_SVR_8560v20 = 0x80700020,
|
301 | 3fc6c082 | bellard | }; |
302 | 3fc6c082 | bellard | |
303 | 3fc6c082 | bellard | /*****************************************************************************/
|
304 | 9a64fbe4 | bellard | /* Instruction types */
|
305 | 9a64fbe4 | bellard | enum {
|
306 | 3fc6c082 | bellard | PPC_NONE = 0x00000000,
|
307 | 3fc6c082 | bellard | /* integer operations instructions */
|
308 | 3fc6c082 | bellard | /* flow control instructions */
|
309 | 3fc6c082 | bellard | /* virtual memory instructions */
|
310 | 3fc6c082 | bellard | /* ld/st with reservation instructions */
|
311 | 3fc6c082 | bellard | /* cache control instructions */
|
312 | 3fc6c082 | bellard | /* spr/msr access instructions */
|
313 | 0487d6a8 | j_mayer | PPC_INSNS_BASE = 0x0000000000000001ULL,
|
314 | 3fc6c082 | bellard | #define PPC_INTEGER PPC_INSNS_BASE
|
315 | 3fc6c082 | bellard | #define PPC_FLOW PPC_INSNS_BASE
|
316 | 3fc6c082 | bellard | #define PPC_MEM PPC_INSNS_BASE
|
317 | 3fc6c082 | bellard | #define PPC_RES PPC_INSNS_BASE
|
318 | 3fc6c082 | bellard | #define PPC_CACHE PPC_INSNS_BASE
|
319 | 3fc6c082 | bellard | #define PPC_MISC PPC_INSNS_BASE
|
320 | 3fc6c082 | bellard | /* floating point operations instructions */
|
321 | 0487d6a8 | j_mayer | PPC_FLOAT = 0x0000000000000002ULL,
|
322 | 3fc6c082 | bellard | /* more floating point operations instructions */
|
323 | 0487d6a8 | j_mayer | PPC_FLOAT_EXT = 0x0000000000000004ULL,
|
324 | 3fc6c082 | bellard | /* external control instructions */
|
325 | 0487d6a8 | j_mayer | PPC_EXTERN = 0x0000000000000008ULL,
|
326 | 3fc6c082 | bellard | /* segment register access instructions */
|
327 | 0487d6a8 | j_mayer | PPC_SEGMENT = 0x0000000000000010ULL,
|
328 | 3fc6c082 | bellard | /* Optional cache control instructions */
|
329 | 0487d6a8 | j_mayer | PPC_CACHE_OPT = 0x0000000000000020ULL,
|
330 | 3fc6c082 | bellard | /* Optional floating point op instructions */
|
331 | 0487d6a8 | j_mayer | PPC_FLOAT_OPT = 0x0000000000000040ULL,
|
332 | 3fc6c082 | bellard | /* Optional memory control instructions */
|
333 | 0487d6a8 | j_mayer | PPC_MEM_TLBIA = 0x0000000000000080ULL,
|
334 | 0487d6a8 | j_mayer | PPC_MEM_TLBIE = 0x0000000000000100ULL,
|
335 | 0487d6a8 | j_mayer | PPC_MEM_TLBSYNC = 0x0000000000000200ULL,
|
336 | 3fc6c082 | bellard | /* eieio & sync */
|
337 | 0487d6a8 | j_mayer | PPC_MEM_SYNC = 0x0000000000000400ULL,
|
338 | 3fc6c082 | bellard | /* PowerPC 6xx TLB management instructions */
|
339 | 0487d6a8 | j_mayer | PPC_6xx_TLB = 0x0000000000000800ULL,
|
340 | 3fc6c082 | bellard | /* Altivec support */
|
341 | 0487d6a8 | j_mayer | PPC_ALTIVEC = 0x0000000000001000ULL,
|
342 | 3fc6c082 | bellard | /* Time base support */
|
343 | 0487d6a8 | j_mayer | PPC_TB = 0x0000000000002000ULL,
|
344 | 3fc6c082 | bellard | /* Embedded PowerPC dedicated instructions */
|
345 | 0487d6a8 | j_mayer | PPC_EMB_COMMON = 0x0000000000004000ULL,
|
346 | 3fc6c082 | bellard | /* PowerPC 40x exception model */
|
347 | 0487d6a8 | j_mayer | PPC_40x_EXCP = 0x0000000000008000ULL,
|
348 | 3fc6c082 | bellard | /* PowerPC 40x specific instructions */
|
349 | 0487d6a8 | j_mayer | PPC_40x_SPEC = 0x0000000000010000ULL,
|
350 | 3fc6c082 | bellard | /* PowerPC 405 Mac instructions */
|
351 | 0487d6a8 | j_mayer | PPC_405_MAC = 0x0000000000020000ULL,
|
352 | 3fc6c082 | bellard | /* PowerPC 440 specific instructions */
|
353 | 0487d6a8 | j_mayer | PPC_440_SPEC = 0x0000000000040000ULL,
|
354 | 3fc6c082 | bellard | /* Specific extensions */
|
355 | 3fc6c082 | bellard | /* Power-to-PowerPC bridge (601) */
|
356 | 0487d6a8 | j_mayer | PPC_POWER_BR = 0x0000000000080000ULL,
|
357 | 3fc6c082 | bellard | /* PowerPC 602 specific */
|
358 | 0487d6a8 | j_mayer | PPC_602_SPEC = 0x0000000000100000ULL,
|
359 | 3fc6c082 | bellard | /* Deprecated instructions */
|
360 | 3fc6c082 | bellard | /* Original POWER instruction set */
|
361 | 0487d6a8 | j_mayer | PPC_POWER = 0x0000000000200000ULL,
|
362 | 3fc6c082 | bellard | /* POWER2 instruction set extension */
|
363 | 0487d6a8 | j_mayer | PPC_POWER2 = 0x0000000000400000ULL,
|
364 | 3fc6c082 | bellard | /* Power RTC support */
|
365 | 0487d6a8 | j_mayer | PPC_POWER_RTC = 0x0000000000800000ULL,
|
366 | 3fc6c082 | bellard | /* 64 bits PowerPC instructions */
|
367 | 3fc6c082 | bellard | /* 64 bits PowerPC instruction set */
|
368 | 0487d6a8 | j_mayer | PPC_64B = 0x0000000001000000ULL,
|
369 | 3fc6c082 | bellard | /* 64 bits hypervisor extensions */
|
370 | 0487d6a8 | j_mayer | PPC_64H = 0x0000000002000000ULL,
|
371 | 3fc6c082 | bellard | /* 64 bits PowerPC "bridge" features */
|
372 | 0487d6a8 | j_mayer | PPC_64_BRIDGE = 0x0000000004000000ULL,
|
373 | 76a66253 | j_mayer | /* BookE (embedded) PowerPC specification */
|
374 | 0487d6a8 | j_mayer | PPC_BOOKE = 0x0000000008000000ULL,
|
375 | 76a66253 | j_mayer | /* eieio */
|
376 | 0487d6a8 | j_mayer | PPC_MEM_EIEIO = 0x0000000010000000ULL,
|
377 | 76a66253 | j_mayer | /* e500 vector instructions */
|
378 | 0487d6a8 | j_mayer | PPC_E500_VECTOR = 0x0000000020000000ULL,
|
379 | 76a66253 | j_mayer | /* PowerPC 4xx dedicated instructions */
|
380 | 0487d6a8 | j_mayer | PPC_4xx_COMMON = 0x0000000040000000ULL,
|
381 | d9bce9d9 | j_mayer | /* PowerPC 2.03 specification extensions */
|
382 | 0487d6a8 | j_mayer | PPC_203 = 0x0000000080000000ULL,
|
383 | 0487d6a8 | j_mayer | /* PowerPC 2.03 SPE extension */
|
384 | 0487d6a8 | j_mayer | PPC_SPE = 0x0000000100000000ULL,
|
385 | 0487d6a8 | j_mayer | /* PowerPC 2.03 SPE floating-point extension */
|
386 | 0487d6a8 | j_mayer | PPC_SPEFPU = 0x0000000200000000ULL,
|
387 | 426613db | j_mayer | /* SLB management */
|
388 | 426613db | j_mayer | PPC_SLBI = 0x0000000400000000ULL,
|
389 | 9a64fbe4 | bellard | }; |
390 | 79aceca5 | bellard | |
391 | 3fc6c082 | bellard | /* CPU run-time flags (MMU and exception model) */
|
392 | 3fc6c082 | bellard | enum {
|
393 | 3fc6c082 | bellard | /* MMU model */
|
394 | 76a66253 | j_mayer | PPC_FLAGS_MMU_MASK = 0x0000000F,
|
395 | 3fc6c082 | bellard | /* Standard 32 bits PowerPC MMU */
|
396 | 3fc6c082 | bellard | PPC_FLAGS_MMU_32B = 0x00000000,
|
397 | 3fc6c082 | bellard | /* Standard 64 bits PowerPC MMU */
|
398 | 3fc6c082 | bellard | PPC_FLAGS_MMU_64B = 0x00000001,
|
399 | 3fc6c082 | bellard | /* PowerPC 601 MMU */
|
400 | 3fc6c082 | bellard | PPC_FLAGS_MMU_601 = 0x00000002,
|
401 | 3fc6c082 | bellard | /* PowerPC 6xx MMU with software TLB */
|
402 | 3fc6c082 | bellard | PPC_FLAGS_MMU_SOFT_6xx = 0x00000003,
|
403 | 3fc6c082 | bellard | /* PowerPC 4xx MMU with software TLB */
|
404 | 3fc6c082 | bellard | PPC_FLAGS_MMU_SOFT_4xx = 0x00000004,
|
405 | 3fc6c082 | bellard | /* PowerPC 403 MMU */
|
406 | 3fc6c082 | bellard | PPC_FLAGS_MMU_403 = 0x00000005,
|
407 | 76a66253 | j_mayer | /* Freescale e500 MMU model */
|
408 | 76a66253 | j_mayer | PPC_FLAGS_MMU_e500 = 0x00000006,
|
409 | d9bce9d9 | j_mayer | /* BookE MMU model */
|
410 | d9bce9d9 | j_mayer | PPC_FLAGS_MMU_BOOKE = 0x00000007,
|
411 | 3fc6c082 | bellard | /* Exception model */
|
412 | 76a66253 | j_mayer | PPC_FLAGS_EXCP_MASK = 0x000000F0,
|
413 | 3fc6c082 | bellard | /* Standard PowerPC exception model */
|
414 | 3fc6c082 | bellard | PPC_FLAGS_EXCP_STD = 0x00000000,
|
415 | 3fc6c082 | bellard | /* PowerPC 40x exception model */
|
416 | 3fc6c082 | bellard | PPC_FLAGS_EXCP_40x = 0x00000010,
|
417 | 3fc6c082 | bellard | /* PowerPC 601 exception model */
|
418 | 3fc6c082 | bellard | PPC_FLAGS_EXCP_601 = 0x00000020,
|
419 | 3fc6c082 | bellard | /* PowerPC 602 exception model */
|
420 | 3fc6c082 | bellard | PPC_FLAGS_EXCP_602 = 0x00000030,
|
421 | 3fc6c082 | bellard | /* PowerPC 603 exception model */
|
422 | 3fc6c082 | bellard | PPC_FLAGS_EXCP_603 = 0x00000040,
|
423 | 3fc6c082 | bellard | /* PowerPC 604 exception model */
|
424 | 3fc6c082 | bellard | PPC_FLAGS_EXCP_604 = 0x00000050,
|
425 | 3fc6c082 | bellard | /* PowerPC 7x0 exception model */
|
426 | 3fc6c082 | bellard | PPC_FLAGS_EXCP_7x0 = 0x00000060,
|
427 | 3fc6c082 | bellard | /* PowerPC 7x5 exception model */
|
428 | 3fc6c082 | bellard | PPC_FLAGS_EXCP_7x5 = 0x00000070,
|
429 | 3fc6c082 | bellard | /* PowerPC 74xx exception model */
|
430 | 3fc6c082 | bellard | PPC_FLAGS_EXCP_74xx = 0x00000080,
|
431 | 3fc6c082 | bellard | /* PowerPC 970 exception model */
|
432 | 3fc6c082 | bellard | PPC_FLAGS_EXCP_970 = 0x00000090,
|
433 | d9bce9d9 | j_mayer | /* BookE exception model */
|
434 | d9bce9d9 | j_mayer | PPC_FLAGS_EXCP_BOOKE = 0x000000A0,
|
435 | 3fc6c082 | bellard | }; |
436 | 3fc6c082 | bellard | |
437 | 3fc6c082 | bellard | #define PPC_MMU(env) (env->flags & PPC_FLAGS_MMU_MASK)
|
438 | 3fc6c082 | bellard | #define PPC_EXCP(env) (env->flags & PPC_FLAGS_EXCP_MASK)
|
439 | 3fc6c082 | bellard | |
440 | 3fc6c082 | bellard | /*****************************************************************************/
|
441 | 3fc6c082 | bellard | /* Supported instruction set definitions */
|
442 | 3fc6c082 | bellard | /* This generates an empty opcode table... */
|
443 | 3fc6c082 | bellard | #define PPC_INSNS_TODO (PPC_NONE)
|
444 | 3fc6c082 | bellard | #define PPC_FLAGS_TODO (0x00000000) |
445 | 3fc6c082 | bellard | |
446 | 3fc6c082 | bellard | /* PowerPC 40x instruction set */
|
447 | 76a66253 | j_mayer | #define PPC_INSNS_EMB (PPC_INSNS_BASE | PPC_MEM_TLBSYNC | PPC_EMB_COMMON)
|
448 | 3fc6c082 | bellard | /* PowerPC 401 */
|
449 | 3fc6c082 | bellard | #define PPC_INSNS_401 (PPC_INSNS_TODO)
|
450 | 3fc6c082 | bellard | #define PPC_FLAGS_401 (PPC_FLAGS_TODO)
|
451 | 3fc6c082 | bellard | /* PowerPC 403 */
|
452 | 76a66253 | j_mayer | #define PPC_INSNS_403 (PPC_INSNS_EMB | PPC_MEM_SYNC | PPC_MEM_EIEIO | \
|
453 | 76a66253 | j_mayer | PPC_MEM_TLBIA | PPC_4xx_COMMON | PPC_40x_EXCP | \ |
454 | 76a66253 | j_mayer | PPC_40x_SPEC) |
455 | 3fc6c082 | bellard | #define PPC_FLAGS_403 (PPC_FLAGS_MMU_403 | PPC_FLAGS_EXCP_40x)
|
456 | 3fc6c082 | bellard | /* PowerPC 405 */
|
457 | 76a66253 | j_mayer | #define PPC_INSNS_405 (PPC_INSNS_EMB | PPC_MEM_SYNC | PPC_MEM_EIEIO | \
|
458 | 76a66253 | j_mayer | PPC_CACHE_OPT | PPC_MEM_TLBIA | PPC_TB | \ |
459 | 76a66253 | j_mayer | PPC_4xx_COMMON | PPC_40x_SPEC | PPC_40x_EXCP | \ |
460 | 3fc6c082 | bellard | PPC_405_MAC) |
461 | 3fc6c082 | bellard | #define PPC_FLAGS_405 (PPC_FLAGS_MMU_SOFT_4xx | PPC_FLAGS_EXCP_40x)
|
462 | 3fc6c082 | bellard | /* PowerPC 440 */
|
463 | 76a66253 | j_mayer | #define PPC_INSNS_440 (PPC_INSNS_EMB | PPC_CACHE_OPT | PPC_BOOKE | \
|
464 | 76a66253 | j_mayer | PPC_4xx_COMMON | PPC_405_MAC | PPC_440_SPEC) |
465 | d9bce9d9 | j_mayer | #define PPC_FLAGS_440 (PPC_FLAGS_MMU_BOOKE | PPC_FLAGS_EXCP_BOOKE)
|
466 | 76a66253 | j_mayer | /* Generic BookE PowerPC */
|
467 | 76a66253 | j_mayer | #define PPC_INSNS_BOOKE (PPC_INSNS_EMB | PPC_BOOKE | PPC_MEM_EIEIO | \
|
468 | 76a66253 | j_mayer | PPC_FLOAT | PPC_FLOAT_OPT | PPC_CACHE_OPT) |
469 | d9bce9d9 | j_mayer | #define PPC_FLAGS_BOOKE (PPC_FLAGS_MMU_BOOKE | PPC_FLAGS_EXCP_BOOKE)
|
470 | 76a66253 | j_mayer | /* e500 core */
|
471 | 76a66253 | j_mayer | #define PPC_INSNS_E500 (PPC_INSNS_EMB | PPC_BOOKE | PPC_MEM_EIEIO | \
|
472 | 76a66253 | j_mayer | PPC_CACHE_OPT | PPC_E500_VECTOR) |
473 | 76a66253 | j_mayer | #define PPC_FLAGS_E500 (PPC_FLAGS_MMU_SOFT_4xx | PPC_FLAGS_EXCP_40x)
|
474 | 3fc6c082 | bellard | /* Non-embedded PowerPC */
|
475 | 3fc6c082 | bellard | #define PPC_INSNS_COMMON (PPC_INSNS_BASE | PPC_FLOAT | PPC_MEM_SYNC | \
|
476 | 76a66253 | j_mayer | PPC_MEM_EIEIO | PPC_SEGMENT | PPC_MEM_TLBIE) |
477 | 3fc6c082 | bellard | /* PowerPC 601 */
|
478 | 3fc6c082 | bellard | #define PPC_INSNS_601 (PPC_INSNS_COMMON | PPC_EXTERN | PPC_POWER_BR)
|
479 | 3fc6c082 | bellard | #define PPC_FLAGS_601 (PPC_FLAGS_MMU_601 | PPC_FLAGS_EXCP_601)
|
480 | 3fc6c082 | bellard | /* PowerPC 602 */
|
481 | 3fc6c082 | bellard | #define PPC_INSNS_602 (PPC_INSNS_COMMON | PPC_FLOAT_EXT | PPC_6xx_TLB | \
|
482 | 76a66253 | j_mayer | PPC_MEM_TLBSYNC | PPC_TB | PPC_602_SPEC) |
483 | 3fc6c082 | bellard | #define PPC_FLAGS_602 (PPC_FLAGS_MMU_SOFT_6xx | PPC_FLAGS_EXCP_602)
|
484 | 3fc6c082 | bellard | /* PowerPC 603 */
|
485 | 3fc6c082 | bellard | #define PPC_INSNS_603 (PPC_INSNS_COMMON | PPC_FLOAT_EXT | PPC_6xx_TLB | \
|
486 | 3fc6c082 | bellard | PPC_MEM_TLBSYNC | PPC_EXTERN | PPC_TB) |
487 | 3fc6c082 | bellard | #define PPC_FLAGS_603 (PPC_FLAGS_MMU_SOFT_6xx | PPC_FLAGS_EXCP_603)
|
488 | 3fc6c082 | bellard | /* PowerPC G2 */
|
489 | 3fc6c082 | bellard | #define PPC_INSNS_G2 (PPC_INSNS_COMMON | PPC_FLOAT_EXT | PPC_6xx_TLB | \
|
490 | 3fc6c082 | bellard | PPC_MEM_TLBSYNC | PPC_EXTERN | PPC_TB) |
491 | 3fc6c082 | bellard | #define PPC_FLAGS_G2 (PPC_FLAGS_MMU_SOFT_6xx | PPC_FLAGS_EXCP_603)
|
492 | 3fc6c082 | bellard | /* PowerPC 604 */
|
493 | 3fc6c082 | bellard | #define PPC_INSNS_604 (PPC_INSNS_COMMON | PPC_FLOAT_EXT | PPC_EXTERN | \
|
494 | 3fc6c082 | bellard | PPC_MEM_TLBSYNC | PPC_TB) |
495 | 3fc6c082 | bellard | #define PPC_FLAGS_604 (PPC_FLAGS_MMU_32B | PPC_FLAGS_EXCP_604)
|
496 | 3fc6c082 | bellard | /* PowerPC 740/750 (aka G3) */
|
497 | 3fc6c082 | bellard | #define PPC_INSNS_7x0 (PPC_INSNS_COMMON | PPC_FLOAT_EXT | PPC_EXTERN | \
|
498 | 3fc6c082 | bellard | PPC_MEM_TLBSYNC | PPC_TB) |
499 | 3fc6c082 | bellard | #define PPC_FLAGS_7x0 (PPC_FLAGS_MMU_32B | PPC_FLAGS_EXCP_7x0)
|
500 | 3fc6c082 | bellard | /* PowerPC 745/755 */
|
501 | 3fc6c082 | bellard | #define PPC_INSNS_7x5 (PPC_INSNS_COMMON | PPC_FLOAT_EXT | PPC_EXTERN | \
|
502 | 3fc6c082 | bellard | PPC_MEM_TLBSYNC | PPC_TB | PPC_6xx_TLB) |
503 | 3fc6c082 | bellard | #define PPC_FLAGS_7x5 (PPC_FLAGS_MMU_SOFT_6xx | PPC_FLAGS_EXCP_7x5)
|
504 | 3fc6c082 | bellard | /* PowerPC 74xx (aka G4) */
|
505 | 3fc6c082 | bellard | #define PPC_INSNS_74xx (PPC_INSNS_COMMON | PPC_FLOAT_EXT | PPC_ALTIVEC | \
|
506 | 3fc6c082 | bellard | PPC_MEM_TLBSYNC | PPC_TB) |
507 | 3fc6c082 | bellard | #define PPC_FLAGS_74xx (PPC_FLAGS_MMU_32B | PPC_FLAGS_EXCP_74xx)
|
508 | 426613db | j_mayer | /* PowerPC 970 (aka G5) */
|
509 | 426613db | j_mayer | #define PPC_INSNS_970 (PPC_INSNS_COMMON | PPC_FLOAT_EXT | PPC_FLOAT_OPT | \
|
510 | 426613db | j_mayer | PPC_ALTIVEC | PPC_MEM_TLBSYNC | PPC_TB | \ |
511 | 426613db | j_mayer | PPC_64B | PPC_64_BRIDGE | PPC_SLBI) |
512 | 426613db | j_mayer | #define PPC_FLAGS_970 (PPC_FLAGS_MMU_64B | PPC_FLAGS_EXCP_970)
|
513 | 3fc6c082 | bellard | |
514 | 3fc6c082 | bellard | /* Default PowerPC will be 604/970 */
|
515 | 3fc6c082 | bellard | #define PPC_INSNS_PPC32 PPC_INSNS_604
|
516 | 3fc6c082 | bellard | #define PPC_FLAGS_PPC32 PPC_FLAGS_604
|
517 | 3fc6c082 | bellard | #define PPC_INSNS_PPC64 PPC_INSNS_970
|
518 | 3fc6c082 | bellard | #define PPC_FLAGS_PPC64 PPC_FLAGS_970
|
519 | 3fc6c082 | bellard | #define PPC_INSNS_DEFAULT PPC_INSNS_604
|
520 | 3fc6c082 | bellard | #define PPC_FLAGS_DEFAULT PPC_FLAGS_604
|
521 | 3fc6c082 | bellard | typedef struct ppc_def_t ppc_def_t; |
522 | 79aceca5 | bellard | |
523 | 3fc6c082 | bellard | /*****************************************************************************/
|
524 | 3fc6c082 | bellard | /* Types used to describe some PowerPC registers */
|
525 | 3fc6c082 | bellard | typedef struct CPUPPCState CPUPPCState; |
526 | 3fc6c082 | bellard | typedef struct opc_handler_t opc_handler_t; |
527 | 9fddaa0c | bellard | typedef struct ppc_tb_t ppc_tb_t; |
528 | 3fc6c082 | bellard | typedef struct ppc_spr_t ppc_spr_t; |
529 | 3fc6c082 | bellard | typedef struct ppc_dcr_t ppc_dcr_t; |
530 | 3fc6c082 | bellard | typedef struct ppc_avr_t ppc_avr_t; |
531 | 1d0a48fb | j_mayer | typedef union ppc_tlb_t ppc_tlb_t; |
532 | 76a66253 | j_mayer | |
533 | 3fc6c082 | bellard | /* SPR access micro-ops generations callbacks */
|
534 | 3fc6c082 | bellard | struct ppc_spr_t {
|
535 | 3fc6c082 | bellard | void (*uea_read)(void *opaque, int spr_num); |
536 | 3fc6c082 | bellard | void (*uea_write)(void *opaque, int spr_num); |
537 | 76a66253 | j_mayer | #if !defined(CONFIG_USER_ONLY)
|
538 | 3fc6c082 | bellard | void (*oea_read)(void *opaque, int spr_num); |
539 | 3fc6c082 | bellard | void (*oea_write)(void *opaque, int spr_num); |
540 | 76a66253 | j_mayer | #endif
|
541 | 3fc6c082 | bellard | const unsigned char *name; |
542 | 3fc6c082 | bellard | }; |
543 | 3fc6c082 | bellard | |
544 | 3fc6c082 | bellard | /* Altivec registers (128 bits) */
|
545 | 3fc6c082 | bellard | struct ppc_avr_t {
|
546 | 3fc6c082 | bellard | uint32_t u[4];
|
547 | 3fc6c082 | bellard | }; |
548 | 9fddaa0c | bellard | |
549 | 3fc6c082 | bellard | /* Software TLB cache */
|
550 | 1d0a48fb | j_mayer | typedef struct ppc6xx_tlb_t ppc6xx_tlb_t; |
551 | 1d0a48fb | j_mayer | struct ppc6xx_tlb_t {
|
552 | 76a66253 | j_mayer | target_ulong pte0; |
553 | 76a66253 | j_mayer | target_ulong pte1; |
554 | 76a66253 | j_mayer | target_ulong EPN; |
555 | 1d0a48fb | j_mayer | }; |
556 | 1d0a48fb | j_mayer | |
557 | 1d0a48fb | j_mayer | typedef struct ppcemb_tlb_t ppcemb_tlb_t; |
558 | 1d0a48fb | j_mayer | struct ppcemb_tlb_t {
|
559 | 1d0a48fb | j_mayer | target_ulong RPN; |
560 | 1d0a48fb | j_mayer | target_ulong EPN; |
561 | 76a66253 | j_mayer | target_ulong PID; |
562 | 76a66253 | j_mayer | int size;
|
563 | 1d0a48fb | j_mayer | int prot;
|
564 | 1d0a48fb | j_mayer | int attr; /* Storage attributes */ |
565 | 1d0a48fb | j_mayer | }; |
566 | 1d0a48fb | j_mayer | |
567 | 1d0a48fb | j_mayer | union ppc_tlb_t {
|
568 | 1d0a48fb | j_mayer | ppc6xx_tlb_t tlb6; |
569 | 1d0a48fb | j_mayer | ppcemb_tlb_t tlbe; |
570 | 3fc6c082 | bellard | }; |
571 | 3fc6c082 | bellard | |
572 | 3fc6c082 | bellard | /*****************************************************************************/
|
573 | 3fc6c082 | bellard | /* Machine state register bits definition */
|
574 | 76a66253 | j_mayer | #define MSR_SF 63 /* Sixty-four-bit mode hflags */ |
575 | 3fc6c082 | bellard | #define MSR_ISF 61 /* Sixty-four-bit interrupt mode on 630 */ |
576 | 76a66253 | j_mayer | #define MSR_HV 60 /* hypervisor state hflags */ |
577 | 363be49c | j_mayer | #define MSR_CM 31 /* Computation mode for BookE hflags */ |
578 | 363be49c | j_mayer | #define MSR_ICM 30 /* Interrupt computation mode for BookE */ |
579 | 363be49c | j_mayer | #define MSR_UCLE 26 /* User-mode cache lock enable for BookE */ |
580 | 76a66253 | j_mayer | #define MSR_VR 25 /* altivec available hflags */ |
581 | 363be49c | j_mayer | #define MSR_SPE 25 /* SPE enable for BookE hflags */ |
582 | 76a66253 | j_mayer | #define MSR_AP 23 /* Access privilege state on 602 hflags */ |
583 | 76a66253 | j_mayer | #define MSR_SA 22 /* Supervisor access mode on 602 hflags */ |
584 | 3fc6c082 | bellard | #define MSR_KEY 19 /* key bit on 603e */ |
585 | 3fc6c082 | bellard | #define MSR_POW 18 /* Power management */ |
586 | 3fc6c082 | bellard | #define MSR_WE 18 /* Wait state enable on embedded PowerPC */ |
587 | 3fc6c082 | bellard | #define MSR_TGPR 17 /* TGPR usage on 602/603 */ |
588 | 76a66253 | j_mayer | #define MSR_TLB 17 /* TLB update on ? */ |
589 | 3fc6c082 | bellard | #define MSR_CE 17 /* Critical interrupt enable on embedded PowerPC */ |
590 | 3fc6c082 | bellard | #define MSR_ILE 16 /* Interrupt little-endian mode */ |
591 | 3fc6c082 | bellard | #define MSR_EE 15 /* External interrupt enable */ |
592 | 76a66253 | j_mayer | #define MSR_PR 14 /* Problem state hflags */ |
593 | 76a66253 | j_mayer | #define MSR_FP 13 /* Floating point available hflags */ |
594 | 3fc6c082 | bellard | #define MSR_ME 12 /* Machine check interrupt enable */ |
595 | 76a66253 | j_mayer | #define MSR_FE0 11 /* Floating point exception mode 0 hflags */ |
596 | 76a66253 | j_mayer | #define MSR_SE 10 /* Single-step trace enable hflags */ |
597 | 3fc6c082 | bellard | #define MSR_DWE 10 /* Debug wait enable on 405 */ |
598 | 76a66253 | j_mayer | #define MSR_UBLE 10 /* User BTB lock enable on e500 */ |
599 | 76a66253 | j_mayer | #define MSR_BE 9 /* Branch trace enable hflags */ |
600 | 3fc6c082 | bellard | #define MSR_DE 9 /* Debug interrupts enable on embedded PowerPC */ |
601 | 76a66253 | j_mayer | #define MSR_FE1 8 /* Floating point exception mode 1 hflags */ |
602 | 3fc6c082 | bellard | #define MSR_AL 7 /* AL bit on POWER */ |
603 | 3fc6c082 | bellard | #define MSR_IP 6 /* Interrupt prefix */ |
604 | 3fc6c082 | bellard | #define MSR_IR 5 /* Instruction relocate */ |
605 | 3fc6c082 | bellard | #define MSR_IS 5 /* Instruction address space on embedded PowerPC */ |
606 | 3fc6c082 | bellard | #define MSR_DR 4 /* Data relocate */ |
607 | 3fc6c082 | bellard | #define MSR_DS 4 /* Data address space on embedded PowerPC */ |
608 | 3fc6c082 | bellard | #define MSR_PE 3 /* Protection enable on 403 */ |
609 | 3fc6c082 | bellard | #define MSR_EP 3 /* Exception prefix on 601 */ |
610 | 3fc6c082 | bellard | #define MSR_PX 2 /* Protection exclusive on 403 */ |
611 | 3fc6c082 | bellard | #define MSR_PMM 2 /* Performance monitor mark on POWER */ |
612 | 3fc6c082 | bellard | #define MSR_RI 1 /* Recoverable interrupt */ |
613 | 76a66253 | j_mayer | #define MSR_LE 0 /* Little-endian mode hflags */ |
614 | 3fc6c082 | bellard | #define msr_sf env->msr[MSR_SF]
|
615 | 3fc6c082 | bellard | #define msr_isf env->msr[MSR_ISF]
|
616 | 3fc6c082 | bellard | #define msr_hv env->msr[MSR_HV]
|
617 | 363be49c | j_mayer | #define msr_cm env->msr[MSR_CM]
|
618 | 363be49c | j_mayer | #define msr_icm env->msr[MSR_ICM]
|
619 | 76a66253 | j_mayer | #define msr_ucle env->msr[MSR_UCLE]
|
620 | 3fc6c082 | bellard | #define msr_vr env->msr[MSR_VR]
|
621 | 76a66253 | j_mayer | #define msr_spe env->msr[MSR_SPE]
|
622 | 3fc6c082 | bellard | #define msr_ap env->msr[MSR_AP]
|
623 | 3fc6c082 | bellard | #define msr_sa env->msr[MSR_SA]
|
624 | 3fc6c082 | bellard | #define msr_key env->msr[MSR_KEY]
|
625 | 76a66253 | j_mayer | #define msr_pow env->msr[MSR_POW]
|
626 | 3fc6c082 | bellard | #define msr_we env->msr[MSR_WE]
|
627 | 3fc6c082 | bellard | #define msr_tgpr env->msr[MSR_TGPR]
|
628 | 3fc6c082 | bellard | #define msr_tlb env->msr[MSR_TLB]
|
629 | 3fc6c082 | bellard | #define msr_ce env->msr[MSR_CE]
|
630 | 76a66253 | j_mayer | #define msr_ile env->msr[MSR_ILE]
|
631 | 76a66253 | j_mayer | #define msr_ee env->msr[MSR_EE]
|
632 | 76a66253 | j_mayer | #define msr_pr env->msr[MSR_PR]
|
633 | 76a66253 | j_mayer | #define msr_fp env->msr[MSR_FP]
|
634 | 76a66253 | j_mayer | #define msr_me env->msr[MSR_ME]
|
635 | 76a66253 | j_mayer | #define msr_fe0 env->msr[MSR_FE0]
|
636 | 76a66253 | j_mayer | #define msr_se env->msr[MSR_SE]
|
637 | 3fc6c082 | bellard | #define msr_dwe env->msr[MSR_DWE]
|
638 | 76a66253 | j_mayer | #define msr_uble env->msr[MSR_UBLE]
|
639 | 76a66253 | j_mayer | #define msr_be env->msr[MSR_BE]
|
640 | 3fc6c082 | bellard | #define msr_de env->msr[MSR_DE]
|
641 | 76a66253 | j_mayer | #define msr_fe1 env->msr[MSR_FE1]
|
642 | 3fc6c082 | bellard | #define msr_al env->msr[MSR_AL]
|
643 | 76a66253 | j_mayer | #define msr_ip env->msr[MSR_IP]
|
644 | 76a66253 | j_mayer | #define msr_ir env->msr[MSR_IR]
|
645 | 3fc6c082 | bellard | #define msr_is env->msr[MSR_IS]
|
646 | 76a66253 | j_mayer | #define msr_dr env->msr[MSR_DR]
|
647 | 3fc6c082 | bellard | #define msr_ds env->msr[MSR_DS]
|
648 | 3fc6c082 | bellard | #define msr_pe env->msr[MSR_PE]
|
649 | 3fc6c082 | bellard | #define msr_ep env->msr[MSR_EP]
|
650 | 3fc6c082 | bellard | #define msr_px env->msr[MSR_PX]
|
651 | 3fc6c082 | bellard | #define msr_pmm env->msr[MSR_PMM]
|
652 | 76a66253 | j_mayer | #define msr_ri env->msr[MSR_RI]
|
653 | 76a66253 | j_mayer | #define msr_le env->msr[MSR_LE]
|
654 | 79aceca5 | bellard | |
655 | 3fc6c082 | bellard | /*****************************************************************************/
|
656 | 3fc6c082 | bellard | /* The whole PowerPC CPU context */
|
657 | 3fc6c082 | bellard | struct CPUPPCState {
|
658 | 3fc6c082 | bellard | /* First are the most commonly used resources
|
659 | 3fc6c082 | bellard | * during translated code execution
|
660 | 3fc6c082 | bellard | */
|
661 | 0487d6a8 | j_mayer | #if TARGET_GPR_BITS > HOST_LONG_BITS
|
662 | 3fc6c082 | bellard | /* temporary fixed-point registers
|
663 | 3fc6c082 | bellard | * used to emulate 64 bits target on 32 bits hosts
|
664 | 0487d6a8 | j_mayer | */
|
665 | 3fc6c082 | bellard | target_ulong t0, t1, t2; |
666 | 3fc6c082 | bellard | #endif
|
667 | d9bce9d9 | j_mayer | ppc_avr_t t0_avr, t1_avr, t2_avr; |
668 | d9bce9d9 | j_mayer | |
669 | 79aceca5 | bellard | /* general purpose registers */
|
670 | 76a66253 | j_mayer | ppc_gpr_t gpr[32];
|
671 | 3fc6c082 | bellard | /* LR */
|
672 | 3fc6c082 | bellard | target_ulong lr; |
673 | 3fc6c082 | bellard | /* CTR */
|
674 | 3fc6c082 | bellard | target_ulong ctr; |
675 | 3fc6c082 | bellard | /* condition register */
|
676 | 3fc6c082 | bellard | uint8_t crf[8];
|
677 | 79aceca5 | bellard | /* XER */
|
678 | 3fc6c082 | bellard | /* XXX: We use only 5 fields, but we want to keep the structure aligned */
|
679 | 3fc6c082 | bellard | uint8_t xer[8];
|
680 | 79aceca5 | bellard | /* Reservation address */
|
681 | 3fc6c082 | bellard | target_ulong reserve; |
682 | 3fc6c082 | bellard | |
683 | 3fc6c082 | bellard | /* Those ones are used in supervisor mode only */
|
684 | 79aceca5 | bellard | /* machine state register */
|
685 | 3fc6c082 | bellard | uint8_t msr[64];
|
686 | 3fc6c082 | bellard | /* temporary general purpose registers */
|
687 | 76a66253 | j_mayer | ppc_gpr_t tgpr[4]; /* Used to speed-up TLB assist handlers */ |
688 | 3fc6c082 | bellard | |
689 | 3fc6c082 | bellard | /* Floating point execution context */
|
690 | 76a66253 | j_mayer | /* temporary float registers */
|
691 | 4ecc3190 | bellard | float64 ft0; |
692 | 4ecc3190 | bellard | float64 ft1; |
693 | 4ecc3190 | bellard | float64 ft2; |
694 | 4ecc3190 | bellard | float_status fp_status; |
695 | 3fc6c082 | bellard | /* floating point registers */
|
696 | 3fc6c082 | bellard | float64 fpr[32];
|
697 | 3fc6c082 | bellard | /* floating point status and control register */
|
698 | 3fc6c082 | bellard | uint8_t fpscr[8];
|
699 | 4ecc3190 | bellard | |
700 | a316d335 | bellard | CPU_COMMON |
701 | a316d335 | bellard | |
702 | 50443c98 | bellard | int halted; /* TRUE if the CPU is in suspend state */ |
703 | 50443c98 | bellard | |
704 | ac9eb073 | bellard | int access_type; /* when a memory exception occurs, the access |
705 | ac9eb073 | bellard | type is stored here */
|
706 | a541f297 | bellard | |
707 | 3fc6c082 | bellard | /* MMU context */
|
708 | 3fc6c082 | bellard | /* Address space register */
|
709 | 3fc6c082 | bellard | target_ulong asr; |
710 | 3fc6c082 | bellard | /* segment registers */
|
711 | 3fc6c082 | bellard | target_ulong sdr1; |
712 | 3fc6c082 | bellard | target_ulong sr[16];
|
713 | 3fc6c082 | bellard | /* BATs */
|
714 | 3fc6c082 | bellard | int nb_BATs;
|
715 | 3fc6c082 | bellard | target_ulong DBAT[2][8]; |
716 | 3fc6c082 | bellard | target_ulong IBAT[2][8]; |
717 | 9fddaa0c | bellard | |
718 | 3fc6c082 | bellard | /* Other registers */
|
719 | 3fc6c082 | bellard | /* Special purpose registers */
|
720 | 3fc6c082 | bellard | target_ulong spr[1024];
|
721 | 3fc6c082 | bellard | /* Altivec registers */
|
722 | 3fc6c082 | bellard | ppc_avr_t avr[32];
|
723 | 3fc6c082 | bellard | uint32_t vscr; |
724 | d9bce9d9 | j_mayer | /* SPE registers */
|
725 | d9bce9d9 | j_mayer | ppc_gpr_t spe_acc; |
726 | 0487d6a8 | j_mayer | float_status spe_status; |
727 | d9bce9d9 | j_mayer | uint32_t spe_fscr; |
728 | 3fc6c082 | bellard | |
729 | 3fc6c082 | bellard | /* Internal devices resources */
|
730 | 9fddaa0c | bellard | /* Time base and decrementer */
|
731 | 9fddaa0c | bellard | ppc_tb_t *tb_env; |
732 | 3fc6c082 | bellard | /* Device control registers */
|
733 | 3fc6c082 | bellard | int (*dcr_read)(ppc_dcr_t *dcr_env, int dcr_num, target_ulong *val); |
734 | 3fc6c082 | bellard | int (*dcr_write)(ppc_dcr_t *dcr_env, int dcr_num, target_ulong val); |
735 | 3fc6c082 | bellard | ppc_dcr_t *dcr_env; |
736 | 3fc6c082 | bellard | |
737 | 3fc6c082 | bellard | /* PowerPC TLB registers (for 4xx and 60x software driven TLBs) */
|
738 | 76a66253 | j_mayer | int nb_tlb; /* Total number of TLB */ |
739 | 76a66253 | j_mayer | int tlb_per_way; /* Speed-up helper: used to avoid divisions at run time */ |
740 | 76a66253 | j_mayer | int nb_ways; /* Number of ways in the TLB set */ |
741 | 76a66253 | j_mayer | int last_way; /* Last used way used to allocate TLB in a LRU way */ |
742 | 76a66253 | j_mayer | int id_tlbs; /* If 1, MMU has separated TLBs for instructions & data */ |
743 | 363be49c | j_mayer | int nb_pids; /* Number of available PID registers */ |
744 | 76a66253 | j_mayer | ppc_tlb_t *tlb; /* TLB is optional. Allocate them only if needed */
|
745 | 3fc6c082 | bellard | /* Callbacks for specific checks on some implementations */
|
746 | 1d0a48fb | j_mayer | int (*tlb_check_more)(CPUPPCState *env, ppc_tlb_t *tlb, int *prot, |
747 | 3fc6c082 | bellard | target_ulong vaddr, int rw, int acc_type, |
748 | 3fc6c082 | bellard | int is_user);
|
749 | 3fc6c082 | bellard | /* 403 dedicated access protection registers */
|
750 | 3fc6c082 | bellard | target_ulong pb[4];
|
751 | 3fc6c082 | bellard | |
752 | 3fc6c082 | bellard | /* Those resources are used during exception processing */
|
753 | 3fc6c082 | bellard | /* CPU model definition */
|
754 | 3fc6c082 | bellard | uint64_t msr_mask; |
755 | 3fc6c082 | bellard | uint32_t flags; |
756 | 3fc6c082 | bellard | |
757 | 3fc6c082 | bellard | int exception_index;
|
758 | 3fc6c082 | bellard | int error_code;
|
759 | 3fc6c082 | bellard | int interrupt_request;
|
760 | 47103572 | j_mayer | uint32_t pending_interrupts; |
761 | 3fc6c082 | bellard | |
762 | 3fc6c082 | bellard | /* Those resources are used only during code translation */
|
763 | 3fc6c082 | bellard | /* Next instruction pointer */
|
764 | 3fc6c082 | bellard | target_ulong nip; |
765 | 3fc6c082 | bellard | /* SPR translation callbacks */
|
766 | 3fc6c082 | bellard | ppc_spr_t spr_cb[1024];
|
767 | 3fc6c082 | bellard | /* opcode handlers */
|
768 | 3fc6c082 | bellard | opc_handler_t *opcodes[0x40];
|
769 | 3fc6c082 | bellard | |
770 | 3fc6c082 | bellard | /* Those resources are used only in Qemu core */
|
771 | 3fc6c082 | bellard | jmp_buf jmp_env; |
772 | 3fc6c082 | bellard | int user_mode_only; /* user mode only simulation */ |
773 | 3fc6c082 | bellard | uint32_t hflags; |
774 | 3fc6c082 | bellard | |
775 | 9fddaa0c | bellard | /* Power management */
|
776 | 9fddaa0c | bellard | int power_mode;
|
777 | a541f297 | bellard | |
778 | 6d506e6d | bellard | /* temporary hack to handle OSI calls (only used if non NULL) */
|
779 | 6d506e6d | bellard | int (*osi_call)(struct CPUPPCState *env); |
780 | 3fc6c082 | bellard | }; |
781 | 79aceca5 | bellard | |
782 | 76a66253 | j_mayer | /* Context used internally during MMU translations */
|
783 | 76a66253 | j_mayer | typedef struct mmu_ctx_t mmu_ctx_t; |
784 | 76a66253 | j_mayer | struct mmu_ctx_t {
|
785 | 76a66253 | j_mayer | target_phys_addr_t raddr; /* Real address */
|
786 | 76a66253 | j_mayer | int prot; /* Protection bits */ |
787 | 76a66253 | j_mayer | target_phys_addr_t pg_addr[2]; /* PTE tables base addresses */ |
788 | 76a66253 | j_mayer | target_ulong ptem; /* Virtual segment ID | API */
|
789 | 76a66253 | j_mayer | int key; /* Access key */ |
790 | 76a66253 | j_mayer | }; |
791 | 76a66253 | j_mayer | |
792 | 3fc6c082 | bellard | /*****************************************************************************/
|
793 | 79aceca5 | bellard | CPUPPCState *cpu_ppc_init(void);
|
794 | 79aceca5 | bellard | int cpu_ppc_exec(CPUPPCState *s);
|
795 | 79aceca5 | bellard | void cpu_ppc_close(CPUPPCState *s);
|
796 | 79aceca5 | bellard | /* you can call this signal handler from your SIGBUS and SIGSEGV
|
797 | 79aceca5 | bellard | signal handlers to inform the virtual CPU of exceptions. non zero
|
798 | 79aceca5 | bellard | is returned if the signal was handled by the virtual CPU. */
|
799 | 5a7b542b | ths | int cpu_ppc_signal_handler(int host_signum, void *pinfo, |
800 | 79aceca5 | bellard | void *puc);
|
801 | 79aceca5 | bellard | |
802 | a541f297 | bellard | void do_interrupt (CPUPPCState *env);
|
803 | 9a64fbe4 | bellard | void cpu_loop_exit(void); |
804 | a541f297 | bellard | |
805 | 9a64fbe4 | bellard | void dump_stack (CPUPPCState *env);
|
806 | a541f297 | bellard | |
807 | 76a66253 | j_mayer | #if !defined(CONFIG_USER_ONLY)
|
808 | 3fc6c082 | bellard | target_ulong do_load_ibatu (CPUPPCState *env, int nr);
|
809 | 3fc6c082 | bellard | target_ulong do_load_ibatl (CPUPPCState *env, int nr);
|
810 | 3fc6c082 | bellard | void do_store_ibatu (CPUPPCState *env, int nr, target_ulong value); |
811 | 3fc6c082 | bellard | void do_store_ibatl (CPUPPCState *env, int nr, target_ulong value); |
812 | 3fc6c082 | bellard | target_ulong do_load_dbatu (CPUPPCState *env, int nr);
|
813 | 3fc6c082 | bellard | target_ulong do_load_dbatl (CPUPPCState *env, int nr);
|
814 | 3fc6c082 | bellard | void do_store_dbatu (CPUPPCState *env, int nr, target_ulong value); |
815 | 3fc6c082 | bellard | void do_store_dbatl (CPUPPCState *env, int nr, target_ulong value); |
816 | 3fc6c082 | bellard | target_ulong do_load_sdr1 (CPUPPCState *env); |
817 | 3fc6c082 | bellard | void do_store_sdr1 (CPUPPCState *env, target_ulong value);
|
818 | d9bce9d9 | j_mayer | #if defined(TARGET_PPC64)
|
819 | d9bce9d9 | j_mayer | target_ulong ppc_load_asr (CPUPPCState *env); |
820 | d9bce9d9 | j_mayer | void ppc_store_asr (CPUPPCState *env, target_ulong value);
|
821 | d9bce9d9 | j_mayer | #endif
|
822 | 3fc6c082 | bellard | target_ulong do_load_sr (CPUPPCState *env, int srnum);
|
823 | 3fc6c082 | bellard | void do_store_sr (CPUPPCState *env, int srnum, target_ulong value); |
824 | 76a66253 | j_mayer | #endif
|
825 | 76a66253 | j_mayer | uint32_t ppc_load_xer (CPUPPCState *env); |
826 | 76a66253 | j_mayer | void ppc_store_xer (CPUPPCState *env, uint32_t value);
|
827 | 3fc6c082 | bellard | target_ulong do_load_msr (CPUPPCState *env); |
828 | 3fc6c082 | bellard | void do_store_msr (CPUPPCState *env, target_ulong value);
|
829 | 426613db | j_mayer | void ppc_store_msr_32 (CPUPPCState *env, uint32_t value);
|
830 | 3fc6c082 | bellard | |
831 | 3fc6c082 | bellard | void do_compute_hflags (CPUPPCState *env);
|
832 | a541f297 | bellard | |
833 | 3fc6c082 | bellard | int ppc_find_by_name (const unsigned char *name, ppc_def_t **def); |
834 | 3fc6c082 | bellard | int ppc_find_by_pvr (uint32_t apvr, ppc_def_t **def);
|
835 | 3fc6c082 | bellard | void ppc_cpu_list (FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...)); |
836 | 3fc6c082 | bellard | int cpu_ppc_register (CPUPPCState *env, ppc_def_t *def);
|
837 | 85c4adf6 | bellard | |
838 | 9fddaa0c | bellard | /* Time-base and decrementer management */
|
839 | 9fddaa0c | bellard | #ifndef NO_CPU_IO_DEFS
|
840 | 9fddaa0c | bellard | uint32_t cpu_ppc_load_tbl (CPUPPCState *env); |
841 | 9fddaa0c | bellard | uint32_t cpu_ppc_load_tbu (CPUPPCState *env); |
842 | 9fddaa0c | bellard | void cpu_ppc_store_tbu (CPUPPCState *env, uint32_t value);
|
843 | 9fddaa0c | bellard | void cpu_ppc_store_tbl (CPUPPCState *env, uint32_t value);
|
844 | 9fddaa0c | bellard | uint32_t cpu_ppc_load_decr (CPUPPCState *env); |
845 | 9fddaa0c | bellard | void cpu_ppc_store_decr (CPUPPCState *env, uint32_t value);
|
846 | d9bce9d9 | j_mayer | uint32_t cpu_ppc601_load_rtcl (CPUPPCState *env); |
847 | d9bce9d9 | j_mayer | uint32_t cpu_ppc601_load_rtcu (CPUPPCState *env); |
848 | d9bce9d9 | j_mayer | #if !defined(CONFIG_USER_ONLY)
|
849 | d9bce9d9 | j_mayer | void cpu_ppc601_store_rtcl (CPUPPCState *env, uint32_t value);
|
850 | d9bce9d9 | j_mayer | void cpu_ppc601_store_rtcu (CPUPPCState *env, uint32_t value);
|
851 | d9bce9d9 | j_mayer | target_ulong load_40x_pit (CPUPPCState *env); |
852 | d9bce9d9 | j_mayer | void store_40x_pit (CPUPPCState *env, target_ulong val);
|
853 | d9bce9d9 | j_mayer | void store_booke_tcr (CPUPPCState *env, target_ulong val);
|
854 | d9bce9d9 | j_mayer | void store_booke_tsr (CPUPPCState *env, target_ulong val);
|
855 | d9bce9d9 | j_mayer | #endif
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856 | 9fddaa0c | bellard | #endif
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857 | 79aceca5 | bellard | |
858 | 79aceca5 | bellard | #define TARGET_PAGE_BITS 12 |
859 | 79aceca5 | bellard | #include "cpu-all.h" |
860 | 79aceca5 | bellard | |
861 | 3fc6c082 | bellard | /*****************************************************************************/
|
862 | 3fc6c082 | bellard | /* Registers definitions */
|
863 | 79aceca5 | bellard | #define ugpr(n) (env->gpr[n])
|
864 | 79aceca5 | bellard | |
865 | 79aceca5 | bellard | #define XER_SO 31 |
866 | 79aceca5 | bellard | #define XER_OV 30 |
867 | 79aceca5 | bellard | #define XER_CA 29 |
868 | 3fc6c082 | bellard | #define XER_CMP 8 |
869 | 79aceca5 | bellard | #define XER_BC 0 |
870 | 3fc6c082 | bellard | #define xer_so env->xer[4] |
871 | 3fc6c082 | bellard | #define xer_ov env->xer[6] |
872 | 3fc6c082 | bellard | #define xer_ca env->xer[2] |
873 | 3fc6c082 | bellard | #define xer_cmp env->xer[1] |
874 | 9a64fbe4 | bellard | #define xer_bc env->xer[0] |
875 | 79aceca5 | bellard | |
876 | 3fc6c082 | bellard | /* SPR definitions */
|
877 | 76a66253 | j_mayer | #define SPR_MQ (0x000) |
878 | 76a66253 | j_mayer | #define SPR_XER (0x001) |
879 | 76a66253 | j_mayer | #define SPR_601_VRTCU (0x004) |
880 | 76a66253 | j_mayer | #define SPR_601_VRTCL (0x005) |
881 | 76a66253 | j_mayer | #define SPR_601_UDECR (0x006) |
882 | 76a66253 | j_mayer | #define SPR_LR (0x008) |
883 | 76a66253 | j_mayer | #define SPR_CTR (0x009) |
884 | 76a66253 | j_mayer | #define SPR_DSISR (0x012) |
885 | 76a66253 | j_mayer | #define SPR_DAR (0x013) |
886 | 76a66253 | j_mayer | #define SPR_601_RTCU (0x014) |
887 | 76a66253 | j_mayer | #define SPR_601_RTCL (0x015) |
888 | 76a66253 | j_mayer | #define SPR_DECR (0x016) |
889 | 76a66253 | j_mayer | #define SPR_SDR1 (0x019) |
890 | 76a66253 | j_mayer | #define SPR_SRR0 (0x01A) |
891 | 76a66253 | j_mayer | #define SPR_SRR1 (0x01B) |
892 | 76a66253 | j_mayer | #define SPR_BOOKE_PID (0x030) |
893 | 76a66253 | j_mayer | #define SPR_BOOKE_DECAR (0x036) |
894 | 363be49c | j_mayer | #define SPR_BOOKE_CSRR0 (0x03A) |
895 | 363be49c | j_mayer | #define SPR_BOOKE_CSRR1 (0x03B) |
896 | 76a66253 | j_mayer | #define SPR_BOOKE_DEAR (0x03D) |
897 | 76a66253 | j_mayer | #define SPR_BOOKE_ESR (0x03E) |
898 | 363be49c | j_mayer | #define SPR_BOOKE_IVPR (0x03F) |
899 | 76a66253 | j_mayer | #define SPR_8xx_EIE (0x050) |
900 | 76a66253 | j_mayer | #define SPR_8xx_EID (0x051) |
901 | 76a66253 | j_mayer | #define SPR_8xx_NRE (0x052) |
902 | 76a66253 | j_mayer | #define SPR_58x_CMPA (0x090) |
903 | 76a66253 | j_mayer | #define SPR_58x_CMPB (0x091) |
904 | 76a66253 | j_mayer | #define SPR_58x_CMPC (0x092) |
905 | 76a66253 | j_mayer | #define SPR_58x_CMPD (0x093) |
906 | 76a66253 | j_mayer | #define SPR_58x_ICR (0x094) |
907 | 76a66253 | j_mayer | #define SPR_58x_DER (0x094) |
908 | 76a66253 | j_mayer | #define SPR_58x_COUNTA (0x096) |
909 | 76a66253 | j_mayer | #define SPR_58x_COUNTB (0x097) |
910 | 76a66253 | j_mayer | #define SPR_58x_CMPE (0x098) |
911 | 76a66253 | j_mayer | #define SPR_58x_CMPF (0x099) |
912 | 76a66253 | j_mayer | #define SPR_58x_CMPG (0x09A) |
913 | 76a66253 | j_mayer | #define SPR_58x_CMPH (0x09B) |
914 | 76a66253 | j_mayer | #define SPR_58x_LCTRL1 (0x09C) |
915 | 76a66253 | j_mayer | #define SPR_58x_LCTRL2 (0x09D) |
916 | 76a66253 | j_mayer | #define SPR_58x_ICTRL (0x09E) |
917 | 76a66253 | j_mayer | #define SPR_58x_BAR (0x09F) |
918 | 76a66253 | j_mayer | #define SPR_VRSAVE (0x100) |
919 | 76a66253 | j_mayer | #define SPR_USPRG0 (0x100) |
920 | 363be49c | j_mayer | #define SPR_USPRG1 (0x101) |
921 | 363be49c | j_mayer | #define SPR_USPRG2 (0x102) |
922 | 363be49c | j_mayer | #define SPR_USPRG3 (0x103) |
923 | 76a66253 | j_mayer | #define SPR_USPRG4 (0x104) |
924 | 76a66253 | j_mayer | #define SPR_USPRG5 (0x105) |
925 | 76a66253 | j_mayer | #define SPR_USPRG6 (0x106) |
926 | 76a66253 | j_mayer | #define SPR_USPRG7 (0x107) |
927 | 76a66253 | j_mayer | #define SPR_VTBL (0x10C) |
928 | 76a66253 | j_mayer | #define SPR_VTBU (0x10D) |
929 | 76a66253 | j_mayer | #define SPR_SPRG0 (0x110) |
930 | 76a66253 | j_mayer | #define SPR_SPRG1 (0x111) |
931 | 76a66253 | j_mayer | #define SPR_SPRG2 (0x112) |
932 | 76a66253 | j_mayer | #define SPR_SPRG3 (0x113) |
933 | 76a66253 | j_mayer | #define SPR_SPRG4 (0x114) |
934 | 76a66253 | j_mayer | #define SPR_SCOMC (0x114) |
935 | 76a66253 | j_mayer | #define SPR_SPRG5 (0x115) |
936 | 76a66253 | j_mayer | #define SPR_SCOMD (0x115) |
937 | 76a66253 | j_mayer | #define SPR_SPRG6 (0x116) |
938 | 76a66253 | j_mayer | #define SPR_SPRG7 (0x117) |
939 | 76a66253 | j_mayer | #define SPR_ASR (0x118) |
940 | 76a66253 | j_mayer | #define SPR_EAR (0x11A) |
941 | 76a66253 | j_mayer | #define SPR_TBL (0x11C) |
942 | 76a66253 | j_mayer | #define SPR_TBU (0x11D) |
943 | 76a66253 | j_mayer | #define SPR_SVR (0x11E) |
944 | 76a66253 | j_mayer | #define SPR_BOOKE_PIR (0x11E) |
945 | 76a66253 | j_mayer | #define SPR_PVR (0x11F) |
946 | 76a66253 | j_mayer | #define SPR_HSPRG0 (0x130) |
947 | 76a66253 | j_mayer | #define SPR_BOOKE_DBSR (0x130) |
948 | 76a66253 | j_mayer | #define SPR_HSPRG1 (0x131) |
949 | 76a66253 | j_mayer | #define SPR_BOOKE_DBCR0 (0x134) |
950 | 76a66253 | j_mayer | #define SPR_IBCR (0x135) |
951 | 76a66253 | j_mayer | #define SPR_BOOKE_DBCR1 (0x135) |
952 | 76a66253 | j_mayer | #define SPR_DBCR (0x136) |
953 | 76a66253 | j_mayer | #define SPR_HDEC (0x136) |
954 | 76a66253 | j_mayer | #define SPR_BOOKE_DBCR2 (0x136) |
955 | 76a66253 | j_mayer | #define SPR_HIOR (0x137) |
956 | 76a66253 | j_mayer | #define SPR_MBAR (0x137) |
957 | 76a66253 | j_mayer | #define SPR_RMOR (0x138) |
958 | 76a66253 | j_mayer | #define SPR_BOOKE_IAC1 (0x138) |
959 | 76a66253 | j_mayer | #define SPR_HRMOR (0x139) |
960 | 76a66253 | j_mayer | #define SPR_BOOKE_IAC2 (0x139) |
961 | 76a66253 | j_mayer | #define SPR_HSSR0 (0x13A) |
962 | 76a66253 | j_mayer | #define SPR_BOOKE_IAC3 (0x13A) |
963 | 76a66253 | j_mayer | #define SPR_HSSR1 (0x13B) |
964 | 76a66253 | j_mayer | #define SPR_BOOKE_IAC4 (0x13B) |
965 | 76a66253 | j_mayer | #define SPR_LPCR (0x13C) |
966 | 76a66253 | j_mayer | #define SPR_BOOKE_DAC1 (0x13C) |
967 | 76a66253 | j_mayer | #define SPR_LPIDR (0x13D) |
968 | 76a66253 | j_mayer | #define SPR_DABR2 (0x13D) |
969 | 76a66253 | j_mayer | #define SPR_BOOKE_DAC2 (0x13D) |
970 | 76a66253 | j_mayer | #define SPR_BOOKE_DVC1 (0x13E) |
971 | 76a66253 | j_mayer | #define SPR_BOOKE_DVC2 (0x13F) |
972 | 76a66253 | j_mayer | #define SPR_BOOKE_TSR (0x150) |
973 | 76a66253 | j_mayer | #define SPR_BOOKE_TCR (0x154) |
974 | 76a66253 | j_mayer | #define SPR_BOOKE_IVOR0 (0x190) |
975 | 76a66253 | j_mayer | #define SPR_BOOKE_IVOR1 (0x191) |
976 | 76a66253 | j_mayer | #define SPR_BOOKE_IVOR2 (0x192) |
977 | 76a66253 | j_mayer | #define SPR_BOOKE_IVOR3 (0x193) |
978 | 76a66253 | j_mayer | #define SPR_BOOKE_IVOR4 (0x194) |
979 | 76a66253 | j_mayer | #define SPR_BOOKE_IVOR5 (0x195) |
980 | 76a66253 | j_mayer | #define SPR_BOOKE_IVOR6 (0x196) |
981 | 76a66253 | j_mayer | #define SPR_BOOKE_IVOR7 (0x197) |
982 | 76a66253 | j_mayer | #define SPR_BOOKE_IVOR8 (0x198) |
983 | 76a66253 | j_mayer | #define SPR_BOOKE_IVOR9 (0x199) |
984 | 76a66253 | j_mayer | #define SPR_BOOKE_IVOR10 (0x19A) |
985 | 76a66253 | j_mayer | #define SPR_BOOKE_IVOR11 (0x19B) |
986 | 76a66253 | j_mayer | #define SPR_BOOKE_IVOR12 (0x19C) |
987 | 76a66253 | j_mayer | #define SPR_BOOKE_IVOR13 (0x19D) |
988 | 76a66253 | j_mayer | #define SPR_BOOKE_IVOR14 (0x19E) |
989 | 76a66253 | j_mayer | #define SPR_BOOKE_IVOR15 (0x19F) |
990 | 76a66253 | j_mayer | #define SPR_E500_SPEFSCR (0x200) |
991 | 76a66253 | j_mayer | #define SPR_E500_BBEAR (0x201) |
992 | 76a66253 | j_mayer | #define SPR_E500_BBTAR (0x202) |
993 | 76a66253 | j_mayer | #define SPR_BOOKE_ATBL (0x20E) |
994 | 76a66253 | j_mayer | #define SPR_BOOKE_ATBU (0x20F) |
995 | 76a66253 | j_mayer | #define SPR_IBAT0U (0x210) |
996 | 363be49c | j_mayer | #define SPR_BOOKE_IVOR32 (0x210) |
997 | 76a66253 | j_mayer | #define SPR_IBAT0L (0x211) |
998 | 363be49c | j_mayer | #define SPR_BOOKE_IVOR33 (0x211) |
999 | 76a66253 | j_mayer | #define SPR_IBAT1U (0x212) |
1000 | 363be49c | j_mayer | #define SPR_BOOKE_IVOR34 (0x212) |
1001 | 76a66253 | j_mayer | #define SPR_IBAT1L (0x213) |
1002 | 363be49c | j_mayer | #define SPR_BOOKE_IVOR35 (0x213) |
1003 | 76a66253 | j_mayer | #define SPR_IBAT2U (0x214) |
1004 | 363be49c | j_mayer | #define SPR_BOOKE_IVOR36 (0x214) |
1005 | 76a66253 | j_mayer | #define SPR_IBAT2L (0x215) |
1006 | 76a66253 | j_mayer | #define SPR_E500_L1CFG0 (0x215) |
1007 | 363be49c | j_mayer | #define SPR_BOOKE_IVOR37 (0x215) |
1008 | 76a66253 | j_mayer | #define SPR_IBAT3U (0x216) |
1009 | 76a66253 | j_mayer | #define SPR_E500_L1CFG1 (0x216) |
1010 | 76a66253 | j_mayer | #define SPR_IBAT3L (0x217) |
1011 | 76a66253 | j_mayer | #define SPR_DBAT0U (0x218) |
1012 | 76a66253 | j_mayer | #define SPR_DBAT0L (0x219) |
1013 | 76a66253 | j_mayer | #define SPR_DBAT1U (0x21A) |
1014 | 76a66253 | j_mayer | #define SPR_DBAT1L (0x21B) |
1015 | 76a66253 | j_mayer | #define SPR_DBAT2U (0x21C) |
1016 | 76a66253 | j_mayer | #define SPR_DBAT2L (0x21D) |
1017 | 76a66253 | j_mayer | #define SPR_DBAT3U (0x21E) |
1018 | 76a66253 | j_mayer | #define SPR_DBAT3L (0x21F) |
1019 | 76a66253 | j_mayer | #define SPR_IBAT4U (0x230) |
1020 | 76a66253 | j_mayer | #define SPR_IBAT4L (0x231) |
1021 | 76a66253 | j_mayer | #define SPR_IBAT5U (0x232) |
1022 | 76a66253 | j_mayer | #define SPR_IBAT5L (0x233) |
1023 | 76a66253 | j_mayer | #define SPR_IBAT6U (0x234) |
1024 | 76a66253 | j_mayer | #define SPR_IBAT6L (0x235) |
1025 | 76a66253 | j_mayer | #define SPR_IBAT7U (0x236) |
1026 | 76a66253 | j_mayer | #define SPR_IBAT7L (0x237) |
1027 | 76a66253 | j_mayer | #define SPR_DBAT4U (0x238) |
1028 | 76a66253 | j_mayer | #define SPR_DBAT4L (0x239) |
1029 | 76a66253 | j_mayer | #define SPR_DBAT5U (0x23A) |
1030 | 363be49c | j_mayer | #define SPR_BOOKE_MCSRR0 (0x23A) |
1031 | 76a66253 | j_mayer | #define SPR_DBAT5L (0x23B) |
1032 | 363be49c | j_mayer | #define SPR_BOOKE_MCSRR1 (0x23B) |
1033 | 76a66253 | j_mayer | #define SPR_DBAT6U (0x23C) |
1034 | 363be49c | j_mayer | #define SPR_BOOKE_MCSR (0x23C) |
1035 | 76a66253 | j_mayer | #define SPR_DBAT6L (0x23D) |
1036 | 76a66253 | j_mayer | #define SPR_E500_MCAR (0x23D) |
1037 | 76a66253 | j_mayer | #define SPR_DBAT7U (0x23E) |
1038 | 363be49c | j_mayer | #define SPR_BOOKE_DSRR0 (0x23E) |
1039 | 76a66253 | j_mayer | #define SPR_DBAT7L (0x23F) |
1040 | 363be49c | j_mayer | #define SPR_BOOKE_DSRR1 (0x23F) |
1041 | 363be49c | j_mayer | #define SPR_BOOKE_SPRG8 (0x25C) |
1042 | 363be49c | j_mayer | #define SPR_BOOKE_SPRG9 (0x25D) |
1043 | 363be49c | j_mayer | #define SPR_BOOKE_MAS0 (0x270) |
1044 | 363be49c | j_mayer | #define SPR_BOOKE_MAS1 (0x271) |
1045 | 363be49c | j_mayer | #define SPR_BOOKE_MAS2 (0x272) |
1046 | 363be49c | j_mayer | #define SPR_BOOKE_MAS3 (0x273) |
1047 | 363be49c | j_mayer | #define SPR_BOOKE_MAS4 (0x274) |
1048 | 363be49c | j_mayer | #define SPR_BOOKE_MAS6 (0x276) |
1049 | 363be49c | j_mayer | #define SPR_BOOKE_PID1 (0x279) |
1050 | 363be49c | j_mayer | #define SPR_BOOKE_PID2 (0x27A) |
1051 | 363be49c | j_mayer | #define SPR_BOOKE_TLB0CFG (0x2B0) |
1052 | 363be49c | j_mayer | #define SPR_BOOKE_TLB1CFG (0x2B1) |
1053 | 363be49c | j_mayer | #define SPR_BOOKE_TLB2CFG (0x2B2) |
1054 | 363be49c | j_mayer | #define SPR_BOOKE_TLB3CFG (0x2B3) |
1055 | 363be49c | j_mayer | #define SPR_BOOKE_EPR (0x2BE) |
1056 | 76a66253 | j_mayer | #define SPR_440_INV0 (0x370) |
1057 | 76a66253 | j_mayer | #define SPR_440_INV1 (0x371) |
1058 | 76a66253 | j_mayer | #define SPR_440_INV2 (0x372) |
1059 | 76a66253 | j_mayer | #define SPR_440_INV3 (0x373) |
1060 | 76a66253 | j_mayer | #define SPR_440_IVT0 (0x374) |
1061 | 76a66253 | j_mayer | #define SPR_440_IVT1 (0x375) |
1062 | 76a66253 | j_mayer | #define SPR_440_IVT2 (0x376) |
1063 | 76a66253 | j_mayer | #define SPR_440_IVT3 (0x377) |
1064 | 76a66253 | j_mayer | #define SPR_440_DNV0 (0x390) |
1065 | 76a66253 | j_mayer | #define SPR_440_DNV1 (0x391) |
1066 | 76a66253 | j_mayer | #define SPR_440_DNV2 (0x392) |
1067 | 76a66253 | j_mayer | #define SPR_440_DNV3 (0x393) |
1068 | 76a66253 | j_mayer | #define SPR_440_DVT0 (0x394) |
1069 | 76a66253 | j_mayer | #define SPR_440_DVT1 (0x395) |
1070 | 76a66253 | j_mayer | #define SPR_440_DVT2 (0x396) |
1071 | 76a66253 | j_mayer | #define SPR_440_DVT3 (0x397) |
1072 | 76a66253 | j_mayer | #define SPR_440_DVLIM (0x398) |
1073 | 76a66253 | j_mayer | #define SPR_440_IVLIM (0x399) |
1074 | 76a66253 | j_mayer | #define SPR_440_RSTCFG (0x39B) |
1075 | 363be49c | j_mayer | #define SPR_BOOKE_DCBTRL (0x39C) |
1076 | 363be49c | j_mayer | #define SPR_BOOKE_DCBTRH (0x39D) |
1077 | 363be49c | j_mayer | #define SPR_BOOKE_ICBTRL (0x39E) |
1078 | 363be49c | j_mayer | #define SPR_BOOKE_ICBTRH (0x39F) |
1079 | 76a66253 | j_mayer | #define SPR_UMMCR0 (0x3A8) |
1080 | 76a66253 | j_mayer | #define SPR_UPMC1 (0x3A9) |
1081 | 76a66253 | j_mayer | #define SPR_UPMC2 (0x3AA) |
1082 | 76a66253 | j_mayer | #define SPR_USIA (0x3AB) |
1083 | 76a66253 | j_mayer | #define SPR_UMMCR1 (0x3AC) |
1084 | 76a66253 | j_mayer | #define SPR_UPMC3 (0x3AD) |
1085 | 76a66253 | j_mayer | #define SPR_UPMC4 (0x3AE) |
1086 | 76a66253 | j_mayer | #define SPR_USDA (0x3AF) |
1087 | 76a66253 | j_mayer | #define SPR_40x_ZPR (0x3B0) |
1088 | 363be49c | j_mayer | #define SPR_BOOKE_MAS7 (0x3B0) |
1089 | 76a66253 | j_mayer | #define SPR_40x_PID (0x3B1) |
1090 | 76a66253 | j_mayer | #define SPR_440_MMUCR (0x3B2) |
1091 | 76a66253 | j_mayer | #define SPR_4xx_CCR0 (0x3B3) |
1092 | 363be49c | j_mayer | #define SPR_BOOKE_EPLC (0x3B3) |
1093 | 76a66253 | j_mayer | #define SPR_405_IAC3 (0x3B4) |
1094 | 363be49c | j_mayer | #define SPR_BOOKE_EPSC (0x3B4) |
1095 | 76a66253 | j_mayer | #define SPR_405_IAC4 (0x3B5) |
1096 | 76a66253 | j_mayer | #define SPR_405_DVC1 (0x3B6) |
1097 | 76a66253 | j_mayer | #define SPR_405_DVC2 (0x3B7) |
1098 | 76a66253 | j_mayer | #define SPR_MMCR0 (0x3B8) |
1099 | 76a66253 | j_mayer | #define SPR_PMC1 (0x3B9) |
1100 | 76a66253 | j_mayer | #define SPR_40x_SGR (0x3B9) |
1101 | 76a66253 | j_mayer | #define SPR_PMC2 (0x3BA) |
1102 | 76a66253 | j_mayer | #define SPR_40x_DCWR (0x3BA) |
1103 | 76a66253 | j_mayer | #define SPR_SIA (0x3BB) |
1104 | 76a66253 | j_mayer | #define SPR_405_SLER (0x3BB) |
1105 | 76a66253 | j_mayer | #define SPR_MMCR1 (0x3BC) |
1106 | 76a66253 | j_mayer | #define SPR_405_SU0R (0x3BC) |
1107 | 76a66253 | j_mayer | #define SPR_PMC3 (0x3BD) |
1108 | 76a66253 | j_mayer | #define SPR_405_DBCR1 (0x3BD) |
1109 | 76a66253 | j_mayer | #define SPR_PMC4 (0x3BE) |
1110 | 76a66253 | j_mayer | #define SPR_SDA (0x3BF) |
1111 | 76a66253 | j_mayer | #define SPR_403_VTBL (0x3CC) |
1112 | 76a66253 | j_mayer | #define SPR_403_VTBU (0x3CD) |
1113 | 76a66253 | j_mayer | #define SPR_DMISS (0x3D0) |
1114 | 76a66253 | j_mayer | #define SPR_DCMP (0x3D1) |
1115 | 76a66253 | j_mayer | #define SPR_HASH1 (0x3D2) |
1116 | 76a66253 | j_mayer | #define SPR_HASH2 (0x3D3) |
1117 | 363be49c | j_mayer | #define SPR_BOOKE_ICBDR (0x3D3) |
1118 | 76a66253 | j_mayer | #define SPR_IMISS (0x3D4) |
1119 | 76a66253 | j_mayer | #define SPR_40x_ESR (0x3D4) |
1120 | 76a66253 | j_mayer | #define SPR_ICMP (0x3D5) |
1121 | 76a66253 | j_mayer | #define SPR_40x_DEAR (0x3D5) |
1122 | 76a66253 | j_mayer | #define SPR_RPA (0x3D6) |
1123 | 76a66253 | j_mayer | #define SPR_40x_EVPR (0x3D6) |
1124 | 76a66253 | j_mayer | #define SPR_403_CDBCR (0x3D7) |
1125 | 76a66253 | j_mayer | #define SPR_TCR (0x3D8) |
1126 | 76a66253 | j_mayer | #define SPR_40x_TSR (0x3D8) |
1127 | 76a66253 | j_mayer | #define SPR_IBR (0x3DA) |
1128 | 76a66253 | j_mayer | #define SPR_40x_TCR (0x3DA) |
1129 | 76a66253 | j_mayer | #define SPR_ESASR (0x3DB) |
1130 | 76a66253 | j_mayer | #define SPR_40x_PIT (0x3DB) |
1131 | 76a66253 | j_mayer | #define SPR_403_TBL (0x3DC) |
1132 | 76a66253 | j_mayer | #define SPR_403_TBU (0x3DD) |
1133 | 76a66253 | j_mayer | #define SPR_SEBR (0x3DE) |
1134 | 76a66253 | j_mayer | #define SPR_40x_SRR2 (0x3DE) |
1135 | 76a66253 | j_mayer | #define SPR_SER (0x3DF) |
1136 | 76a66253 | j_mayer | #define SPR_40x_SRR3 (0x3DF) |
1137 | 76a66253 | j_mayer | #define SPR_HID0 (0x3F0) |
1138 | 76a66253 | j_mayer | #define SPR_40x_DBSR (0x3F0) |
1139 | 76a66253 | j_mayer | #define SPR_HID1 (0x3F1) |
1140 | 76a66253 | j_mayer | #define SPR_IABR (0x3F2) |
1141 | 76a66253 | j_mayer | #define SPR_40x_DBCR0 (0x3F2) |
1142 | 76a66253 | j_mayer | #define SPR_601_HID2 (0x3F2) |
1143 | 76a66253 | j_mayer | #define SPR_E500_L1CSR0 (0x3F2) |
1144 | 76a66253 | j_mayer | #define SPR_HID2 (0x3F3) |
1145 | 76a66253 | j_mayer | #define SPR_E500_L1CSR1 (0x3F3) |
1146 | 76a66253 | j_mayer | #define SPR_440_DBDR (0x3F3) |
1147 | 76a66253 | j_mayer | #define SPR_40x_IAC1 (0x3F4) |
1148 | 363be49c | j_mayer | #define SPR_BOOKE_MMUCSR0 (0x3F4) |
1149 | 76a66253 | j_mayer | #define SPR_DABR (0x3F5) |
1150 | 3fc6c082 | bellard | #define DABR_MASK (~(target_ulong)0x7) |
1151 | 76a66253 | j_mayer | #define SPR_E500_BUCSR (0x3F5) |
1152 | 76a66253 | j_mayer | #define SPR_40x_IAC2 (0x3F5) |
1153 | 76a66253 | j_mayer | #define SPR_601_HID5 (0x3F5) |
1154 | 76a66253 | j_mayer | #define SPR_40x_DAC1 (0x3F6) |
1155 | 76a66253 | j_mayer | #define SPR_40x_DAC2 (0x3F7) |
1156 | 363be49c | j_mayer | #define SPR_BOOKE_MMUCFG (0x3F7) |
1157 | 76a66253 | j_mayer | #define SPR_L2PM (0x3F8) |
1158 | 76a66253 | j_mayer | #define SPR_750_HID2 (0x3F8) |
1159 | 76a66253 | j_mayer | #define SPR_L2CR (0x3F9) |
1160 | 76a66253 | j_mayer | #define SPR_IABR2 (0x3FA) |
1161 | 76a66253 | j_mayer | #define SPR_40x_DCCR (0x3FA) |
1162 | 76a66253 | j_mayer | #define SPR_ICTC (0x3FB) |
1163 | 76a66253 | j_mayer | #define SPR_40x_ICCR (0x3FB) |
1164 | 76a66253 | j_mayer | #define SPR_THRM1 (0x3FC) |
1165 | 76a66253 | j_mayer | #define SPR_403_PBL1 (0x3FC) |
1166 | 76a66253 | j_mayer | #define SPR_SP (0x3FD) |
1167 | 76a66253 | j_mayer | #define SPR_THRM2 (0x3FD) |
1168 | 76a66253 | j_mayer | #define SPR_403_PBU1 (0x3FD) |
1169 | 76a66253 | j_mayer | #define SPR_LT (0x3FE) |
1170 | 76a66253 | j_mayer | #define SPR_THRM3 (0x3FE) |
1171 | 76a66253 | j_mayer | #define SPR_FPECR (0x3FE) |
1172 | 76a66253 | j_mayer | #define SPR_403_PBL2 (0x3FE) |
1173 | 76a66253 | j_mayer | #define SPR_PIR (0x3FF) |
1174 | 76a66253 | j_mayer | #define SPR_403_PBU2 (0x3FF) |
1175 | 76a66253 | j_mayer | #define SPR_601_HID15 (0x3FF) |
1176 | 76a66253 | j_mayer | #define SPR_E500_SVR (0x3FF) |
1177 | 79aceca5 | bellard | |
1178 | 76a66253 | j_mayer | /*****************************************************************************/
|
1179 | 9a64fbe4 | bellard | /* Memory access type :
|
1180 | 9a64fbe4 | bellard | * may be needed for precise access rights control and precise exceptions.
|
1181 | 9a64fbe4 | bellard | */
|
1182 | 79aceca5 | bellard | enum {
|
1183 | 9a64fbe4 | bellard | /* 1 bit to define user level / supervisor access */
|
1184 | 9a64fbe4 | bellard | ACCESS_USER = 0x00,
|
1185 | 9a64fbe4 | bellard | ACCESS_SUPER = 0x01,
|
1186 | 9a64fbe4 | bellard | /* Type of instruction that generated the access */
|
1187 | 9a64fbe4 | bellard | ACCESS_CODE = 0x10, /* Code fetch access */ |
1188 | 9a64fbe4 | bellard | ACCESS_INT = 0x20, /* Integer load/store access */ |
1189 | 9a64fbe4 | bellard | ACCESS_FLOAT = 0x30, /* floating point load/store access */ |
1190 | 9a64fbe4 | bellard | ACCESS_RES = 0x40, /* load/store with reservation */ |
1191 | 9a64fbe4 | bellard | ACCESS_EXT = 0x50, /* external access */ |
1192 | 9a64fbe4 | bellard | ACCESS_CACHE = 0x60, /* Cache manipulation */ |
1193 | 9a64fbe4 | bellard | }; |
1194 | 9a64fbe4 | bellard | |
1195 | 9a64fbe4 | bellard | /*****************************************************************************/
|
1196 | 9a64fbe4 | bellard | /* Exceptions */
|
1197 | 2be0071f | bellard | #define EXCP_NONE -1 |
1198 | 2be0071f | bellard | /* PowerPC hardware exceptions : exception vectors defined in PowerPC book 3 */
|
1199 | 2be0071f | bellard | #define EXCP_RESET 0x0100 /* System reset */ |
1200 | 2be0071f | bellard | #define EXCP_MACHINE_CHECK 0x0200 /* Machine check exception */ |
1201 | 2be0071f | bellard | #define EXCP_DSI 0x0300 /* Data storage exception */ |
1202 | 2be0071f | bellard | #define EXCP_DSEG 0x0380 /* Data segment exception */ |
1203 | 2be0071f | bellard | #define EXCP_ISI 0x0400 /* Instruction storage exception */ |
1204 | 2be0071f | bellard | #define EXCP_ISEG 0x0480 /* Instruction segment exception */ |
1205 | 2be0071f | bellard | #define EXCP_EXTERNAL 0x0500 /* External interruption */ |
1206 | 2be0071f | bellard | #define EXCP_ALIGN 0x0600 /* Alignment exception */ |
1207 | 2be0071f | bellard | #define EXCP_PROGRAM 0x0700 /* Program exception */ |
1208 | 2be0071f | bellard | #define EXCP_NO_FP 0x0800 /* Floating point unavailable exception */ |
1209 | 2be0071f | bellard | #define EXCP_DECR 0x0900 /* Decrementer exception */ |
1210 | 2be0071f | bellard | #define EXCP_HDECR 0x0980 /* Hypervisor decrementer exception */ |
1211 | 2be0071f | bellard | #define EXCP_SYSCALL 0x0C00 /* System call */ |
1212 | 2be0071f | bellard | #define EXCP_TRACE 0x0D00 /* Trace exception */ |
1213 | 2be0071f | bellard | #define EXCP_PERF 0x0F00 /* Performance monitor exception */ |
1214 | 2be0071f | bellard | /* Exceptions defined in PowerPC 32 bits programming environment manual */
|
1215 | 2be0071f | bellard | #define EXCP_FP_ASSIST 0x0E00 /* Floating-point assist */ |
1216 | 2be0071f | bellard | /* Implementation specific exceptions */
|
1217 | 2be0071f | bellard | /* 40x exceptions */
|
1218 | 2be0071f | bellard | #define EXCP_40x_PIT 0x1000 /* Programmable interval timer interrupt */ |
1219 | 2be0071f | bellard | #define EXCP_40x_FIT 0x1010 /* Fixed interval timer interrupt */ |
1220 | 2be0071f | bellard | #define EXCP_40x_WATCHDOG 0x1020 /* Watchdog timer exception */ |
1221 | 2be0071f | bellard | #define EXCP_40x_DTLBMISS 0x1100 /* Data TLB miss exception */ |
1222 | 2be0071f | bellard | #define EXCP_40x_ITLBMISS 0x1200 /* Instruction TLB miss exception */ |
1223 | 2be0071f | bellard | #define EXCP_40x_DEBUG 0x2000 /* Debug exception */ |
1224 | 2be0071f | bellard | /* 405 specific exceptions */
|
1225 | 2be0071f | bellard | #define EXCP_405_APU 0x0F20 /* APU unavailable exception */ |
1226 | 2be0071f | bellard | /* TLB assist exceptions (602/603) */
|
1227 | 2be0071f | bellard | #define EXCP_I_TLBMISS 0x1000 /* Instruction TLB miss */ |
1228 | 2be0071f | bellard | #define EXCP_DL_TLBMISS 0x1100 /* Data load TLB miss */ |
1229 | 2be0071f | bellard | #define EXCP_DS_TLBMISS 0x1200 /* Data store TLB miss */ |
1230 | 2be0071f | bellard | /* Breakpoint exceptions (602/603/604/620/740/745/750/755...) */
|
1231 | 2be0071f | bellard | #define EXCP_IABR 0x1300 /* Instruction address breakpoint */ |
1232 | 2be0071f | bellard | #define EXCP_SMI 0x1400 /* System management interrupt */ |
1233 | 2be0071f | bellard | /* Altivec related exceptions */
|
1234 | 2be0071f | bellard | #define EXCP_VPU 0x0F20 /* VPU unavailable exception */ |
1235 | 2be0071f | bellard | /* 601 specific exceptions */
|
1236 | 2be0071f | bellard | #define EXCP_601_IO 0x0600 /* IO error exception */ |
1237 | 2be0071f | bellard | #define EXCP_601_RUNM 0x2000 /* Run mode exception */ |
1238 | 2be0071f | bellard | /* 602 specific exceptions */
|
1239 | 2be0071f | bellard | #define EXCP_602_WATCHDOG 0x1500 /* Watchdog exception */ |
1240 | 2be0071f | bellard | #define EXCP_602_EMUL 0x1600 /* Emulation trap exception */ |
1241 | 2be0071f | bellard | /* G2 specific exceptions */
|
1242 | 2be0071f | bellard | #define EXCP_G2_CRIT 0x0A00 /* Critical interrupt */ |
1243 | 2be0071f | bellard | /* MPC740/745/750 & IBM 750 specific exceptions */
|
1244 | 2be0071f | bellard | #define EXCP_THRM 0x1700 /* Thermal management interrupt */ |
1245 | 2be0071f | bellard | /* 74xx specific exceptions */
|
1246 | 2be0071f | bellard | #define EXCP_74xx_VPUA 0x1600 /* VPU assist exception */ |
1247 | 2be0071f | bellard | /* 970FX specific exceptions */
|
1248 | 2be0071f | bellard | #define EXCP_970_SOFTP 0x1500 /* Soft patch exception */ |
1249 | 2be0071f | bellard | #define EXCP_970_MAINT 0x1600 /* Maintenance exception */ |
1250 | 2be0071f | bellard | #define EXCP_970_THRM 0x1800 /* Thermal exception */ |
1251 | 2be0071f | bellard | #define EXCP_970_VPUA 0x1700 /* VPU assist exception */ |
1252 | 0487d6a8 | j_mayer | /* SPE related exceptions */
|
1253 | 0487d6a8 | j_mayer | #define EXCP_NO_SPE 0x0F20 /* SPE unavailable exception */ |
1254 | 2be0071f | bellard | /* End of exception vectors area */
|
1255 | 2be0071f | bellard | #define EXCP_PPC_MAX 0x4000 |
1256 | 2be0071f | bellard | /* Qemu exceptions: special cases we want to stop translation */
|
1257 | 2be0071f | bellard | #define EXCP_MTMSR 0x11000 /* mtmsr instruction: */ |
1258 | 76a66253 | j_mayer | /* may change privilege level */
|
1259 | 2be0071f | bellard | #define EXCP_BRANCH 0x11001 /* branch instruction */ |
1260 | 2be0071f | bellard | #define EXCP_SYSCALL_USER 0x12000 /* System call in user mode only */ |
1261 | 2be0071f | bellard | #define EXCP_INTERRUPT_CRITICAL 0x13000 /* critical IRQ */ |
1262 | 2be0071f | bellard | |
1263 | 9a64fbe4 | bellard | /* Error codes */
|
1264 | 9a64fbe4 | bellard | enum {
|
1265 | 9a64fbe4 | bellard | /* Exception subtypes for EXCP_ALIGN */
|
1266 | 9a64fbe4 | bellard | EXCP_ALIGN_FP = 0x01, /* FP alignment exception */ |
1267 | 9a64fbe4 | bellard | EXCP_ALIGN_LST = 0x02, /* Unaligned mult/extern load/store */ |
1268 | 9a64fbe4 | bellard | EXCP_ALIGN_LE = 0x03, /* Multiple little-endian access */ |
1269 | 9a64fbe4 | bellard | EXCP_ALIGN_PROT = 0x04, /* Access cross protection boundary */ |
1270 | 9a64fbe4 | bellard | EXCP_ALIGN_BAT = 0x05, /* Access cross a BAT/seg boundary */ |
1271 | 9a64fbe4 | bellard | EXCP_ALIGN_CACHE = 0x06, /* Impossible dcbz access */ |
1272 | 9a64fbe4 | bellard | /* Exception subtypes for EXCP_PROGRAM */
|
1273 | 79aceca5 | bellard | /* FP exceptions */
|
1274 | 9a64fbe4 | bellard | EXCP_FP = 0x10,
|
1275 | 9a64fbe4 | bellard | EXCP_FP_OX = 0x01, /* FP overflow */ |
1276 | 9a64fbe4 | bellard | EXCP_FP_UX = 0x02, /* FP underflow */ |
1277 | 9a64fbe4 | bellard | EXCP_FP_ZX = 0x03, /* FP divide by zero */ |
1278 | 9a64fbe4 | bellard | EXCP_FP_XX = 0x04, /* FP inexact */ |
1279 | 9a64fbe4 | bellard | EXCP_FP_VXNAN = 0x05, /* FP invalid SNaN op */ |
1280 | 9a64fbe4 | bellard | EXCP_FP_VXISI = 0x06, /* FP invalid infinite substraction */ |
1281 | 9a64fbe4 | bellard | EXCP_FP_VXIDI = 0x07, /* FP invalid infinite divide */ |
1282 | 9a64fbe4 | bellard | EXCP_FP_VXZDZ = 0x08, /* FP invalid zero divide */ |
1283 | 9a64fbe4 | bellard | EXCP_FP_VXIMZ = 0x09, /* FP invalid infinite * zero */ |
1284 | 9a64fbe4 | bellard | EXCP_FP_VXVC = 0x0A, /* FP invalid compare */ |
1285 | 9a64fbe4 | bellard | EXCP_FP_VXSOFT = 0x0B, /* FP invalid operation */ |
1286 | 9a64fbe4 | bellard | EXCP_FP_VXSQRT = 0x0C, /* FP invalid square root */ |
1287 | 9a64fbe4 | bellard | EXCP_FP_VXCVI = 0x0D, /* FP invalid integer conversion */ |
1288 | 79aceca5 | bellard | /* Invalid instruction */
|
1289 | 9a64fbe4 | bellard | EXCP_INVAL = 0x20,
|
1290 | 9a64fbe4 | bellard | EXCP_INVAL_INVAL = 0x01, /* Invalid instruction */ |
1291 | 9a64fbe4 | bellard | EXCP_INVAL_LSWX = 0x02, /* Invalid lswx instruction */ |
1292 | 9a64fbe4 | bellard | EXCP_INVAL_SPR = 0x03, /* Invalid SPR access */ |
1293 | 9a64fbe4 | bellard | EXCP_INVAL_FP = 0x04, /* Unimplemented mandatory fp instr */ |
1294 | 79aceca5 | bellard | /* Privileged instruction */
|
1295 | 9a64fbe4 | bellard | EXCP_PRIV = 0x30,
|
1296 | 9a64fbe4 | bellard | EXCP_PRIV_OPC = 0x01,
|
1297 | 9a64fbe4 | bellard | EXCP_PRIV_REG = 0x02,
|
1298 | 79aceca5 | bellard | /* Trap */
|
1299 | 9a64fbe4 | bellard | EXCP_TRAP = 0x40,
|
1300 | 79aceca5 | bellard | }; |
1301 | 79aceca5 | bellard | |
1302 | 47103572 | j_mayer | /* Hardware interruption sources:
|
1303 | 47103572 | j_mayer | * all those exception can be raised simulteaneously
|
1304 | 47103572 | j_mayer | */
|
1305 | 47103572 | j_mayer | enum {
|
1306 | 47103572 | j_mayer | PPC_INTERRUPT_RESET = 0, /* Reset / critical input */ |
1307 | 47103572 | j_mayer | PPC_INTERRUPT_MCK = 1, /* Machine check exception */ |
1308 | 47103572 | j_mayer | PPC_INTERRUPT_EXT = 2, /* External interrupt */ |
1309 | 47103572 | j_mayer | PPC_INTERRUPT_DECR = 3, /* Decrementer exception */ |
1310 | 47103572 | j_mayer | PPC_INTERRUPT_HDECR = 4, /* Hypervisor decrementer exception */ |
1311 | 47103572 | j_mayer | PPC_INTERRUPT_PIT = 5, /* Programmable inteval timer interrupt */ |
1312 | 47103572 | j_mayer | PPC_INTERRUPT_FIT = 6, /* Fixed interval timer interrupt */ |
1313 | 47103572 | j_mayer | PPC_INTERRUPT_WDT = 7, /* Watchdog timer interrupt */ |
1314 | 47103572 | j_mayer | PPC_INTERRUPT_DEBUG = 8, /* External debug exception */ |
1315 | 47103572 | j_mayer | }; |
1316 | 47103572 | j_mayer | |
1317 | 9a64fbe4 | bellard | /*****************************************************************************/
|
1318 | 9a64fbe4 | bellard | |
1319 | 79aceca5 | bellard | #endif /* !defined (__CPU_PPC_H__) */ |