root / target-ppc / op_template.h @ 86cc1ce0
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1 | 28b6751f | bellard | /*
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2 | 3fc6c082 | bellard | * PowerPC emulation micro-operations for qemu.
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3 | 28b6751f | bellard | *
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4 | 76a66253 | j_mayer | * Copyright (c) 2003-2007 Jocelyn Mayer
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5 | 28b6751f | bellard | *
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6 | 28b6751f | bellard | * This library is free software; you can redistribute it and/or
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7 | 28b6751f | bellard | * modify it under the terms of the GNU Lesser General Public
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8 | 28b6751f | bellard | * License as published by the Free Software Foundation; either
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9 | 28b6751f | bellard | * version 2 of the License, or (at your option) any later version.
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10 | 28b6751f | bellard | *
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11 | 28b6751f | bellard | * This library is distributed in the hope that it will be useful,
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12 | 28b6751f | bellard | * but WITHOUT ANY WARRANTY; without even the implied warranty of
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13 | 28b6751f | bellard | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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14 | 28b6751f | bellard | * Lesser General Public License for more details.
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15 | 28b6751f | bellard | *
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16 | 28b6751f | bellard | * You should have received a copy of the GNU Lesser General Public
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17 | 28b6751f | bellard | * License along with this library; if not, write to the Free Software
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18 | 28b6751f | bellard | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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19 | 28b6751f | bellard | */
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20 | 28b6751f | bellard | |
21 | 9a64fbe4 | bellard | /* General purpose registers moves */
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22 | 76a66253 | j_mayer | void OPPROTO glue(op_load_gpr_T0_gpr, REG) (void) |
23 | 28b6751f | bellard | { |
24 | 28b6751f | bellard | T0 = regs->gpr[REG]; |
25 | 9a64fbe4 | bellard | RETURN(); |
26 | 28b6751f | bellard | } |
27 | 28b6751f | bellard | |
28 | 76a66253 | j_mayer | void OPPROTO glue(op_load_gpr_T1_gpr, REG) (void) |
29 | 28b6751f | bellard | { |
30 | 28b6751f | bellard | T1 = regs->gpr[REG]; |
31 | 9a64fbe4 | bellard | RETURN(); |
32 | 28b6751f | bellard | } |
33 | 28b6751f | bellard | |
34 | 76a66253 | j_mayer | void OPPROTO glue(op_load_gpr_T2_gpr, REG) (void) |
35 | 28b6751f | bellard | { |
36 | 28b6751f | bellard | T2 = regs->gpr[REG]; |
37 | 9a64fbe4 | bellard | RETURN(); |
38 | 28b6751f | bellard | } |
39 | 28b6751f | bellard | |
40 | 76a66253 | j_mayer | void OPPROTO glue(op_store_T0_gpr_gpr, REG) (void) |
41 | 28b6751f | bellard | { |
42 | 28b6751f | bellard | regs->gpr[REG] = T0; |
43 | 9a64fbe4 | bellard | RETURN(); |
44 | 28b6751f | bellard | } |
45 | 28b6751f | bellard | |
46 | 76a66253 | j_mayer | void OPPROTO glue(op_store_T1_gpr_gpr, REG) (void) |
47 | 28b6751f | bellard | { |
48 | 28b6751f | bellard | regs->gpr[REG] = T1; |
49 | 9a64fbe4 | bellard | RETURN(); |
50 | 28b6751f | bellard | } |
51 | 28b6751f | bellard | |
52 | 76a66253 | j_mayer | #if 0 // unused
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53 | 76a66253 | j_mayer | void OPPROTO glue(op_store_T2_gpr_gpr, REG) (void)
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54 | 28b6751f | bellard | {
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55 | 28b6751f | bellard | regs->gpr[REG] = T2;
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56 | 9a64fbe4 | bellard | RETURN();
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57 | 28b6751f | bellard | }
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58 | 76a66253 | j_mayer | #endif
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59 | 28b6751f | bellard | |
60 | 0487d6a8 | j_mayer | #if defined(TARGET_PPCSPE)
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61 | 0487d6a8 | j_mayer | void OPPROTO glue(op_load_gpr64_T0_gpr, REG) (void) |
62 | 0487d6a8 | j_mayer | { |
63 | 0487d6a8 | j_mayer | T0_64 = regs->gpr[REG]; |
64 | 0487d6a8 | j_mayer | RETURN(); |
65 | 0487d6a8 | j_mayer | } |
66 | 0487d6a8 | j_mayer | |
67 | 0487d6a8 | j_mayer | void OPPROTO glue(op_load_gpr64_T1_gpr, REG) (void) |
68 | 0487d6a8 | j_mayer | { |
69 | 0487d6a8 | j_mayer | T1_64 = regs->gpr[REG]; |
70 | 0487d6a8 | j_mayer | RETURN(); |
71 | 0487d6a8 | j_mayer | } |
72 | 0487d6a8 | j_mayer | |
73 | 0487d6a8 | j_mayer | #if 0 // unused
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74 | 0487d6a8 | j_mayer | void OPPROTO glue(op_load_gpr64_T2_gpr, REG) (void)
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75 | 0487d6a8 | j_mayer | {
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76 | 0487d6a8 | j_mayer | T2_64 = regs->gpr[REG];
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77 | 0487d6a8 | j_mayer | RETURN();
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78 | 0487d6a8 | j_mayer | }
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79 | 0487d6a8 | j_mayer | #endif
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80 | 0487d6a8 | j_mayer | |
81 | 0487d6a8 | j_mayer | void OPPROTO glue(op_store_T0_gpr64_gpr, REG) (void) |
82 | 0487d6a8 | j_mayer | { |
83 | 0487d6a8 | j_mayer | regs->gpr[REG] = T0_64; |
84 | 0487d6a8 | j_mayer | RETURN(); |
85 | 0487d6a8 | j_mayer | } |
86 | 0487d6a8 | j_mayer | |
87 | 0487d6a8 | j_mayer | void OPPROTO glue(op_store_T1_gpr64_gpr, REG) (void) |
88 | 0487d6a8 | j_mayer | { |
89 | 0487d6a8 | j_mayer | regs->gpr[REG] = T1_64; |
90 | 0487d6a8 | j_mayer | RETURN(); |
91 | 0487d6a8 | j_mayer | } |
92 | 0487d6a8 | j_mayer | |
93 | 0487d6a8 | j_mayer | #if 0 // unused
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94 | 0487d6a8 | j_mayer | void OPPROTO glue(op_store_T2_gpr64_gpr, REG) (void)
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95 | 0487d6a8 | j_mayer | {
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96 | 0487d6a8 | j_mayer | regs->gpr[REG] = T2_64;
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97 | 0487d6a8 | j_mayer | RETURN();
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98 | 0487d6a8 | j_mayer | }
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99 | 0487d6a8 | j_mayer | #endif
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100 | 0487d6a8 | j_mayer | #endif /* defined(TARGET_PPCSPE) */ |
101 | 0487d6a8 | j_mayer | |
102 | 28b6751f | bellard | #if REG <= 7 |
103 | 9a64fbe4 | bellard | /* Condition register moves */
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104 | 76a66253 | j_mayer | void OPPROTO glue(op_load_crf_T0_crf, REG) (void) |
105 | 28b6751f | bellard | { |
106 | 28b6751f | bellard | T0 = regs->crf[REG]; |
107 | 9a64fbe4 | bellard | RETURN(); |
108 | 28b6751f | bellard | } |
109 | 28b6751f | bellard | |
110 | 76a66253 | j_mayer | void OPPROTO glue(op_load_crf_T1_crf, REG) (void) |
111 | 28b6751f | bellard | { |
112 | 28b6751f | bellard | T1 = regs->crf[REG]; |
113 | 9a64fbe4 | bellard | RETURN(); |
114 | 28b6751f | bellard | } |
115 | 28b6751f | bellard | |
116 | 76a66253 | j_mayer | void OPPROTO glue(op_store_T0_crf_crf, REG) (void) |
117 | 28b6751f | bellard | { |
118 | 28b6751f | bellard | regs->crf[REG] = T0; |
119 | 9a64fbe4 | bellard | RETURN(); |
120 | 28b6751f | bellard | } |
121 | 28b6751f | bellard | |
122 | 76a66253 | j_mayer | void OPPROTO glue(op_store_T1_crf_crf, REG) (void) |
123 | 28b6751f | bellard | { |
124 | 28b6751f | bellard | regs->crf[REG] = T1; |
125 | 9a64fbe4 | bellard | RETURN(); |
126 | 28b6751f | bellard | } |
127 | 28b6751f | bellard | |
128 | fb0eaffc | bellard | /* Floating point condition and status register moves */
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129 | 76a66253 | j_mayer | void OPPROTO glue(op_load_fpscr_T0_fpscr, REG) (void) |
130 | fb0eaffc | bellard | { |
131 | fb0eaffc | bellard | T0 = regs->fpscr[REG]; |
132 | fb0eaffc | bellard | RETURN(); |
133 | fb0eaffc | bellard | } |
134 | fb0eaffc | bellard | |
135 | fb0eaffc | bellard | #if REG == 0 |
136 | 76a66253 | j_mayer | void OPPROTO glue(op_store_T0_fpscr_fpscr, REG) (void) |
137 | fb0eaffc | bellard | { |
138 | fb0eaffc | bellard | regs->fpscr[REG] = (regs->fpscr[REG] & 0x9) | (T0 & ~0x9); |
139 | fb0eaffc | bellard | RETURN(); |
140 | fb0eaffc | bellard | } |
141 | fb0eaffc | bellard | |
142 | 76a66253 | j_mayer | void OPPROTO glue(op_clear_fpscr_fpscr, REG) (void) |
143 | fb0eaffc | bellard | { |
144 | fb0eaffc | bellard | regs->fpscr[REG] = (regs->fpscr[REG] & 0x9);
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145 | fb0eaffc | bellard | RETURN(); |
146 | fb0eaffc | bellard | } |
147 | fb0eaffc | bellard | #else
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148 | 76a66253 | j_mayer | void OPPROTO glue(op_store_T0_fpscr_fpscr, REG) (void) |
149 | fb0eaffc | bellard | { |
150 | fb0eaffc | bellard | regs->fpscr[REG] = T0; |
151 | fb0eaffc | bellard | RETURN(); |
152 | fb0eaffc | bellard | } |
153 | fb0eaffc | bellard | |
154 | 76a66253 | j_mayer | void OPPROTO glue(op_clear_fpscr_fpscr, REG) (void) |
155 | fb0eaffc | bellard | { |
156 | fb0eaffc | bellard | regs->fpscr[REG] = 0x0;
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157 | fb0eaffc | bellard | RETURN(); |
158 | fb0eaffc | bellard | } |
159 | fb0eaffc | bellard | #endif
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160 | fb0eaffc | bellard | |
161 | 28b6751f | bellard | #endif /* REG <= 7 */ |
162 | 28b6751f | bellard | |
163 | fb0eaffc | bellard | /* floating point registers moves */
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164 | 76a66253 | j_mayer | void OPPROTO glue(op_load_fpr_FT0_fpr, REG) (void) |
165 | 28b6751f | bellard | { |
166 | 28b6751f | bellard | FT0 = env->fpr[REG]; |
167 | fb0eaffc | bellard | RETURN(); |
168 | 28b6751f | bellard | } |
169 | 28b6751f | bellard | |
170 | 76a66253 | j_mayer | void OPPROTO glue(op_store_FT0_fpr_fpr, REG) (void) |
171 | 28b6751f | bellard | { |
172 | 28b6751f | bellard | env->fpr[REG] = FT0; |
173 | fb0eaffc | bellard | RETURN(); |
174 | fb0eaffc | bellard | } |
175 | fb0eaffc | bellard | |
176 | 76a66253 | j_mayer | void OPPROTO glue(op_load_fpr_FT1_fpr, REG) (void) |
177 | fb0eaffc | bellard | { |
178 | fb0eaffc | bellard | FT1 = env->fpr[REG]; |
179 | fb0eaffc | bellard | RETURN(); |
180 | fb0eaffc | bellard | } |
181 | fb0eaffc | bellard | |
182 | 76a66253 | j_mayer | void OPPROTO glue(op_store_FT1_fpr_fpr, REG) (void) |
183 | fb0eaffc | bellard | { |
184 | fb0eaffc | bellard | env->fpr[REG] = FT1; |
185 | fb0eaffc | bellard | RETURN(); |
186 | fb0eaffc | bellard | } |
187 | fb0eaffc | bellard | |
188 | 76a66253 | j_mayer | void OPPROTO glue(op_load_fpr_FT2_fpr, REG) (void) |
189 | fb0eaffc | bellard | { |
190 | fb0eaffc | bellard | FT2 = env->fpr[REG]; |
191 | fb0eaffc | bellard | RETURN(); |
192 | fb0eaffc | bellard | } |
193 | fb0eaffc | bellard | |
194 | 76a66253 | j_mayer | #if 0 // unused
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195 | 76a66253 | j_mayer | void OPPROTO glue(op_store_FT2_fpr_fpr, REG) (void)
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196 | fb0eaffc | bellard | {
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197 | fb0eaffc | bellard | env->fpr[REG] = FT2;
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198 | fb0eaffc | bellard | RETURN();
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199 | 28b6751f | bellard | }
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200 | 9a64fbe4 | bellard | #endif
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201 | 9a64fbe4 | bellard | |
202 | 28b6751f | bellard | #undef REG |