root / tcg / hppa / tcg-target.c @ 86dbdd40
History | View | Annotate | Download (28.8 kB)
1 | f54b3f92 | aurel32 | /*
|
---|---|---|---|
2 | f54b3f92 | aurel32 | * Tiny Code Generator for QEMU
|
3 | f54b3f92 | aurel32 | *
|
4 | f54b3f92 | aurel32 | * Copyright (c) 2008 Fabrice Bellard
|
5 | f54b3f92 | aurel32 | *
|
6 | f54b3f92 | aurel32 | * Permission is hereby granted, free of charge, to any person obtaining a copy
|
7 | f54b3f92 | aurel32 | * of this software and associated documentation files (the "Software"), to deal
|
8 | f54b3f92 | aurel32 | * in the Software without restriction, including without limitation the rights
|
9 | f54b3f92 | aurel32 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
10 | f54b3f92 | aurel32 | * copies of the Software, and to permit persons to whom the Software is
|
11 | f54b3f92 | aurel32 | * furnished to do so, subject to the following conditions:
|
12 | f54b3f92 | aurel32 | *
|
13 | f54b3f92 | aurel32 | * The above copyright notice and this permission notice shall be included in
|
14 | f54b3f92 | aurel32 | * all copies or substantial portions of the Software.
|
15 | f54b3f92 | aurel32 | *
|
16 | f54b3f92 | aurel32 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
17 | f54b3f92 | aurel32 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
18 | f54b3f92 | aurel32 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
19 | f54b3f92 | aurel32 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
20 | f54b3f92 | aurel32 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
21 | f54b3f92 | aurel32 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
22 | f54b3f92 | aurel32 | * THE SOFTWARE.
|
23 | f54b3f92 | aurel32 | */
|
24 | f54b3f92 | aurel32 | |
25 | d4a9eb1f | blueswir1 | #ifndef NDEBUG
|
26 | f54b3f92 | aurel32 | static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = { |
27 | f54b3f92 | aurel32 | "%r0",
|
28 | f54b3f92 | aurel32 | "%r1",
|
29 | f54b3f92 | aurel32 | "%rp",
|
30 | f54b3f92 | aurel32 | "%r3",
|
31 | f54b3f92 | aurel32 | "%r4",
|
32 | f54b3f92 | aurel32 | "%r5",
|
33 | f54b3f92 | aurel32 | "%r6",
|
34 | f54b3f92 | aurel32 | "%r7",
|
35 | f54b3f92 | aurel32 | "%r8",
|
36 | f54b3f92 | aurel32 | "%r9",
|
37 | f54b3f92 | aurel32 | "%r10",
|
38 | f54b3f92 | aurel32 | "%r11",
|
39 | f54b3f92 | aurel32 | "%r12",
|
40 | f54b3f92 | aurel32 | "%r13",
|
41 | f54b3f92 | aurel32 | "%r14",
|
42 | f54b3f92 | aurel32 | "%r15",
|
43 | f54b3f92 | aurel32 | "%r16",
|
44 | f54b3f92 | aurel32 | "%r17",
|
45 | f54b3f92 | aurel32 | "%r18",
|
46 | f54b3f92 | aurel32 | "%r19",
|
47 | f54b3f92 | aurel32 | "%r20",
|
48 | f54b3f92 | aurel32 | "%r21",
|
49 | f54b3f92 | aurel32 | "%r22",
|
50 | f54b3f92 | aurel32 | "%r23",
|
51 | f54b3f92 | aurel32 | "%r24",
|
52 | f54b3f92 | aurel32 | "%r25",
|
53 | f54b3f92 | aurel32 | "%r26",
|
54 | f54b3f92 | aurel32 | "%dp",
|
55 | f54b3f92 | aurel32 | "%ret0",
|
56 | f54b3f92 | aurel32 | "%ret1",
|
57 | f54b3f92 | aurel32 | "%sp",
|
58 | f54b3f92 | aurel32 | "%r31",
|
59 | f54b3f92 | aurel32 | }; |
60 | d4a9eb1f | blueswir1 | #endif
|
61 | f54b3f92 | aurel32 | |
62 | f54b3f92 | aurel32 | static const int tcg_target_reg_alloc_order[] = { |
63 | f54b3f92 | aurel32 | TCG_REG_R4, |
64 | f54b3f92 | aurel32 | TCG_REG_R5, |
65 | f54b3f92 | aurel32 | TCG_REG_R6, |
66 | f54b3f92 | aurel32 | TCG_REG_R7, |
67 | f54b3f92 | aurel32 | TCG_REG_R8, |
68 | f54b3f92 | aurel32 | TCG_REG_R9, |
69 | f54b3f92 | aurel32 | TCG_REG_R10, |
70 | f54b3f92 | aurel32 | TCG_REG_R11, |
71 | f54b3f92 | aurel32 | TCG_REG_R12, |
72 | f54b3f92 | aurel32 | TCG_REG_R13, |
73 | f54b3f92 | aurel32 | |
74 | f54b3f92 | aurel32 | TCG_REG_R17, |
75 | f54b3f92 | aurel32 | TCG_REG_R14, |
76 | f54b3f92 | aurel32 | TCG_REG_R15, |
77 | f54b3f92 | aurel32 | TCG_REG_R16, |
78 | f54b3f92 | aurel32 | }; |
79 | f54b3f92 | aurel32 | |
80 | f54b3f92 | aurel32 | static const int tcg_target_call_iarg_regs[4] = { |
81 | f54b3f92 | aurel32 | TCG_REG_R26, |
82 | f54b3f92 | aurel32 | TCG_REG_R25, |
83 | f54b3f92 | aurel32 | TCG_REG_R24, |
84 | f54b3f92 | aurel32 | TCG_REG_R23, |
85 | f54b3f92 | aurel32 | }; |
86 | f54b3f92 | aurel32 | |
87 | f54b3f92 | aurel32 | static const int tcg_target_call_oarg_regs[2] = { |
88 | f54b3f92 | aurel32 | TCG_REG_RET0, |
89 | f54b3f92 | aurel32 | TCG_REG_RET1, |
90 | f54b3f92 | aurel32 | }; |
91 | f54b3f92 | aurel32 | |
92 | f54b3f92 | aurel32 | static void patch_reloc(uint8_t *code_ptr, int type, |
93 | f54b3f92 | aurel32 | tcg_target_long value, tcg_target_long addend) |
94 | f54b3f92 | aurel32 | { |
95 | f54b3f92 | aurel32 | switch (type) {
|
96 | f54b3f92 | aurel32 | case R_PARISC_PCREL17F:
|
97 | f54b3f92 | aurel32 | hppa_patch17f((uint32_t *)code_ptr, value, addend); |
98 | f54b3f92 | aurel32 | break;
|
99 | f54b3f92 | aurel32 | default:
|
100 | f54b3f92 | aurel32 | tcg_abort(); |
101 | f54b3f92 | aurel32 | } |
102 | f54b3f92 | aurel32 | } |
103 | f54b3f92 | aurel32 | |
104 | f54b3f92 | aurel32 | /* maximum number of register used for input function arguments */
|
105 | f54b3f92 | aurel32 | static inline int tcg_target_get_call_iarg_regs_count(int flags) |
106 | f54b3f92 | aurel32 | { |
107 | f54b3f92 | aurel32 | return 4; |
108 | f54b3f92 | aurel32 | } |
109 | f54b3f92 | aurel32 | |
110 | f54b3f92 | aurel32 | /* parse target specific constraints */
|
111 | d4a9eb1f | blueswir1 | static int target_parse_constraint(TCGArgConstraint *ct, const char **pct_str) |
112 | f54b3f92 | aurel32 | { |
113 | f54b3f92 | aurel32 | const char *ct_str; |
114 | f54b3f92 | aurel32 | |
115 | f54b3f92 | aurel32 | ct_str = *pct_str; |
116 | f54b3f92 | aurel32 | switch (ct_str[0]) { |
117 | f54b3f92 | aurel32 | case 'r': |
118 | f54b3f92 | aurel32 | ct->ct |= TCG_CT_REG; |
119 | f54b3f92 | aurel32 | tcg_regset_set32(ct->u.regs, 0, 0xffffffff); |
120 | f54b3f92 | aurel32 | break;
|
121 | f54b3f92 | aurel32 | case 'L': /* qemu_ld/st constraint */ |
122 | f54b3f92 | aurel32 | ct->ct |= TCG_CT_REG; |
123 | f54b3f92 | aurel32 | tcg_regset_set32(ct->u.regs, 0, 0xffffffff); |
124 | f54b3f92 | aurel32 | tcg_regset_reset_reg(ct->u.regs, TCG_REG_R26); |
125 | f54b3f92 | aurel32 | tcg_regset_reset_reg(ct->u.regs, TCG_REG_R25); |
126 | f54b3f92 | aurel32 | tcg_regset_reset_reg(ct->u.regs, TCG_REG_R24); |
127 | f54b3f92 | aurel32 | tcg_regset_reset_reg(ct->u.regs, TCG_REG_R23); |
128 | f54b3f92 | aurel32 | break;
|
129 | f54b3f92 | aurel32 | default:
|
130 | f54b3f92 | aurel32 | return -1; |
131 | f54b3f92 | aurel32 | } |
132 | f54b3f92 | aurel32 | ct_str++; |
133 | f54b3f92 | aurel32 | *pct_str = ct_str; |
134 | f54b3f92 | aurel32 | return 0; |
135 | f54b3f92 | aurel32 | } |
136 | f54b3f92 | aurel32 | |
137 | f54b3f92 | aurel32 | /* test if a constant matches the constraint */
|
138 | f54b3f92 | aurel32 | static inline int tcg_target_const_match(tcg_target_long val, |
139 | f54b3f92 | aurel32 | const TCGArgConstraint *arg_ct)
|
140 | f54b3f92 | aurel32 | { |
141 | f54b3f92 | aurel32 | int ct;
|
142 | f54b3f92 | aurel32 | |
143 | f54b3f92 | aurel32 | ct = arg_ct->ct; |
144 | f54b3f92 | aurel32 | |
145 | f54b3f92 | aurel32 | /* TODO */
|
146 | f54b3f92 | aurel32 | |
147 | f54b3f92 | aurel32 | return 0; |
148 | f54b3f92 | aurel32 | } |
149 | f54b3f92 | aurel32 | |
150 | f54b3f92 | aurel32 | #define INSN_OP(x) ((x) << 26) |
151 | f54b3f92 | aurel32 | #define INSN_EXT3BR(x) ((x) << 13) |
152 | f54b3f92 | aurel32 | #define INSN_EXT3SH(x) ((x) << 10) |
153 | f54b3f92 | aurel32 | #define INSN_EXT4(x) ((x) << 6) |
154 | f54b3f92 | aurel32 | #define INSN_EXT5(x) (x)
|
155 | f54b3f92 | aurel32 | #define INSN_EXT6(x) ((x) << 6) |
156 | f54b3f92 | aurel32 | #define INSN_EXT7(x) ((x) << 6) |
157 | f54b3f92 | aurel32 | #define INSN_EXT8A(x) ((x) << 6) |
158 | f54b3f92 | aurel32 | #define INSN_EXT8B(x) ((x) << 5) |
159 | f54b3f92 | aurel32 | #define INSN_T(x) (x)
|
160 | f54b3f92 | aurel32 | #define INSN_R1(x) ((x) << 16) |
161 | f54b3f92 | aurel32 | #define INSN_R2(x) ((x) << 21) |
162 | f54b3f92 | aurel32 | #define INSN_DEP_LEN(x) (32 - (x)) |
163 | f54b3f92 | aurel32 | #define INSN_SHDEP_CP(x) ((31 - (x)) << 5) |
164 | f54b3f92 | aurel32 | #define INSN_SHDEP_P(x) ((x) << 5) |
165 | f54b3f92 | aurel32 | #define INSN_COND(x) ((x) << 13) |
166 | f54b3f92 | aurel32 | |
167 | f54b3f92 | aurel32 | #define COND_NEVER 0 |
168 | f54b3f92 | aurel32 | #define COND_EQUAL 1 |
169 | f54b3f92 | aurel32 | #define COND_LT 2 |
170 | f54b3f92 | aurel32 | #define COND_LTEQ 3 |
171 | f54b3f92 | aurel32 | #define COND_LTU 4 |
172 | f54b3f92 | aurel32 | #define COND_LTUEQ 5 |
173 | f54b3f92 | aurel32 | #define COND_SV 6 |
174 | f54b3f92 | aurel32 | #define COND_OD 7 |
175 | f54b3f92 | aurel32 | |
176 | f54b3f92 | aurel32 | |
177 | f54b3f92 | aurel32 | /* Logical ADD */
|
178 | f54b3f92 | aurel32 | #define ARITH_ADD (INSN_OP(0x02) | INSN_EXT6(0x28)) |
179 | f54b3f92 | aurel32 | #define ARITH_AND (INSN_OP(0x02) | INSN_EXT6(0x08)) |
180 | f54b3f92 | aurel32 | #define ARITH_OR (INSN_OP(0x02) | INSN_EXT6(0x09)) |
181 | f54b3f92 | aurel32 | #define ARITH_XOR (INSN_OP(0x02) | INSN_EXT6(0x0a)) |
182 | f54b3f92 | aurel32 | #define ARITH_SUB (INSN_OP(0x02) | INSN_EXT6(0x10)) |
183 | f54b3f92 | aurel32 | |
184 | f54b3f92 | aurel32 | #define SHD (INSN_OP(0x34) | INSN_EXT3SH(2)) |
185 | f54b3f92 | aurel32 | #define VSHD (INSN_OP(0x34) | INSN_EXT3SH(0)) |
186 | f54b3f92 | aurel32 | #define DEP (INSN_OP(0x35) | INSN_EXT3SH(3)) |
187 | f54b3f92 | aurel32 | #define ZDEP (INSN_OP(0x35) | INSN_EXT3SH(2)) |
188 | f54b3f92 | aurel32 | #define ZVDEP (INSN_OP(0x35) | INSN_EXT3SH(0)) |
189 | f54b3f92 | aurel32 | #define EXTRU (INSN_OP(0x34) | INSN_EXT3SH(6)) |
190 | f54b3f92 | aurel32 | #define EXTRS (INSN_OP(0x34) | INSN_EXT3SH(7)) |
191 | f54b3f92 | aurel32 | #define VEXTRS (INSN_OP(0x34) | INSN_EXT3SH(5)) |
192 | f54b3f92 | aurel32 | |
193 | f54b3f92 | aurel32 | #define SUBI (INSN_OP(0x25)) |
194 | f54b3f92 | aurel32 | #define MTCTL (INSN_OP(0x00) | INSN_EXT8B(0xc2)) |
195 | f54b3f92 | aurel32 | |
196 | f54b3f92 | aurel32 | #define BL (INSN_OP(0x3a) | INSN_EXT3BR(0)) |
197 | f54b3f92 | aurel32 | #define BLE_SR4 (INSN_OP(0x39) | (1 << 13)) |
198 | f54b3f92 | aurel32 | #define BV (INSN_OP(0x3a) | INSN_EXT3BR(6)) |
199 | f54b3f92 | aurel32 | #define BV_N (INSN_OP(0x3a) | INSN_EXT3BR(6) | 2) |
200 | f54b3f92 | aurel32 | #define LDIL (INSN_OP(0x08)) |
201 | f54b3f92 | aurel32 | #define LDO (INSN_OP(0x0d)) |
202 | f54b3f92 | aurel32 | |
203 | f54b3f92 | aurel32 | #define LDB (INSN_OP(0x10)) |
204 | f54b3f92 | aurel32 | #define LDH (INSN_OP(0x11)) |
205 | f54b3f92 | aurel32 | #define LDW (INSN_OP(0x12)) |
206 | f54b3f92 | aurel32 | #define LDWM (INSN_OP(0x13)) |
207 | f54b3f92 | aurel32 | |
208 | f54b3f92 | aurel32 | #define STB (INSN_OP(0x18)) |
209 | f54b3f92 | aurel32 | #define STH (INSN_OP(0x19)) |
210 | f54b3f92 | aurel32 | #define STW (INSN_OP(0x1a)) |
211 | f54b3f92 | aurel32 | #define STWM (INSN_OP(0x1b)) |
212 | f54b3f92 | aurel32 | |
213 | f54b3f92 | aurel32 | #define COMBT (INSN_OP(0x20)) |
214 | f54b3f92 | aurel32 | #define COMBF (INSN_OP(0x22)) |
215 | f54b3f92 | aurel32 | |
216 | f54b3f92 | aurel32 | static int lowsignext(uint32_t val, int start, int length) |
217 | f54b3f92 | aurel32 | { |
218 | f54b3f92 | aurel32 | return (((val << 1) & ~(~0 << length)) | |
219 | f54b3f92 | aurel32 | ((val >> (length - 1)) & 1)) << start; |
220 | f54b3f92 | aurel32 | } |
221 | f54b3f92 | aurel32 | |
222 | f54b3f92 | aurel32 | static inline void tcg_out_mov(TCGContext *s, int ret, int arg) |
223 | f54b3f92 | aurel32 | { |
224 | f54b3f92 | aurel32 | /* PA1.1 defines COPY as OR r,0,t */
|
225 | f54b3f92 | aurel32 | tcg_out32(s, ARITH_OR | INSN_T(ret) | INSN_R1(arg) | INSN_R2(TCG_REG_R0)); |
226 | f54b3f92 | aurel32 | |
227 | f54b3f92 | aurel32 | /* PA2.0 defines COPY as LDO 0(r),t
|
228 | f54b3f92 | aurel32 | * but hppa-dis.c is unaware of this definition */
|
229 | f54b3f92 | aurel32 | /* tcg_out32(s, LDO | INSN_R1(ret) | INSN_R2(arg) | reassemble_14(0)); */
|
230 | f54b3f92 | aurel32 | } |
231 | f54b3f92 | aurel32 | |
232 | f54b3f92 | aurel32 | static inline void tcg_out_movi(TCGContext *s, TCGType type, |
233 | f54b3f92 | aurel32 | int ret, tcg_target_long arg)
|
234 | f54b3f92 | aurel32 | { |
235 | f54b3f92 | aurel32 | if (arg == (arg & 0x1fff)) { |
236 | f54b3f92 | aurel32 | tcg_out32(s, LDO | INSN_R1(ret) | INSN_R2(TCG_REG_R0) | |
237 | f54b3f92 | aurel32 | reassemble_14(arg)); |
238 | f54b3f92 | aurel32 | } else {
|
239 | f54b3f92 | aurel32 | tcg_out32(s, LDIL | INSN_R2(ret) | |
240 | f54b3f92 | aurel32 | reassemble_21(lrsel((uint32_t)arg, 0)));
|
241 | f54b3f92 | aurel32 | if (arg & 0x7ff) |
242 | f54b3f92 | aurel32 | tcg_out32(s, LDO | INSN_R1(ret) | INSN_R2(ret) | |
243 | f54b3f92 | aurel32 | reassemble_14(rrsel((uint32_t)arg, 0)));
|
244 | f54b3f92 | aurel32 | } |
245 | f54b3f92 | aurel32 | } |
246 | f54b3f92 | aurel32 | |
247 | f54b3f92 | aurel32 | static inline void tcg_out_ld_raw(TCGContext *s, int ret, |
248 | f54b3f92 | aurel32 | tcg_target_long arg) |
249 | f54b3f92 | aurel32 | { |
250 | f54b3f92 | aurel32 | tcg_out32(s, LDIL | INSN_R2(ret) | |
251 | f54b3f92 | aurel32 | reassemble_21(lrsel((uint32_t)arg, 0)));
|
252 | f54b3f92 | aurel32 | tcg_out32(s, LDW | INSN_R1(ret) | INSN_R2(ret) | |
253 | f54b3f92 | aurel32 | reassemble_14(rrsel((uint32_t)arg, 0)));
|
254 | f54b3f92 | aurel32 | } |
255 | f54b3f92 | aurel32 | |
256 | f54b3f92 | aurel32 | static inline void tcg_out_ld_ptr(TCGContext *s, int ret, |
257 | f54b3f92 | aurel32 | tcg_target_long arg) |
258 | f54b3f92 | aurel32 | { |
259 | f54b3f92 | aurel32 | tcg_out_ld_raw(s, ret, arg); |
260 | f54b3f92 | aurel32 | } |
261 | f54b3f92 | aurel32 | |
262 | f54b3f92 | aurel32 | static inline void tcg_out_ldst(TCGContext *s, int ret, int addr, int offset, |
263 | f54b3f92 | aurel32 | int op)
|
264 | f54b3f92 | aurel32 | { |
265 | f54b3f92 | aurel32 | if (offset == (offset & 0xfff)) |
266 | f54b3f92 | aurel32 | tcg_out32(s, op | INSN_R1(ret) | INSN_R2(addr) | |
267 | f54b3f92 | aurel32 | reassemble_14(offset)); |
268 | f54b3f92 | aurel32 | else {
|
269 | f54b3f92 | aurel32 | fprintf(stderr, "unimplemented %s with offset %d\n", __func__, offset);
|
270 | f54b3f92 | aurel32 | tcg_abort(); |
271 | f54b3f92 | aurel32 | } |
272 | f54b3f92 | aurel32 | } |
273 | f54b3f92 | aurel32 | |
274 | f54b3f92 | aurel32 | static inline void tcg_out_ld(TCGContext *s, TCGType type, int ret, |
275 | f54b3f92 | aurel32 | int arg1, tcg_target_long arg2)
|
276 | f54b3f92 | aurel32 | { |
277 | f54b3f92 | aurel32 | fprintf(stderr, "unimplemented %s\n", __func__);
|
278 | f54b3f92 | aurel32 | tcg_abort(); |
279 | f54b3f92 | aurel32 | } |
280 | f54b3f92 | aurel32 | |
281 | f54b3f92 | aurel32 | static inline void tcg_out_st(TCGContext *s, TCGType type, int ret, |
282 | f54b3f92 | aurel32 | int arg1, tcg_target_long arg2)
|
283 | f54b3f92 | aurel32 | { |
284 | f54b3f92 | aurel32 | fprintf(stderr, "unimplemented %s\n", __func__);
|
285 | f54b3f92 | aurel32 | tcg_abort(); |
286 | f54b3f92 | aurel32 | } |
287 | f54b3f92 | aurel32 | |
288 | f54b3f92 | aurel32 | static inline void tcg_out_arith(TCGContext *s, int t, int r1, int r2, int op) |
289 | f54b3f92 | aurel32 | { |
290 | f54b3f92 | aurel32 | tcg_out32(s, op | INSN_T(t) | INSN_R1(r1) | INSN_R2(r2)); |
291 | f54b3f92 | aurel32 | } |
292 | f54b3f92 | aurel32 | |
293 | f54b3f92 | aurel32 | static inline void tcg_out_arithi(TCGContext *s, int t, int r1, |
294 | f54b3f92 | aurel32 | tcg_target_long val, int op)
|
295 | f54b3f92 | aurel32 | { |
296 | f54b3f92 | aurel32 | tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R20, val); |
297 | f54b3f92 | aurel32 | tcg_out_arith(s, t, r1, TCG_REG_R20, op); |
298 | f54b3f92 | aurel32 | } |
299 | f54b3f92 | aurel32 | |
300 | f54b3f92 | aurel32 | static inline void tcg_out_addi(TCGContext *s, int reg, tcg_target_long val) |
301 | f54b3f92 | aurel32 | { |
302 | f54b3f92 | aurel32 | tcg_out_arithi(s, reg, reg, val, ARITH_ADD); |
303 | f54b3f92 | aurel32 | } |
304 | f54b3f92 | aurel32 | |
305 | f54b3f92 | aurel32 | static inline void tcg_out_nop(TCGContext *s) |
306 | f54b3f92 | aurel32 | { |
307 | f54b3f92 | aurel32 | tcg_out32(s, ARITH_OR | INSN_T(TCG_REG_R0) | INSN_R1(TCG_REG_R0) | |
308 | f54b3f92 | aurel32 | INSN_R2(TCG_REG_R0)); |
309 | f54b3f92 | aurel32 | } |
310 | f54b3f92 | aurel32 | |
311 | f54b3f92 | aurel32 | static inline void tcg_out_ext8s(TCGContext *s, int ret, int arg) { |
312 | f54b3f92 | aurel32 | tcg_out32(s, EXTRS | INSN_R1(ret) | INSN_R2(arg) | |
313 | f54b3f92 | aurel32 | INSN_SHDEP_P(31) | INSN_DEP_LEN(8)); |
314 | f54b3f92 | aurel32 | } |
315 | f54b3f92 | aurel32 | |
316 | f54b3f92 | aurel32 | static inline void tcg_out_ext16s(TCGContext *s, int ret, int arg) { |
317 | f54b3f92 | aurel32 | tcg_out32(s, EXTRS | INSN_R1(ret) | INSN_R2(arg) | |
318 | f54b3f92 | aurel32 | INSN_SHDEP_P(31) | INSN_DEP_LEN(16)); |
319 | f54b3f92 | aurel32 | } |
320 | f54b3f92 | aurel32 | |
321 | f54b3f92 | aurel32 | static inline void tcg_out_bswap16(TCGContext *s, int ret, int arg) { |
322 | f54b3f92 | aurel32 | if(ret != arg)
|
323 | f54b3f92 | aurel32 | tcg_out_mov(s, ret, arg); |
324 | f54b3f92 | aurel32 | tcg_out32(s, DEP | INSN_R2(ret) | INSN_R1(ret) | |
325 | f54b3f92 | aurel32 | INSN_SHDEP_CP(15) | INSN_DEP_LEN(8)); |
326 | f54b3f92 | aurel32 | tcg_out32(s, SHD | INSN_T(ret) | INSN_R1(TCG_REG_R0) | |
327 | f54b3f92 | aurel32 | INSN_R2(ret) | INSN_SHDEP_CP(8));
|
328 | f54b3f92 | aurel32 | } |
329 | f54b3f92 | aurel32 | |
330 | f54b3f92 | aurel32 | static inline void tcg_out_bswap32(TCGContext *s, int ret, int arg, int temp) { |
331 | f54b3f92 | aurel32 | tcg_out32(s, SHD | INSN_T(temp) | INSN_R1(arg) | |
332 | f54b3f92 | aurel32 | INSN_R2(arg) | INSN_SHDEP_CP(16));
|
333 | f54b3f92 | aurel32 | tcg_out32(s, DEP | INSN_R2(temp) | INSN_R1(temp) | |
334 | f54b3f92 | aurel32 | INSN_SHDEP_CP(15) | INSN_DEP_LEN(8)); |
335 | f54b3f92 | aurel32 | tcg_out32(s, SHD | INSN_T(ret) | INSN_R1(arg) | |
336 | f54b3f92 | aurel32 | INSN_R2(temp) | INSN_SHDEP_CP(8));
|
337 | f54b3f92 | aurel32 | } |
338 | f54b3f92 | aurel32 | |
339 | f54b3f92 | aurel32 | static inline void tcg_out_call(TCGContext *s, void *func) |
340 | f54b3f92 | aurel32 | { |
341 | f54b3f92 | aurel32 | uint32_t val = (uint32_t)__canonicalize_funcptr_for_compare(func); |
342 | f54b3f92 | aurel32 | tcg_out32(s, LDIL | INSN_R2(TCG_REG_R20) | |
343 | f54b3f92 | aurel32 | reassemble_21(lrsel(val, 0)));
|
344 | f54b3f92 | aurel32 | tcg_out32(s, BLE_SR4 | INSN_R2(TCG_REG_R20) | |
345 | f54b3f92 | aurel32 | reassemble_17(rrsel(val, 0) >> 2)); |
346 | f54b3f92 | aurel32 | tcg_out_mov(s, TCG_REG_RP, TCG_REG_R31); |
347 | f54b3f92 | aurel32 | } |
348 | f54b3f92 | aurel32 | |
349 | f54b3f92 | aurel32 | #if defined(CONFIG_SOFTMMU)
|
350 | 79383c9c | blueswir1 | |
351 | 79383c9c | blueswir1 | #include "../../softmmu_defs.h" |
352 | f54b3f92 | aurel32 | |
353 | f54b3f92 | aurel32 | static void *qemu_ld_helpers[4] = { |
354 | f54b3f92 | aurel32 | __ldb_mmu, |
355 | f54b3f92 | aurel32 | __ldw_mmu, |
356 | f54b3f92 | aurel32 | __ldl_mmu, |
357 | f54b3f92 | aurel32 | __ldq_mmu, |
358 | f54b3f92 | aurel32 | }; |
359 | f54b3f92 | aurel32 | |
360 | f54b3f92 | aurel32 | static void *qemu_st_helpers[4] = { |
361 | f54b3f92 | aurel32 | __stb_mmu, |
362 | f54b3f92 | aurel32 | __stw_mmu, |
363 | f54b3f92 | aurel32 | __stl_mmu, |
364 | f54b3f92 | aurel32 | __stq_mmu, |
365 | f54b3f92 | aurel32 | }; |
366 | f54b3f92 | aurel32 | #endif
|
367 | f54b3f92 | aurel32 | |
368 | f54b3f92 | aurel32 | static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, int opc) |
369 | f54b3f92 | aurel32 | { |
370 | f54b3f92 | aurel32 | int addr_reg, data_reg, data_reg2, r0, r1, mem_index, s_bits, bswap;
|
371 | f54b3f92 | aurel32 | #if defined(CONFIG_SOFTMMU)
|
372 | f54b3f92 | aurel32 | uint32_t *label1_ptr, *label2_ptr; |
373 | f54b3f92 | aurel32 | #endif
|
374 | f54b3f92 | aurel32 | #if TARGET_LONG_BITS == 64 |
375 | f54b3f92 | aurel32 | #if defined(CONFIG_SOFTMMU)
|
376 | f54b3f92 | aurel32 | uint32_t *label3_ptr; |
377 | f54b3f92 | aurel32 | #endif
|
378 | f54b3f92 | aurel32 | int addr_reg2;
|
379 | f54b3f92 | aurel32 | #endif
|
380 | f54b3f92 | aurel32 | |
381 | f54b3f92 | aurel32 | data_reg = *args++; |
382 | f54b3f92 | aurel32 | if (opc == 3) |
383 | f54b3f92 | aurel32 | data_reg2 = *args++; |
384 | f54b3f92 | aurel32 | else
|
385 | f54b3f92 | aurel32 | data_reg2 = 0; /* surpress warning */ |
386 | f54b3f92 | aurel32 | addr_reg = *args++; |
387 | f54b3f92 | aurel32 | #if TARGET_LONG_BITS == 64 |
388 | f54b3f92 | aurel32 | addr_reg2 = *args++; |
389 | f54b3f92 | aurel32 | #endif
|
390 | f54b3f92 | aurel32 | mem_index = *args; |
391 | f54b3f92 | aurel32 | s_bits = opc & 3;
|
392 | f54b3f92 | aurel32 | |
393 | f54b3f92 | aurel32 | r0 = TCG_REG_R26; |
394 | f54b3f92 | aurel32 | r1 = TCG_REG_R25; |
395 | f54b3f92 | aurel32 | |
396 | f54b3f92 | aurel32 | #if defined(CONFIG_SOFTMMU)
|
397 | f54b3f92 | aurel32 | tcg_out_mov(s, r1, addr_reg); |
398 | f54b3f92 | aurel32 | |
399 | f54b3f92 | aurel32 | tcg_out_mov(s, r0, addr_reg); |
400 | f54b3f92 | aurel32 | |
401 | f54b3f92 | aurel32 | tcg_out32(s, SHD | INSN_T(r1) | INSN_R1(TCG_REG_R0) | INSN_R2(r1) | |
402 | f54b3f92 | aurel32 | INSN_SHDEP_CP(TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS)); |
403 | f54b3f92 | aurel32 | |
404 | f54b3f92 | aurel32 | tcg_out_arithi(s, r0, r0, TARGET_PAGE_MASK | ((1 << s_bits) - 1), |
405 | f54b3f92 | aurel32 | ARITH_AND); |
406 | f54b3f92 | aurel32 | |
407 | f54b3f92 | aurel32 | tcg_out_arithi(s, r1, r1, (CPU_TLB_SIZE - 1) << CPU_TLB_ENTRY_BITS,
|
408 | f54b3f92 | aurel32 | ARITH_AND); |
409 | f54b3f92 | aurel32 | |
410 | f54b3f92 | aurel32 | tcg_out_arith(s, r1, r1, TCG_AREG0, ARITH_ADD); |
411 | f54b3f92 | aurel32 | tcg_out_arithi(s, r1, r1, |
412 | f54b3f92 | aurel32 | offsetof(CPUState, tlb_table[mem_index][0].addr_read),
|
413 | f54b3f92 | aurel32 | ARITH_ADD); |
414 | f54b3f92 | aurel32 | |
415 | f54b3f92 | aurel32 | tcg_out_ldst(s, TCG_REG_R20, r1, 0, LDW);
|
416 | f54b3f92 | aurel32 | |
417 | f54b3f92 | aurel32 | #if TARGET_LONG_BITS == 32 |
418 | f54b3f92 | aurel32 | /* if equal, jump to label1 */
|
419 | f54b3f92 | aurel32 | label1_ptr = (uint32_t *)s->code_ptr; |
420 | f54b3f92 | aurel32 | tcg_out32(s, COMBT | INSN_R1(TCG_REG_R20) | INSN_R2(r0) | |
421 | f54b3f92 | aurel32 | INSN_COND(COND_EQUAL)); |
422 | f54b3f92 | aurel32 | tcg_out_mov(s, r0, addr_reg); /* delay slot */
|
423 | f54b3f92 | aurel32 | #else
|
424 | f54b3f92 | aurel32 | /* if not equal, jump to label3 */
|
425 | f54b3f92 | aurel32 | label3_ptr = (uint32_t *)s->code_ptr; |
426 | f54b3f92 | aurel32 | tcg_out32(s, COMBF | INSN_R1(TCG_REG_R20) | INSN_R2(r0) | |
427 | f54b3f92 | aurel32 | INSN_COND(COND_EQUAL)); |
428 | f54b3f92 | aurel32 | tcg_out_mov(s, r0, addr_reg); /* delay slot */
|
429 | f54b3f92 | aurel32 | |
430 | f54b3f92 | aurel32 | tcg_out_ldst(s, TCG_REG_R20, r1, 4, LDW);
|
431 | f54b3f92 | aurel32 | |
432 | f54b3f92 | aurel32 | /* if equal, jump to label1 */
|
433 | f54b3f92 | aurel32 | label1_ptr = (uint32_t *)s->code_ptr; |
434 | f54b3f92 | aurel32 | tcg_out32(s, COMBT | INSN_R1(TCG_REG_R20) | INSN_R2(addr_reg2) | |
435 | f54b3f92 | aurel32 | INSN_COND(COND_EQUAL)); |
436 | f54b3f92 | aurel32 | tcg_out_nop(s); /* delay slot */
|
437 | f54b3f92 | aurel32 | |
438 | f54b3f92 | aurel32 | /* label3: */
|
439 | f54b3f92 | aurel32 | *label3_ptr |= reassemble_12((uint32_t *)s->code_ptr - label3_ptr - 2);
|
440 | f54b3f92 | aurel32 | #endif
|
441 | f54b3f92 | aurel32 | |
442 | f54b3f92 | aurel32 | #if TARGET_LONG_BITS == 32 |
443 | f54b3f92 | aurel32 | tcg_out_mov(s, TCG_REG_R26, addr_reg); |
444 | f54b3f92 | aurel32 | tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_R25, mem_index); |
445 | f54b3f92 | aurel32 | #else
|
446 | f54b3f92 | aurel32 | tcg_out_mov(s, TCG_REG_R26, addr_reg); |
447 | f54b3f92 | aurel32 | tcg_out_mov(s, TCG_REG_R25, addr_reg2); |
448 | f54b3f92 | aurel32 | tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_R24, mem_index); |
449 | f54b3f92 | aurel32 | #endif
|
450 | f54b3f92 | aurel32 | |
451 | f54b3f92 | aurel32 | tcg_out_call(s, qemu_ld_helpers[s_bits]); |
452 | f54b3f92 | aurel32 | |
453 | f54b3f92 | aurel32 | switch(opc) {
|
454 | f54b3f92 | aurel32 | case 0 | 4: |
455 | f54b3f92 | aurel32 | tcg_out_ext8s(s, data_reg, TCG_REG_RET0); |
456 | f54b3f92 | aurel32 | break;
|
457 | f54b3f92 | aurel32 | case 1 | 4: |
458 | f54b3f92 | aurel32 | tcg_out_ext16s(s, data_reg, TCG_REG_RET0); |
459 | f54b3f92 | aurel32 | break;
|
460 | f54b3f92 | aurel32 | case 0: |
461 | f54b3f92 | aurel32 | case 1: |
462 | f54b3f92 | aurel32 | case 2: |
463 | f54b3f92 | aurel32 | default:
|
464 | f54b3f92 | aurel32 | tcg_out_mov(s, data_reg, TCG_REG_RET0); |
465 | f54b3f92 | aurel32 | break;
|
466 | f54b3f92 | aurel32 | case 3: |
467 | f54b3f92 | aurel32 | tcg_abort(); |
468 | f54b3f92 | aurel32 | tcg_out_mov(s, data_reg, TCG_REG_RET0); |
469 | f54b3f92 | aurel32 | tcg_out_mov(s, data_reg2, TCG_REG_RET1); |
470 | f54b3f92 | aurel32 | break;
|
471 | f54b3f92 | aurel32 | } |
472 | f54b3f92 | aurel32 | |
473 | f54b3f92 | aurel32 | /* jump to label2 */
|
474 | f54b3f92 | aurel32 | label2_ptr = (uint32_t *)s->code_ptr; |
475 | f54b3f92 | aurel32 | tcg_out32(s, BL | INSN_R2(TCG_REG_R0) | 2);
|
476 | f54b3f92 | aurel32 | |
477 | f54b3f92 | aurel32 | /* label1: */
|
478 | f54b3f92 | aurel32 | *label1_ptr |= reassemble_12((uint32_t *)s->code_ptr - label1_ptr - 2);
|
479 | f54b3f92 | aurel32 | |
480 | f54b3f92 | aurel32 | tcg_out_arithi(s, TCG_REG_R20, r1, |
481 | f54b3f92 | aurel32 | offsetof(CPUTLBEntry, addend) - offsetof(CPUTLBEntry, addr_read), |
482 | f54b3f92 | aurel32 | ARITH_ADD); |
483 | f54b3f92 | aurel32 | tcg_out_ldst(s, TCG_REG_R20, TCG_REG_R20, 0, LDW);
|
484 | f54b3f92 | aurel32 | tcg_out_arith(s, r0, r0, TCG_REG_R20, ARITH_ADD); |
485 | f54b3f92 | aurel32 | #else
|
486 | f54b3f92 | aurel32 | r0 = addr_reg; |
487 | f54b3f92 | aurel32 | #endif
|
488 | f54b3f92 | aurel32 | |
489 | f54b3f92 | aurel32 | #ifdef TARGET_WORDS_BIGENDIAN
|
490 | f54b3f92 | aurel32 | bswap = 0;
|
491 | f54b3f92 | aurel32 | #else
|
492 | f54b3f92 | aurel32 | bswap = 1;
|
493 | f54b3f92 | aurel32 | #endif
|
494 | f54b3f92 | aurel32 | switch (opc) {
|
495 | f54b3f92 | aurel32 | case 0: |
496 | f54b3f92 | aurel32 | tcg_out_ldst(s, data_reg, r0, 0, LDB);
|
497 | f54b3f92 | aurel32 | break;
|
498 | f54b3f92 | aurel32 | case 0 | 4: |
499 | f54b3f92 | aurel32 | tcg_out_ldst(s, data_reg, r0, 0, LDB);
|
500 | f54b3f92 | aurel32 | tcg_out_ext8s(s, data_reg, data_reg); |
501 | f54b3f92 | aurel32 | break;
|
502 | f54b3f92 | aurel32 | case 1: |
503 | f54b3f92 | aurel32 | tcg_out_ldst(s, data_reg, r0, 0, LDH);
|
504 | f54b3f92 | aurel32 | if (bswap)
|
505 | f54b3f92 | aurel32 | tcg_out_bswap16(s, data_reg, data_reg); |
506 | f54b3f92 | aurel32 | break;
|
507 | f54b3f92 | aurel32 | case 1 | 4: |
508 | f54b3f92 | aurel32 | tcg_out_ldst(s, data_reg, r0, 0, LDH);
|
509 | f54b3f92 | aurel32 | if (bswap)
|
510 | f54b3f92 | aurel32 | tcg_out_bswap16(s, data_reg, data_reg); |
511 | f54b3f92 | aurel32 | tcg_out_ext16s(s, data_reg, data_reg); |
512 | f54b3f92 | aurel32 | break;
|
513 | f54b3f92 | aurel32 | case 2: |
514 | f54b3f92 | aurel32 | tcg_out_ldst(s, data_reg, r0, 0, LDW);
|
515 | f54b3f92 | aurel32 | if (bswap)
|
516 | f54b3f92 | aurel32 | tcg_out_bswap32(s, data_reg, data_reg, TCG_REG_R20); |
517 | f54b3f92 | aurel32 | break;
|
518 | f54b3f92 | aurel32 | case 3: |
519 | f54b3f92 | aurel32 | tcg_abort(); |
520 | f54b3f92 | aurel32 | if (!bswap) {
|
521 | f54b3f92 | aurel32 | tcg_out_ldst(s, data_reg, r0, 0, LDW);
|
522 | f54b3f92 | aurel32 | tcg_out_ldst(s, data_reg2, r0, 4, LDW);
|
523 | f54b3f92 | aurel32 | } else {
|
524 | f54b3f92 | aurel32 | tcg_out_ldst(s, data_reg, r0, 4, LDW);
|
525 | f54b3f92 | aurel32 | tcg_out_bswap32(s, data_reg, data_reg, TCG_REG_R20); |
526 | f54b3f92 | aurel32 | tcg_out_ldst(s, data_reg2, r0, 0, LDW);
|
527 | f54b3f92 | aurel32 | tcg_out_bswap32(s, data_reg2, data_reg2, TCG_REG_R20); |
528 | f54b3f92 | aurel32 | } |
529 | f54b3f92 | aurel32 | break;
|
530 | f54b3f92 | aurel32 | default:
|
531 | f54b3f92 | aurel32 | tcg_abort(); |
532 | f54b3f92 | aurel32 | } |
533 | f54b3f92 | aurel32 | |
534 | f54b3f92 | aurel32 | #if defined(CONFIG_SOFTMMU)
|
535 | f54b3f92 | aurel32 | /* label2: */
|
536 | f54b3f92 | aurel32 | *label2_ptr |= reassemble_17((uint32_t *)s->code_ptr - label2_ptr - 2);
|
537 | f54b3f92 | aurel32 | #endif
|
538 | f54b3f92 | aurel32 | } |
539 | f54b3f92 | aurel32 | |
540 | f54b3f92 | aurel32 | static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, int opc) |
541 | f54b3f92 | aurel32 | { |
542 | f54b3f92 | aurel32 | int addr_reg, data_reg, data_reg2, r0, r1, mem_index, s_bits, bswap;
|
543 | f54b3f92 | aurel32 | #if defined(CONFIG_SOFTMMU)
|
544 | f54b3f92 | aurel32 | uint32_t *label1_ptr, *label2_ptr; |
545 | f54b3f92 | aurel32 | #endif
|
546 | f54b3f92 | aurel32 | #if TARGET_LONG_BITS == 64 |
547 | f54b3f92 | aurel32 | #if defined(CONFIG_SOFTMMU)
|
548 | f54b3f92 | aurel32 | uint32_t *label3_ptr; |
549 | f54b3f92 | aurel32 | #endif
|
550 | f54b3f92 | aurel32 | int addr_reg2;
|
551 | f54b3f92 | aurel32 | #endif
|
552 | f54b3f92 | aurel32 | |
553 | f54b3f92 | aurel32 | data_reg = *args++; |
554 | f54b3f92 | aurel32 | if (opc == 3) |
555 | f54b3f92 | aurel32 | data_reg2 = *args++; |
556 | f54b3f92 | aurel32 | else
|
557 | f54b3f92 | aurel32 | data_reg2 = 0; /* surpress warning */ |
558 | f54b3f92 | aurel32 | addr_reg = *args++; |
559 | f54b3f92 | aurel32 | #if TARGET_LONG_BITS == 64 |
560 | f54b3f92 | aurel32 | addr_reg2 = *args++; |
561 | f54b3f92 | aurel32 | #endif
|
562 | f54b3f92 | aurel32 | mem_index = *args; |
563 | f54b3f92 | aurel32 | |
564 | f54b3f92 | aurel32 | s_bits = opc; |
565 | f54b3f92 | aurel32 | |
566 | f54b3f92 | aurel32 | r0 = TCG_REG_R26; |
567 | f54b3f92 | aurel32 | r1 = TCG_REG_R25; |
568 | f54b3f92 | aurel32 | |
569 | f54b3f92 | aurel32 | #if defined(CONFIG_SOFTMMU)
|
570 | f54b3f92 | aurel32 | tcg_out_mov(s, r1, addr_reg); |
571 | f54b3f92 | aurel32 | |
572 | f54b3f92 | aurel32 | tcg_out_mov(s, r0, addr_reg); |
573 | f54b3f92 | aurel32 | |
574 | f54b3f92 | aurel32 | tcg_out32(s, SHD | INSN_T(r1) | INSN_R1(TCG_REG_R0) | INSN_R2(r1) | |
575 | f54b3f92 | aurel32 | INSN_SHDEP_CP(TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS)); |
576 | f54b3f92 | aurel32 | |
577 | f54b3f92 | aurel32 | tcg_out_arithi(s, r0, r0, TARGET_PAGE_MASK | ((1 << s_bits) - 1), |
578 | f54b3f92 | aurel32 | ARITH_AND); |
579 | f54b3f92 | aurel32 | |
580 | f54b3f92 | aurel32 | tcg_out_arithi(s, r1, r1, (CPU_TLB_SIZE - 1) << CPU_TLB_ENTRY_BITS,
|
581 | f54b3f92 | aurel32 | ARITH_AND); |
582 | f54b3f92 | aurel32 | |
583 | f54b3f92 | aurel32 | tcg_out_arith(s, r1, r1, TCG_AREG0, ARITH_ADD); |
584 | f54b3f92 | aurel32 | tcg_out_arithi(s, r1, r1, |
585 | f54b3f92 | aurel32 | offsetof(CPUState, tlb_table[mem_index][0].addr_write),
|
586 | f54b3f92 | aurel32 | ARITH_ADD); |
587 | f54b3f92 | aurel32 | |
588 | f54b3f92 | aurel32 | tcg_out_ldst(s, TCG_REG_R20, r1, 0, LDW);
|
589 | f54b3f92 | aurel32 | |
590 | f54b3f92 | aurel32 | #if TARGET_LONG_BITS == 32 |
591 | f54b3f92 | aurel32 | /* if equal, jump to label1 */
|
592 | f54b3f92 | aurel32 | label1_ptr = (uint32_t *)s->code_ptr; |
593 | f54b3f92 | aurel32 | tcg_out32(s, COMBT | INSN_R1(TCG_REG_R20) | INSN_R2(r0) | |
594 | f54b3f92 | aurel32 | INSN_COND(COND_EQUAL)); |
595 | f54b3f92 | aurel32 | tcg_out_mov(s, r0, addr_reg); /* delay slot */
|
596 | f54b3f92 | aurel32 | #else
|
597 | f54b3f92 | aurel32 | /* if not equal, jump to label3 */
|
598 | f54b3f92 | aurel32 | label3_ptr = (uint32_t *)s->code_ptr; |
599 | f54b3f92 | aurel32 | tcg_out32(s, COMBF | INSN_R1(TCG_REG_R20) | INSN_R2(r0) | |
600 | f54b3f92 | aurel32 | INSN_COND(COND_EQUAL)); |
601 | f54b3f92 | aurel32 | tcg_out_mov(s, r0, addr_reg); /* delay slot */
|
602 | f54b3f92 | aurel32 | |
603 | f54b3f92 | aurel32 | tcg_out_ldst(s, TCG_REG_R20, r1, 4, LDW);
|
604 | f54b3f92 | aurel32 | |
605 | f54b3f92 | aurel32 | /* if equal, jump to label1 */
|
606 | f54b3f92 | aurel32 | label1_ptr = (uint32_t *)s->code_ptr; |
607 | f54b3f92 | aurel32 | tcg_out32(s, COMBT | INSN_R1(TCG_REG_R20) | INSN_R2(addr_reg2) | |
608 | f54b3f92 | aurel32 | INSN_COND(COND_EQUAL)); |
609 | f54b3f92 | aurel32 | tcg_out_nop(s); /* delay slot */
|
610 | f54b3f92 | aurel32 | |
611 | f54b3f92 | aurel32 | /* label3: */
|
612 | f54b3f92 | aurel32 | *label3_ptr |= reassemble_12((uint32_t *)s->code_ptr - label3_ptr - 2);
|
613 | f54b3f92 | aurel32 | #endif
|
614 | f54b3f92 | aurel32 | |
615 | f54b3f92 | aurel32 | tcg_out_mov(s, TCG_REG_R26, addr_reg); |
616 | f54b3f92 | aurel32 | #if TARGET_LONG_BITS == 64 |
617 | f54b3f92 | aurel32 | tcg_out_mov(s, TCG_REG_R25, addr_reg2); |
618 | f54b3f92 | aurel32 | if (opc == 3) { |
619 | f54b3f92 | aurel32 | tcg_abort(); |
620 | f54b3f92 | aurel32 | tcg_out_mov(s, TCG_REG_R24, data_reg); |
621 | f54b3f92 | aurel32 | tcg_out_mov(s, TCG_REG_R23, data_reg2); |
622 | f54b3f92 | aurel32 | /* TODO: push mem_index */
|
623 | f54b3f92 | aurel32 | tcg_abort(); |
624 | f54b3f92 | aurel32 | } else {
|
625 | f54b3f92 | aurel32 | switch(opc) {
|
626 | f54b3f92 | aurel32 | case 0: |
627 | f54b3f92 | aurel32 | tcg_out32(s, EXTRU | INSN_R1(TCG_REG_R24) | INSN_R2(data_reg) | |
628 | f54b3f92 | aurel32 | INSN_SHDEP_P(31) | INSN_DEP_LEN(8)); |
629 | f54b3f92 | aurel32 | break;
|
630 | f54b3f92 | aurel32 | case 1: |
631 | f54b3f92 | aurel32 | tcg_out32(s, EXTRU | INSN_R1(TCG_REG_R24) | INSN_R2(data_reg) | |
632 | f54b3f92 | aurel32 | INSN_SHDEP_P(31) | INSN_DEP_LEN(16)); |
633 | f54b3f92 | aurel32 | break;
|
634 | f54b3f92 | aurel32 | case 2: |
635 | f54b3f92 | aurel32 | tcg_out_mov(s, TCG_REG_R24, data_reg); |
636 | f54b3f92 | aurel32 | break;
|
637 | f54b3f92 | aurel32 | } |
638 | f54b3f92 | aurel32 | tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_R23, mem_index); |
639 | f54b3f92 | aurel32 | } |
640 | f54b3f92 | aurel32 | #else
|
641 | f54b3f92 | aurel32 | if (opc == 3) { |
642 | f54b3f92 | aurel32 | tcg_abort(); |
643 | f54b3f92 | aurel32 | tcg_out_mov(s, TCG_REG_R25, data_reg); |
644 | f54b3f92 | aurel32 | tcg_out_mov(s, TCG_REG_R24, data_reg2); |
645 | f54b3f92 | aurel32 | tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_R23, mem_index); |
646 | f54b3f92 | aurel32 | } else {
|
647 | f54b3f92 | aurel32 | switch(opc) {
|
648 | f54b3f92 | aurel32 | case 0: |
649 | f54b3f92 | aurel32 | tcg_out32(s, EXTRU | INSN_R1(TCG_REG_R25) | INSN_R2(data_reg) | |
650 | f54b3f92 | aurel32 | INSN_SHDEP_P(31) | INSN_DEP_LEN(8)); |
651 | f54b3f92 | aurel32 | break;
|
652 | f54b3f92 | aurel32 | case 1: |
653 | f54b3f92 | aurel32 | tcg_out32(s, EXTRU | INSN_R1(TCG_REG_R25) | INSN_R2(data_reg) | |
654 | f54b3f92 | aurel32 | INSN_SHDEP_P(31) | INSN_DEP_LEN(16)); |
655 | f54b3f92 | aurel32 | break;
|
656 | f54b3f92 | aurel32 | case 2: |
657 | f54b3f92 | aurel32 | tcg_out_mov(s, TCG_REG_R25, data_reg); |
658 | f54b3f92 | aurel32 | break;
|
659 | f54b3f92 | aurel32 | } |
660 | f54b3f92 | aurel32 | tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_R24, mem_index); |
661 | f54b3f92 | aurel32 | } |
662 | f54b3f92 | aurel32 | #endif
|
663 | f54b3f92 | aurel32 | tcg_out_call(s, qemu_st_helpers[s_bits]); |
664 | f54b3f92 | aurel32 | |
665 | f54b3f92 | aurel32 | /* jump to label2 */
|
666 | f54b3f92 | aurel32 | label2_ptr = (uint32_t *)s->code_ptr; |
667 | f54b3f92 | aurel32 | tcg_out32(s, BL | INSN_R2(TCG_REG_R0) | 2);
|
668 | f54b3f92 | aurel32 | |
669 | f54b3f92 | aurel32 | /* label1: */
|
670 | f54b3f92 | aurel32 | *label1_ptr |= reassemble_12((uint32_t *)s->code_ptr - label1_ptr - 2);
|
671 | f54b3f92 | aurel32 | |
672 | f54b3f92 | aurel32 | tcg_out_arithi(s, TCG_REG_R20, r1, |
673 | f54b3f92 | aurel32 | offsetof(CPUTLBEntry, addend) - offsetof(CPUTLBEntry, addr_write), |
674 | f54b3f92 | aurel32 | ARITH_ADD); |
675 | f54b3f92 | aurel32 | tcg_out_ldst(s, TCG_REG_R20, TCG_REG_R20, 0, LDW);
|
676 | f54b3f92 | aurel32 | tcg_out_arith(s, r0, r0, TCG_REG_R20, ARITH_ADD); |
677 | f54b3f92 | aurel32 | #else
|
678 | f54b3f92 | aurel32 | r0 = addr_reg; |
679 | f54b3f92 | aurel32 | #endif
|
680 | f54b3f92 | aurel32 | |
681 | f54b3f92 | aurel32 | #ifdef TARGET_WORDS_BIGENDIAN
|
682 | f54b3f92 | aurel32 | bswap = 0;
|
683 | f54b3f92 | aurel32 | #else
|
684 | f54b3f92 | aurel32 | bswap = 1;
|
685 | f54b3f92 | aurel32 | #endif
|
686 | f54b3f92 | aurel32 | switch (opc) {
|
687 | f54b3f92 | aurel32 | case 0: |
688 | f54b3f92 | aurel32 | tcg_out_ldst(s, data_reg, r0, 0, STB);
|
689 | f54b3f92 | aurel32 | break;
|
690 | f54b3f92 | aurel32 | case 1: |
691 | f54b3f92 | aurel32 | if (bswap) {
|
692 | f54b3f92 | aurel32 | tcg_out_bswap16(s, TCG_REG_R20, data_reg); |
693 | f54b3f92 | aurel32 | data_reg = TCG_REG_R20; |
694 | f54b3f92 | aurel32 | } |
695 | f54b3f92 | aurel32 | tcg_out_ldst(s, data_reg, r0, 0, STH);
|
696 | f54b3f92 | aurel32 | break;
|
697 | f54b3f92 | aurel32 | case 2: |
698 | f54b3f92 | aurel32 | if (bswap) {
|
699 | f54b3f92 | aurel32 | tcg_out_bswap32(s, TCG_REG_R20, data_reg, TCG_REG_R20); |
700 | f54b3f92 | aurel32 | data_reg = TCG_REG_R20; |
701 | f54b3f92 | aurel32 | } |
702 | f54b3f92 | aurel32 | tcg_out_ldst(s, data_reg, r0, 0, STW);
|
703 | f54b3f92 | aurel32 | break;
|
704 | f54b3f92 | aurel32 | case 3: |
705 | f54b3f92 | aurel32 | tcg_abort(); |
706 | f54b3f92 | aurel32 | if (!bswap) {
|
707 | f54b3f92 | aurel32 | tcg_out_ldst(s, data_reg, r0, 0, STW);
|
708 | f54b3f92 | aurel32 | tcg_out_ldst(s, data_reg2, r0, 4, STW);
|
709 | f54b3f92 | aurel32 | } else {
|
710 | f54b3f92 | aurel32 | tcg_out_bswap32(s, TCG_REG_R20, data_reg, TCG_REG_R20); |
711 | f54b3f92 | aurel32 | tcg_out_ldst(s, TCG_REG_R20, r0, 4, STW);
|
712 | f54b3f92 | aurel32 | tcg_out_bswap32(s, TCG_REG_R20, data_reg2, TCG_REG_R20); |
713 | f54b3f92 | aurel32 | tcg_out_ldst(s, TCG_REG_R20, r0, 0, STW);
|
714 | f54b3f92 | aurel32 | } |
715 | f54b3f92 | aurel32 | break;
|
716 | f54b3f92 | aurel32 | default:
|
717 | f54b3f92 | aurel32 | tcg_abort(); |
718 | f54b3f92 | aurel32 | } |
719 | f54b3f92 | aurel32 | |
720 | f54b3f92 | aurel32 | #if defined(CONFIG_SOFTMMU)
|
721 | f54b3f92 | aurel32 | /* label2: */
|
722 | f54b3f92 | aurel32 | *label2_ptr |= reassemble_17((uint32_t *)s->code_ptr - label2_ptr - 2);
|
723 | f54b3f92 | aurel32 | #endif
|
724 | f54b3f92 | aurel32 | } |
725 | f54b3f92 | aurel32 | |
726 | f54b3f92 | aurel32 | static inline void tcg_out_op(TCGContext *s, int opc, const TCGArg *args, |
727 | f54b3f92 | aurel32 | const int *const_args) |
728 | f54b3f92 | aurel32 | { |
729 | f54b3f92 | aurel32 | int c;
|
730 | f54b3f92 | aurel32 | |
731 | f54b3f92 | aurel32 | switch (opc) {
|
732 | f54b3f92 | aurel32 | case INDEX_op_exit_tb:
|
733 | f54b3f92 | aurel32 | tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_RET0, args[0]);
|
734 | f54b3f92 | aurel32 | tcg_out32(s, BV_N | INSN_R2(TCG_REG_R18)); |
735 | f54b3f92 | aurel32 | break;
|
736 | f54b3f92 | aurel32 | case INDEX_op_goto_tb:
|
737 | f54b3f92 | aurel32 | if (s->tb_jmp_offset) {
|
738 | f54b3f92 | aurel32 | /* direct jump method */
|
739 | f54b3f92 | aurel32 | fprintf(stderr, "goto_tb direct\n");
|
740 | f54b3f92 | aurel32 | tcg_abort(); |
741 | f54b3f92 | aurel32 | tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R20, args[0]);
|
742 | f54b3f92 | aurel32 | tcg_out32(s, BV_N | INSN_R2(TCG_REG_R20)); |
743 | f54b3f92 | aurel32 | s->tb_jmp_offset[args[0]] = s->code_ptr - s->code_buf;
|
744 | f54b3f92 | aurel32 | } else {
|
745 | f54b3f92 | aurel32 | /* indirect jump method */
|
746 | f54b3f92 | aurel32 | tcg_out_ld_ptr(s, TCG_REG_R20, |
747 | f54b3f92 | aurel32 | (tcg_target_long)(s->tb_next + args[0]));
|
748 | f54b3f92 | aurel32 | tcg_out32(s, BV_N | INSN_R2(TCG_REG_R20)); |
749 | f54b3f92 | aurel32 | } |
750 | f54b3f92 | aurel32 | s->tb_next_offset[args[0]] = s->code_ptr - s->code_buf;
|
751 | f54b3f92 | aurel32 | break;
|
752 | f54b3f92 | aurel32 | case INDEX_op_call:
|
753 | f54b3f92 | aurel32 | tcg_out32(s, BLE_SR4 | INSN_R2(args[0]));
|
754 | f54b3f92 | aurel32 | tcg_out_mov(s, TCG_REG_RP, TCG_REG_R31); |
755 | f54b3f92 | aurel32 | break;
|
756 | f54b3f92 | aurel32 | case INDEX_op_jmp:
|
757 | f54b3f92 | aurel32 | fprintf(stderr, "unimplemented jmp\n");
|
758 | f54b3f92 | aurel32 | tcg_abort(); |
759 | f54b3f92 | aurel32 | break;
|
760 | f54b3f92 | aurel32 | case INDEX_op_br:
|
761 | f54b3f92 | aurel32 | fprintf(stderr, "unimplemented br\n");
|
762 | f54b3f92 | aurel32 | tcg_abort(); |
763 | f54b3f92 | aurel32 | break;
|
764 | f54b3f92 | aurel32 | case INDEX_op_movi_i32:
|
765 | f54b3f92 | aurel32 | tcg_out_movi(s, TCG_TYPE_I32, args[0], (uint32_t)args[1]); |
766 | f54b3f92 | aurel32 | break;
|
767 | f54b3f92 | aurel32 | |
768 | f54b3f92 | aurel32 | case INDEX_op_ld8u_i32:
|
769 | f54b3f92 | aurel32 | tcg_out_ldst(s, args[0], args[1], args[2], LDB); |
770 | f54b3f92 | aurel32 | break;
|
771 | f54b3f92 | aurel32 | case INDEX_op_ld8s_i32:
|
772 | f54b3f92 | aurel32 | tcg_out_ldst(s, args[0], args[1], args[2], LDB); |
773 | f54b3f92 | aurel32 | tcg_out_ext8s(s, args[0], args[0]); |
774 | f54b3f92 | aurel32 | break;
|
775 | f54b3f92 | aurel32 | case INDEX_op_ld16u_i32:
|
776 | f54b3f92 | aurel32 | tcg_out_ldst(s, args[0], args[1], args[2], LDH); |
777 | f54b3f92 | aurel32 | break;
|
778 | f54b3f92 | aurel32 | case INDEX_op_ld16s_i32:
|
779 | f54b3f92 | aurel32 | tcg_out_ldst(s, args[0], args[1], args[2], LDH); |
780 | f54b3f92 | aurel32 | tcg_out_ext16s(s, args[0], args[0]); |
781 | f54b3f92 | aurel32 | break;
|
782 | f54b3f92 | aurel32 | case INDEX_op_ld_i32:
|
783 | f54b3f92 | aurel32 | tcg_out_ldst(s, args[0], args[1], args[2], LDW); |
784 | f54b3f92 | aurel32 | break;
|
785 | f54b3f92 | aurel32 | |
786 | f54b3f92 | aurel32 | case INDEX_op_st8_i32:
|
787 | f54b3f92 | aurel32 | tcg_out_ldst(s, args[0], args[1], args[2], STB); |
788 | f54b3f92 | aurel32 | break;
|
789 | f54b3f92 | aurel32 | case INDEX_op_st16_i32:
|
790 | f54b3f92 | aurel32 | tcg_out_ldst(s, args[0], args[1], args[2], STH); |
791 | f54b3f92 | aurel32 | break;
|
792 | f54b3f92 | aurel32 | case INDEX_op_st_i32:
|
793 | f54b3f92 | aurel32 | tcg_out_ldst(s, args[0], args[1], args[2], STW); |
794 | f54b3f92 | aurel32 | break;
|
795 | f54b3f92 | aurel32 | |
796 | f54b3f92 | aurel32 | case INDEX_op_sub_i32:
|
797 | f54b3f92 | aurel32 | c = ARITH_SUB; |
798 | f54b3f92 | aurel32 | goto gen_arith;
|
799 | f54b3f92 | aurel32 | case INDEX_op_and_i32:
|
800 | f54b3f92 | aurel32 | c = ARITH_AND; |
801 | f54b3f92 | aurel32 | goto gen_arith;
|
802 | f54b3f92 | aurel32 | case INDEX_op_or_i32:
|
803 | f54b3f92 | aurel32 | c = ARITH_OR; |
804 | f54b3f92 | aurel32 | goto gen_arith;
|
805 | f54b3f92 | aurel32 | case INDEX_op_xor_i32:
|
806 | f54b3f92 | aurel32 | c = ARITH_XOR; |
807 | f54b3f92 | aurel32 | goto gen_arith;
|
808 | f54b3f92 | aurel32 | case INDEX_op_add_i32:
|
809 | f54b3f92 | aurel32 | c = ARITH_ADD; |
810 | f54b3f92 | aurel32 | goto gen_arith;
|
811 | f54b3f92 | aurel32 | |
812 | f54b3f92 | aurel32 | case INDEX_op_shl_i32:
|
813 | f54b3f92 | aurel32 | tcg_out32(s, SUBI | INSN_R1(TCG_REG_R20) | INSN_R2(args[2]) |
|
814 | f54b3f92 | aurel32 | lowsignext(0x1f, 0, 11)); |
815 | f54b3f92 | aurel32 | tcg_out32(s, MTCTL | INSN_R2(11) | INSN_R1(TCG_REG_R20));
|
816 | f54b3f92 | aurel32 | tcg_out32(s, ZVDEP | INSN_R2(args[0]) | INSN_R1(args[1]) | |
817 | f54b3f92 | aurel32 | INSN_DEP_LEN(32));
|
818 | f54b3f92 | aurel32 | break;
|
819 | f54b3f92 | aurel32 | case INDEX_op_shr_i32:
|
820 | f54b3f92 | aurel32 | tcg_out32(s, MTCTL | INSN_R2(11) | INSN_R1(args[2])); |
821 | f54b3f92 | aurel32 | tcg_out32(s, VSHD | INSN_T(args[0]) | INSN_R1(TCG_REG_R0) |
|
822 | f54b3f92 | aurel32 | INSN_R2(args[1]));
|
823 | f54b3f92 | aurel32 | break;
|
824 | f54b3f92 | aurel32 | case INDEX_op_sar_i32:
|
825 | f54b3f92 | aurel32 | tcg_out32(s, SUBI | INSN_R1(TCG_REG_R20) | INSN_R2(args[2]) |
|
826 | f54b3f92 | aurel32 | lowsignext(0x1f, 0, 11)); |
827 | f54b3f92 | aurel32 | tcg_out32(s, MTCTL | INSN_R2(11) | INSN_R1(TCG_REG_R20));
|
828 | f54b3f92 | aurel32 | tcg_out32(s, VEXTRS | INSN_R1(args[0]) | INSN_R2(args[1]) | |
829 | f54b3f92 | aurel32 | INSN_DEP_LEN(32));
|
830 | f54b3f92 | aurel32 | break;
|
831 | f54b3f92 | aurel32 | |
832 | f54b3f92 | aurel32 | case INDEX_op_mul_i32:
|
833 | f54b3f92 | aurel32 | fprintf(stderr, "unimplemented mul\n");
|
834 | f54b3f92 | aurel32 | tcg_abort(); |
835 | f54b3f92 | aurel32 | break;
|
836 | f54b3f92 | aurel32 | case INDEX_op_mulu2_i32:
|
837 | f54b3f92 | aurel32 | fprintf(stderr, "unimplemented mulu2\n");
|
838 | f54b3f92 | aurel32 | tcg_abort(); |
839 | f54b3f92 | aurel32 | break;
|
840 | f54b3f92 | aurel32 | case INDEX_op_div2_i32:
|
841 | f54b3f92 | aurel32 | fprintf(stderr, "unimplemented div2\n");
|
842 | f54b3f92 | aurel32 | tcg_abort(); |
843 | f54b3f92 | aurel32 | break;
|
844 | f54b3f92 | aurel32 | case INDEX_op_divu2_i32:
|
845 | f54b3f92 | aurel32 | fprintf(stderr, "unimplemented divu2\n");
|
846 | f54b3f92 | aurel32 | tcg_abort(); |
847 | f54b3f92 | aurel32 | break;
|
848 | f54b3f92 | aurel32 | |
849 | f54b3f92 | aurel32 | case INDEX_op_brcond_i32:
|
850 | f54b3f92 | aurel32 | fprintf(stderr, "unimplemented brcond\n");
|
851 | f54b3f92 | aurel32 | tcg_abort(); |
852 | f54b3f92 | aurel32 | break;
|
853 | f54b3f92 | aurel32 | |
854 | f54b3f92 | aurel32 | case INDEX_op_qemu_ld8u:
|
855 | f54b3f92 | aurel32 | tcg_out_qemu_ld(s, args, 0);
|
856 | f54b3f92 | aurel32 | break;
|
857 | f54b3f92 | aurel32 | case INDEX_op_qemu_ld8s:
|
858 | f54b3f92 | aurel32 | tcg_out_qemu_ld(s, args, 0 | 4); |
859 | f54b3f92 | aurel32 | break;
|
860 | f54b3f92 | aurel32 | case INDEX_op_qemu_ld16u:
|
861 | f54b3f92 | aurel32 | tcg_out_qemu_ld(s, args, 1);
|
862 | f54b3f92 | aurel32 | break;
|
863 | f54b3f92 | aurel32 | case INDEX_op_qemu_ld16s:
|
864 | f54b3f92 | aurel32 | tcg_out_qemu_ld(s, args, 1 | 4); |
865 | f54b3f92 | aurel32 | break;
|
866 | f54b3f92 | aurel32 | case INDEX_op_qemu_ld32u:
|
867 | f54b3f92 | aurel32 | tcg_out_qemu_ld(s, args, 2);
|
868 | f54b3f92 | aurel32 | break;
|
869 | f54b3f92 | aurel32 | |
870 | f54b3f92 | aurel32 | case INDEX_op_qemu_st8:
|
871 | f54b3f92 | aurel32 | tcg_out_qemu_st(s, args, 0);
|
872 | f54b3f92 | aurel32 | break;
|
873 | f54b3f92 | aurel32 | case INDEX_op_qemu_st16:
|
874 | f54b3f92 | aurel32 | tcg_out_qemu_st(s, args, 1);
|
875 | f54b3f92 | aurel32 | break;
|
876 | f54b3f92 | aurel32 | case INDEX_op_qemu_st32:
|
877 | f54b3f92 | aurel32 | tcg_out_qemu_st(s, args, 2);
|
878 | f54b3f92 | aurel32 | break;
|
879 | f54b3f92 | aurel32 | |
880 | f54b3f92 | aurel32 | default:
|
881 | f54b3f92 | aurel32 | fprintf(stderr, "unknown opcode 0x%x\n", opc);
|
882 | f54b3f92 | aurel32 | tcg_abort(); |
883 | f54b3f92 | aurel32 | } |
884 | f54b3f92 | aurel32 | return;
|
885 | f54b3f92 | aurel32 | |
886 | f54b3f92 | aurel32 | gen_arith:
|
887 | f54b3f92 | aurel32 | tcg_out_arith(s, args[0], args[1], args[2], c); |
888 | f54b3f92 | aurel32 | } |
889 | f54b3f92 | aurel32 | |
890 | f54b3f92 | aurel32 | static const TCGTargetOpDef hppa_op_defs[] = { |
891 | f54b3f92 | aurel32 | { INDEX_op_exit_tb, { } }, |
892 | f54b3f92 | aurel32 | { INDEX_op_goto_tb, { } }, |
893 | f54b3f92 | aurel32 | |
894 | f54b3f92 | aurel32 | { INDEX_op_call, { "r" } },
|
895 | f54b3f92 | aurel32 | { INDEX_op_jmp, { "r" } },
|
896 | f54b3f92 | aurel32 | { INDEX_op_br, { } }, |
897 | f54b3f92 | aurel32 | |
898 | f54b3f92 | aurel32 | { INDEX_op_mov_i32, { "r", "r" } }, |
899 | f54b3f92 | aurel32 | { INDEX_op_movi_i32, { "r" } },
|
900 | f54b3f92 | aurel32 | { INDEX_op_ld8u_i32, { "r", "r" } }, |
901 | f54b3f92 | aurel32 | { INDEX_op_ld8s_i32, { "r", "r" } }, |
902 | f54b3f92 | aurel32 | { INDEX_op_ld16u_i32, { "r", "r" } }, |
903 | f54b3f92 | aurel32 | { INDEX_op_ld16s_i32, { "r", "r" } }, |
904 | f54b3f92 | aurel32 | { INDEX_op_ld_i32, { "r", "r" } }, |
905 | f54b3f92 | aurel32 | { INDEX_op_st8_i32, { "r", "r" } }, |
906 | f54b3f92 | aurel32 | { INDEX_op_st16_i32, { "r", "r" } }, |
907 | f54b3f92 | aurel32 | { INDEX_op_st_i32, { "r", "r" } }, |
908 | f54b3f92 | aurel32 | |
909 | f54b3f92 | aurel32 | { INDEX_op_add_i32, { "r", "r", "r" } }, |
910 | f54b3f92 | aurel32 | { INDEX_op_sub_i32, { "r", "r", "r" } }, |
911 | f54b3f92 | aurel32 | { INDEX_op_and_i32, { "r", "r", "r" } }, |
912 | f54b3f92 | aurel32 | { INDEX_op_or_i32, { "r", "r", "r" } }, |
913 | f54b3f92 | aurel32 | { INDEX_op_xor_i32, { "r", "r", "r" } }, |
914 | f54b3f92 | aurel32 | |
915 | f54b3f92 | aurel32 | { INDEX_op_shl_i32, { "r", "r", "r" } }, |
916 | f54b3f92 | aurel32 | { INDEX_op_shr_i32, { "r", "r", "r" } }, |
917 | f54b3f92 | aurel32 | { INDEX_op_sar_i32, { "r", "r", "r" } }, |
918 | f54b3f92 | aurel32 | |
919 | f54b3f92 | aurel32 | { INDEX_op_brcond_i32, { "r", "r" } }, |
920 | f54b3f92 | aurel32 | |
921 | f54b3f92 | aurel32 | #if TARGET_LONG_BITS == 32 |
922 | f54b3f92 | aurel32 | { INDEX_op_qemu_ld8u, { "r", "L" } }, |
923 | f54b3f92 | aurel32 | { INDEX_op_qemu_ld8s, { "r", "L" } }, |
924 | f54b3f92 | aurel32 | { INDEX_op_qemu_ld16u, { "r", "L" } }, |
925 | f54b3f92 | aurel32 | { INDEX_op_qemu_ld16s, { "r", "L" } }, |
926 | f54b3f92 | aurel32 | { INDEX_op_qemu_ld32u, { "r", "L" } }, |
927 | f54b3f92 | aurel32 | { INDEX_op_qemu_ld64, { "r", "r", "L" } }, |
928 | f54b3f92 | aurel32 | |
929 | f54b3f92 | aurel32 | { INDEX_op_qemu_st8, { "L", "L" } }, |
930 | f54b3f92 | aurel32 | { INDEX_op_qemu_st16, { "L", "L" } }, |
931 | f54b3f92 | aurel32 | { INDEX_op_qemu_st32, { "L", "L" } }, |
932 | f54b3f92 | aurel32 | { INDEX_op_qemu_st64, { "L", "L", "L" } }, |
933 | f54b3f92 | aurel32 | #else
|
934 | f54b3f92 | aurel32 | { INDEX_op_qemu_ld8u, { "r", "L", "L" } }, |
935 | f54b3f92 | aurel32 | { INDEX_op_qemu_ld8s, { "r", "L", "L" } }, |
936 | f54b3f92 | aurel32 | { INDEX_op_qemu_ld16u, { "r", "L", "L" } }, |
937 | f54b3f92 | aurel32 | { INDEX_op_qemu_ld16s, { "r", "L", "L" } }, |
938 | f54b3f92 | aurel32 | { INDEX_op_qemu_ld32u, { "r", "L", "L" } }, |
939 | f54b3f92 | aurel32 | { INDEX_op_qemu_ld32s, { "r", "L", "L" } }, |
940 | f54b3f92 | aurel32 | { INDEX_op_qemu_ld64, { "r", "r", "L", "L" } }, |
941 | f54b3f92 | aurel32 | |
942 | f54b3f92 | aurel32 | { INDEX_op_qemu_st8, { "L", "L", "L" } }, |
943 | f54b3f92 | aurel32 | { INDEX_op_qemu_st16, { "L", "L", "L" } }, |
944 | f54b3f92 | aurel32 | { INDEX_op_qemu_st32, { "L", "L", "L" } }, |
945 | f54b3f92 | aurel32 | { INDEX_op_qemu_st64, { "L", "L", "L", "L" } }, |
946 | f54b3f92 | aurel32 | #endif
|
947 | f54b3f92 | aurel32 | { -1 },
|
948 | f54b3f92 | aurel32 | }; |
949 | f54b3f92 | aurel32 | |
950 | f54b3f92 | aurel32 | void tcg_target_init(TCGContext *s)
|
951 | f54b3f92 | aurel32 | { |
952 | f54b3f92 | aurel32 | tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_I32], 0, 0xffffffff); |
953 | f54b3f92 | aurel32 | tcg_regset_set32(tcg_target_call_clobber_regs, 0,
|
954 | f54b3f92 | aurel32 | (1 << TCG_REG_R20) |
|
955 | f54b3f92 | aurel32 | (1 << TCG_REG_R21) |
|
956 | f54b3f92 | aurel32 | (1 << TCG_REG_R22) |
|
957 | f54b3f92 | aurel32 | (1 << TCG_REG_R23) |
|
958 | f54b3f92 | aurel32 | (1 << TCG_REG_R24) |
|
959 | f54b3f92 | aurel32 | (1 << TCG_REG_R25) |
|
960 | f54b3f92 | aurel32 | (1 << TCG_REG_R26));
|
961 | f54b3f92 | aurel32 | |
962 | f54b3f92 | aurel32 | tcg_regset_clear(s->reserved_regs); |
963 | f54b3f92 | aurel32 | tcg_regset_set_reg(s->reserved_regs, TCG_REG_R0); /* hardwired to zero */
|
964 | f54b3f92 | aurel32 | tcg_regset_set_reg(s->reserved_regs, TCG_REG_R1); /* addil target */
|
965 | f54b3f92 | aurel32 | tcg_regset_set_reg(s->reserved_regs, TCG_REG_RP); /* link register */
|
966 | f54b3f92 | aurel32 | tcg_regset_set_reg(s->reserved_regs, TCG_REG_R3); /* frame pointer */
|
967 | f54b3f92 | aurel32 | tcg_regset_set_reg(s->reserved_regs, TCG_REG_R18); /* return pointer */
|
968 | f54b3f92 | aurel32 | tcg_regset_set_reg(s->reserved_regs, TCG_REG_R19); /* clobbered w/o pic */
|
969 | f54b3f92 | aurel32 | tcg_regset_set_reg(s->reserved_regs, TCG_REG_R20); /* reserved */
|
970 | f54b3f92 | aurel32 | tcg_regset_set_reg(s->reserved_regs, TCG_REG_DP); /* data pointer */
|
971 | f54b3f92 | aurel32 | tcg_regset_set_reg(s->reserved_regs, TCG_REG_SP); /* stack pointer */
|
972 | f54b3f92 | aurel32 | tcg_regset_set_reg(s->reserved_regs, TCG_REG_R31); /* ble link reg */
|
973 | f54b3f92 | aurel32 | |
974 | f54b3f92 | aurel32 | tcg_add_target_add_op_defs(hppa_op_defs); |
975 | f54b3f92 | aurel32 | } |