root / tcg / x86_64 / tcg-target.h @ 86dbdd40
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1 | c896fe29 | bellard | /*
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2 | c896fe29 | bellard | * Tiny Code Generator for QEMU
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3 | c896fe29 | bellard | *
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4 | c896fe29 | bellard | * Copyright (c) 2008 Fabrice Bellard
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5 | c896fe29 | bellard | *
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6 | c896fe29 | bellard | * Permission is hereby granted, free of charge, to any person obtaining a copy
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7 | c896fe29 | bellard | * of this software and associated documentation files (the "Software"), to deal
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8 | c896fe29 | bellard | * in the Software without restriction, including without limitation the rights
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9 | c896fe29 | bellard | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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10 | c896fe29 | bellard | * copies of the Software, and to permit persons to whom the Software is
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11 | c896fe29 | bellard | * furnished to do so, subject to the following conditions:
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12 | c896fe29 | bellard | *
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13 | c896fe29 | bellard | * The above copyright notice and this permission notice shall be included in
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14 | c896fe29 | bellard | * all copies or substantial portions of the Software.
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15 | c896fe29 | bellard | *
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16 | c896fe29 | bellard | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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17 | c896fe29 | bellard | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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18 | c896fe29 | bellard | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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19 | c896fe29 | bellard | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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20 | c896fe29 | bellard | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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21 | c896fe29 | bellard | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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22 | c896fe29 | bellard | * THE SOFTWARE.
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23 | c896fe29 | bellard | */
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24 | c896fe29 | bellard | #define TCG_TARGET_X86_64 1 |
25 | c896fe29 | bellard | |
26 | c896fe29 | bellard | #define TCG_TARGET_REG_BITS 64 |
27 | c896fe29 | bellard | //#define TCG_TARGET_WORDS_BIGENDIAN
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28 | c896fe29 | bellard | |
29 | c896fe29 | bellard | #define TCG_TARGET_NB_REGS 16 |
30 | c896fe29 | bellard | |
31 | c896fe29 | bellard | enum {
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32 | c896fe29 | bellard | TCG_REG_RAX = 0,
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33 | c896fe29 | bellard | TCG_REG_RCX, |
34 | c896fe29 | bellard | TCG_REG_RDX, |
35 | c896fe29 | bellard | TCG_REG_RBX, |
36 | c896fe29 | bellard | TCG_REG_RSP, |
37 | c896fe29 | bellard | TCG_REG_RBP, |
38 | c896fe29 | bellard | TCG_REG_RSI, |
39 | c896fe29 | bellard | TCG_REG_RDI, |
40 | c896fe29 | bellard | TCG_REG_R8, |
41 | c896fe29 | bellard | TCG_REG_R9, |
42 | c896fe29 | bellard | TCG_REG_R10, |
43 | c896fe29 | bellard | TCG_REG_R11, |
44 | c896fe29 | bellard | TCG_REG_R12, |
45 | c896fe29 | bellard | TCG_REG_R13, |
46 | c896fe29 | bellard | TCG_REG_R14, |
47 | c896fe29 | bellard | TCG_REG_R15, |
48 | c896fe29 | bellard | }; |
49 | c896fe29 | bellard | |
50 | c896fe29 | bellard | #define TCG_CT_CONST_S32 0x100 |
51 | c896fe29 | bellard | #define TCG_CT_CONST_U32 0x200 |
52 | c896fe29 | bellard | |
53 | c896fe29 | bellard | /* used for function call generation */
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54 | c896fe29 | bellard | #define TCG_REG_CALL_STACK TCG_REG_RSP
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55 | c896fe29 | bellard | #define TCG_TARGET_STACK_ALIGN 16 |
56 | 39cf05d3 | bellard | #define TCG_TARGET_CALL_STACK_OFFSET 0 |
57 | c896fe29 | bellard | |
58 | c896fe29 | bellard | /* optional instructions */
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59 | 86dbdd40 | aurel32 | #define TCG_TARGET_HAS_bswap16_i32
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60 | 86dbdd40 | aurel32 | #define TCG_TARGET_HAS_bswap16_i64
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61 | 66896cb8 | aurel32 | #define TCG_TARGET_HAS_bswap32_i32
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62 | 86dbdd40 | aurel32 | #define TCG_TARGET_HAS_bswap32_i64
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63 | 66896cb8 | aurel32 | #define TCG_TARGET_HAS_bswap64_i64
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64 | 390efc54 | pbrook | #define TCG_TARGET_HAS_neg_i32
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65 | 390efc54 | pbrook | #define TCG_TARGET_HAS_neg_i64
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66 | d2604285 | aurel32 | #define TCG_TARGET_HAS_not_i32
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67 | d2604285 | aurel32 | #define TCG_TARGET_HAS_not_i64
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68 | b6d17150 | pbrook | #define TCG_TARGET_HAS_ext8s_i32
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69 | b6d17150 | pbrook | #define TCG_TARGET_HAS_ext16s_i32
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70 | b6d17150 | pbrook | #define TCG_TARGET_HAS_ext8s_i64
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71 | b6d17150 | pbrook | #define TCG_TARGET_HAS_ext16s_i64
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72 | b6d17150 | pbrook | #define TCG_TARGET_HAS_ext32s_i64
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73 | d42f183c | aurel32 | #define TCG_TARGET_HAS_rot_i32
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74 | d42f183c | aurel32 | #define TCG_TARGET_HAS_rot_i64
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75 | c896fe29 | bellard | |
76 | c896fe29 | bellard | /* Note: must be synced with dyngen-exec.h */
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77 | c896fe29 | bellard | #define TCG_AREG0 TCG_REG_R14
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78 | c896fe29 | bellard | #define TCG_AREG1 TCG_REG_R15
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79 | c896fe29 | bellard | #define TCG_AREG2 TCG_REG_R12
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80 | c896fe29 | bellard | |
81 | c896fe29 | bellard | static inline void flush_icache_range(unsigned long start, unsigned long stop) |
82 | c896fe29 | bellard | { |
83 | c896fe29 | bellard | } |