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/*
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* QEMU ESP/NCR53C9x emulation
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*
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* Copyright (c) 2005-2006 Fabrice Bellard
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "hw.h" |
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#include "block.h" |
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#include "scsi-disk.h" |
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#include "sun4m.h" |
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/* FIXME: Only needed for MAX_DISKS, which is probably wrong. */
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#include "sysemu.h" |
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/* debug ESP card */
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//#define DEBUG_ESP
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/*
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* On Sparc32, this is the ESP (NCR53C90) part of chip STP2000 (Master I/O), also
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* produced as NCR89C100. See
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* http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR89C100.txt
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* and
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* http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR53C9X.txt
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*/
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#ifdef DEBUG_ESP
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#define DPRINTF(fmt, args...) \
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do { printf("ESP: " fmt , ##args); } while (0) |
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#else
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#define DPRINTF(fmt, args...)
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#endif
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#define ESP_MASK 0x3f |
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#define ESP_REGS 16 |
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#define ESP_SIZE (ESP_REGS * 4) |
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#define TI_BUFSZ 32 |
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/* The HBA is ID 7, so for simplicitly limit to 7 devices. */
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#define ESP_MAX_DEVS 7 |
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typedef struct ESPState ESPState; |
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struct ESPState {
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qemu_irq irq; |
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BlockDriverState **bd; |
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uint8_t rregs[ESP_REGS]; |
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uint8_t wregs[ESP_REGS]; |
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int32_t ti_size; |
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uint32_t ti_rptr, ti_wptr; |
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uint8_t ti_buf[TI_BUFSZ]; |
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int sense;
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int dma;
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SCSIDevice *scsi_dev[MAX_DISKS]; |
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SCSIDevice *current_dev; |
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uint8_t cmdbuf[TI_BUFSZ]; |
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int cmdlen;
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int do_cmd;
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/* The amount of data left in the current DMA transfer. */
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uint32_t dma_left; |
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/* The size of the current DMA transfer. Zero if no transfer is in
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progress. */
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uint32_t dma_counter; |
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uint8_t *async_buf; |
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uint32_t async_len; |
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void *dma_opaque;
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}; |
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#define STAT_DO 0x00 |
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#define STAT_DI 0x01 |
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#define STAT_CD 0x02 |
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#define STAT_ST 0x03 |
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#define STAT_MI 0x06 |
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#define STAT_MO 0x07 |
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#define STAT_TC 0x10 |
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#define STAT_PE 0x20 |
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#define STAT_GE 0x40 |
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#define STAT_IN 0x80 |
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#define INTR_FC 0x08 |
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#define INTR_BS 0x10 |
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#define INTR_DC 0x20 |
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#define INTR_RST 0x80 |
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#define SEQ_0 0x0 |
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#define SEQ_CD 0x4 |
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static int get_cmd(ESPState *s, uint8_t *buf) |
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{ |
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uint32_t dmalen; |
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int target;
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dmalen = s->rregs[0] | (s->rregs[1] << 8); |
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target = s->wregs[4] & 7; |
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DPRINTF("get_cmd: len %d target %d\n", dmalen, target);
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if (s->dma) {
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espdma_memory_read(s->dma_opaque, buf, dmalen); |
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} else {
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buf[0] = 0; |
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memcpy(&buf[1], s->ti_buf, dmalen);
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dmalen++; |
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} |
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s->ti_size = 0;
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s->ti_rptr = 0;
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s->ti_wptr = 0;
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if (s->current_dev) {
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/* Started a new command before the old one finished. Cancel it. */
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scsi_cancel_io(s->current_dev, 0);
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s->async_len = 0;
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} |
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if (target >= MAX_DISKS || !s->scsi_dev[target]) {
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// No such drive
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s->rregs[4] = STAT_IN;
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s->rregs[5] = INTR_DC;
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s->rregs[6] = SEQ_0;
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qemu_irq_raise(s->irq); |
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return 0; |
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} |
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s->current_dev = s->scsi_dev[target]; |
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return dmalen;
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} |
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static void do_cmd(ESPState *s, uint8_t *buf) |
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{ |
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int32_t datalen; |
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int lun;
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DPRINTF("do_cmd: busid 0x%x\n", buf[0]); |
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lun = buf[0] & 7; |
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datalen = scsi_send_command(s->current_dev, 0, &buf[1], lun); |
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s->ti_size = datalen; |
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if (datalen != 0) { |
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s->rregs[4] = STAT_IN | STAT_TC;
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s->dma_left = 0;
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s->dma_counter = 0;
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if (datalen > 0) { |
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s->rregs[4] |= STAT_DI;
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scsi_read_data(s->current_dev, 0);
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} else {
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s->rregs[4] |= STAT_DO;
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scsi_write_data(s->current_dev, 0);
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} |
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} |
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s->rregs[5] = INTR_BS | INTR_FC;
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s->rregs[6] = SEQ_CD;
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qemu_irq_raise(s->irq); |
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} |
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static void handle_satn(ESPState *s) |
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{ |
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uint8_t buf[32];
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int len;
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len = get_cmd(s, buf); |
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if (len)
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do_cmd(s, buf); |
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} |
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static void handle_satn_stop(ESPState *s) |
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{ |
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s->cmdlen = get_cmd(s, s->cmdbuf); |
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if (s->cmdlen) {
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DPRINTF("Set ATN & Stop: cmdlen %d\n", s->cmdlen);
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s->do_cmd = 1;
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s->rregs[4] = STAT_IN | STAT_TC | STAT_CD;
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s->rregs[5] = INTR_BS | INTR_FC;
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s->rregs[6] = SEQ_CD;
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qemu_irq_raise(s->irq); |
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} |
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} |
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static void write_response(ESPState *s) |
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{ |
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DPRINTF("Transfer status (sense=%d)\n", s->sense);
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s->ti_buf[0] = s->sense;
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s->ti_buf[1] = 0; |
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if (s->dma) {
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espdma_memory_write(s->dma_opaque, s->ti_buf, 2);
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s->rregs[4] = STAT_IN | STAT_TC | STAT_ST;
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s->rregs[5] = INTR_BS | INTR_FC;
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s->rregs[6] = SEQ_CD;
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} else {
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s->ti_size = 2;
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s->ti_rptr = 0;
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s->ti_wptr = 0;
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s->rregs[7] = 2; |
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} |
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qemu_irq_raise(s->irq); |
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} |
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static void esp_dma_done(ESPState *s) |
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{ |
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s->rregs[4] |= STAT_IN | STAT_TC;
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s->rregs[5] = INTR_BS;
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s->rregs[6] = 0; |
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s->rregs[7] = 0; |
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s->rregs[0] = 0; |
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s->rregs[1] = 0; |
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qemu_irq_raise(s->irq); |
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} |
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static void esp_do_dma(ESPState *s) |
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{ |
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uint32_t len; |
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int to_device;
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to_device = (s->ti_size < 0);
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len = s->dma_left; |
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if (s->do_cmd) {
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DPRINTF("command len %d + %d\n", s->cmdlen, len);
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espdma_memory_read(s->dma_opaque, &s->cmdbuf[s->cmdlen], len); |
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s->ti_size = 0;
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s->cmdlen = 0;
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s->do_cmd = 0;
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do_cmd(s, s->cmdbuf); |
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return;
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} |
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if (s->async_len == 0) { |
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/* Defer until data is available. */
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return;
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} |
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if (len > s->async_len) {
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len = s->async_len; |
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} |
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if (to_device) {
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espdma_memory_read(s->dma_opaque, s->async_buf, len); |
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} else {
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espdma_memory_write(s->dma_opaque, s->async_buf, len); |
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} |
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s->dma_left -= len; |
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s->async_buf += len; |
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s->async_len -= len; |
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if (to_device)
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s->ti_size += len; |
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else
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s->ti_size -= len; |
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if (s->async_len == 0) { |
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if (to_device) {
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// ti_size is negative
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scsi_write_data(s->current_dev, 0);
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} else {
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scsi_read_data(s->current_dev, 0);
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/* If there is still data to be read from the device then
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complete the DMA operation immeriately. Otherwise defer
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until the scsi layer has completed. */
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if (s->dma_left == 0 && s->ti_size > 0) { |
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esp_dma_done(s); |
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} |
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} |
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} else {
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/* Partially filled a scsi buffer. Complete immediately. */
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esp_dma_done(s); |
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} |
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} |
274 |
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static void esp_command_complete(void *opaque, int reason, uint32_t tag, |
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uint32_t arg) |
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{ |
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ESPState *s = (ESPState *)opaque; |
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if (reason == SCSI_REASON_DONE) {
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DPRINTF("SCSI Command complete\n");
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if (s->ti_size != 0) |
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DPRINTF("SCSI command completed unexpectedly\n");
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s->ti_size = 0;
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s->dma_left = 0;
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s->async_len = 0;
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if (arg)
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DPRINTF("Command failed\n");
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s->sense = arg; |
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s->rregs[4] = STAT_ST;
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esp_dma_done(s); |
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s->current_dev = NULL;
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} else {
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DPRINTF("transfer %d/%d\n", s->dma_left, s->ti_size);
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s->async_len = arg; |
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s->async_buf = scsi_get_buf(s->current_dev, 0);
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if (s->dma_left) {
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esp_do_dma(s); |
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} else if (s->dma_counter != 0 && s->ti_size <= 0) { |
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/* If this was the last part of a DMA transfer then the
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completion interrupt is deferred to here. */
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esp_dma_done(s); |
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} |
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} |
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} |
306 |
|
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static void handle_ti(ESPState *s) |
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{ |
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uint32_t dmalen, minlen; |
310 |
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dmalen = s->rregs[0] | (s->rregs[1] << 8); |
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if (dmalen==0) { |
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dmalen=0x10000;
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} |
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s->dma_counter = dmalen; |
316 |
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if (s->do_cmd)
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minlen = (dmalen < 32) ? dmalen : 32; |
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else if (s->ti_size < 0) |
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minlen = (dmalen < -s->ti_size) ? dmalen : -s->ti_size; |
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else
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minlen = (dmalen < s->ti_size) ? dmalen : s->ti_size; |
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DPRINTF("Transfer Information len %d\n", minlen);
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if (s->dma) {
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s->dma_left = minlen; |
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s->rregs[4] &= ~STAT_TC;
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esp_do_dma(s); |
328 |
} else if (s->do_cmd) { |
329 |
DPRINTF("command len %d\n", s->cmdlen);
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s->ti_size = 0;
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s->cmdlen = 0;
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s->do_cmd = 0;
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do_cmd(s, s->cmdbuf); |
334 |
return;
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} |
336 |
} |
337 |
|
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static void esp_reset(void *opaque) |
339 |
{ |
340 |
ESPState *s = opaque; |
341 |
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memset(s->rregs, 0, ESP_REGS);
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memset(s->wregs, 0, ESP_REGS);
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s->rregs[0x0e] = 0x4; // Indicate fas100a |
345 |
s->ti_size = 0;
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s->ti_rptr = 0;
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s->ti_wptr = 0;
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s->dma = 0;
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s->do_cmd = 0;
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} |
351 |
|
352 |
static void parent_esp_reset(void *opaque, int irq, int level) |
353 |
{ |
354 |
if (level)
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esp_reset(opaque); |
356 |
} |
357 |
|
358 |
static uint32_t esp_mem_readb(void *opaque, target_phys_addr_t addr) |
359 |
{ |
360 |
ESPState *s = opaque; |
361 |
uint32_t saddr; |
362 |
|
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saddr = (addr & ESP_MASK) >> 2;
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364 |
DPRINTF("read reg[%d]: 0x%2.2x\n", saddr, s->rregs[saddr]);
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switch (saddr) {
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366 |
case 2: |
367 |
// FIFO
|
368 |
if (s->ti_size > 0) { |
369 |
s->ti_size--; |
370 |
if ((s->rregs[4] & 6) == 0) { |
371 |
/* Data in/out. */
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372 |
fprintf(stderr, "esp: PIO data read not implemented\n");
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373 |
s->rregs[2] = 0; |
374 |
} else {
|
375 |
s->rregs[2] = s->ti_buf[s->ti_rptr++];
|
376 |
} |
377 |
qemu_irq_raise(s->irq); |
378 |
} |
379 |
if (s->ti_size == 0) { |
380 |
s->ti_rptr = 0;
|
381 |
s->ti_wptr = 0;
|
382 |
} |
383 |
break;
|
384 |
case 5: |
385 |
// interrupt
|
386 |
// Clear interrupt/error status bits
|
387 |
s->rregs[4] &= ~(STAT_IN | STAT_GE | STAT_PE);
|
388 |
qemu_irq_lower(s->irq); |
389 |
break;
|
390 |
default:
|
391 |
break;
|
392 |
} |
393 |
return s->rregs[saddr];
|
394 |
} |
395 |
|
396 |
static void esp_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val) |
397 |
{ |
398 |
ESPState *s = opaque; |
399 |
uint32_t saddr; |
400 |
|
401 |
saddr = (addr & ESP_MASK) >> 2;
|
402 |
DPRINTF("write reg[%d]: 0x%2.2x -> 0x%2.2x\n", saddr, s->wregs[saddr], val);
|
403 |
switch (saddr) {
|
404 |
case 0: |
405 |
case 1: |
406 |
s->rregs[4] &= ~STAT_TC;
|
407 |
break;
|
408 |
case 2: |
409 |
// FIFO
|
410 |
if (s->do_cmd) {
|
411 |
s->cmdbuf[s->cmdlen++] = val & 0xff;
|
412 |
} else if ((s->rregs[4] & 6) == 0) { |
413 |
uint8_t buf; |
414 |
buf = val & 0xff;
|
415 |
s->ti_size--; |
416 |
fprintf(stderr, "esp: PIO data write not implemented\n");
|
417 |
} else {
|
418 |
s->ti_size++; |
419 |
s->ti_buf[s->ti_wptr++] = val & 0xff;
|
420 |
} |
421 |
break;
|
422 |
case 3: |
423 |
s->rregs[saddr] = val; |
424 |
// Command
|
425 |
if (val & 0x80) { |
426 |
s->dma = 1;
|
427 |
/* Reload DMA counter. */
|
428 |
s->rregs[0] = s->wregs[0]; |
429 |
s->rregs[1] = s->wregs[1]; |
430 |
} else {
|
431 |
s->dma = 0;
|
432 |
} |
433 |
switch(val & 0x7f) { |
434 |
case 0: |
435 |
DPRINTF("NOP (%2.2x)\n", val);
|
436 |
break;
|
437 |
case 1: |
438 |
DPRINTF("Flush FIFO (%2.2x)\n", val);
|
439 |
//s->ti_size = 0;
|
440 |
s->rregs[5] = INTR_FC;
|
441 |
s->rregs[6] = 0; |
442 |
break;
|
443 |
case 2: |
444 |
DPRINTF("Chip reset (%2.2x)\n", val);
|
445 |
esp_reset(s); |
446 |
break;
|
447 |
case 3: |
448 |
DPRINTF("Bus reset (%2.2x)\n", val);
|
449 |
s->rregs[5] = INTR_RST;
|
450 |
if (!(s->wregs[8] & 0x40)) { |
451 |
qemu_irq_raise(s->irq); |
452 |
} |
453 |
break;
|
454 |
case 0x10: |
455 |
handle_ti(s); |
456 |
break;
|
457 |
case 0x11: |
458 |
DPRINTF("Initiator Command Complete Sequence (%2.2x)\n", val);
|
459 |
write_response(s); |
460 |
break;
|
461 |
case 0x12: |
462 |
DPRINTF("Message Accepted (%2.2x)\n", val);
|
463 |
write_response(s); |
464 |
s->rregs[5] = INTR_DC;
|
465 |
s->rregs[6] = 0; |
466 |
break;
|
467 |
case 0x1a: |
468 |
DPRINTF("Set ATN (%2.2x)\n", val);
|
469 |
break;
|
470 |
case 0x42: |
471 |
DPRINTF("Set ATN (%2.2x)\n", val);
|
472 |
handle_satn(s); |
473 |
break;
|
474 |
case 0x43: |
475 |
DPRINTF("Set ATN & stop (%2.2x)\n", val);
|
476 |
handle_satn_stop(s); |
477 |
break;
|
478 |
case 0x44: |
479 |
DPRINTF("Enable selection (%2.2x)\n", val);
|
480 |
break;
|
481 |
default:
|
482 |
DPRINTF("Unhandled ESP command (%2.2x)\n", val);
|
483 |
break;
|
484 |
} |
485 |
break;
|
486 |
case 4 ... 7: |
487 |
break;
|
488 |
case 8: |
489 |
s->rregs[saddr] = val; |
490 |
break;
|
491 |
case 9 ... 10: |
492 |
break;
|
493 |
case 11: |
494 |
s->rregs[saddr] = val & 0x15;
|
495 |
break;
|
496 |
case 12 ... 15: |
497 |
s->rregs[saddr] = val; |
498 |
break;
|
499 |
default:
|
500 |
break;
|
501 |
} |
502 |
s->wregs[saddr] = val; |
503 |
} |
504 |
|
505 |
static CPUReadMemoryFunc *esp_mem_read[3] = { |
506 |
esp_mem_readb, |
507 |
esp_mem_readb, |
508 |
esp_mem_readb, |
509 |
}; |
510 |
|
511 |
static CPUWriteMemoryFunc *esp_mem_write[3] = { |
512 |
esp_mem_writeb, |
513 |
esp_mem_writeb, |
514 |
esp_mem_writeb, |
515 |
}; |
516 |
|
517 |
static void esp_save(QEMUFile *f, void *opaque) |
518 |
{ |
519 |
ESPState *s = opaque; |
520 |
|
521 |
qemu_put_buffer(f, s->rregs, ESP_REGS); |
522 |
qemu_put_buffer(f, s->wregs, ESP_REGS); |
523 |
qemu_put_be32s(f, &s->ti_size); |
524 |
qemu_put_be32s(f, &s->ti_rptr); |
525 |
qemu_put_be32s(f, &s->ti_wptr); |
526 |
qemu_put_buffer(f, s->ti_buf, TI_BUFSZ); |
527 |
qemu_put_be32s(f, &s->sense); |
528 |
qemu_put_be32s(f, &s->dma); |
529 |
qemu_put_buffer(f, s->cmdbuf, TI_BUFSZ); |
530 |
qemu_put_be32s(f, &s->cmdlen); |
531 |
qemu_put_be32s(f, &s->do_cmd); |
532 |
qemu_put_be32s(f, &s->dma_left); |
533 |
// There should be no transfers in progress, so dma_counter is not saved
|
534 |
} |
535 |
|
536 |
static int esp_load(QEMUFile *f, void *opaque, int version_id) |
537 |
{ |
538 |
ESPState *s = opaque; |
539 |
|
540 |
if (version_id != 3) |
541 |
return -EINVAL; // Cannot emulate 2 |
542 |
|
543 |
qemu_get_buffer(f, s->rregs, ESP_REGS); |
544 |
qemu_get_buffer(f, s->wregs, ESP_REGS); |
545 |
qemu_get_be32s(f, &s->ti_size); |
546 |
qemu_get_be32s(f, &s->ti_rptr); |
547 |
qemu_get_be32s(f, &s->ti_wptr); |
548 |
qemu_get_buffer(f, s->ti_buf, TI_BUFSZ); |
549 |
qemu_get_be32s(f, &s->sense); |
550 |
qemu_get_be32s(f, &s->dma); |
551 |
qemu_get_buffer(f, s->cmdbuf, TI_BUFSZ); |
552 |
qemu_get_be32s(f, &s->cmdlen); |
553 |
qemu_get_be32s(f, &s->do_cmd); |
554 |
qemu_get_be32s(f, &s->dma_left); |
555 |
|
556 |
return 0; |
557 |
} |
558 |
|
559 |
void esp_scsi_attach(void *opaque, BlockDriverState *bd, int id) |
560 |
{ |
561 |
ESPState *s = (ESPState *)opaque; |
562 |
|
563 |
if (id < 0) { |
564 |
for (id = 0; id < ESP_MAX_DEVS; id++) { |
565 |
if (s->scsi_dev[id] == NULL) |
566 |
break;
|
567 |
} |
568 |
} |
569 |
if (id >= ESP_MAX_DEVS) {
|
570 |
DPRINTF("Bad Device ID %d\n", id);
|
571 |
return;
|
572 |
} |
573 |
if (s->scsi_dev[id]) {
|
574 |
DPRINTF("Destroying device %d\n", id);
|
575 |
scsi_disk_destroy(s->scsi_dev[id]); |
576 |
} |
577 |
DPRINTF("Attaching block device %d\n", id);
|
578 |
/* Command queueing is not implemented. */
|
579 |
s->scsi_dev[id] = scsi_disk_init(bd, 0, esp_command_complete, s);
|
580 |
} |
581 |
|
582 |
void *esp_init(BlockDriverState **bd, target_phys_addr_t espaddr,
|
583 |
void *dma_opaque, qemu_irq irq, qemu_irq *reset)
|
584 |
{ |
585 |
ESPState *s; |
586 |
int esp_io_memory;
|
587 |
|
588 |
s = qemu_mallocz(sizeof(ESPState));
|
589 |
if (!s)
|
590 |
return NULL; |
591 |
|
592 |
s->bd = bd; |
593 |
s->irq = irq; |
594 |
s->dma_opaque = dma_opaque; |
595 |
|
596 |
esp_io_memory = cpu_register_io_memory(0, esp_mem_read, esp_mem_write, s);
|
597 |
cpu_register_physical_memory(espaddr, ESP_SIZE, esp_io_memory); |
598 |
|
599 |
esp_reset(s); |
600 |
|
601 |
register_savevm("esp", espaddr, 3, esp_save, esp_load, s); |
602 |
qemu_register_reset(esp_reset, s); |
603 |
|
604 |
*reset = *qemu_allocate_irqs(parent_esp_reset, s, 1);
|
605 |
|
606 |
return s;
|
607 |
} |