root / hw / misc / a9scu.c @ 881d588a
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1 | 353575f0 | Peter Crosthwaite | /*
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2 | 353575f0 | Peter Crosthwaite | * Cortex-A9MPCore Snoop Control Unit (SCU) emulation.
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3 | 353575f0 | Peter Crosthwaite | *
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4 | 353575f0 | Peter Crosthwaite | * Copyright (c) 2009 CodeSourcery.
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5 | 353575f0 | Peter Crosthwaite | * Copyright (c) 2011 Linaro Limited.
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6 | 353575f0 | Peter Crosthwaite | * Written by Paul Brook, Peter Maydell.
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7 | 353575f0 | Peter Crosthwaite | *
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8 | 353575f0 | Peter Crosthwaite | * This code is licensed under the GPL.
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9 | 353575f0 | Peter Crosthwaite | */
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10 | 353575f0 | Peter Crosthwaite | |
11 | 83c9f4ca | Paolo Bonzini | #include "hw/sysbus.h" |
12 | 353575f0 | Peter Crosthwaite | |
13 | 353575f0 | Peter Crosthwaite | /* A9MP private memory region. */
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14 | 353575f0 | Peter Crosthwaite | |
15 | 353575f0 | Peter Crosthwaite | typedef struct A9SCUState { |
16 | 353575f0 | Peter Crosthwaite | SysBusDevice busdev; |
17 | 353575f0 | Peter Crosthwaite | MemoryRegion iomem; |
18 | 353575f0 | Peter Crosthwaite | uint32_t control; |
19 | 353575f0 | Peter Crosthwaite | uint32_t status; |
20 | 353575f0 | Peter Crosthwaite | uint32_t num_cpu; |
21 | 353575f0 | Peter Crosthwaite | } A9SCUState; |
22 | 353575f0 | Peter Crosthwaite | |
23 | 353575f0 | Peter Crosthwaite | #define TYPE_A9_SCU "a9-scu" |
24 | 353575f0 | Peter Crosthwaite | #define A9_SCU(obj) OBJECT_CHECK(A9SCUState, (obj), TYPE_A9_SCU)
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25 | 353575f0 | Peter Crosthwaite | |
26 | 353575f0 | Peter Crosthwaite | static uint64_t a9_scu_read(void *opaque, hwaddr offset, |
27 | 353575f0 | Peter Crosthwaite | unsigned size)
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28 | 353575f0 | Peter Crosthwaite | { |
29 | 353575f0 | Peter Crosthwaite | A9SCUState *s = (A9SCUState *)opaque; |
30 | 353575f0 | Peter Crosthwaite | switch (offset) {
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31 | 353575f0 | Peter Crosthwaite | case 0x00: /* Control */ |
32 | 353575f0 | Peter Crosthwaite | return s->control;
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33 | 353575f0 | Peter Crosthwaite | case 0x04: /* Configuration */ |
34 | 353575f0 | Peter Crosthwaite | return (((1 << s->num_cpu) - 1) << 4) | (s->num_cpu - 1); |
35 | 353575f0 | Peter Crosthwaite | case 0x08: /* CPU Power Status */ |
36 | 353575f0 | Peter Crosthwaite | return s->status;
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37 | 353575f0 | Peter Crosthwaite | case 0x09: /* CPU status. */ |
38 | 353575f0 | Peter Crosthwaite | return s->status >> 8; |
39 | 353575f0 | Peter Crosthwaite | case 0x0a: /* CPU status. */ |
40 | 353575f0 | Peter Crosthwaite | return s->status >> 16; |
41 | 353575f0 | Peter Crosthwaite | case 0x0b: /* CPU status. */ |
42 | 353575f0 | Peter Crosthwaite | return s->status >> 24; |
43 | 353575f0 | Peter Crosthwaite | case 0x0c: /* Invalidate All Registers In Secure State */ |
44 | 353575f0 | Peter Crosthwaite | return 0; |
45 | 353575f0 | Peter Crosthwaite | case 0x40: /* Filtering Start Address Register */ |
46 | 353575f0 | Peter Crosthwaite | case 0x44: /* Filtering End Address Register */ |
47 | 353575f0 | Peter Crosthwaite | /* RAZ/WI, like an implementation with only one AXI master */
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48 | 353575f0 | Peter Crosthwaite | return 0; |
49 | 353575f0 | Peter Crosthwaite | case 0x50: /* SCU Access Control Register */ |
50 | 353575f0 | Peter Crosthwaite | case 0x54: /* SCU Non-secure Access Control Register */ |
51 | 353575f0 | Peter Crosthwaite | /* unimplemented, fall through */
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52 | 353575f0 | Peter Crosthwaite | default:
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53 | 353575f0 | Peter Crosthwaite | return 0; |
54 | 353575f0 | Peter Crosthwaite | } |
55 | 353575f0 | Peter Crosthwaite | } |
56 | 353575f0 | Peter Crosthwaite | |
57 | 353575f0 | Peter Crosthwaite | static void a9_scu_write(void *opaque, hwaddr offset, |
58 | 353575f0 | Peter Crosthwaite | uint64_t value, unsigned size)
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59 | 353575f0 | Peter Crosthwaite | { |
60 | 353575f0 | Peter Crosthwaite | A9SCUState *s = (A9SCUState *)opaque; |
61 | 353575f0 | Peter Crosthwaite | uint32_t mask; |
62 | 353575f0 | Peter Crosthwaite | uint32_t shift; |
63 | 353575f0 | Peter Crosthwaite | switch (size) {
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64 | 353575f0 | Peter Crosthwaite | case 1: |
65 | 353575f0 | Peter Crosthwaite | mask = 0xff;
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66 | 353575f0 | Peter Crosthwaite | break;
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67 | 353575f0 | Peter Crosthwaite | case 2: |
68 | 353575f0 | Peter Crosthwaite | mask = 0xffff;
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69 | 353575f0 | Peter Crosthwaite | break;
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70 | 353575f0 | Peter Crosthwaite | case 4: |
71 | 353575f0 | Peter Crosthwaite | mask = 0xffffffff;
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72 | 353575f0 | Peter Crosthwaite | break;
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73 | 353575f0 | Peter Crosthwaite | default:
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74 | 353575f0 | Peter Crosthwaite | fprintf(stderr, "Invalid size %u in write to a9 scu register %x\n",
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75 | 353575f0 | Peter Crosthwaite | size, (unsigned)offset);
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76 | 353575f0 | Peter Crosthwaite | return;
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77 | 353575f0 | Peter Crosthwaite | } |
78 | 353575f0 | Peter Crosthwaite | |
79 | 353575f0 | Peter Crosthwaite | switch (offset) {
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80 | 353575f0 | Peter Crosthwaite | case 0x00: /* Control */ |
81 | 353575f0 | Peter Crosthwaite | s->control = value & 1;
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82 | 353575f0 | Peter Crosthwaite | break;
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83 | 353575f0 | Peter Crosthwaite | case 0x4: /* Configuration: RO */ |
84 | 353575f0 | Peter Crosthwaite | break;
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85 | 353575f0 | Peter Crosthwaite | case 0x08: case 0x09: case 0x0A: case 0x0B: /* Power Control */ |
86 | 353575f0 | Peter Crosthwaite | shift = (offset - 0x8) * 8; |
87 | 353575f0 | Peter Crosthwaite | s->status &= ~(mask << shift); |
88 | 353575f0 | Peter Crosthwaite | s->status |= ((value & mask) << shift); |
89 | 353575f0 | Peter Crosthwaite | break;
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90 | 353575f0 | Peter Crosthwaite | case 0x0c: /* Invalidate All Registers In Secure State */ |
91 | 353575f0 | Peter Crosthwaite | /* no-op as we do not implement caches */
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92 | 353575f0 | Peter Crosthwaite | break;
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93 | 353575f0 | Peter Crosthwaite | case 0x40: /* Filtering Start Address Register */ |
94 | 353575f0 | Peter Crosthwaite | case 0x44: /* Filtering End Address Register */ |
95 | 353575f0 | Peter Crosthwaite | /* RAZ/WI, like an implementation with only one AXI master */
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96 | 353575f0 | Peter Crosthwaite | break;
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97 | 353575f0 | Peter Crosthwaite | case 0x50: /* SCU Access Control Register */ |
98 | 353575f0 | Peter Crosthwaite | case 0x54: /* SCU Non-secure Access Control Register */ |
99 | 353575f0 | Peter Crosthwaite | /* unimplemented, fall through */
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100 | 353575f0 | Peter Crosthwaite | default:
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101 | 353575f0 | Peter Crosthwaite | break;
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102 | 353575f0 | Peter Crosthwaite | } |
103 | 353575f0 | Peter Crosthwaite | } |
104 | 353575f0 | Peter Crosthwaite | |
105 | 353575f0 | Peter Crosthwaite | static const MemoryRegionOps a9_scu_ops = { |
106 | 353575f0 | Peter Crosthwaite | .read = a9_scu_read, |
107 | 353575f0 | Peter Crosthwaite | .write = a9_scu_write, |
108 | 353575f0 | Peter Crosthwaite | .endianness = DEVICE_NATIVE_ENDIAN, |
109 | 353575f0 | Peter Crosthwaite | }; |
110 | 353575f0 | Peter Crosthwaite | |
111 | 353575f0 | Peter Crosthwaite | static void a9_scu_reset(DeviceState *dev) |
112 | 353575f0 | Peter Crosthwaite | { |
113 | 353575f0 | Peter Crosthwaite | A9SCUState *s = A9_SCU(dev); |
114 | 353575f0 | Peter Crosthwaite | s->control = 0;
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115 | 353575f0 | Peter Crosthwaite | } |
116 | 353575f0 | Peter Crosthwaite | |
117 | 353575f0 | Peter Crosthwaite | static void a9_scu_realize(DeviceState *dev, Error ** errp) |
118 | 353575f0 | Peter Crosthwaite | { |
119 | 353575f0 | Peter Crosthwaite | A9SCUState *s = A9_SCU(dev); |
120 | 353575f0 | Peter Crosthwaite | SysBusDevice *sbd = SYS_BUS_DEVICE(dev); |
121 | 353575f0 | Peter Crosthwaite | |
122 | 353575f0 | Peter Crosthwaite | memory_region_init_io(&s->iomem, &a9_scu_ops, s, "a9-scu", 0x100); |
123 | 353575f0 | Peter Crosthwaite | sysbus_init_mmio(sbd, &s->iomem); |
124 | 353575f0 | Peter Crosthwaite | } |
125 | 353575f0 | Peter Crosthwaite | |
126 | 353575f0 | Peter Crosthwaite | static const VMStateDescription vmstate_a9_scu = { |
127 | 353575f0 | Peter Crosthwaite | .name = "a9-scu",
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128 | 353575f0 | Peter Crosthwaite | .version_id = 1,
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129 | 353575f0 | Peter Crosthwaite | .minimum_version_id = 1,
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130 | 353575f0 | Peter Crosthwaite | .fields = (VMStateField[]) { |
131 | 353575f0 | Peter Crosthwaite | VMSTATE_UINT32(control, A9SCUState), |
132 | 353575f0 | Peter Crosthwaite | VMSTATE_UINT32(status, A9SCUState), |
133 | 353575f0 | Peter Crosthwaite | VMSTATE_END_OF_LIST() |
134 | 353575f0 | Peter Crosthwaite | } |
135 | 353575f0 | Peter Crosthwaite | }; |
136 | 353575f0 | Peter Crosthwaite | |
137 | 353575f0 | Peter Crosthwaite | static Property a9_scu_properties[] = {
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138 | 353575f0 | Peter Crosthwaite | DEFINE_PROP_UINT32("num-cpu", A9SCUState, num_cpu, 1), |
139 | 353575f0 | Peter Crosthwaite | DEFINE_PROP_END_OF_LIST(), |
140 | 353575f0 | Peter Crosthwaite | }; |
141 | 353575f0 | Peter Crosthwaite | |
142 | 353575f0 | Peter Crosthwaite | static void a9_scu_class_init(ObjectClass *klass, void *data) |
143 | 353575f0 | Peter Crosthwaite | { |
144 | 353575f0 | Peter Crosthwaite | DeviceClass *dc = DEVICE_CLASS(klass); |
145 | 353575f0 | Peter Crosthwaite | |
146 | 353575f0 | Peter Crosthwaite | dc->realize = a9_scu_realize; |
147 | 353575f0 | Peter Crosthwaite | dc->props = a9_scu_properties; |
148 | 353575f0 | Peter Crosthwaite | dc->vmsd = &vmstate_a9_scu; |
149 | 353575f0 | Peter Crosthwaite | dc->reset = a9_scu_reset; |
150 | 353575f0 | Peter Crosthwaite | } |
151 | 353575f0 | Peter Crosthwaite | |
152 | 353575f0 | Peter Crosthwaite | static const TypeInfo a9_scu_info = { |
153 | 353575f0 | Peter Crosthwaite | .name = TYPE_A9_SCU, |
154 | 353575f0 | Peter Crosthwaite | .parent = TYPE_SYS_BUS_DEVICE, |
155 | 353575f0 | Peter Crosthwaite | .instance_size = sizeof(A9SCUState),
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156 | 353575f0 | Peter Crosthwaite | .class_init = a9_scu_class_init, |
157 | 353575f0 | Peter Crosthwaite | }; |
158 | 353575f0 | Peter Crosthwaite | |
159 | 353575f0 | Peter Crosthwaite | static void a9mp_register_types(void) |
160 | 353575f0 | Peter Crosthwaite | { |
161 | 353575f0 | Peter Crosthwaite | type_register_static(&a9_scu_info); |
162 | 353575f0 | Peter Crosthwaite | } |
163 | 353575f0 | Peter Crosthwaite | |
164 | 353575f0 | Peter Crosthwaite | type_init(a9mp_register_types) |