root / target-sparc / cpu.h @ 88738c09
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1 | 7a3f1944 | bellard | #ifndef CPU_SPARC_H
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2 | 7a3f1944 | bellard | #define CPU_SPARC_H
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3 | 7a3f1944 | bellard | |
4 | af7bf89b | bellard | #include "config.h" |
5 | af7bf89b | bellard | |
6 | af7bf89b | bellard | #if !defined(TARGET_SPARC64)
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7 | 3cf1e035 | bellard | #define TARGET_LONG_BITS 32 |
8 | af7bf89b | bellard | #define TARGET_FPREGS 32 |
9 | 83469015 | bellard | #define TARGET_PAGE_BITS 12 /* 4k */ |
10 | af7bf89b | bellard | #else
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11 | af7bf89b | bellard | #define TARGET_LONG_BITS 64 |
12 | af7bf89b | bellard | #define TARGET_FPREGS 64 |
13 | 33b37802 | blueswir1 | #define TARGET_PAGE_BITS 13 /* 8k */ |
14 | af7bf89b | bellard | #endif
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15 | 3cf1e035 | bellard | |
16 | 92b72cbc | blueswir1 | #define TARGET_PHYS_ADDR_BITS 64 |
17 | 92b72cbc | blueswir1 | |
18 | 7a3f1944 | bellard | #include "cpu-defs.h" |
19 | 7a3f1944 | bellard | |
20 | 7a0e1f41 | bellard | #include "softfloat.h" |
21 | 7a0e1f41 | bellard | |
22 | 1fddef4b | bellard | #define TARGET_HAS_ICE 1 |
23 | 1fddef4b | bellard | |
24 | 9042c0e2 | ths | #if !defined(TARGET_SPARC64)
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25 | 0f8a249a | blueswir1 | #define ELF_MACHINE EM_SPARC
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26 | 9042c0e2 | ths | #else
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27 | 0f8a249a | blueswir1 | #define ELF_MACHINE EM_SPARCV9
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28 | 9042c0e2 | ths | #endif
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29 | 9042c0e2 | ths | |
30 | 7a3f1944 | bellard | /*#define EXCP_INTERRUPT 0x100*/
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31 | 7a3f1944 | bellard | |
32 | cf495bcf | bellard | /* trap definitions */
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33 | 3475187d | bellard | #ifndef TARGET_SPARC64
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34 | 878d3096 | bellard | #define TT_TFAULT 0x01 |
35 | cf495bcf | bellard | #define TT_ILL_INSN 0x02 |
36 | e8af50a3 | bellard | #define TT_PRIV_INSN 0x03 |
37 | e80cfcfc | bellard | #define TT_NFPU_INSN 0x04 |
38 | cf495bcf | bellard | #define TT_WIN_OVF 0x05 |
39 | 5fafdf24 | ths | #define TT_WIN_UNF 0x06 |
40 | d2889a3e | blueswir1 | #define TT_UNALIGNED 0x07 |
41 | e8af50a3 | bellard | #define TT_FP_EXCP 0x08 |
42 | 878d3096 | bellard | #define TT_DFAULT 0x09 |
43 | e32f879d | blueswir1 | #define TT_TOVF 0x0a |
44 | 878d3096 | bellard | #define TT_EXTINT 0x10 |
45 | 1b2e93c1 | blueswir1 | #define TT_CODE_ACCESS 0x21 |
46 | b4f0a316 | blueswir1 | #define TT_DATA_ACCESS 0x29 |
47 | cf495bcf | bellard | #define TT_DIV_ZERO 0x2a |
48 | fcc72045 | blueswir1 | #define TT_NCP_INSN 0x24 |
49 | cf495bcf | bellard | #define TT_TRAP 0x80 |
50 | 3475187d | bellard | #else
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51 | 3475187d | bellard | #define TT_TFAULT 0x08 |
52 | 83469015 | bellard | #define TT_TMISS 0x09 |
53 | 1b2e93c1 | blueswir1 | #define TT_CODE_ACCESS 0x0a |
54 | 3475187d | bellard | #define TT_ILL_INSN 0x10 |
55 | 3475187d | bellard | #define TT_PRIV_INSN 0x11 |
56 | 3475187d | bellard | #define TT_NFPU_INSN 0x20 |
57 | 3475187d | bellard | #define TT_FP_EXCP 0x21 |
58 | e32f879d | blueswir1 | #define TT_TOVF 0x23 |
59 | 3475187d | bellard | #define TT_CLRWIN 0x24 |
60 | 3475187d | bellard | #define TT_DIV_ZERO 0x28 |
61 | 3475187d | bellard | #define TT_DFAULT 0x30 |
62 | 83469015 | bellard | #define TT_DMISS 0x31 |
63 | b4f0a316 | blueswir1 | #define TT_DATA_ACCESS 0x32 |
64 | b4f0a316 | blueswir1 | #define TT_DPROT 0x33 |
65 | d2889a3e | blueswir1 | #define TT_UNALIGNED 0x34 |
66 | 83469015 | bellard | #define TT_PRIV_ACT 0x37 |
67 | 3475187d | bellard | #define TT_EXTINT 0x40 |
68 | 3475187d | bellard | #define TT_SPILL 0x80 |
69 | 3475187d | bellard | #define TT_FILL 0xc0 |
70 | 3475187d | bellard | #define TT_WOTHER 0x10 |
71 | 3475187d | bellard | #define TT_TRAP 0x100 |
72 | 3475187d | bellard | #endif
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73 | 7a3f1944 | bellard | |
74 | 7a3f1944 | bellard | #define PSR_NEG (1<<23) |
75 | 7a3f1944 | bellard | #define PSR_ZERO (1<<22) |
76 | 7a3f1944 | bellard | #define PSR_OVF (1<<21) |
77 | 7a3f1944 | bellard | #define PSR_CARRY (1<<20) |
78 | e8af50a3 | bellard | #define PSR_ICC (PSR_NEG|PSR_ZERO|PSR_OVF|PSR_CARRY)
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79 | e80cfcfc | bellard | #define PSR_EF (1<<12) |
80 | e80cfcfc | bellard | #define PSR_PIL 0xf00 |
81 | e8af50a3 | bellard | #define PSR_S (1<<7) |
82 | e8af50a3 | bellard | #define PSR_PS (1<<6) |
83 | e8af50a3 | bellard | #define PSR_ET (1<<5) |
84 | e8af50a3 | bellard | #define PSR_CWP 0x1f |
85 | e8af50a3 | bellard | |
86 | e8af50a3 | bellard | /* Trap base register */
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87 | e8af50a3 | bellard | #define TBR_BASE_MASK 0xfffff000 |
88 | e8af50a3 | bellard | |
89 | 3475187d | bellard | #if defined(TARGET_SPARC64)
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90 | 83469015 | bellard | #define PS_IG (1<<11) |
91 | 83469015 | bellard | #define PS_MG (1<<10) |
92 | 6ef905f6 | blueswir1 | #define PS_RMO (1<<7) |
93 | 83469015 | bellard | #define PS_RED (1<<5) |
94 | 3475187d | bellard | #define PS_PEF (1<<4) |
95 | 3475187d | bellard | #define PS_AM (1<<3) |
96 | 3475187d | bellard | #define PS_PRIV (1<<2) |
97 | 3475187d | bellard | #define PS_IE (1<<1) |
98 | 83469015 | bellard | #define PS_AG (1<<0) |
99 | a80dde08 | bellard | |
100 | a80dde08 | bellard | #define FPRS_FEF (1<<2) |
101 | 6f27aba6 | blueswir1 | |
102 | 6f27aba6 | blueswir1 | #define HS_PRIV (1<<2) |
103 | 3475187d | bellard | #endif
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104 | 3475187d | bellard | |
105 | e8af50a3 | bellard | /* Fcc */
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106 | e8af50a3 | bellard | #define FSR_RD1 (1<<31) |
107 | e8af50a3 | bellard | #define FSR_RD0 (1<<30) |
108 | e8af50a3 | bellard | #define FSR_RD_MASK (FSR_RD1 | FSR_RD0)
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109 | e8af50a3 | bellard | #define FSR_RD_NEAREST 0 |
110 | e8af50a3 | bellard | #define FSR_RD_ZERO FSR_RD0
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111 | e8af50a3 | bellard | #define FSR_RD_POS FSR_RD1
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112 | e8af50a3 | bellard | #define FSR_RD_NEG (FSR_RD1 | FSR_RD0)
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113 | e8af50a3 | bellard | |
114 | e8af50a3 | bellard | #define FSR_NVM (1<<27) |
115 | e8af50a3 | bellard | #define FSR_OFM (1<<26) |
116 | e8af50a3 | bellard | #define FSR_UFM (1<<25) |
117 | e8af50a3 | bellard | #define FSR_DZM (1<<24) |
118 | e8af50a3 | bellard | #define FSR_NXM (1<<23) |
119 | e8af50a3 | bellard | #define FSR_TEM_MASK (FSR_NVM | FSR_OFM | FSR_UFM | FSR_DZM | FSR_NXM)
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120 | e8af50a3 | bellard | |
121 | e8af50a3 | bellard | #define FSR_NVA (1<<9) |
122 | e8af50a3 | bellard | #define FSR_OFA (1<<8) |
123 | e8af50a3 | bellard | #define FSR_UFA (1<<7) |
124 | e8af50a3 | bellard | #define FSR_DZA (1<<6) |
125 | e8af50a3 | bellard | #define FSR_NXA (1<<5) |
126 | e8af50a3 | bellard | #define FSR_AEXC_MASK (FSR_NVA | FSR_OFA | FSR_UFA | FSR_DZA | FSR_NXA)
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127 | e8af50a3 | bellard | |
128 | e8af50a3 | bellard | #define FSR_NVC (1<<4) |
129 | e8af50a3 | bellard | #define FSR_OFC (1<<3) |
130 | e8af50a3 | bellard | #define FSR_UFC (1<<2) |
131 | e8af50a3 | bellard | #define FSR_DZC (1<<1) |
132 | e8af50a3 | bellard | #define FSR_NXC (1<<0) |
133 | e8af50a3 | bellard | #define FSR_CEXC_MASK (FSR_NVC | FSR_OFC | FSR_UFC | FSR_DZC | FSR_NXC)
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134 | e8af50a3 | bellard | |
135 | e8af50a3 | bellard | #define FSR_FTT2 (1<<16) |
136 | e8af50a3 | bellard | #define FSR_FTT1 (1<<15) |
137 | e8af50a3 | bellard | #define FSR_FTT0 (1<<14) |
138 | e8af50a3 | bellard | #define FSR_FTT_MASK (FSR_FTT2 | FSR_FTT1 | FSR_FTT0)
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139 | e80cfcfc | bellard | #define FSR_FTT_IEEE_EXCP (1 << 14) |
140 | e80cfcfc | bellard | #define FSR_FTT_UNIMPFPOP (3 << 14) |
141 | 9143e598 | blueswir1 | #define FSR_FTT_SEQ_ERROR (4 << 14) |
142 | e80cfcfc | bellard | #define FSR_FTT_INVAL_FPR (6 << 14) |
143 | e8af50a3 | bellard | |
144 | e8af50a3 | bellard | #define FSR_FCC1 (1<<11) |
145 | e8af50a3 | bellard | #define FSR_FCC0 (1<<10) |
146 | e8af50a3 | bellard | |
147 | e8af50a3 | bellard | /* MMU */
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148 | 0f8a249a | blueswir1 | #define MMU_E (1<<0) |
149 | 0f8a249a | blueswir1 | #define MMU_NF (1<<1) |
150 | e8af50a3 | bellard | |
151 | e8af50a3 | bellard | #define PTE_ENTRYTYPE_MASK 3 |
152 | e8af50a3 | bellard | #define PTE_ACCESS_MASK 0x1c |
153 | e8af50a3 | bellard | #define PTE_ACCESS_SHIFT 2 |
154 | 8d5f07fa | bellard | #define PTE_PPN_SHIFT 7 |
155 | e8af50a3 | bellard | #define PTE_ADDR_MASK 0xffffff00 |
156 | e8af50a3 | bellard | |
157 | 0f8a249a | blueswir1 | #define PG_ACCESSED_BIT 5 |
158 | 0f8a249a | blueswir1 | #define PG_MODIFIED_BIT 6 |
159 | e8af50a3 | bellard | #define PG_CACHE_BIT 7 |
160 | e8af50a3 | bellard | |
161 | e8af50a3 | bellard | #define PG_ACCESSED_MASK (1 << PG_ACCESSED_BIT) |
162 | e8af50a3 | bellard | #define PG_MODIFIED_MASK (1 << PG_MODIFIED_BIT) |
163 | e8af50a3 | bellard | #define PG_CACHE_MASK (1 << PG_CACHE_BIT) |
164 | e8af50a3 | bellard | |
165 | 1d6e34fd | bellard | /* 2 <= NWINDOWS <= 32. In QEMU it must also be a power of two. */
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166 | 1d6e34fd | bellard | #define NWINDOWS 8 |
167 | cf495bcf | bellard | |
168 | 6f27aba6 | blueswir1 | #if !defined(TARGET_SPARC64)
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169 | 6ebbf390 | j_mayer | #define NB_MMU_MODES 2 |
170 | 6f27aba6 | blueswir1 | #else
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171 | 6f27aba6 | blueswir1 | #define NB_MMU_MODES 3 |
172 | 375ee38b | blueswir1 | typedef struct trap_state { |
173 | 375ee38b | blueswir1 | uint64_t tpc; |
174 | 375ee38b | blueswir1 | uint64_t tnpc; |
175 | 375ee38b | blueswir1 | uint64_t tstate; |
176 | 375ee38b | blueswir1 | uint32_t tt; |
177 | 375ee38b | blueswir1 | } trap_state; |
178 | 6f27aba6 | blueswir1 | #endif
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179 | 6ebbf390 | j_mayer | |
180 | 7a3f1944 | bellard | typedef struct CPUSPARCState { |
181 | af7bf89b | bellard | target_ulong gregs[8]; /* general registers */ |
182 | af7bf89b | bellard | target_ulong *regwptr; /* pointer to current register window */
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183 | 65ce8c2f | bellard | float32 fpr[TARGET_FPREGS]; /* floating point registers */
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184 | af7bf89b | bellard | target_ulong pc; /* program counter */
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185 | af7bf89b | bellard | target_ulong npc; /* next program counter */
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186 | af7bf89b | bellard | target_ulong y; /* multiply/divide register */
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187 | dc99a3f2 | blueswir1 | |
188 | dc99a3f2 | blueswir1 | /* emulator internal flags handling */
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189 | d9bdab86 | blueswir1 | target_ulong cc_src, cc_src2; |
190 | dc99a3f2 | blueswir1 | target_ulong cc_dst; |
191 | dc99a3f2 | blueswir1 | |
192 | cf495bcf | bellard | uint32_t psr; /* processor state register */
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193 | 3475187d | bellard | target_ulong fsr; /* FPU state register */
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194 | cf495bcf | bellard | uint32_t cwp; /* index of current register window (extracted
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195 | cf495bcf | bellard | from PSR) */
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196 | cf495bcf | bellard | uint32_t wim; /* window invalid mask */
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197 | 3475187d | bellard | target_ulong tbr; /* trap base register */
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198 | e8af50a3 | bellard | int psrs; /* supervisor mode (extracted from PSR) */ |
199 | e8af50a3 | bellard | int psrps; /* previous supervisor mode */ |
200 | e8af50a3 | bellard | int psret; /* enable traps */ |
201 | 327ac2e7 | blueswir1 | uint32_t psrpil; /* interrupt blocking level */
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202 | 327ac2e7 | blueswir1 | uint32_t pil_in; /* incoming interrupt level bitmap */
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203 | e80cfcfc | bellard | int psref; /* enable fpu */ |
204 | 62724a37 | blueswir1 | target_ulong version; |
205 | cf495bcf | bellard | jmp_buf jmp_env; |
206 | cf495bcf | bellard | int user_mode_only;
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207 | cf495bcf | bellard | int exception_index;
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208 | cf495bcf | bellard | int interrupt_index;
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209 | cf495bcf | bellard | int interrupt_request;
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210 | ba3c64fb | bellard | int halted;
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211 | 6d5f237a | blueswir1 | uint32_t mmu_bm; |
212 | 3deaeab7 | blueswir1 | uint32_t mmu_ctpr_mask; |
213 | 3deaeab7 | blueswir1 | uint32_t mmu_cxr_mask; |
214 | 3deaeab7 | blueswir1 | uint32_t mmu_sfsr_mask; |
215 | 3deaeab7 | blueswir1 | uint32_t mmu_trcr_mask; |
216 | cf495bcf | bellard | /* NOTE: we allow 8 more registers to handle wrapping */
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217 | af7bf89b | bellard | target_ulong regbase[NWINDOWS * 16 + 8]; |
218 | d720b93d | bellard | |
219 | a316d335 | bellard | CPU_COMMON |
220 | a316d335 | bellard | |
221 | e8af50a3 | bellard | /* MMU regs */
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222 | 3475187d | bellard | #if defined(TARGET_SPARC64)
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223 | 3475187d | bellard | uint64_t lsu; |
224 | 3475187d | bellard | #define DMMU_E 0x8 |
225 | 3475187d | bellard | #define IMMU_E 0x4 |
226 | 3475187d | bellard | uint64_t immuregs[16];
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227 | 3475187d | bellard | uint64_t dmmuregs[16];
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228 | 3475187d | bellard | uint64_t itlb_tag[64];
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229 | 3475187d | bellard | uint64_t itlb_tte[64];
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230 | 3475187d | bellard | uint64_t dtlb_tag[64];
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231 | 3475187d | bellard | uint64_t dtlb_tte[64];
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232 | 3475187d | bellard | #else
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233 | 3dd9a152 | blueswir1 | uint32_t mmuregs[32];
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234 | 952a328f | blueswir1 | uint64_t mxccdata[4];
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235 | 952a328f | blueswir1 | uint64_t mxccregs[8];
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236 | 3ebf5aaf | blueswir1 | uint64_t prom_addr; |
237 | 3475187d | bellard | #endif
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238 | e8af50a3 | bellard | /* temporary float registers */
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239 | 65ce8c2f | bellard | float32 ft0, ft1; |
240 | 65ce8c2f | bellard | float64 dt0, dt1; |
241 | 1f587329 | blueswir1 | #if defined(CONFIG_USER_ONLY)
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242 | 1f587329 | blueswir1 | float128 qt0, qt1; |
243 | 1f587329 | blueswir1 | #endif
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244 | 7a0e1f41 | bellard | float_status fp_status; |
245 | af7bf89b | bellard | #if defined(TARGET_SPARC64)
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246 | 3475187d | bellard | #define MAXTL 4 |
247 | 3475187d | bellard | uint64_t t0, t1, t2; |
248 | 375ee38b | blueswir1 | trap_state *tsptr; |
249 | 375ee38b | blueswir1 | trap_state ts[MAXTL]; |
250 | 0f8a249a | blueswir1 | uint32_t xcc; /* Extended integer condition codes */
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251 | 3475187d | bellard | uint32_t asi; |
252 | 3475187d | bellard | uint32_t pstate; |
253 | 3475187d | bellard | uint32_t tl; |
254 | 3475187d | bellard | uint32_t cansave, canrestore, otherwin, wstate, cleanwin; |
255 | 83469015 | bellard | uint64_t agregs[8]; /* alternate general registers */ |
256 | 83469015 | bellard | uint64_t bgregs[8]; /* backup for normal global registers */ |
257 | 83469015 | bellard | uint64_t igregs[8]; /* interrupt general registers */ |
258 | 83469015 | bellard | uint64_t mgregs[8]; /* mmu general registers */ |
259 | 3475187d | bellard | uint64_t fprs; |
260 | 83469015 | bellard | uint64_t tick_cmpr, stick_cmpr; |
261 | 20c9f095 | blueswir1 | void *tick, *stick;
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262 | 725cb90b | bellard | uint64_t gsr; |
263 | e9ebed4d | blueswir1 | uint32_t gl; // UA2005
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264 | e9ebed4d | blueswir1 | /* UA 2005 hyperprivileged registers */
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265 | e9ebed4d | blueswir1 | uint64_t hpstate, htstate[MAXTL], hintp, htba, hver, hstick_cmpr, ssr; |
266 | 20c9f095 | blueswir1 | void *hstick; // UA 2005 |
267 | 3475187d | bellard | #endif
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268 | 3475187d | bellard | #if !defined(TARGET_SPARC64) && !defined(reg_T2)
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269 | 3475187d | bellard | target_ulong t2; |
270 | af7bf89b | bellard | #endif
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271 | 7a3f1944 | bellard | } CPUSPARCState; |
272 | 3475187d | bellard | #if defined(TARGET_SPARC64)
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273 | 3475187d | bellard | #define GET_FSR32(env) (env->fsr & 0xcfc1ffff) |
274 | 0f8a249a | blueswir1 | #define PUT_FSR32(env, val) do { uint32_t _tmp = val; \ |
275 | 0f8a249a | blueswir1 | env->fsr = (_tmp & 0xcfc1c3ff) | (env->fsr & 0x3f00000000ULL); \ |
276 | 3475187d | bellard | } while (0) |
277 | 3475187d | bellard | #define GET_FSR64(env) (env->fsr & 0x3fcfc1ffffULL) |
278 | 0f8a249a | blueswir1 | #define PUT_FSR64(env, val) do { uint64_t _tmp = val; \ |
279 | 0f8a249a | blueswir1 | env->fsr = _tmp & 0x3fcfc1c3ffULL; \
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280 | 3475187d | bellard | } while (0) |
281 | 3475187d | bellard | #else
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282 | 3475187d | bellard | #define GET_FSR32(env) (env->fsr)
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283 | 3e736bf4 | blueswir1 | #define PUT_FSR32(env, val) do { uint32_t _tmp = val; \ |
284 | 9143e598 | blueswir1 | env->fsr = (_tmp & 0xcfc1dfff) | (env->fsr & 0x000e0000); \ |
285 | 3475187d | bellard | } while (0) |
286 | 3475187d | bellard | #endif
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287 | 7a3f1944 | bellard | |
288 | aaed909a | bellard | CPUSPARCState *cpu_sparc_init(const char *cpu_model); |
289 | 7a3f1944 | bellard | int cpu_sparc_exec(CPUSPARCState *s);
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290 | 7a3f1944 | bellard | int cpu_sparc_close(CPUSPARCState *s);
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291 | 62724a37 | blueswir1 | void sparc_cpu_list (FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, |
292 | 62724a37 | blueswir1 | ...)); |
293 | aaed909a | bellard | void cpu_sparc_set_id(CPUSPARCState *env, unsigned int cpu); |
294 | 7a3f1944 | bellard | |
295 | 62724a37 | blueswir1 | #define GET_PSR(env) (env->version | (env->psr & PSR_ICC) | \
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296 | 0f8a249a | blueswir1 | (env->psref? PSR_EF : 0) | \
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297 | 0f8a249a | blueswir1 | (env->psrpil << 8) | \
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298 | 0f8a249a | blueswir1 | (env->psrs? PSR_S : 0) | \
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299 | 0f8a249a | blueswir1 | (env->psrps? PSR_PS : 0) | \
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300 | 0f8a249a | blueswir1 | (env->psret? PSR_ET : 0) | env->cwp)
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301 | b4ff5987 | bellard | |
302 | b4ff5987 | bellard | #ifndef NO_CPU_IO_DEFS
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303 | b4ff5987 | bellard | void cpu_set_cwp(CPUSPARCState *env1, int new_cwp); |
304 | b4ff5987 | bellard | #endif
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305 | b4ff5987 | bellard | |
306 | 0f8a249a | blueswir1 | #define PUT_PSR(env, val) do { int _tmp = val; \ |
307 | 0f8a249a | blueswir1 | env->psr = _tmp & PSR_ICC; \ |
308 | 0f8a249a | blueswir1 | env->psref = (_tmp & PSR_EF)? 1 : 0; \ |
309 | 0f8a249a | blueswir1 | env->psrpil = (_tmp & PSR_PIL) >> 8; \
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310 | 0f8a249a | blueswir1 | env->psrs = (_tmp & PSR_S)? 1 : 0; \ |
311 | 0f8a249a | blueswir1 | env->psrps = (_tmp & PSR_PS)? 1 : 0; \ |
312 | 0f8a249a | blueswir1 | env->psret = (_tmp & PSR_ET)? 1 : 0; \ |
313 | d4218d99 | blueswir1 | cpu_set_cwp(env, _tmp & PSR_CWP); \ |
314 | b4ff5987 | bellard | } while (0) |
315 | b4ff5987 | bellard | |
316 | 3475187d | bellard | #ifdef TARGET_SPARC64
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317 | 17d996e1 | blueswir1 | #define GET_CCR(env) (((env->xcc >> 20) << 4) | ((env->psr & PSR_ICC) >> 20)) |
318 | 0f8a249a | blueswir1 | #define PUT_CCR(env, val) do { int _tmp = val; \ |
319 | 0f8a249a | blueswir1 | env->xcc = (_tmp >> 4) << 20; \ |
320 | 0f8a249a | blueswir1 | env->psr = (_tmp & 0xf) << 20; \ |
321 | 3475187d | bellard | } while (0) |
322 | 17d996e1 | blueswir1 | #define GET_CWP64(env) (NWINDOWS - 1 - (env)->cwp) |
323 | 8f1f22f6 | blueswir1 | #define PUT_CWP64(env, val) \
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324 | 8f1f22f6 | blueswir1 | cpu_set_cwp(env, NWINDOWS - 1 - ((val) & (NWINDOWS - 1))) |
325 | 17d996e1 | blueswir1 | |
326 | 3475187d | bellard | #endif
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327 | 3475187d | bellard | |
328 | 5a7b542b | ths | int cpu_sparc_signal_handler(int host_signum, void *pinfo, void *puc); |
329 | 5dcb6b91 | blueswir1 | void do_unassigned_access(target_phys_addr_t addr, int is_write, int is_exec, |
330 | 6c36d3fa | blueswir1 | int is_asi);
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331 | 327ac2e7 | blueswir1 | void cpu_check_irqs(CPUSPARCState *env);
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332 | 7a3f1944 | bellard | |
333 | 9467d44c | ths | #define CPUState CPUSPARCState
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334 | 9467d44c | ths | #define cpu_init cpu_sparc_init
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335 | 9467d44c | ths | #define cpu_exec cpu_sparc_exec
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336 | 9467d44c | ths | #define cpu_gen_code cpu_sparc_gen_code
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337 | 9467d44c | ths | #define cpu_signal_handler cpu_sparc_signal_handler
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338 | c732abe2 | j_mayer | #define cpu_list sparc_cpu_list
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339 | 9467d44c | ths | |
340 | 6ebbf390 | j_mayer | /* MMU modes definitions */
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341 | 6f27aba6 | blueswir1 | #define MMU_MODE0_SUFFIX _user
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342 | 6f27aba6 | blueswir1 | #define MMU_MODE1_SUFFIX _kernel
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343 | 6f27aba6 | blueswir1 | #ifdef TARGET_SPARC64
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344 | 6f27aba6 | blueswir1 | #define MMU_MODE2_SUFFIX _hypv
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345 | 6f27aba6 | blueswir1 | #endif
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346 | 9e31b9e2 | blueswir1 | #define MMU_USER_IDX 0 |
347 | 9e31b9e2 | blueswir1 | #define MMU_KERNEL_IDX 1 |
348 | 9e31b9e2 | blueswir1 | #define MMU_HYPV_IDX 2 |
349 | 9e31b9e2 | blueswir1 | |
350 | 6ebbf390 | j_mayer | static inline int cpu_mmu_index (CPUState *env) |
351 | 6ebbf390 | j_mayer | { |
352 | 6f27aba6 | blueswir1 | #if defined(CONFIG_USER_ONLY)
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353 | 9e31b9e2 | blueswir1 | return MMU_USER_IDX;
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354 | 6f27aba6 | blueswir1 | #elif !defined(TARGET_SPARC64)
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355 | 6f27aba6 | blueswir1 | return env->psrs;
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356 | 6f27aba6 | blueswir1 | #else
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357 | 6f27aba6 | blueswir1 | if (!env->psrs)
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358 | 9e31b9e2 | blueswir1 | return MMU_USER_IDX;
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359 | 6f27aba6 | blueswir1 | else if ((env->hpstate & HS_PRIV) == 0) |
360 | 9e31b9e2 | blueswir1 | return MMU_KERNEL_IDX;
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361 | 6f27aba6 | blueswir1 | else
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362 | 9e31b9e2 | blueswir1 | return MMU_HYPV_IDX;
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363 | 6f27aba6 | blueswir1 | #endif
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364 | 6f27aba6 | blueswir1 | } |
365 | 6f27aba6 | blueswir1 | |
366 | 6f27aba6 | blueswir1 | static inline int cpu_fpu_enabled(CPUState *env) |
367 | 6f27aba6 | blueswir1 | { |
368 | 6f27aba6 | blueswir1 | #if defined(CONFIG_USER_ONLY)
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369 | 6f27aba6 | blueswir1 | return 1; |
370 | 6f27aba6 | blueswir1 | #elif !defined(TARGET_SPARC64)
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371 | 6f27aba6 | blueswir1 | return env->psref;
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372 | 6f27aba6 | blueswir1 | #else
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373 | 6f27aba6 | blueswir1 | return ((env->pstate & PS_PEF) != 0) && ((env->fprs & FPRS_FEF) != 0); |
374 | 6f27aba6 | blueswir1 | #endif
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375 | 6ebbf390 | j_mayer | } |
376 | 6ebbf390 | j_mayer | |
377 | 7a3f1944 | bellard | #include "cpu-all.h" |
378 | 7a3f1944 | bellard | |
379 | 7a3f1944 | bellard | #endif |