root / hw / xilinx_ethlite.c @ 88b3be20
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1 | b43848a1 | Edgar E. Iglesias | /*
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2 | b43848a1 | Edgar E. Iglesias | * QEMU model of the Xilinx Ethernet Lite MAC.
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3 | b43848a1 | Edgar E. Iglesias | *
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4 | b43848a1 | Edgar E. Iglesias | * Copyright (c) 2009 Edgar E. Iglesias.
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5 | b43848a1 | Edgar E. Iglesias | *
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6 | b43848a1 | Edgar E. Iglesias | * Permission is hereby granted, free of charge, to any person obtaining a copy
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7 | b43848a1 | Edgar E. Iglesias | * of this software and associated documentation files (the "Software"), to deal
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8 | b43848a1 | Edgar E. Iglesias | * in the Software without restriction, including without limitation the rights
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9 | b43848a1 | Edgar E. Iglesias | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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10 | b43848a1 | Edgar E. Iglesias | * copies of the Software, and to permit persons to whom the Software is
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11 | b43848a1 | Edgar E. Iglesias | * furnished to do so, subject to the following conditions:
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12 | b43848a1 | Edgar E. Iglesias | *
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13 | b43848a1 | Edgar E. Iglesias | * The above copyright notice and this permission notice shall be included in
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14 | b43848a1 | Edgar E. Iglesias | * all copies or substantial portions of the Software.
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15 | b43848a1 | Edgar E. Iglesias | *
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16 | b43848a1 | Edgar E. Iglesias | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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17 | b43848a1 | Edgar E. Iglesias | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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18 | b43848a1 | Edgar E. Iglesias | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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19 | b43848a1 | Edgar E. Iglesias | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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20 | b43848a1 | Edgar E. Iglesias | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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21 | b43848a1 | Edgar E. Iglesias | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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22 | b43848a1 | Edgar E. Iglesias | * THE SOFTWARE.
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23 | b43848a1 | Edgar E. Iglesias | */
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24 | b43848a1 | Edgar E. Iglesias | |
25 | b43848a1 | Edgar E. Iglesias | #include "sysbus.h" |
26 | b43848a1 | Edgar E. Iglesias | #include "hw.h" |
27 | b43848a1 | Edgar E. Iglesias | #include "net.h" |
28 | b43848a1 | Edgar E. Iglesias | |
29 | b43848a1 | Edgar E. Iglesias | #define D(x)
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30 | b43848a1 | Edgar E. Iglesias | #define R_TX_BUF0 0 |
31 | b43848a1 | Edgar E. Iglesias | #define R_TX_LEN0 (0x07f4 / 4) |
32 | b43848a1 | Edgar E. Iglesias | #define R_TX_GIE0 (0x07f8 / 4) |
33 | b43848a1 | Edgar E. Iglesias | #define R_TX_CTRL0 (0x07fc / 4) |
34 | b43848a1 | Edgar E. Iglesias | #define R_TX_BUF1 (0x0800 / 4) |
35 | b43848a1 | Edgar E. Iglesias | #define R_TX_LEN1 (0x0ff4 / 4) |
36 | b43848a1 | Edgar E. Iglesias | #define R_TX_CTRL1 (0x0ffc / 4) |
37 | b43848a1 | Edgar E. Iglesias | |
38 | b43848a1 | Edgar E. Iglesias | #define R_RX_BUF0 (0x1000 / 4) |
39 | b43848a1 | Edgar E. Iglesias | #define R_RX_CTRL0 (0x17fc / 4) |
40 | b43848a1 | Edgar E. Iglesias | #define R_RX_BUF1 (0x1800 / 4) |
41 | b43848a1 | Edgar E. Iglesias | #define R_RX_CTRL1 (0x1ffc / 4) |
42 | b43848a1 | Edgar E. Iglesias | #define R_MAX (0x2000 / 4) |
43 | b43848a1 | Edgar E. Iglesias | |
44 | b43848a1 | Edgar E. Iglesias | #define GIE_GIE 0x80000000 |
45 | b43848a1 | Edgar E. Iglesias | |
46 | b43848a1 | Edgar E. Iglesias | #define CTRL_I 0x8 |
47 | b43848a1 | Edgar E. Iglesias | #define CTRL_P 0x2 |
48 | b43848a1 | Edgar E. Iglesias | #define CTRL_S 0x1 |
49 | b43848a1 | Edgar E. Iglesias | |
50 | b43848a1 | Edgar E. Iglesias | struct xlx_ethlite
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51 | b43848a1 | Edgar E. Iglesias | { |
52 | b43848a1 | Edgar E. Iglesias | SysBusDevice busdev; |
53 | b43848a1 | Edgar E. Iglesias | qemu_irq irq; |
54 | b43848a1 | Edgar E. Iglesias | VLANClientState *vc; |
55 | b43848a1 | Edgar E. Iglesias | |
56 | ee6847d1 | Gerd Hoffmann | uint32_t c_tx_pingpong; |
57 | ee6847d1 | Gerd Hoffmann | uint32_t c_rx_pingpong; |
58 | b43848a1 | Edgar E. Iglesias | unsigned int txbuf; |
59 | b43848a1 | Edgar E. Iglesias | unsigned int rxbuf; |
60 | b43848a1 | Edgar E. Iglesias | |
61 | b43848a1 | Edgar E. Iglesias | uint8_t macaddr[6];
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62 | b43848a1 | Edgar E. Iglesias | uint32_t regs[R_MAX]; |
63 | b43848a1 | Edgar E. Iglesias | }; |
64 | b43848a1 | Edgar E. Iglesias | |
65 | b43848a1 | Edgar E. Iglesias | static inline void eth_pulse_irq(struct xlx_ethlite *s) |
66 | b43848a1 | Edgar E. Iglesias | { |
67 | b43848a1 | Edgar E. Iglesias | /* Only the first gie reg is active. */
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68 | b43848a1 | Edgar E. Iglesias | if (s->regs[R_TX_GIE0] & GIE_GIE) {
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69 | b43848a1 | Edgar E. Iglesias | qemu_irq_pulse(s->irq); |
70 | b43848a1 | Edgar E. Iglesias | } |
71 | b43848a1 | Edgar E. Iglesias | } |
72 | b43848a1 | Edgar E. Iglesias | |
73 | b43848a1 | Edgar E. Iglesias | static uint32_t eth_readl (void *opaque, target_phys_addr_t addr) |
74 | b43848a1 | Edgar E. Iglesias | { |
75 | b43848a1 | Edgar E. Iglesias | struct xlx_ethlite *s = opaque;
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76 | b43848a1 | Edgar E. Iglesias | uint32_t r = 0;
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77 | b43848a1 | Edgar E. Iglesias | |
78 | b43848a1 | Edgar E. Iglesias | addr >>= 2;
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79 | b43848a1 | Edgar E. Iglesias | |
80 | b43848a1 | Edgar E. Iglesias | switch (addr)
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81 | b43848a1 | Edgar E. Iglesias | { |
82 | b43848a1 | Edgar E. Iglesias | case R_TX_GIE0:
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83 | b43848a1 | Edgar E. Iglesias | case R_TX_LEN0:
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84 | b43848a1 | Edgar E. Iglesias | case R_TX_LEN1:
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85 | b43848a1 | Edgar E. Iglesias | case R_TX_CTRL1:
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86 | b43848a1 | Edgar E. Iglesias | case R_TX_CTRL0:
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87 | b43848a1 | Edgar E. Iglesias | case R_RX_CTRL1:
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88 | b43848a1 | Edgar E. Iglesias | case R_RX_CTRL0:
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89 | b43848a1 | Edgar E. Iglesias | r = s->regs[addr]; |
90 | b43848a1 | Edgar E. Iglesias | D(qemu_log("%s %x=%x\n", __func__, addr * 4, r)); |
91 | b43848a1 | Edgar E. Iglesias | break;
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92 | b43848a1 | Edgar E. Iglesias | |
93 | b43848a1 | Edgar E. Iglesias | /* Rx packet data is endian fixed at the way into the rx rams. This
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94 | b43848a1 | Edgar E. Iglesias | * speeds things up because the ethlite MAC does not have a len
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95 | b43848a1 | Edgar E. Iglesias | * register. That means the CPU will issue MMIO reads for the entire
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96 | b43848a1 | Edgar E. Iglesias | * 2k rx buffer even for small packets.
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97 | b43848a1 | Edgar E. Iglesias | */
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98 | b43848a1 | Edgar E. Iglesias | default:
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99 | b43848a1 | Edgar E. Iglesias | r = s->regs[addr]; |
100 | b43848a1 | Edgar E. Iglesias | break;
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101 | b43848a1 | Edgar E. Iglesias | } |
102 | b43848a1 | Edgar E. Iglesias | return r;
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103 | b43848a1 | Edgar E. Iglesias | } |
104 | b43848a1 | Edgar E. Iglesias | |
105 | b43848a1 | Edgar E. Iglesias | static void |
106 | b43848a1 | Edgar E. Iglesias | eth_writel (void *opaque, target_phys_addr_t addr, uint32_t value)
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107 | b43848a1 | Edgar E. Iglesias | { |
108 | b43848a1 | Edgar E. Iglesias | struct xlx_ethlite *s = opaque;
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109 | b43848a1 | Edgar E. Iglesias | unsigned int base = 0; |
110 | b43848a1 | Edgar E. Iglesias | |
111 | b43848a1 | Edgar E. Iglesias | addr >>= 2;
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112 | b43848a1 | Edgar E. Iglesias | switch (addr)
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113 | b43848a1 | Edgar E. Iglesias | { |
114 | b43848a1 | Edgar E. Iglesias | case R_TX_CTRL0:
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115 | b43848a1 | Edgar E. Iglesias | case R_TX_CTRL1:
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116 | b43848a1 | Edgar E. Iglesias | if (addr == R_TX_CTRL1)
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117 | b43848a1 | Edgar E. Iglesias | base = 0x800 / 4; |
118 | b43848a1 | Edgar E. Iglesias | |
119 | b43848a1 | Edgar E. Iglesias | D(qemu_log("%s addr=%x val=%x\n", __func__, addr * 4, value)); |
120 | b43848a1 | Edgar E. Iglesias | if ((value & (CTRL_P | CTRL_S)) == CTRL_S) {
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121 | b43848a1 | Edgar E. Iglesias | qemu_send_packet(s->vc, |
122 | b43848a1 | Edgar E. Iglesias | (void *) &s->regs[base],
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123 | b43848a1 | Edgar E. Iglesias | s->regs[base + R_TX_LEN0]); |
124 | b43848a1 | Edgar E. Iglesias | D(qemu_log("eth_tx %d\n", s->regs[base + R_TX_LEN0]));
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125 | b43848a1 | Edgar E. Iglesias | if (s->regs[base + R_TX_CTRL0] & CTRL_I)
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126 | b43848a1 | Edgar E. Iglesias | eth_pulse_irq(s); |
127 | b43848a1 | Edgar E. Iglesias | } else if ((value & (CTRL_P | CTRL_S)) == (CTRL_P | CTRL_S)) { |
128 | b43848a1 | Edgar E. Iglesias | memcpy(&s->macaddr[0], &s->regs[base], 6); |
129 | b43848a1 | Edgar E. Iglesias | if (s->regs[base + R_TX_CTRL0] & CTRL_I)
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130 | b43848a1 | Edgar E. Iglesias | eth_pulse_irq(s); |
131 | b43848a1 | Edgar E. Iglesias | } |
132 | b43848a1 | Edgar E. Iglesias | |
133 | b43848a1 | Edgar E. Iglesias | /* We are fast and get ready pretty much immediately so
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134 | b43848a1 | Edgar E. Iglesias | we actually never flip the S nor P bits to one. */
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135 | b43848a1 | Edgar E. Iglesias | s->regs[addr] = value & ~(CTRL_P | CTRL_S); |
136 | b43848a1 | Edgar E. Iglesias | break;
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137 | b43848a1 | Edgar E. Iglesias | |
138 | b43848a1 | Edgar E. Iglesias | /* Keep these native. */
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139 | b43848a1 | Edgar E. Iglesias | case R_TX_LEN0:
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140 | b43848a1 | Edgar E. Iglesias | case R_TX_LEN1:
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141 | b43848a1 | Edgar E. Iglesias | case R_TX_GIE0:
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142 | b43848a1 | Edgar E. Iglesias | case R_RX_CTRL0:
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143 | b43848a1 | Edgar E. Iglesias | case R_RX_CTRL1:
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144 | b43848a1 | Edgar E. Iglesias | D(qemu_log("%s addr=%x val=%x\n", __func__, addr * 4, value)); |
145 | b43848a1 | Edgar E. Iglesias | s->regs[addr] = value; |
146 | b43848a1 | Edgar E. Iglesias | break;
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147 | b43848a1 | Edgar E. Iglesias | |
148 | b43848a1 | Edgar E. Iglesias | /* Packet data, make sure it stays BE. */
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149 | b43848a1 | Edgar E. Iglesias | default:
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150 | b43848a1 | Edgar E. Iglesias | s->regs[addr] = cpu_to_be32(value); |
151 | b43848a1 | Edgar E. Iglesias | break;
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152 | b43848a1 | Edgar E. Iglesias | } |
153 | b43848a1 | Edgar E. Iglesias | } |
154 | b43848a1 | Edgar E. Iglesias | |
155 | d60efc6b | Blue Swirl | static CPUReadMemoryFunc * const eth_read[] = { |
156 | b43848a1 | Edgar E. Iglesias | NULL, NULL, ð_readl, |
157 | b43848a1 | Edgar E. Iglesias | }; |
158 | b43848a1 | Edgar E. Iglesias | |
159 | d60efc6b | Blue Swirl | static CPUWriteMemoryFunc * const eth_write[] = { |
160 | b43848a1 | Edgar E. Iglesias | NULL, NULL, ð_writel, |
161 | b43848a1 | Edgar E. Iglesias | }; |
162 | b43848a1 | Edgar E. Iglesias | |
163 | df12c1f5 | Jan Kiszka | static int eth_can_rx(VLANClientState *vc) |
164 | b43848a1 | Edgar E. Iglesias | { |
165 | df12c1f5 | Jan Kiszka | struct xlx_ethlite *s = vc->opaque;
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166 | b43848a1 | Edgar E. Iglesias | int r;
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167 | b43848a1 | Edgar E. Iglesias | r = !(s->regs[R_RX_CTRL0] & CTRL_S); |
168 | b43848a1 | Edgar E. Iglesias | return r;
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169 | b43848a1 | Edgar E. Iglesias | } |
170 | b43848a1 | Edgar E. Iglesias | |
171 | df12c1f5 | Jan Kiszka | static ssize_t eth_rx(VLANClientState *vc, const uint8_t *buf, size_t size) |
172 | b43848a1 | Edgar E. Iglesias | { |
173 | df12c1f5 | Jan Kiszka | struct xlx_ethlite *s = vc->opaque;
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174 | b43848a1 | Edgar E. Iglesias | unsigned int rxbase = s->rxbuf * (0x800 / 4); |
175 | b43848a1 | Edgar E. Iglesias | int i;
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176 | b43848a1 | Edgar E. Iglesias | |
177 | b43848a1 | Edgar E. Iglesias | /* DA filter. */
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178 | b43848a1 | Edgar E. Iglesias | if (!(buf[0] & 0x80) && memcmp(&s->macaddr[0], buf, 6)) |
179 | df12c1f5 | Jan Kiszka | return size;
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180 | b43848a1 | Edgar E. Iglesias | |
181 | b43848a1 | Edgar E. Iglesias | if (s->regs[rxbase + R_RX_CTRL0] & CTRL_S) {
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182 | b43848a1 | Edgar E. Iglesias | D(qemu_log("ethlite lost packet %x\n", s->regs[R_RX_CTRL0]));
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183 | df12c1f5 | Jan Kiszka | return -1; |
184 | b43848a1 | Edgar E. Iglesias | } |
185 | b43848a1 | Edgar E. Iglesias | |
186 | b43848a1 | Edgar E. Iglesias | D(qemu_log("%s %d rxbase=%x\n", __func__, size, rxbase));
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187 | b43848a1 | Edgar E. Iglesias | memcpy(&s->regs[rxbase + R_RX_BUF0], buf, size); |
188 | b43848a1 | Edgar E. Iglesias | |
189 | b43848a1 | Edgar E. Iglesias | /* Bring it into host endianess. */
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190 | b43848a1 | Edgar E. Iglesias | for (i = 0; i < ((size + 3) / 4); i++) { |
191 | b43848a1 | Edgar E. Iglesias | uint32_t d = s->regs[rxbase + R_RX_BUF0 + i]; |
192 | b43848a1 | Edgar E. Iglesias | s->regs[rxbase + R_RX_BUF0 + i] = be32_to_cpu(d); |
193 | b43848a1 | Edgar E. Iglesias | } |
194 | b43848a1 | Edgar E. Iglesias | |
195 | b43848a1 | Edgar E. Iglesias | s->regs[rxbase + R_RX_CTRL0] |= CTRL_S; |
196 | b43848a1 | Edgar E. Iglesias | if (s->regs[rxbase + R_RX_CTRL0] & CTRL_I)
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197 | b43848a1 | Edgar E. Iglesias | eth_pulse_irq(s); |
198 | b43848a1 | Edgar E. Iglesias | |
199 | b43848a1 | Edgar E. Iglesias | /* If c_rx_pingpong was set flip buffers. */
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200 | b43848a1 | Edgar E. Iglesias | s->rxbuf ^= s->c_rx_pingpong; |
201 | df12c1f5 | Jan Kiszka | return size;
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202 | b43848a1 | Edgar E. Iglesias | } |
203 | b43848a1 | Edgar E. Iglesias | |
204 | b43848a1 | Edgar E. Iglesias | static void eth_cleanup(VLANClientState *vc) |
205 | b43848a1 | Edgar E. Iglesias | { |
206 | b43848a1 | Edgar E. Iglesias | struct xlx_ethlite *s = vc->opaque;
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207 | b43848a1 | Edgar E. Iglesias | qemu_free(s); |
208 | b43848a1 | Edgar E. Iglesias | } |
209 | b43848a1 | Edgar E. Iglesias | |
210 | b43848a1 | Edgar E. Iglesias | static void xilinx_ethlite_init(SysBusDevice *dev) |
211 | b43848a1 | Edgar E. Iglesias | { |
212 | b43848a1 | Edgar E. Iglesias | struct xlx_ethlite *s = FROM_SYSBUS(typeof (*s), dev);
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213 | b43848a1 | Edgar E. Iglesias | int regs;
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214 | b43848a1 | Edgar E. Iglesias | |
215 | b43848a1 | Edgar E. Iglesias | sysbus_init_irq(dev, &s->irq); |
216 | b43848a1 | Edgar E. Iglesias | s->rxbuf = 0;
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217 | b43848a1 | Edgar E. Iglesias | |
218 | 1eed09cb | Avi Kivity | regs = cpu_register_io_memory(eth_read, eth_write, s); |
219 | b43848a1 | Edgar E. Iglesias | sysbus_init_mmio(dev, R_MAX * 4, regs);
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220 | b43848a1 | Edgar E. Iglesias | |
221 | b43848a1 | Edgar E. Iglesias | qdev_get_macaddr(&dev->qdev, s->macaddr); |
222 | b43848a1 | Edgar E. Iglesias | s->vc = qdev_get_vlan_client(&dev->qdev, |
223 | df12c1f5 | Jan Kiszka | eth_can_rx, eth_rx, NULL, eth_cleanup, s);
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224 | b43848a1 | Edgar E. Iglesias | } |
225 | b43848a1 | Edgar E. Iglesias | |
226 | ee6847d1 | Gerd Hoffmann | static SysBusDeviceInfo xilinx_ethlite_info = {
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227 | ee6847d1 | Gerd Hoffmann | .init = xilinx_ethlite_init, |
228 | ee6847d1 | Gerd Hoffmann | .qdev.name = "xilinx,ethlite",
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229 | ee6847d1 | Gerd Hoffmann | .qdev.size = sizeof(struct xlx_ethlite), |
230 | ee6847d1 | Gerd Hoffmann | .qdev.props = (Property[]) { |
231 | 05f02579 | Gerd Hoffmann | DEFINE_PROP_UINT32("txpingpong", struct xlx_ethlite, c_tx_pingpong, 1), |
232 | 05f02579 | Gerd Hoffmann | DEFINE_PROP_UINT32("rxpingpong", struct xlx_ethlite, c_rx_pingpong, 1), |
233 | 05f02579 | Gerd Hoffmann | DEFINE_PROP_END_OF_LIST(), |
234 | ee6847d1 | Gerd Hoffmann | } |
235 | ee6847d1 | Gerd Hoffmann | }; |
236 | ee6847d1 | Gerd Hoffmann | |
237 | b43848a1 | Edgar E. Iglesias | static void xilinx_ethlite_register(void) |
238 | b43848a1 | Edgar E. Iglesias | { |
239 | ee6847d1 | Gerd Hoffmann | sysbus_register_withprop(&xilinx_ethlite_info); |
240 | b43848a1 | Edgar E. Iglesias | } |
241 | b43848a1 | Edgar E. Iglesias | |
242 | b43848a1 | Edgar E. Iglesias | device_init(xilinx_ethlite_register) |